From: Eric Biggers
Replace all calls to in_interrupt() in the PowerPC crypto code with
!crypto_simd_usable(). This causes the crypto self-tests to test the
no-SIMD code paths when CONFIG_CRYPTO_MANAGER_EXTRA_TESTS=y.
The p8_ghash algorithm is currently failing and needs to be fixed, as it
On 4/12/19 8:56 PM, Josh Poimboeuf wrote:
> Add ARM64 to the legend of architectures. It's already used in several
> places in kernel-parameters.txt.
>
> Suggested-by: Randy Dunlap
> Signed-off-by: Josh Poimboeuf
> ---
> Documentation/admin-guide/kernel-parameters.rst | 1 +
> 1 file changed,
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Hi Linus,
Please pull some more powerpc fixes for 5.1:
The following changes since commit 6f845ebec2706841d15831fab3cfd9e676fa:
powerpc/pseries/mce: Fix misleading print for TLB mutlihit (2019-03-29
16:59:19 +1100)
are available in the git
Add ARM64 to the legend of architectures. It's already used in several
places in kernel-parameters.txt.
Suggested-by: Randy Dunlap
Signed-off-by: Josh Poimboeuf
---
Documentation/admin-guide/kernel-parameters.rst | 1 +
1 file changed, 1 insertion(+)
diff --git
Nayna writes:
> On 04/11/2019 10:47 AM, Daniel Axtens wrote:
>> Eric Biggers writes:
>>
>>> Are you still planning to fix the remaining bug? I booted a ppc64le VM,
>>> and I
>>> see the same test failure (I think) you were referring to:
>>>
>>> alg: skcipher: p8_aes_ctr encryption test failed
Nicholas Piggin writes:
> Michael Ellerman's on April 11, 2019 12:49 am:
>> On Fri, 2019-03-29 at 07:42:57 UTC, Nicholas Piggin wrote:
>>> Commit 48e7b76957 ("powerpc/64s/hash: Convert SLB miss handlers to C")
>>> broke the radix-mode segment exception handler. In radix mode, this is
>>>
On 4/12/19 9:04 AM, Jonathan Corbet wrote:
On Thu, 11 Apr 2019 14:07:31 -0700
Guenter Roeck wrote:
While nobody does such split, IMHO, the best would be to keep the
information outside Documentation/admin-guide. But hey! You're
the Doc maintainer. If you prefer to move, I'm perfectly fine
Hi Nicholas,
I love your patch! Yet something to improve:
[auto build test ERROR on powerpc/next]
[also build test ERROR on v5.1-rc4 next-20190412]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux
The new mprofile-kernel mcount sequence is
mflr r0
bl_mcount
Dynamic ftrace patches the branch instruction with a noop, but leaves
the mflr. mflr is executed by the branch unit that can only execute one
per cycle on POWER9 and shared with branches, so it would be nice to
avoid it where
On 4/12/19 5:25 PM, Mauro Carvalho Chehab wrote:
Em Fri, 12 Apr 2019 09:12:52 -0700
Guenter Roeck escreveu:
On 4/12/19 9:04 AM, Jonathan Corbet wrote:
On Thu, 11 Apr 2019 14:07:31 -0700
Guenter Roeck wrote:
While nobody does such split, IMHO, the best would be to keep the
information
Em Fri, 12 Apr 2019 09:12:52 -0700
Guenter Roeck escreveu:
> On 4/12/19 9:04 AM, Jonathan Corbet wrote:
> > On Thu, 11 Apr 2019 14:07:31 -0700
> > Guenter Roeck wrote:
> >
> >>> While nobody does such split, IMHO, the best would be to keep the
> >>> information outside
On 4/12/19 1:39 PM, Josh Poimboeuf wrote:
> Configure arm64 runtime CPU speculation bug mitigations in accordance
> with the 'mitigations=' cmdline option. This affects Meltdown, Spectre
> v2, and Speculative Store Bypass.
>
> The default behavior is unchanged.
>
> Signed-off-by: Josh Poimboeuf
Configure arm64 runtime CPU speculation bug mitigations in accordance
with the 'mitigations=' cmdline option. This affects Meltdown, Spectre
v2, and Speculative Store Bypass.
The default behavior is unchanged.
Signed-off-by: Josh Poimboeuf
---
NOTE: This is based on top of Jeremy Linton's
Configure s390 runtime CPU speculation bug mitigations in accordance
with the 'mitigations=' cmdline option. This affects Spectre v1 and
Spectre v2.
The default behavior is unchanged.
Signed-off-by: Josh Poimboeuf
---
Documentation/admin-guide/kernel-parameters.txt | 5 +++--
Configure powerpc CPU runtime speculation bug mitigations in accordance
with the 'mitigations=' cmdline option. This affects Meltdown, Spectre
v1, Spectre v2, and Speculative Store Bypass.
The default behavior is unchanged.
Signed-off-by: Josh Poimboeuf
---
Configure x86 runtime CPU speculation bug mitigations in accordance with
the 'mitigations=' cmdline option. This affects Meltdown, Spectre v2,
Speculative Store Bypass, and L1TF.
The default behavior is unchanged.
Signed-off-by: Josh Poimboeuf
---
Keeping track of the number of mitigations for all the CPU speculation
bugs has become overwhelming for many users. It's getting more and more
complicated to decide which mitigations are needed for a given
architecture. Complicating matters is the fact that each arch tends to
have its own custom
v2:
- docs improvements: [Randy, Michael]
- Rename to "mitigations=" [Michael]
- Add cpu_mitigations_off() function wrapper [Michael]
- x86: Simplify logic [Boris]
- powerpc: Fix no_rfi_flush checking bug (use '&&' instead of '||')
- arm64: Rebase onto Jeremy Linton's v7 patches [Will]
- arm64:
On Fri, Apr 12, 2019 at 07:56:02PM +0100, Robin Murphy wrote:
> ARCH_HAS_ZONE_DEVICE is somewhat meaningless in itself, and combined
> with the long-out-of-date comment can lead to the impression than an
> architecture may just enable it (since __add_pages() now "comprehends
> device memory" for
On Fri, Apr 12, 2019 at 12:02 PM Robin Murphy wrote:
>
> ARCH_HAS_ZONE_DEVICE is somewhat meaningless in itself, and combined
> with the long-out-of-date comment can lead to the impression than an
> architecture may just enable it (since __add_pages() now "comprehends
> device memory" for itself)
On Fri, Apr 12, 2019 at 11:57 AM Robin Murphy wrote:
>
> Trying to activatee ZONE_DEVICE for arm64 reveals that memremap's
s/activatee/activate/
> internal helpers for sparsemem sections conflict with and arm64's
> definitions for hugepages, which inherit the name of "sections" from
> earlier
ARCH_HAS_ZONE_DEVICE is somewhat meaningless in itself, and combined
with the long-out-of-date comment can lead to the impression than an
architecture may just enable it (since __add_pages() now "comprehends
device memory" for itself) and expect things to work.
In practice, however, ZONE_DEVICE
Refactor is_device_{public,private}_page() with is_pci_p2pdma_page()
to make them all consistent in depending on their respective config
options even when CONFIG_DEV_PAGEMAP_OPS is enabled for other reasons.
This allows a little more compile-time optimisation as well as the
conceptual and cosmetic
Trying to activatee ZONE_DEVICE for arm64 reveals that memremap's
internal helpers for sparsemem sections conflict with and arm64's
definitions for hugepages, which inherit the name of "sections" from
earlier versions of the ARM architecture.
Disambiguate memremap (and now HMM too) by propagating
Hi,
As promised, these are my preparatory cleanup patches that have so far
fallen out of pmem DAX work for arm64. Patch #1 has already been out for
a ride in Anshuman's hot-remove series, so I've collected the acks
already given.
Since we have various things in flight at the moment touching
On Thu, 2019-04-11 at 06:12 -0700, Paul E. McKenney wrote:
> If my email address were
> to change again, I would instead go with the "(IBM)" approach and let
> the git log and MAINTAINERS file keep the contact information. Not that
> we get to update the git log, of course. ;-)
Add entries to
On 4/12/19 9:04 AM, Jonathan Corbet wrote:
On Thu, 11 Apr 2019 14:07:31 -0700
Guenter Roeck wrote:
While nobody does such split, IMHO, the best would be to keep the
information outside Documentation/admin-guide. But hey! You're
the Doc maintainer. If you prefer to move, I'm perfectly fine
On Thu, 11 Apr 2019 14:07:31 -0700
Guenter Roeck wrote:
> > While nobody does such split, IMHO, the best would be to keep the
> > information outside Documentation/admin-guide. But hey! You're
> > the Doc maintainer. If you prefer to move, I'm perfectly fine
> > with that.
> >
>
> Same here,
This is the KVM update to the new idle code. A few improvements:
- Idle sleepers now always return to caller rather than branch out
to KVM first.
- This allows optimisations like very fast return to caller when no
state has been lost.
- KVM no longer requires nap_state_lost because it
Reimplement Book3S idle code in C, moving POWER7/8/9 implementation
speific HV idle code to the powernv platform code.
Book3S assembly stubs are kept in common code and used only to save
the stack frame and non-volatile GPRs before executing architected
idle instructions, and restoring the stack
On Fri, Apr 12, 2019 at 12:28:01PM +1000, Michael Ellerman wrote:
Sasha Levin writes:
On Thu, Apr 11, 2019 at 09:45:55PM +1000, Michael Ellerman wrote:
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Hi Greg,
Please queue up these powerpc patches for 4.9 if you have no objections.
There's
On 12/04/2019 11:26, John Garry wrote:
On 09/04/2019 13:53, Zhen Lei wrote:
Currently the IOMMU dma contains 3 modes: passthrough, lazy, strict. The
passthrough mode bypass the IOMMU, the lazy mode defer the invalidation
of hardware TLBs, and the strict mode invalidate IOMMU hardware TLBs
Satheesh Rajendran's on April 8, 2019 5:32 pm:
> Hi,
>
> Hit with below kernel crash during Power8 Host boot with this patch series on
> top
> of powerpc merge branch commit
>
On 09/04/2019 13:53, Zhen Lei wrote:
Currently the IOMMU dma contains 3 modes: passthrough, lazy, strict. The
passthrough mode bypass the IOMMU, the lazy mode defer the invalidation
of hardware TLBs, and the strict mode invalidate IOMMU hardware TLBs
synchronously. The three modes are mutually
On Tue, Apr 09, 2019 at 08:53:03PM +0800, Zhen Lei wrote:
> +static int __init iommu_dma_mode_setup(char *str)
> +{
> + if (!str)
> + goto fail;
> +
> + if (!strncmp(str, "passthrough", 11))
> + iommu_default_dma_mode = IOMMU_DMA_MODE_PASSTHROUGH;
> + else if
From: Laurentiu Tudor
Set SI in the default kernel's MSR so that the architected way of
detecting unrecoverable machine check interrupts has a chance to work.
This is inline with the MSR setup of the rest of booke powerpc
architectures configured here.
Signed-off-by: Laurentiu Tudor
Cc:
* Adhemerval Zanella:
> On 11/04/2019 08:07, Florian Weimer wrote:
>> * Adhemerval Zanella:
>>
>>> This allows us to adjust the baud rates to non-standard values using termios
>>> interfaces without to resorting to add new headers and use a different API
>>> (ioctl).
>>
>> How much symbol
I'm gonna try and benchmark this on a few different devices for performance,
with 64k TCEs (as is), with larger TCE sizes, and against sketchy bypass.
Hopefully if performance isn't too far off, we can get rid of sketchy bypass
entirely and have a more robust solution.
--
Russell Currey
At the moment we create a small window only for 32bit devices, the window
maps 0..2GB of the PCI space only. For other devices we either use
a sketchy bypass or hardware bypass but the former can only work if
the amount of RAM is no bigger than the device's DMA mask and the latter
requires devices
We allocate only the first level of multilevel TCE tables for KVM
already (alloc_userspace_copy==true), and the rest is allocated on demand.
This is not enabled though for baremetal.
This removes the KVM limitation (implicit, via the alloc_userspace_copy
parameter) and always allocates just the
This is an attempt to allow DMA mask 40 or similar which are not large
enough to use either a PHB3 bypass mode or a sketchy bypass.
This is based on sha1
582549e3fbe1 Linus Torvalds Merge tag 'for-linus' of
git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma
Please comment. Thanks.
Hello Nicholas,
On Tue, Apr 09, 2019 at 02:40:05PM +1000, Nicholas Piggin wrote:
> Using a jiffies timer creates a dependency on the tick_do_timer_cpu
> incrementing jiffies. If that CPU has locked up and jiffies is not
> incrementing, the watchdog heartbeat timer for all CPUs stops and
>
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