[PATCH V2 2/2] ASoC: fsl_esai: recover the channel swap after xrun
From: Shengjiu Wang
There is chip errata ERR008000, the reference doc is
(https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf),
The issue is "While using ESAI transmit or receive and
an underrun/overrun happens, channel swap may occur.
The only recovery mechanism is to reset the ESAI."
This issue exist in imx3/imx5/imx6(partial) series.
In this commit add a tasklet to handle reset of ESAI
after xrun happens to recover the channel swap.
Signed-off-by: Shengjiu Wang
---
sound/soc/fsl/fsl_esai.c | 76
1 file changed, 76 insertions(+)
diff --git a/sound/soc/fsl/fsl_esai.c b/sound/soc/fsl/fsl_esai.c
index 20039ae9893b..8c92e49ad6d8 100644
--- a/sound/soc/fsl/fsl_esai.c
+++ b/sound/soc/fsl/fsl_esai.c
@@ -32,6 +32,7 @@
* @extalclk: esai clock source to derive HCK, SCK and FS
* @fsysclk: system clock source to derive HCK, SCK and FS
* @spbaclk: SPBA clock (optional, depending on SoC design)
+ * @task: tasklet to handle the reset operation
* @fifo_depth: depth of tx/rx FIFO
* @slot_width: width of each DAI slot
* @slots: number of slots
@@ -42,6 +43,7 @@
* @sck_div: if using PSR/PM dividers for SCKx clock
* @slave_mode: if fully using DAI slave mode
* @synchronous: if using tx/rx synchronous mode
+ * @reset_at_xrun: flags for enable reset operaton
* @name: driver name
*/
struct fsl_esai {
@@ -53,6 +55,7 @@ struct fsl_esai {
struct clk *extalclk;
struct clk *fsysclk;
struct clk *spbaclk;
+ struct tasklet_struct task;
u32 fifo_depth;
u32 slot_width;
u32 slots;
@@ -65,6 +68,7 @@ struct fsl_esai {
bool sck_div[2];
bool slave_mode;
bool synchronous;
+ bool reset_at_xrun;
char name[32];
};
@@ -73,8 +77,16 @@ static irqreturn_t esai_isr(int irq, void *devid)
struct fsl_esai *esai_priv = (struct fsl_esai *)devid;
struct platform_device *pdev = esai_priv->pdev;
u32 esr;
+ u32 saisr;
regmap_read(esai_priv->regmap, REG_ESAI_ESR, &esr);
+ regmap_read(esai_priv->regmap, REG_ESAI_SAISR, &saisr);
+
+ if ((saisr & (ESAI_SAISR_TUE | ESAI_SAISR_ROE)) &&
+ esai_priv->reset_at_xrun) {
+ dev_dbg(&pdev->dev, "reset module for xrun\n");
+ tasklet_schedule(&esai_priv->task);
+ }
if (esr & ESAI_ESR_TINIT_MASK)
dev_dbg(&pdev->dev, "isr: Transmission Initialized\n");
@@ -634,10 +646,17 @@ static void fsl_esai_trigger_start(struct fsl_esai
*esai_priv, bool tx)
ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(mask));
regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx),
ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(mask));
+
+ /* Enable Exception interrupt */
+ regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
+ ESAI_xCR_xEIE_MASK, ESAI_xCR_xEIE);
}
static void fsl_esai_trigger_stop(struct fsl_esai *esai_priv, bool tx)
{
+ regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
+ ESAI_xCR_xEIE_MASK, 0);
+
regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, 0);
regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx),
@@ -652,6 +671,53 @@ static void fsl_esai_trigger_stop(struct fsl_esai
*esai_priv, bool tx)
ESAI_xFCR_xFR, 0);
}
+static void fsl_esai_reset(unsigned long arg)
+{
+ struct fsl_esai *esai_priv = (struct fsl_esai *)arg;
+ u32 saisr, tfcr, rfcr;
+
+ /* save the registers */
+ regmap_read(esai_priv->regmap, REG_ESAI_TFCR, &tfcr);
+ regmap_read(esai_priv->regmap, REG_ESAI_RFCR, &rfcr);
+
+ /* stop the tx & rx */
+ fsl_esai_trigger_stop(esai_priv, 1);
+ fsl_esai_trigger_stop(esai_priv, 0);
+
+ /* reset the esai, and restore the registers */
+ fsl_esai_init(esai_priv);
+
+ regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR,
+ ESAI_xCR_xPR_MASK,
+ ESAI_xCR_xPR);
+ regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR,
+ ESAI_xCR_xPR_MASK,
+ ESAI_xCR_xPR);
+
+ /* restore registers by regcache_sync */
+ fsl_esai_register_restore(esai_priv);
+
+ regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR,
+ ESAI_xCR_xPR_MASK, 0);
+ regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR,
+ ESAI_xCR_xPR_MASK, 0);
+
+ regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,
+ ESAI_PRRC_PDC_MASK,
+ ESAI_PRRC_PDC(ESAI_GPIO));
+ regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,
+ ESAI_PCRC_PC_MASK,
+ ESAI_PCRC_PC(ESAI_GPIO));
+
+ regmap_read(esai_priv->regmap, REG_ESAI_SAISR, &saisr);
+
+ /*
[PATCH V2 1/2] ASoC: fsl_esai: Wrap some operations to be functions
From: Shengjiu Wang
Extract the operation to be functions, to improve the
readability.
In this patch, fsl_esai_init, fsl_esai_register_restore,
fsl_esai_trigger_start and fsl_esai_trigger_stop are
extracted.
Signed-off-by: Shengjiu Wang
---
sound/soc/fsl/fsl_esai.c | 191 ---
1 file changed, 118 insertions(+), 73 deletions(-)
diff --git a/sound/soc/fsl/fsl_esai.c b/sound/soc/fsl/fsl_esai.c
index 10d2210c91ef..20039ae9893b 100644
--- a/sound/soc/fsl/fsl_esai.c
+++ b/sound/soc/fsl/fsl_esai.c
@@ -35,6 +35,7 @@
* @fifo_depth: depth of tx/rx FIFO
* @slot_width: width of each DAI slot
* @slots: number of slots
+ * @channels: channel num for tx or rx
* @hck_rate: clock rate of desired HCKx clock
* @sck_rate: clock rate of desired SCKx clock
* @hck_dir: the direction of HCKx pads
@@ -57,6 +58,7 @@ struct fsl_esai {
u32 slots;
u32 tx_mask;
u32 rx_mask;
+ u32 channels[2];
u32 hck_rate[2];
u32 sck_rate[2];
bool hck_dir[2];
@@ -543,64 +545,131 @@ static int fsl_esai_hw_params(struct snd_pcm_substream
*substream,
return 0;
}
-static int fsl_esai_trigger(struct snd_pcm_substream *substream, int cmd,
- struct snd_soc_dai *dai)
+static int fsl_esai_init(struct fsl_esai *esai_priv)
{
- struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
- bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
- u8 i, channels = substream->runtime->channels;
+ struct platform_device *pdev = esai_priv->pdev;
+ int ret;
+
+ /* Reset ESAI unit */
+ ret = regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,
+ESAI_ECR_ESAIEN_MASK | ESAI_ECR_ERST_MASK,
+ESAI_ECR_ESAIEN | ESAI_ECR_ERST);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to reset ESAI: %d\n", ret);
+ return ret;
+ }
+
+ /*
+* We need to enable ESAI so as to access some of its registers.
+* Otherwise, we would fail to dump regmap from user space.
+*/
+ ret = regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,
+ESAI_ECR_ESAIEN_MASK | ESAI_ECR_ERST_MASK,
+ESAI_ECR_ESAIEN);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to enable ESAI: %d\n", ret);
+ return ret;
+ }
+
+ regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,
+ ESAI_PRRC_PDC_MASK, 0);
+ regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,
+ ESAI_PCRC_PC_MASK, 0);
+
+ return 0;
+}
+
+static int fsl_esai_register_restore(struct fsl_esai *esai_priv)
+{
+ int ret;
+ /* FIFO reset for safety */
+ regmap_update_bits(esai_priv->regmap, REG_ESAI_TFCR,
+ ESAI_xFCR_xFR, ESAI_xFCR_xFR);
+ regmap_update_bits(esai_priv->regmap, REG_ESAI_RFCR,
+ ESAI_xFCR_xFR, ESAI_xFCR_xFR);
+
+ regcache_mark_dirty(esai_priv->regmap);
+ ret = regcache_sync(esai_priv->regmap);
+ if (ret)
+ return ret;
+
+ /* FIFO reset done */
+ regmap_update_bits(esai_priv->regmap, REG_ESAI_TFCR, ESAI_xFCR_xFR, 0);
+ regmap_update_bits(esai_priv->regmap, REG_ESAI_RFCR, ESAI_xFCR_xFR, 0);
+
+ return 0;
+}
+
+static void fsl_esai_trigger_start(struct fsl_esai *esai_priv, bool tx)
+{
+ u8 i, channels = esai_priv->channels[tx];
u32 pins = DIV_ROUND_UP(channels, esai_priv->slots);
u32 mask;
+ regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
+ ESAI_xFCR_xFEN_MASK, ESAI_xFCR_xFEN);
+
+ /* Write initial words reqiured by ESAI as normal procedure */
+ for (i = 0; tx && i < channels; i++)
+ regmap_write(esai_priv->regmap, REG_ESAI_ETDR, 0x0);
+
+ /*
+* When set the TE/RE in the end of enablement flow, there
+* will be channel swap issue for multi data line case.
+* In order to workaround this issue, we switch the bit
+* enablement sequence to below sequence
+* 1) clear the xSMB & xSMA: which is done in probe and
+* stop state.
+* 2) set TE/RE
+* 3) set xSMB
+* 4) set xSMA: xSMA is the last one in this flow, which
+* will trigger esai to start.
+*/
+ regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
+ tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK,
+ tx ? ESAI_xCR_TE(pins) : ESAI_xCR_RE(pins));
+ mask = tx ? esai_priv->tx_mask : esai_priv->rx_mask;
+
+ regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx),
+ ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(mask));
+ regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx),
+ ESAI_xSMA_x
[PATCH V2 0/2] recover the channel swap after xrun
From: Shengjiu Wang recover the channel swap after xrun Shengjiu Wang (2): ASoC: fsl_esai: Wrap some operations to be functions ASoC: fsl_esai: recover the channel swap after xrun sound/soc/fsl/fsl_esai.c | 267 --- 1 file changed, 194 insertions(+), 73 deletions(-) Changes in v2 - add one patch for wrap operations to functions. - fix some coding style issue -- 2.21.0
Re: [RFC PATCH v2 00/12] Reduce ifdef mess in ptrace
On 6/28/19 9:17 PM, Christophe Leroy wrote: > The purpose of this series is to reduce the amount of #ifdefs > in ptrace.c > > This is a first try. Most of it is done, there are still some #ifdefs that > could go away. > > Please comment and tell whether it is worth continuing in that direction. Hi Christopher, I'm seeing this warning with all the patches. WARNING: Improper SPDX comment style for 'arch/powerpc/kernel/ptrace/ptrace-view.c', please use '//' instead #100: FILE: arch/powerpc/kernel/ptrace/ptrace-view.c:1: +/* SPDX-License-Identifier: GPL-2.0-or-later */
Re: [PATCH] i2c: remove casting dma_alloc
From: Vasyl
Generated by: alloc_cast.cocci
Signed-off-by: Vasyl
Acked-by: Jochen Friedrich
---
drivers/i2c/busses/i2c-cpm.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/i2c/busses/i2c-cpm.c b/drivers/i2c/busses/i2c-cpm.c
index 187900594e3d..1213e1932ccb 100644
--- a/drivers/i2c/busses/i2c-cpm.c
+++ b/drivers/i2c/busses/i2c-cpm.c
@@ -531,7 +531,9 @@ static int cpm_i2c_setup(struct cpm_i2c *cpm)
}
out_be32(&rbdf[i].cbd_bufaddr, ((cpm->rxdma[i] + 1) & ~1));
- cpm->txbuf[i] = (unsigned char *)dma_alloc_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1, &cpm->txdma[i], GFP_KERNEL);
+ cpm->txbuf[i] = dma_alloc_coherent(&cpm->ofdev->dev,
+ CPM_MAX_READ + 1,
+ &cpm->txdma[i], GFP_KERNEL);
if (!cpm->txbuf[i]) {
ret = -ENOMEM;
goto out_muram;
Re: [PATCH] powerpc/hw_breakpoint: move instruction stepping out of hw_breakpoint_handler()
On 6/28/19 9:25 PM, Christophe Leroy wrote:
> On 8xx, breakpoints stop after executing the instruction, so
> stepping/emulation is not needed. Move it into a sub-function and
> remove the #ifdefs.
>
> Signed-off-by: Christophe Leroy
> ---
Reviewed-by: Ravi Bangoria
Just one neat below...
[...]
> -#ifndef CONFIG_PPC_8xx
> - /* Do not emulate user-space instructions, instead single-step them */
> - if (user_mode(regs)) {
> - current->thread.last_hit_ubp = bp;
> - regs->msr |= MSR_SE;
> + if (!IS_ENABLED(CONFIG_PPC_8xx) && !stepping_handler(regs, bp,
> info->address))
May be split this line. It's 86 chars long and checkpatch.pl is warning
about this:
WARNING: line over 80 characters
#257: FILE: arch/powerpc/kernel/hw_breakpoint.c:282:
+ if (!IS_ENABLED(CONFIG_PPC_8xx) && !stepping_handler(regs, bp,
info->address))
Re: [PATCH v3 03/16] pseries/fadump: move out platform specific support from generic code
On Wed, 2019-06-26 at 02:16 +0530, Hari Bathini wrote:
> Introduce callbacks for platform specific operations like register,
> unregister, invalidate & such, and move pseries specific code into
> platform code.
Please don't move around large blocks of code *and* change the code in
a single patch. It makes reviewing the changes extremely tedious since
the changes are mixed in with hundreds of lines of nothing.
> Signed-off-by: Hari Bathini
> ---
> arch/powerpc/include/asm/fadump.h| 75
> arch/powerpc/kernel/fadump-common.h | 38 ++
> arch/powerpc/kernel/fadump.c | 500 ++---
> arch/powerpc/platforms/pseries/Makefile |1
> arch/powerpc/platforms/pseries/rtas-fadump.c | 529
> ++
> arch/powerpc/platforms/pseries/rtas-fadump.h | 96 +
> 6 files changed, 700 insertions(+), 539 deletions(-)
> create mode 100644 arch/powerpc/platforms/pseries/rtas-fadump.c
> create mode 100644 arch/powerpc/platforms/pseries/rtas-fadump.h
>
> +static struct fadump_ops pseries_fadump_ops = {
> + .init_fadump_mem_struct = pseries_init_fadump_mem_struct,
> + .register_fadump= pseries_register_fadump,
I realise you are just translating the existing interface, but why is
init_fadump_mem_struct() done as a seperate step and not as a part of
the registration function? The struct doesn't seem to be necessary
until the actual registration happens.
> + .unregister_fadump = pseries_unregister_fadump,
> + .invalidate_fadump = pseries_invalidate_fadump,
> + .process_fadump = pseries_process_fadump,
> + .fadump_region_show = pseries_fadump_region_show,
> + .crash_fadump = pseries_crash_fadump,
Rename this to fadump_trigger or something, it's not clear what it
does.
Re: [PATCH v3 01/16] powerpc/fadump: move internal fadump code to a new file
On Wed, 2019-06-26 at 02:15 +0530, Hari Bathini wrote: > Refactoring fadump code means internal fadump code is referenced from > different places. For ease, move internal code to a new file. Can you elaborate a bit? I don't really get what the difference between fadump and fadump-internal code is supposed to be. Why can't all this just live in fadump.c?
Re: [RFC PATCH v2 11/12] powerpc/ptrace: create ppc_gethwdinfo()
On 6/28/19 9:18 PM, Christophe Leroy wrote: > Create ippc_gethwdinfo() to handle PPC_PTRACE_GETHWDBGINFO and > reduce ifdef mess > > Signed-off-by: Christophe Leroy > --- Reviewed-by: Ravi Bangoria
Re: [RFC PATCH v2 12/12] powerpc/ptrace: move ptrace_triggered() into hw_breakpoint.c
On 6/28/19 9:18 PM, Christophe Leroy wrote: > ptrace_triggered() is declared in asm/hw_breakpoint.h and > only needed when CONFIG_HW_BREAKPOINT is set, so move it > into hw_breakpoint.c > > Signed-off-by: Christophe Leroy Reviewed-by: Ravi Bangoria
Re: [RFC PATCH v2 10/12] powerpc/ptrace: create ptrace_get_debugreg()
On 6/28/19 9:17 PM, Christophe Leroy wrote:
> Create ptrace_get_debugreg() to handle PTRACE_GET_DEBUGREG and
> reduce ifdef mess
>
> Signed-off-by: Christophe Leroy
> ---
> arch/powerpc/kernel/ptrace/ptrace-adv.c | 9 +
> arch/powerpc/kernel/ptrace/ptrace-decl.h | 2 ++
> arch/powerpc/kernel/ptrace/ptrace-noadv.c | 13 +
> arch/powerpc/kernel/ptrace/ptrace.c | 18 ++
> 4 files changed, 26 insertions(+), 16 deletions(-)
>
> diff --git a/arch/powerpc/kernel/ptrace/ptrace-adv.c
> b/arch/powerpc/kernel/ptrace/ptrace-adv.c
> index 86e71fa6c5c8..dcc765940344 100644
> --- a/arch/powerpc/kernel/ptrace/ptrace-adv.c
> +++ b/arch/powerpc/kernel/ptrace/ptrace-adv.c
> @@ -83,6 +83,15 @@ void user_disable_single_step(struct task_struct *task)
> clear_tsk_thread_flag(task, TIF_SINGLESTEP);
> }
>
> +int ptrace_get_debugreg(struct task_struct *child, unsigned long addr,
> + unsigned long __user *datalp)
> +{
> + /* We only support one DABR and no IABRS at the moment */
No DABR / IABR in ptrace-adv.c
> + if (addr > 0)
> + return -EINVAL;
> + return put_user(child->thread.debug.dac1, datalp);
> +}
> +
> int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
> unsigned long data)
> {
> /* For ppc64 we support one DABR and no IABR's at the moment (ppc64).
> diff --git a/arch/powerpc/kernel/ptrace/ptrace-decl.h
> b/arch/powerpc/kernel/ptrace/ptrace-decl.h
> index bdba09a87aea..4b4b6a1d508a 100644
> --- a/arch/powerpc/kernel/ptrace/ptrace-decl.h
> +++ b/arch/powerpc/kernel/ptrace/ptrace-decl.h
> @@ -176,6 +176,8 @@ int tm_cgpr32_set(struct task_struct *target, const
> struct user_regset *regset,
> extern const struct user_regset_view user_ppc_native_view;
>
> /* ptrace-(no)adv */
> +int ptrace_get_debugreg(struct task_struct *child, unsigned long addr,
> + unsigned long __user *datalp);
> int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
> unsigned long data);
> long ppc_set_hwdebug(struct task_struct *child, struct ppc_hw_breakpoint
> *bp_info);
> long ppc_del_hwdebug(struct task_struct *child, long data);
> diff --git a/arch/powerpc/kernel/ptrace/ptrace-noadv.c
> b/arch/powerpc/kernel/ptrace/ptrace-noadv.c
> index 7db330c94538..985cca136f85 100644
> --- a/arch/powerpc/kernel/ptrace/ptrace-noadv.c
> +++ b/arch/powerpc/kernel/ptrace/ptrace-noadv.c
> @@ -64,6 +64,19 @@ void user_disable_single_step(struct task_struct *task)
> clear_tsk_thread_flag(task, TIF_SINGLESTEP);
> }
>
> +int ptrace_get_debugreg(struct task_struct *child, unsigned long addr,
> + unsigned long __user *datalp)
> +{
> + unsigned long dabr_fake;
> +
> + /* We only support one DABR and no IABRS at the moment */
> + if (addr > 0)
> + return -EINVAL;
> + dabr_fake = ((child->thread.hw_brk.address & (~HW_BRK_TYPE_DABR)) |
> + (child->thread.hw_brk.type & HW_BRK_TYPE_DABR));
> + return put_user(dabr_fake, datalp);
> +}
> +
> int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
> unsigned long data)
> {
> #ifdef CONFIG_HAVE_HW_BREAKPOINT
> diff --git a/arch/powerpc/kernel/ptrace/ptrace.c
> b/arch/powerpc/kernel/ptrace/ptrace.c
> index 377e0e541d5f..e789afae6f56 100644
> --- a/arch/powerpc/kernel/ptrace/ptrace.c
> +++ b/arch/powerpc/kernel/ptrace/ptrace.c
> @@ -211,23 +211,9 @@ long arch_ptrace(struct task_struct *child, long request,
> break;
> }
>
> - case PTRACE_GET_DEBUGREG: {
> -#ifndef CONFIG_PPC_ADV_DEBUG_REGS
> - unsigned long dabr_fake;
> -#endif
> - ret = -EINVAL;
> - /* We only support one DABR and no IABRS at the moment */
> - if (addr > 0)
> - break;
> -#ifdef CONFIG_PPC_ADV_DEBUG_REGS
> - ret = put_user(child->thread.debug.dac1, datalp);
> -#else
> - dabr_fake = ((child->thread.hw_brk.address &
> (~HW_BRK_TYPE_DABR)) |
> - (child->thread.hw_brk.type & HW_BRK_TYPE_DABR));
> - ret = put_user(dabr_fake, datalp);
> -#endif
> + case PTRACE_GET_DEBUGREG:
> + ret = ptrace_get_debugreg(child, addr, datalp);
> break;
> - }
>
> case PTRACE_SET_DEBUGREG:
> ret = ptrace_set_debugreg(child, addr, data);
>
Otherwise,
Reviewed-by: Ravi Bangoria
Re: [RFC PATCH v2 09/12] powerpc/ptrace: split out ADV_DEBUG_REGS related functions.
On 6/28/19 9:17 PM, Christophe Leroy wrote:
> diff --git a/arch/powerpc/kernel/ptrace/ptrace-adv.c
> b/arch/powerpc/kernel/ptrace/ptrace-adv.c
> new file mode 100644
> index ..86e71fa6c5c8
> --- /dev/null
> +++ b/arch/powerpc/kernel/ptrace/ptrace-adv.c
> @@ -0,0 +1,487 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include
> +
> +void user_enable_single_step(struct task_struct *task)
> +{
> + struct pt_regs *regs = task->thread.regs;
> +
> + if (regs != NULL) {
> + task->thread.debug.dbcr0 &= ~DBCR0_BT;
> + task->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC;
> + regs->msr |= MSR_DE;
> + }
> + set_tsk_thread_flag(task, TIF_SINGLESTEP);
> +}
> +
> +void user_enable_block_step(struct task_struct *task)
> +{
> + struct pt_regs *regs = task->thread.regs;
> +
> + if (regs != NULL) {
> + task->thread.debug.dbcr0 &= ~DBCR0_IC;
> + task->thread.debug.dbcr0 = DBCR0_IDM | DBCR0_BT;
> + regs->msr |= MSR_DE;
> + }
> + set_tsk_thread_flag(task, TIF_SINGLESTEP);
> +}
> +
> +void user_disable_single_step(struct task_struct *task)
> +{
> + struct pt_regs *regs = task->thread.regs;
> +
> + if (regs != NULL) {
> + /*
> + * The logic to disable single stepping should be as
> + * simple as turning off the Instruction Complete flag.
> + * And, after doing so, if all debug flags are off, turn
> + * off DBCR0(IDM) and MSR(DE) Torez
> + */
> + task->thread.debug.dbcr0 &= ~(DBCR0_IC|DBCR0_BT);
> + /*
> + * Test to see if any of the DBCR_ACTIVE_EVENTS bits are set.
> + */
> + if (!DBCR_ACTIVE_EVENTS(task->thread.debug.dbcr0,
> + task->thread.debug.dbcr1)) {
> + /*
> + * All debug events were off.
> + */
> + task->thread.debug.dbcr0 &= ~DBCR0_IDM;
> + regs->msr &= ~MSR_DE;
> + }
> + }
> + clear_tsk_thread_flag(task, TIF_SINGLESTEP);
> +}
> +
> +int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
> unsigned long data)
> +{
> + /* For ppc64 we support one DABR and no IABR's at the moment (ppc64).
> + * For embedded processors we support one DAC and no IAC's at the
> + * moment.
> + */
I guess mentioning DABR and IABR doesn't make sense in ptrace-adv.c?
> + if (addr > 0)
> + return -EINVAL;
> +
> + /* The bottom 3 bits in dabr are flags */
Same here.
> + if ((data & ~0x7UL) >= TASK_SIZE)
> + return -EIO;
> +
> + /* As described above, it was assumed 3 bits were passed with the data
> + * address, but we will assume only the mode bits will be passed
> + * as to not cause alignment restrictions for DAC-based processors.
> + */
> +
> + /* DAC's hold the whole address without any mode flags */
> + task->thread.debug.dac1 = data & ~0x3UL;
> +
> + if (task->thread.debug.dac1 == 0) {
> + dbcr_dac(task) &= ~(DBCR_DAC1R | DBCR_DAC1W);
> + if (!DBCR_ACTIVE_EVENTS(task->thread.debug.dbcr0,
> + task->thread.debug.dbcr1)) {
> + task->thread.regs->msr &= ~MSR_DE;
> + task->thread.debug.dbcr0 &= ~DBCR0_IDM;
> + }
> + return 0;
> + }
> +
> + /* Read or Write bits must be set */
> +
> + if (!(data & 0x3UL))
> + return -EINVAL;
> +
> + /* Set the Internal Debugging flag (IDM bit 1) for the DBCR0
> +register */
> + task->thread.debug.dbcr0 |= DBCR0_IDM;
> +
> + /* Check for write and read flags and set DBCR0
> +accordingly */
> + dbcr_dac(task) &= ~(DBCR_DAC1R|DBCR_DAC1W);
> + if (data & 0x1UL)
> + dbcr_dac(task) |= DBCR_DAC1R;
> + if (data & 0x2UL)
> + dbcr_dac(task) |= DBCR_DAC1W;
> + task->thread.regs->msr |= MSR_DE;
> + return 0;
> +}
> +
> +static long set_instruction_bp(struct task_struct *child,
> + struct ppc_hw_breakpoint *bp_info)
> +{
> + int slot;
> + int slot1_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC1) != 0);
> + int slot2_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC2) != 0);
> + int slot3_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC3) != 0);
> + int slot4_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC4) != 0);
> +
> + if (dbcr_iac_range(child)
[PATCH AUTOSEL 5.1 09/39] selftests/powerpc: Add test of fork with mapping above 512TB
From: Michael Ellerman
[ Upstream commit 16391bfc862342f285195013b73c1394fab28b97 ]
This tests that when a process with a mapping above 512TB forks we
correctly separate the parent and child address spaces. This exercises
the bug in the context id handling fixed in the previous commit.
Signed-off-by: Michael Ellerman
Signed-off-by: Sasha Levin
---
tools/testing/selftests/powerpc/mm/.gitignore | 3 +-
tools/testing/selftests/powerpc/mm/Makefile | 4 +-
.../powerpc/mm/large_vm_fork_separation.c | 87 +++
3 files changed, 92 insertions(+), 2 deletions(-)
create mode 100644
tools/testing/selftests/powerpc/mm/large_vm_fork_separation.c
diff --git a/tools/testing/selftests/powerpc/mm/.gitignore
b/tools/testing/selftests/powerpc/mm/.gitignore
index ba919308fe30..d503b8764a8e 100644
--- a/tools/testing/selftests/powerpc/mm/.gitignore
+++ b/tools/testing/selftests/powerpc/mm/.gitignore
@@ -3,4 +3,5 @@ subpage_prot
tempfile
prot_sao
segv_errors
-wild_bctr
\ No newline at end of file
+wild_bctr
+large_vm_fork_separation
\ No newline at end of file
diff --git a/tools/testing/selftests/powerpc/mm/Makefile
b/tools/testing/selftests/powerpc/mm/Makefile
index 43d68420e363..f1fbc15800c4 100644
--- a/tools/testing/selftests/powerpc/mm/Makefile
+++ b/tools/testing/selftests/powerpc/mm/Makefile
@@ -2,7 +2,8 @@
noarg:
$(MAKE) -C ../
-TEST_GEN_PROGS := hugetlb_vs_thp_test subpage_prot prot_sao segv_errors
wild_bctr
+TEST_GEN_PROGS := hugetlb_vs_thp_test subpage_prot prot_sao segv_errors
wild_bctr \
+ large_vm_fork_separation
TEST_GEN_FILES := tempfile
top_srcdir = ../../../../..
@@ -13,6 +14,7 @@ $(TEST_GEN_PROGS): ../harness.c
$(OUTPUT)/prot_sao: ../utils.c
$(OUTPUT)/wild_bctr: CFLAGS += -m64
+$(OUTPUT)/large_vm_fork_separation: CFLAGS += -m64
$(OUTPUT)/tempfile:
dd if=/dev/zero of=$@ bs=64k count=1
diff --git a/tools/testing/selftests/powerpc/mm/large_vm_fork_separation.c
b/tools/testing/selftests/powerpc/mm/large_vm_fork_separation.c
new file mode 100644
index ..2363a7f3ab0d
--- /dev/null
+++ b/tools/testing/selftests/powerpc/mm/large_vm_fork_separation.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright 2019, Michael Ellerman, IBM Corp.
+//
+// Test that allocating memory beyond the memory limit and then forking is
+// handled correctly, ie. the child is able to access the mappings beyond the
+// memory limit and the child's writes are not visible to the parent.
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "utils.h"
+
+
+#ifndef MAP_FIXED_NOREPLACE
+#define MAP_FIXED_NOREPLACEMAP_FIXED // "Should be safe" above 512TB
+#endif
+
+
+static int test(void)
+{
+ int p2c[2], c2p[2], rc, status, c, *p;
+ unsigned long page_size;
+ pid_t pid;
+
+ page_size = sysconf(_SC_PAGESIZE);
+ SKIP_IF(page_size != 65536);
+
+ // Create a mapping at 512TB to allocate an extended_id
+ p = mmap((void *)(512ul << 40), page_size, PROT_READ | PROT_WRITE,
+ MAP_PRIVATE | MAP_ANONYMOUS | MAP_FIXED_NOREPLACE, -1, 0);
+ if (p == MAP_FAILED) {
+ perror("mmap");
+ printf("Error: couldn't mmap(), confirm kernel has 4TB
support?\n");
+ return 1;
+ }
+
+ printf("parent writing %p = 1\n", p);
+ *p = 1;
+
+ FAIL_IF(pipe(p2c) == -1 || pipe(c2p) == -1);
+
+ pid = fork();
+ if (pid == 0) {
+ FAIL_IF(read(p2c[0], &c, 1) != 1);
+
+ pid = getpid();
+ printf("child writing %p = %d\n", p, pid);
+ *p = pid;
+
+ FAIL_IF(write(c2p[1], &c, 1) != 1);
+ FAIL_IF(read(p2c[0], &c, 1) != 1);
+ exit(0);
+ }
+
+ c = 0;
+ FAIL_IF(write(p2c[1], &c, 1) != 1);
+ FAIL_IF(read(c2p[0], &c, 1) != 1);
+
+ // Prevent compiler optimisation
+ barrier();
+
+ rc = 0;
+ printf("parent reading %p = %d\n", p, *p);
+ if (*p != 1) {
+ printf("Error: BUG! parent saw child's write! *p = %d\n", *p);
+ rc = 1;
+ }
+
+ FAIL_IF(write(p2c[1], &c, 1) != 1);
+ FAIL_IF(waitpid(pid, &status, 0) == -1);
+ FAIL_IF(!WIFEXITED(status) || WEXITSTATUS(status));
+
+ if (rc == 0)
+ printf("success: test completed OK\n");
+
+ return rc;
+}
+
+int main(void)
+{
+ return test_harness(test, "large_vm_fork_separation");
+}
--
2.20.1
Re: [PATCH v2] powerpc/mm/nvdimm: Add an informative message if we fail to allocate altmap block
On Tue, Jul 2, 2019 at 12:33 AM Aneesh Kumar K.V
wrote:
>
> Allocation from altmap area can fail based on vmemmap page size used. Add
> kernel
> info message to indicate the failure. That allows the user to identify
> whether they
> are really using persistent memory reserved space for per-page metadata.
>
> The message looks like:
> [ 136.587212] altmap block allocation failed, falling back to system memory
>
> Signed-off-by: Aneesh Kumar K.V
> ---
> arch/powerpc/mm/init_64.c | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/arch/powerpc/mm/init_64.c b/arch/powerpc/mm/init_64.c
> index a4e17a979e45..f3b64f49082b 100644
> --- a/arch/powerpc/mm/init_64.c
> +++ b/arch/powerpc/mm/init_64.c
> @@ -194,8 +194,12 @@ int __meminit vmemmap_populate(unsigned long start,
> unsigned long end, int node,
> * fail due to alignment issues when using 16MB hugepages, so
> * fall back to system memory if the altmap allocation fail.
> */
> - if (altmap)
> + if (altmap) {
> p = altmap_alloc_block_buf(page_size, altmap);
> + if (!p)
> + pr_debug("altmap block allocation failed, " \
> + "falling back to system memory");
> + }
> if (!p)
> p = vmemmap_alloc_block_buf(page_size, node);
> if (!p)
> --
> 2.21.0
>
I'll let mpe decide if he cares about the split line thing :)
Reviewed-by: Oliver O'Halloran
[PATCH 3/3] KVM: PPC: Book3S HV: Save and restore guest visible PSSCR bits on pseries
The performance stop status and control register (PSSCR) is used to
control the power saving facilities of the processor. This register has
various fields, some of which can be modified only in hypervisor state,
and others which can be modified in both hypervisor and priviledged
non-hypervisor state. The bits which can be modified in priviledged
non-hypervisor state are referred to as guest visible.
Currently the L0 hypervisor saves and restores both it's own host value
as well as the guest value of the psscr when context switching between
the hypervisor and guest. However a nested hypervisor running it's own
nested guests (as indicated by kvmhv_on_pseries()) doesn't context
switch the psscr register. This means that if a nested (L2) guest
modified the psscr that the L1 guest hypervisor will run with this
value, and if the L1 guest hypervisor modified this value and then goes
to run the nested (L2) guest again that the L2 psscr value will be lost.
Fix this by having the (L1) nested hypervisor save and restore both its
host and the guest psscr value when entering and exiting a nested (L2)
guest. Note that only the guest visible parts of the psscr are context
switched since this is all the L1 nested hypervisor can access, this is
fine however as these are the only fields the L0 hypervisor provides
guest control of anyway and so all other fields are ignored.
This could also have been implemented by adding the psscr register to
the hv_regs passed to the L0 hypervisor as input to the H_ENTER_NESTED
hcall, however this would have meant updating the structure layout and
thus required modifications to both the L0 and L1 kernels. Whereas the
approach used doesn't require L0 kernel modifications while achieving
the same result.
Fixes: 95a6432ce903 "KVM: PPC: Book3S HV: Streamlined guest entry/exit path on
P9 for radix guests"
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/kvm/book3s_hv.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index b682a429f3ef..cde3f5a4b3e4 100644
--- a/arch/powerpc/kvm/book3s_hv.c
+++ b/arch/powerpc/kvm/book3s_hv.c
@@ -3569,9 +3569,18 @@ int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64
time_limit,
mtspr(SPRN_DEC, vcpu->arch.dec_expires - mftb());
if (kvmhv_on_pseries()) {
+ /*
+* We need to save and restore the guest visible part of the
+* psscr (i.e. using SPRN_PSSCR_PR) since the hypervisor
+* doesn't do this for us. Note only required if pseries since
+* this is done in kvmhv_load_hv_regs_and_go() below otherwise.
+*/
+ unsigned long host_psscr;
/* call our hypervisor to load up HV regs and go */
struct hv_guest_state hvregs;
+ host_psscr = mfspr(SPRN_PSSCR_PR);
+ mtspr(SPRN_PSSCR_PR, vcpu->arch.psscr);
kvmhv_save_hv_regs(vcpu, &hvregs);
hvregs.lpcr = lpcr;
vcpu->arch.regs.msr = vcpu->arch.shregs.msr;
@@ -3590,6 +3599,8 @@ int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64
time_limit,
vcpu->arch.shregs.msr = vcpu->arch.regs.msr;
vcpu->arch.shregs.dar = mfspr(SPRN_DAR);
vcpu->arch.shregs.dsisr = mfspr(SPRN_DSISR);
+ vcpu->arch.psscr = mfspr(SPRN_PSSCR_PR);
+ mtspr(SPRN_PSSCR_PR, host_psscr);
/* H_CEDE has to be handled now, not later */
if (trap == BOOK3S_INTERRUPT_SYSCALL && !vcpu->arch.nested &&
--
2.13.6
[PATCH 2/3] PPC: PMC: Set pmcregs_in_use in paca when running as LPAR
The ability to run nested guests under KVM means that a guest can also
act as a hypervisor for it's own nested guest. Currently
ppc_set_pmu_inuse() assumes that either FW_FEATURE_LPAR is set,
indicating a guest environment, and so sets the pmcregs_in_use flag in
the lppaca, or that it isn't set, indicating a hypervisor environment,
and so sets the pmcregs_in_use flag in the paca.
The pmcregs_in_use flag in the lppaca is used to communicate this
information to a hypervisor and so must be set in a guest environment.
The pmcregs_in_use flag in the paca is used by KVM code to determine
whether the host state of the performance monitoring unit (PMU) must be
saved and restored when running a guest.
Thus when a guest also acts as a hypervisor it must set this bit in both
places since it needs to ensure both that the real hypervisor saves it's
pmu registers when it runs (requires pmcregs_in_use flag in lppaca), and
that it saves it's own pmu registers when running a nested guest
(requires pmcregs_in_use flag in paca).
Modify ppc_set_pmu_inuse() so that the pmcregs_in_use bit is set in both
the lppaca and the paca when a guest (LPAR) is running with the
capability of running it's own guests (CONFIG_KVM_BOOK3S_HV_POSSIBLE).
Fixes: 95a6432ce903 "KVM: PPC: Book3S HV: Streamlined guest entry/exit path on
P9 for radix guests"
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/include/asm/pmc.h | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/include/asm/pmc.h b/arch/powerpc/include/asm/pmc.h
index dc9a1ca70edf..c6bbe9778d3c 100644
--- a/arch/powerpc/include/asm/pmc.h
+++ b/arch/powerpc/include/asm/pmc.h
@@ -27,11 +27,10 @@ static inline void ppc_set_pmu_inuse(int inuse)
#ifdef CONFIG_PPC_PSERIES
get_lppaca()->pmcregs_in_use = inuse;
#endif
- } else {
+ }
#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
- get_paca()->pmcregs_in_use = inuse;
+ get_paca()->pmcregs_in_use = inuse;
#endif
- }
#endif
}
--
2.13.6
[PATCH 1/3] KVM: PPC: Book3S HV: Always save guest pmu for guest capable of nesting
The performance monitoring unit (PMU) registers are saved on guest exit when the guest has set the pmcregs_in_use flag in its lppaca, if it exists, or unconditionally if it doesn't. If a nested guest is being run then the hypervisor doesn't, and in most cases can't, know if the pmu registers are in use since it doesn't know the location of the lppaca for the nested guest, although it may have one for its immediate guest. This results in the values of these registers being lost across nested guest entry and exit in the case where the nested guest was making use of the performance monitoring facility while it's nested guest hypervisor wasn't. Further more the hypervisor could interrupt a guest hypervisor between when it has loaded up the pmu registers and it calling H_ENTER_NESTED or between returning from the nested guest to the guest hypervisor and the guest hypervisor reading the pmu registers, in kvmhv_p9_guest_entry(). This means that it isn't sufficient to just save the pmu registers when entering or exiting a nested guest, but that it is necessary to always save the pmu registers whenever a guest is capable of running nested guests to ensure the register values aren't lost in the context switch. Ensure the pmu register values are preserved by always saving their value into the vcpu struct when a guest is capable of running nested guests. This should have minimal performance impact however any impact can be avoided by booting a guest with "-machine pseries,cap-nested-hv=false" on the qemu commandline. Fixes: 95a6432ce903 "KVM: PPC: Book3S HV: Streamlined guest entry/exit path on P9 for radix guests" Signed-off-by: Suraj Jitindar Singh --- arch/powerpc/kvm/book3s_hv.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c index ec1804f822af..b682a429f3ef 100644 --- a/arch/powerpc/kvm/book3s_hv.c +++ b/arch/powerpc/kvm/book3s_hv.c @@ -3654,6 +3654,8 @@ int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit, vcpu->arch.vpa.dirty = 1; save_pmu = lp->pmcregs_in_use; } + /* Must save pmu if this guest is capable of running nested guests */ + save_pmu |= nesting_enabled(vcpu->kvm); kvmhv_save_guest_pmu(vcpu, save_pmu); -- 2.13.6
Re: [PATCH] powerpc/powernv/idle: Fix restore of SPRN_LDBAR for POWER9 stop state.
Madhavan Srinivasan's on July 2, 2019 8:58 pm:
> From: Athira Rajeev
>
> commit 10d91611f426 ("powerpc/64s: Reimplement book3s idle code in C")
> reimplemented book3S code to pltform/powernv/idle.c. But when doing so
> missed to add the per-thread LDBAR update in the core_woken path of
> the power9_idle_stop(). Patch fixes the same.
>
> Fixes: 10d91611f426 ("powerpc/64s: Reimplement book3s idle code in C")
> Signed-off-by: Athira Rajeev
> Signed-off-by: Madhavan Srinivasan
> ---
> arch/powerpc/platforms/powernv/idle.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/powerpc/platforms/powernv/idle.c
> b/arch/powerpc/platforms/powernv/idle.c
> index 2f4479b94ac3..fd14a6237954 100644
> --- a/arch/powerpc/platforms/powernv/idle.c
> +++ b/arch/powerpc/platforms/powernv/idle.c
> @@ -758,7 +758,6 @@ static unsigned long power9_idle_stop(unsigned long
> psscr, bool mmu_on)
> mtspr(SPRN_PTCR,sprs.ptcr);
> mtspr(SPRN_RPR, sprs.rpr);
> mtspr(SPRN_TSCR,sprs.tscr);
> - mtspr(SPRN_LDBAR, sprs.ldbar);
>
> if (pls >= pnv_first_tb_loss_level) {
> /* TB loss */
> @@ -790,6 +789,7 @@ static unsigned long power9_idle_stop(unsigned long
> psscr, bool mmu_on)
> mtspr(SPRN_MMCR0, sprs.mmcr0);
> mtspr(SPRN_MMCR1, sprs.mmcr1);
> mtspr(SPRN_MMCR2, sprs.mmcr2);
> + mtspr(SPRN_LDBAR, sprs.ldbar);
Oh that's another one I messed up, thanks for the fix. I must have
confused myself with the SPR table in the UM :(
Reviewed-by: Nicholas Piggin
Re: [PATCH V2] mm/ioremap: Probe platform for p4d huge map support
On Fri, 28 Jun 2019 10:50:31 +0530 Anshuman Khandual
wrote:
> Finishing up what the commit c2febafc67734a ("mm: convert generic code to
> 5-level paging") started out while levelling up P4D huge mapping support
> at par with PUD and PMD. A new arch call back arch_ioremap_p4d_supported()
> is being added which just maintains status quo (P4D huge map not supported)
> on x86, arm64 and powerpc.
Does this have any runtime effects? If so, what are they and why? If
not, what's the actual point?
Re: [PATCH net] net/ibmvnic: Report last valid speed and duplex values to ethtool
From: Thomas Falcon Date: Thu, 27 Jun 2019 12:09:13 -0500 > This patch resolves an issue with sensitive bonding modes > that require valid speed and duplex settings to function > properly. Currently, the adapter will report that device > speed and duplex is unknown if the communication link > with firmware is unavailable. This decision can break LACP > configurations if the timing is right. > > For example, if invalid speeds are reported, the slave > device's link state is set to a transitional "fail" state > and the LACP port is disabled. However, if valid speeds > are reported later but the link state has not been altered, > the LACP port will remain disabled. If the link state then > transitions back to "up" from "fail," it results in a state > such that the slave reports valid speed/duplex and is up, > but the LACP port will remain disabled. > > Workaround this by reporting the last recorded speed > and duplex settings unless the device has never been > activated. In that case or when the hypervisor gives > invalid values, continue to report unknown speed or > duplex to ethtool. > > Signed-off-by: Thomas Falcon Like Andrew, I have my conerns about this. If the firmware is unavailable, the link is effectively down. So you should report link down and unknown link parameters. Bonding and LACP should do the right thing when the firwmare is reachable again after the migration and the link goes back up. If bonding/LACP isn't doing that, then the bug is there.
Re: [RFC PATCH] Replaces long number representation by BIT() macro
On Tue, Jul 02, 2019 at 11:16:35AM -0500, Segher Boessenkool wrote: > On Wed, Jul 03, 2019 at 01:19:34AM +1000, Michael Ellerman wrote: > > What we could do is switch to the `UL` macro from include/linux/const.h, > > rather than using our own ASM_CONST. > > You need gas 2.28 or later for that though. Oh, but apparently I cannot read. That macro should work fine. Segher
Re: [RFC PATCH] Replaces long number representation by BIT() macro
On Wed, Jul 03, 2019 at 01:19:34AM +1000, Michael Ellerman wrote: > What we could do is switch to the `UL` macro from include/linux/const.h, > rather than using our own ASM_CONST. You need gas 2.28 or later for that though. https://sourceware.org/git/?p=binutils-gdb.git;a=commitdiff;h=86b80085 https://sourceware.org/git/?p=binutils-gdb.git;a=commitdiff;h=e140100a What is the minimum required (for powerpc) now? Segher
Re: ["RFC PATCH" 1/2] powerpc/mm: Fix node look up with numa=off boot
"Aneesh Kumar K.V" writes: >> Just checking: do people still need numa=off? Seems like it's a >> maintenance burden :-) >> > > That is used in kdump kernel. I see, thanks.
[PATCH] powerpc: Enable CONFIG_IPV6 in ppc64_defconfig
From: Satheesh Rajendran Enable CONFIG_IPV6 in ppc64_defconfig to enable certain network functionalities required for tests. Signed-off-by: Michael Ellerman Signed-off-by: Satheesh Rajendran --- arch/powerpc/configs/ppc64_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/configs/ppc64_defconfig b/arch/powerpc/configs/ppc64_defconfig index 91fdb619b484..93fd9792d030 100644 --- a/arch/powerpc/configs/ppc64_defconfig +++ b/arch/powerpc/configs/ppc64_defconfig @@ -89,7 +89,7 @@ CONFIG_SYN_COOKIES=y CONFIG_INET_AH=m CONFIG_INET_ESP=m CONFIG_INET_IPCOMP=m -# CONFIG_IPV6 is not set +CONFIG_IPV6=y CONFIG_NETFILTER=y # CONFIG_NETFILTER_ADVANCED is not set CONFIG_BRIDGE=m -- 2.21.0
Re: [RFC PATCH] Replaces long number representation by BIT() macro
Hi Leonardo, Leonardo Bras writes: > The main reason of this change is to make these bitmasks more readable. > > The macro ASM_CONST() just appends an UL to it's parameter, so it can be > easily replaced by BIT_MASK, that already uses a UL representation. > > ASM_CONST() in this file may behave different if __ASSEMBLY__ is defined, > as it is used on .S files, just leaving the parameter as is. Thanks for the patch, but I don't consider this an improvement in readability. At boot we print the firmware features, eg: firmware_features = 0x0001c45ffc5f And it's much easier to match that up to the full constants, than to the bit numbers. Similarly in memory or register dumps. What we could do is switch to the `UL` macro from include/linux/const.h, rather than using our own ASM_CONST. cheers > diff --git a/arch/powerpc/include/asm/firmware.h > b/arch/powerpc/include/asm/firmware.h > index 00bc42d95679..7a5b0cc0bc85 100644 > --- a/arch/powerpc/include/asm/firmware.h > +++ b/arch/powerpc/include/asm/firmware.h > @@ -14,46 +14,45 @@ > > #ifdef __KERNEL__ > > -#include > - > +#include > /* firmware feature bitmask values */ > > -#define FW_FEATURE_PFT ASM_CONST(0x0001) > -#define FW_FEATURE_TCE ASM_CONST(0x0002) > -#define FW_FEATURE_SPRG0 ASM_CONST(0x0004) > -#define FW_FEATURE_DABR ASM_CONST(0x0008) > -#define FW_FEATURE_COPY ASM_CONST(0x0010) > -#define FW_FEATURE_ASR ASM_CONST(0x0020) > -#define FW_FEATURE_DEBUG ASM_CONST(0x0040) > -#define FW_FEATURE_TERM ASM_CONST(0x0080) > -#define FW_FEATURE_PERF ASM_CONST(0x0100) > -#define FW_FEATURE_DUMP ASM_CONST(0x0200) > -#define FW_FEATURE_INTERRUPT ASM_CONST(0x0400) > -#define FW_FEATURE_MIGRATE ASM_CONST(0x0800) > -#define FW_FEATURE_PERFMON ASM_CONST(0x1000) > -#define FW_FEATURE_CRQ ASM_CONST(0x2000) > -#define FW_FEATURE_VIO ASM_CONST(0x4000) > -#define FW_FEATURE_RDMA ASM_CONST(0x8000) > -#define FW_FEATURE_LLAN ASM_CONST(0x0001) > -#define FW_FEATURE_BULK_REMOVE ASM_CONST(0x0002) > -#define FW_FEATURE_XDABR ASM_CONST(0x0004) > -#define FW_FEATURE_MULTITCE ASM_CONST(0x0008) > -#define FW_FEATURE_SPLPARASM_CONST(0x0010) > -#define FW_FEATURE_LPAR ASM_CONST(0x0040) > -#define FW_FEATURE_PS3_LV1 ASM_CONST(0x0080) > -#define FW_FEATURE_HPT_RESIZEASM_CONST(0x0100) > -#define FW_FEATURE_CMO ASM_CONST(0x0200) > -#define FW_FEATURE_VPHN ASM_CONST(0x0400) > -#define FW_FEATURE_XCMO ASM_CONST(0x0800) > -#define FW_FEATURE_OPAL ASM_CONST(0x1000) > -#define FW_FEATURE_SET_MODE ASM_CONST(0x4000) > -#define FW_FEATURE_BEST_ENERGY ASM_CONST(0x8000) > -#define FW_FEATURE_TYPE1_AFFINITY ASM_CONST(0x0001) > -#define FW_FEATURE_PRRN ASM_CONST(0x0002) > -#define FW_FEATURE_DRMEM_V2 ASM_CONST(0x0004) > -#define FW_FEATURE_DRC_INFO ASM_CONST(0x0008) > -#define FW_FEATURE_BLOCK_REMOVE ASM_CONST(0x0010) > -#define FW_FEATURE_PAPR_SCM ASM_CONST(0x0020) > +#define FW_FEATURE_PFT BIT(0) > +#define FW_FEATURE_TCE BIT(1) > +#define FW_FEATURE_SPRG0 BIT(2) > +#define FW_FEATURE_DABR BIT(3) > +#define FW_FEATURE_COPY BIT(4) > +#define FW_FEATURE_ASR BIT(5) > +#define FW_FEATURE_DEBUG BIT(6) > +#define FW_FEATURE_TERM BIT(7) > +#define FW_FEATURE_PERF BIT(8) > +#define FW_FEATURE_DUMP BIT(9) > +#define FW_FEATURE_INTERRUPT BIT(10) > +#define FW_FEATURE_MIGRATE BIT(11) > +#define FW_FEATURE_PERFMON BIT(12) > +#define FW_FEATURE_CRQ BIT(13) > +#define FW_FEATURE_VIO BIT(14) > +#define FW_FEATURE_RDMA BIT(15) > +#define FW_FEATURE_LLAN BIT(16) > +#define FW_FEATURE_BULK_REMOVE BIT(17) > +#define FW_FEATURE_XDABR BIT(18) > +#define FW_FEATURE_MULTITCE BIT(19) > +#define FW_FEATURE_SPLPARBIT(20) > +#define FW_FEATURE_LPAR BIT(22) > +#define FW_FEATURE_PS3_LV1 BIT(23) > +#define FW_FEATURE_HPT_RESIZEBIT(24) > +#define FW_FEATURE_CMO BIT(25) > +#define FW_FEATURE_VPHN BIT(26) > +#define FW_FEATURE_XCMO BIT(27) > +#define FW_FEATURE_OPAL BIT(28) > +#define FW_FEATURE_SET_MODE BIT(30) > +#define FW_FEATURE_BEST_ENERGY BIT(31) > +#define FW_FEATURE_TYPE1_AFFINITY BIT(32) > +#define
Re: [v2 03/12] powerpc/mce: Add MCE notification chain
On Tue, Jul 02, 2019 at 10:49:23AM +0530, Santosh Sivaraj wrote: +static BLOCKING_NOTIFIER_HEAD(mce_notifier_list); Mahesh suggested using an atomic notifier chain instead of blocking, since we are in an interrupt. -- Reza Arbab
[PATCH -next] powerpc/powernv: Make some sysbols static
Fix sparse warnings:
arch/powerpc/platforms/powernv/opal-psr.c:20:1:
warning: symbol 'psr_mutex' was not declared. Should it be static?
arch/powerpc/platforms/powernv/opal-psr.c:27:3:
warning: symbol 'psr_attrs' was not declared. Should it be static?
arch/powerpc/platforms/powernv/opal-powercap.c:20:1:
warning: symbol 'powercap_mutex' was not declared. Should it be static?
arch/powerpc/platforms/powernv/opal-sensor-groups.c:20:1:
warning: symbol 'sg_mutex' was not declared. Should it be static?
Reported-by: Hulk Robot
Signed-off-by: YueHaibing
---
arch/powerpc/platforms/powernv/opal-powercap.c | 2 +-
arch/powerpc/platforms/powernv/opal-psr.c | 4 ++--
arch/powerpc/platforms/powernv/opal-sensor-groups.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/platforms/powernv/opal-powercap.c
b/arch/powerpc/platforms/powernv/opal-powercap.c
index dc599e7..c16d44f 100644
--- a/arch/powerpc/platforms/powernv/opal-powercap.c
+++ b/arch/powerpc/platforms/powernv/opal-powercap.c
@@ -13,7 +13,7 @@
#include
-DEFINE_MUTEX(powercap_mutex);
+static DEFINE_MUTEX(powercap_mutex);
static struct kobject *powercap_kobj;
diff --git a/arch/powerpc/platforms/powernv/opal-psr.c
b/arch/powerpc/platforms/powernv/opal-psr.c
index b6ccb30..69d7e75 100644
--- a/arch/powerpc/platforms/powernv/opal-psr.c
+++ b/arch/powerpc/platforms/powernv/opal-psr.c
@@ -13,11 +13,11 @@
#include
-DEFINE_MUTEX(psr_mutex);
+static DEFINE_MUTEX(psr_mutex);
static struct kobject *psr_kobj;
-struct psr_attr {
+static struct psr_attr {
u32 handle;
struct kobj_attribute attr;
} *psr_attrs;
diff --git a/arch/powerpc/platforms/powernv/opal-sensor-groups.c
b/arch/powerpc/platforms/powernv/opal-sensor-groups.c
index 31f13c1..f8ae1fb 100644
--- a/arch/powerpc/platforms/powernv/opal-sensor-groups.c
+++ b/arch/powerpc/platforms/powernv/opal-sensor-groups.c
@@ -13,7 +13,7 @@
#include
-DEFINE_MUTEX(sg_mutex);
+static DEFINE_MUTEX(sg_mutex);
static struct kobject *sg_kobj;
--
2.7.4
[PATCH] powerpc/setup: Adjust six seq_printf() calls in show_cpuinfo()
From: Markus Elfring
Date: Tue, 2 Jul 2019 14:41:42 +0200
A bit of information should be put into a sequence.
Thus improve the execution speed for this data output by better usage
of corresponding functions.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring
---
arch/powerpc/kernel/setup-common.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/setup-common.c
b/arch/powerpc/kernel/setup-common.c
index 1f8db666468d..a381723b11bd 100644
--- a/arch/powerpc/kernel/setup-common.c
+++ b/arch/powerpc/kernel/setup-common.c
@@ -239,18 +239,17 @@ static int show_cpuinfo(struct seq_file *m, void *v)
maj = (pvr >> 8) & 0xFF;
min = pvr & 0xFF;
- seq_printf(m, "processor\t: %lu\n", cpu_id);
- seq_printf(m, "cpu\t\t: ");
+ seq_printf(m, "processor\t: %lu\ncpu\t\t: ", cpu_id);
if (cur_cpu_spec->pvr_mask && cur_cpu_spec->cpu_name)
- seq_printf(m, "%s", cur_cpu_spec->cpu_name);
+ seq_puts(m, cur_cpu_spec->cpu_name);
else
seq_printf(m, "unknown (%08x)", pvr);
if (cpu_has_feature(CPU_FTR_ALTIVEC))
- seq_printf(m, ", altivec supported");
+ seq_puts(m, ", altivec supported");
- seq_printf(m, "\n");
+ seq_putc(m, '\n');
#ifdef CONFIG_TAU
if (cpu_has_feature(CPU_FTR_TAU)) {
@@ -332,7 +331,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
seq_printf(m, "bogomips\t: %lu.%02lu\n", loops_per_jiffy /
(50 / HZ),
(loops_per_jiffy / (5000 / HZ)) % 100);
- seq_printf(m, "\n");
+ seq_putc(m, '\n');
/* If this is the last cpu, print the summary */
if (cpumask_next(cpu_id, cpu_online_mask) >= nr_cpu_ids)
--
2.22.0
[PATCH] powerpc/powernv/idle: Fix restore of SPRN_LDBAR for POWER9 stop state.
From: Athira Rajeev
commit 10d91611f426 ("powerpc/64s: Reimplement book3s idle code in C")
reimplemented book3S code to pltform/powernv/idle.c. But when doing so
missed to add the per-thread LDBAR update in the core_woken path of
the power9_idle_stop(). Patch fixes the same.
Fixes: 10d91611f426 ("powerpc/64s: Reimplement book3s idle code in C")
Signed-off-by: Athira Rajeev
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/platforms/powernv/idle.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/platforms/powernv/idle.c
b/arch/powerpc/platforms/powernv/idle.c
index 2f4479b94ac3..fd14a6237954 100644
--- a/arch/powerpc/platforms/powernv/idle.c
+++ b/arch/powerpc/platforms/powernv/idle.c
@@ -758,7 +758,6 @@ static unsigned long power9_idle_stop(unsigned long psscr,
bool mmu_on)
mtspr(SPRN_PTCR,sprs.ptcr);
mtspr(SPRN_RPR, sprs.rpr);
mtspr(SPRN_TSCR,sprs.tscr);
- mtspr(SPRN_LDBAR, sprs.ldbar);
if (pls >= pnv_first_tb_loss_level) {
/* TB loss */
@@ -790,6 +789,7 @@ static unsigned long power9_idle_stop(unsigned long psscr,
bool mmu_on)
mtspr(SPRN_MMCR0, sprs.mmcr0);
mtspr(SPRN_MMCR1, sprs.mmcr1);
mtspr(SPRN_MMCR2, sprs.mmcr2);
+ mtspr(SPRN_LDBAR, sprs.ldbar);
mtspr(SPRN_SPRG3, local_paca->sprg_vdso);
--
2.20.1
Re: Re: [PATCH 1/3] arm64: mm: Add p?d_large() definitions
On Tue, Jul 02, 2019 at 01:07:11PM +1000, Nicholas Piggin wrote: > Will Deacon's on July 1, 2019 8:15 pm: > > On Mon, Jul 01, 2019 at 11:03:51AM +0100, Steven Price wrote: > >> On 01/07/2019 10:27, Will Deacon wrote: > >> > On Sun, Jun 23, 2019 at 07:44:44PM +1000, Nicholas Piggin wrote: > >> >> walk_page_range() is going to be allowed to walk page tables other than > >> >> those of user space. For this it needs to know when it has reached a > >> >> 'leaf' entry in the page tables. This information will be provided by > >> >> the > >> >> p?d_large() functions/macros. > >> > > >> > I can't remember whether or not I asked this before, but why not call > >> > this macro p?d_leaf() if that's what it's identifying? "Large" and "huge" > >> > are usually synonymous, so I find this naming needlessly confusing based > >> > on this patch in isolation. > > Those page table macro names are horrible. Large, huge, leaf, wtf? > They could do with a sensible renaming. But this series just follows > naming that's alreay there on x86. I realise that, and I wasn't meaning to have a go at you. Just wanted to make my opinion clear by having a moan :) Will
[PATCH] powerpc: Use nid as fallback for chip_id
One of the uses of chip_id is to find out all cores that are part of the same
chip. However ibm,chip_id property is not present in device-tree of PowerVM
Lpars. Hence lscpu output shows one core per socket and multiple cores.
Before the patch.
# lscpu
Architecture:ppc64le
Byte Order: Little Endian
CPU(s): 128
On-line CPU(s) list: 0-127
Thread(s) per core: 8
Core(s) per socket: 1
Socket(s): 16
NUMA node(s):2
Model: 2.2 (pvr 004e 0202)
Model name: POWER9 (architected), altivec supported
Hypervisor vendor: pHyp
Virtualization type: para
L1d cache: 32K
L1i cache: 32K
L2 cache:512K
L3 cache:10240K
NUMA node0 CPU(s): 0-63
NUMA node1 CPU(s): 64-127
# cat /sys/devices/system/cpu/cpu0/topology/physical_package_id
-1
Signed-off-by: Srikar Dronamraju
---
arch/powerpc/kernel/prom.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
index 7159e791a70d..0b8918b43580 100644
--- a/arch/powerpc/kernel/prom.c
+++ b/arch/powerpc/kernel/prom.c
@@ -867,18 +867,24 @@ EXPORT_SYMBOL(of_get_ibm_chip_id);
* @cpu: The logical cpu number.
*
* Return the value of the ibm,chip-id property corresponding to the given
- * logical cpu number. If the chip-id can not be found, returns -1.
+ * logical cpu number. If the chip-id can not be found, return nid.
+ *
*/
int cpu_to_chip_id(int cpu)
{
struct device_node *np;
+ int chip_id = -1;
np = of_get_cpu_node(cpu, NULL);
if (!np)
return -1;
+ chip_id = of_get_ibm_chip_id(np);
+ if (chip_id == -1)
+ chip_id = of_node_to_nid(np);
+
of_node_put(np);
- return of_get_ibm_chip_id(np);
+ return chip_id;
}
EXPORT_SYMBOL(cpu_to_chip_id);
--
2.18.1
Re: [v2 09/12] powerpc/mce: Enable MCE notifiers in external modules
On 7/2/19 11:47 AM, Nicholas Piggin wrote: > Santosh Sivaraj's on July 2, 2019 3:19 pm: >> From: Reza Arbab >> >> Signed-off-by: Reza Arbab >> --- >> arch/powerpc/kernel/exceptions-64s.S | 6 ++ >> arch/powerpc/kernel/mce.c| 2 ++ >> 2 files changed, 8 insertions(+) >> >> diff --git a/arch/powerpc/kernel/exceptions-64s.S >> b/arch/powerpc/kernel/exceptions-64s.S >> index c83e38a403fd..311f1392a2ec 100644 >> --- a/arch/powerpc/kernel/exceptions-64s.S >> +++ b/arch/powerpc/kernel/exceptions-64s.S >> @@ -458,6 +458,12 @@ EXC_COMMON_BEGIN(machine_check_handle_early) >> bl machine_check_early >> std r3,RESULT(r1) /* Save result */ >> >> +/* Notifiers may be in a module, so enable virtual addressing. */ >> +mfmsr r11 >> +ori r11,r11,MSR_IR >> +ori r11,r11,MSR_DR >> +mtmsr r11 > > Can't do this, we could take a machine check somewhere the MMU is > not sane (in fact the guest early mce handling that was added recently > should not be enabling virtual mode either, which needs to be fixed). Looks like they need this to be able to run notifier chain which may fail in real mode. > > Thanks, > Nick >
Re: [PATCH v5 0/4] Additional fixes on Talitos driver
Hi Herbert, Le 24/06/2019 à 09:21, Christophe Leroy a écrit : This series is the last set of fixes for the Talitos driver. Do you plan to apply this series, or are you expecting anythink from myself ? Thanks Christophe We now get a fully clean boot on both SEC1 (SEC1.2 on mpc885) and SEC2 (SEC2.2 on mpc8321E) with CONFIG_CRYPTO_MANAGER_EXTRA_TESTS: [3.385197] bus: 'platform': really_probe: probing driver talitos with device ff02.crypto [3.450982] random: fast init done [ 12.252548] alg: No test for authenc(hmac(md5),cbc(aes)) (authenc-hmac-md5-cbc-aes-talitos-hsna) [ 12.262226] alg: No test for authenc(hmac(md5),cbc(des3_ede)) (authenc-hmac-md5-cbc-3des-talitos-hsna) [ 43.310737] Bug in SEC1, padding ourself [ 45.603318] random: crng init done [ 54.612333] talitos ff02.crypto: fsl,sec1.2 algorithms registered in /proc/crypto [ 54.620232] driver: 'talitos': driver_bound: bound to device 'ff02.crypto' [1.193721] bus: 'platform': really_probe: probing driver talitos with device b003.crypto [1.229197] random: fast init done [2.714920] alg: No test for authenc(hmac(sha224),cbc(aes)) (authenc-hmac-sha224-cbc-aes-talitos) [2.724312] alg: No test for authenc(hmac(sha224),cbc(aes)) (authenc-hmac-sha224-cbc-aes-talitos-hsna) [4.482045] alg: No test for authenc(hmac(md5),cbc(aes)) (authenc-hmac-md5-cbc-aes-talitos) [4.490940] alg: No test for authenc(hmac(md5),cbc(aes)) (authenc-hmac-md5-cbc-aes-talitos-hsna) [4.500280] alg: No test for authenc(hmac(md5),cbc(des3_ede)) (authenc-hmac-md5-cbc-3des-talitos) [4.509727] alg: No test for authenc(hmac(md5),cbc(des3_ede)) (authenc-hmac-md5-cbc-3des-talitos-hsna) [6.631781] random: crng init done [ 11.521795] talitos b003.crypto: fsl,sec2.2 algorithms registered in /proc/crypto [ 11.529803] driver: 'talitos': driver_bound: bound to device 'b003.crypto' v2: dropped patch 1 which was irrelevant due to a rebase weirdness. Added Cc to stable on the 2 first patches. v3: - removed stable reference in patch 1 - reworded patch 1 to include name of patch 2 for the dependency. - mentionned this dependency in patch 2 as well. - corrected the Fixes: sha1 in patch 4 v4: - using scatterwalk_ffwd() instead of opencodying SG list forwarding. - Added a patch to fix sg_copy_to_buffer() when sg->offset() is greater than PAGE_SIZE, otherwise sg_copy_to_buffer() fails when the list has been forwarded with scatterwalk_ffwd(). - taken the patch "crypto: talitos - eliminate unneeded 'done' functions at build time" out of the series because it is independent. - added a helper to find the header field associated to a request in flush_channe() v5: - Replacing the while loop by a direct shift/mask operation, as suggested by Herbert in patch 1. Christophe Leroy (4): lib/scatterlist: Fix mapping iterator when sg->offset is greater than PAGE_SIZE crypto: talitos - move struct talitos_edesc into talitos.h crypto: talitos - fix hash on SEC1. crypto: talitos - drop icv_ool drivers/crypto/talitos.c | 102 +++ drivers/crypto/talitos.h | 28 + lib/scatterlist.c| 9 +++-- 3 files changed, 74 insertions(+), 65 deletions(-)
[PATCH v2] powerpc/imc: Dont create debugfs files for cpu-less nodes
Commit <684d984038aa> ('powerpc/powernv: Add debugfs interface for imc-mode
and imc') added debugfs interface for the nest imc pmu devices to support
changing of different ucode modes. Primarily adding this capability for
debug. But when doing so, the code did not consider the case of cpu-less
nodes. So when reading the _cmd_ or _mode_ file of a cpu-less node
will create this crash.
[ 1139.415461][ T5301] Faulting instruction address: 0xc00d0d58
[ 1139.415492][ T5301] Oops: Kernel access of bad area, sig: 11 [#1]
[ 1139.415509][ T5301] LE PAGE_SIZE=64K MMU=Radix MMU=Hash SMP NR_CPUS=256
DEBUG_PAGEALLOC NUMA PowerNV
[ 1139.415542][ T5301] Modules linked in: i2c_opal i2c_core ip_tables x_tables
xfs sd_mod bnx2x mdio ahci libahci tg3 libphy libata firmware_class dm_mirror
dm_region_hash dm_log dm_mod
[ 1139.415595][ T5301] CPU: 67 PID: 5301 Comm: cat Not tainted 5.2.0-rc6-next-
20190627+ #19
[ 1139.415634][ T5301] NIP: c00d0d58 LR: c049aa18
CTR:c00d0d50
[ 1139.415675][ T5301] REGS: c00020194548f9e0 TRAP: 0300 Not tainted
(5.2.0-rc6-next-20190627+)
[ 1139.415705][ T5301] MSR: 90009033
CR:28022822 XER:
[ 1139.415777][ T5301] CFAR: c049aa14 DAR: 0003fc08
DSISR:4000 IRQMASK: 0
[ 1139.415777][ T5301] GPR00: c049aa18 c00020194548fc70
c16f8b03fc08
[ 1139.415777][ T5301] GPR04: c00020194548fcd0
14884e7300011eaa
[ 1139.415777][ T5301] GPR08: 7eea5a52 c00d0d50
[ 1139.415777][ T5301] GPR12: c00d0d50 c000201fff7f8c00
[ 1139.415777][ T5301] GPR16: 000d 7fffeb0c3368
[ 1139.415777][ T5301] GPR20:
0002
[ 1139.415777][ T5301] GPR24:
000200010ec9
[ 1139.415777][ T5301] GPR28: c00020194548fdf0 c00020049a584ef8
c00020049a584ea8
[ 1139.416116][ T5301] NIP [c00d0d58] imc_mem_get+0x8/0x20
[ 1139.416143][ T5301] LR [c049aa18] simple_attr_read+0x118/0x170
[ 1139.416158][ T5301] Call Trace:
[ 1139.416182][ T5301] [c00020194548fc70]
[c049a970]simple_attr_read+0x70/0x170 (unreliable)
[ 1139.416255][ T5301] [c00020194548fd10]
[c054385c]debugfs_attr_read+0x6c/0xb0
[ 1139.416305][ T5301] [c00020194548fd60] [c0454c1c]__vfs_read+0x3c/0x70
[ 1139.416363][ T5301] [c00020194548fd80] [c0454d0c] vfs_read+0xbc/0x1a0
[ 1139.416392][ T5301] [c00020194548fdd0] [c045519c]ksys_read+0x7c/0x140
[ 1139.416434][ T5301] [c00020194548fe20]
[c000b108]system_call+0x5c/0x70
[ 1139.416473][ T5301] Instruction dump:
[ 1139.416511][ T5301] 4e800020 6000 7c0802a6 6000 7c801d28 3860
4e800020 6000
[ 1139.416572][ T5301] 6000 6000 7c0802a6 6000 <7d201c28> 3860
f924 4e800020
[ 1139.416636][ T5301] ---[ end trace c44d1fb4ace04784 ]---
[ 1139.520686][ T5301]
[ 1140.520820][ T5301] Kernel panic - not syncing: Fatal exception
Patch fixes the issue with a more robust check for vbase to NULL.
Before patch, ls output for the debugfs imc directory
# ls /sys/kernel/debug/powerpc/imc/
imc_cmd_0imc_cmd_251 imc_cmd_253 imc_cmd_255 imc_mode_0imc_mode_251
imc_mode_253 imc_mode_255
imc_cmd_250 imc_cmd_252 imc_cmd_254 imc_cmd_8imc_mode_250 imc_mode_252
imc_mode_254 imc_mode_8
After patch, ls output for the debugfs imc directory
# ls /sys/kernel/debug/powerpc/imc/
imc_cmd_0 imc_cmd_8 imc_mode_0 imc_mode_8
Fixes: 684d984038aa ('powerpc/powernv: Add debugfs interface for imc-mode and
imc')
Reported-by: Qian Cai
Suggested-by: Michael Ellerman
Signed-off-by: Madhavan Srinivasan
---
Changelog v1:
- Modified the cpumask check.
arch/powerpc/platforms/powernv/opal-imc.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/platforms/powernv/opal-imc.c
b/arch/powerpc/platforms/powernv/opal-imc.c
index 186109bdd41b..e04b20625cb9 100644
--- a/arch/powerpc/platforms/powernv/opal-imc.c
+++ b/arch/powerpc/platforms/powernv/opal-imc.c
@@ -53,9 +53,9 @@ static void export_imc_mode_and_cmd(struct device_node *node,
struct imc_pmu *pmu_ptr)
{
static u64 loc, *imc_mode_addr, *imc_cmd_addr;
- int chip = 0, nid;
char mode[16], cmd[16];
u32 cb_offset;
+ struct imc_mem_info *ptr = pmu_ptr->mem_info;
imc_debugfs_parent = debugfs_create_dir("imc", powerpc_debugfs_root);
@@ -69,20 +69,20 @@ static void export_imc_mode_and_cmd(struct device_node
*node,
if (of_property_read_u32(node, "cb_offset", &cb_offset))
cb_offset = IMC_CNTL_BLK_OFFSET;
- for_each_node(nid) {
- loc = (u64)(pmu_ptr->mem_info[chip].vbase) + cb_offset;
+ while (ptr->vbase != NULL) {
+ loc = (u64)(
[PATCH] powerpc/64s/exception: Remove unused SOFTEN_VALUE_0x980
Remove SOFTEN_VALUE_0x980, it's been unused since commit
dabe859ec636 ("powerpc: Give hypervisor decrementer interrupts their
own handler") (Sep 2012).
Signed-off-by: Michael Ellerman
---
arch/powerpc/include/asm/exception-64s.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/powerpc/include/asm/exception-64s.h
b/arch/powerpc/include/asm/exception-64s.h
index b590765f6e45..b4f8b745ba01 100644
--- a/arch/powerpc/include/asm/exception-64s.h
+++ b/arch/powerpc/include/asm/exception-64s.h
@@ -583,7 +583,6 @@ END_FTR_SECTION_NESTED(ftr,ftr,943)
/* This associate vector numbers with bits in paca->irq_happened */
#define SOFTEN_VALUE_0x500 PACA_IRQ_EE
#define SOFTEN_VALUE_0x900 PACA_IRQ_DEC
-#define SOFTEN_VALUE_0x980 PACA_IRQ_DEC
#define SOFTEN_VALUE_0xa00 PACA_IRQ_DBELL
#define SOFTEN_VALUE_0xe80 PACA_IRQ_DBELL
#define SOFTEN_VALUE_0xe60 PACA_IRQ_HMI
--
2.20.1
Re: [RFC 09/11] pci/hotplug/pnv-php: Relax check when disabling slot
On 19/6/19 11:28 pm, Frederic Barrat wrote: The driver only allows to disable a slot in the POPULATED state. However, if an error occurs while enabling the slot, say because the link couldn't be trained, then the POPULATED state may not be reached, yet the power state of the slot is on. So allow to disable a slot in the REGISTERED state. Removing the devices will do nothing since it's not populated, and we'll set the power state of the slot back to off. Signed-off-by: Frederic Barrat Reviewed-by: Andrew Donnellan --- drivers/pci/hotplug/pnv_php.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/pci/hotplug/pnv_php.c b/drivers/pci/hotplug/pnv_php.c index f9c624334ef7..74b62a8e11e7 100644 --- a/drivers/pci/hotplug/pnv_php.c +++ b/drivers/pci/hotplug/pnv_php.c @@ -523,7 +523,13 @@ static int pnv_php_disable_slot(struct hotplug_slot *slot) struct pnv_php_slot *php_slot = to_pnv_php_slot(slot); int ret; - if (php_slot->state != PNV_PHP_STATE_POPULATED) + /* +* Allow to disable a slot already in the registered state to +* cover cases where the slot couldn't be enabled and never +* reached the populated state +*/ + if (php_slot->state != PNV_PHP_STATE_POPULATED && + php_slot->state != PNV_PHP_STATE_REGISTERED) return 0; /* Remove all devices behind the slot */ -- Andrew Donnellan OzLabs, ADL Canberra a...@linux.ibm.com IBM Australia Limited
Re: [RFC 11/11] ocxl: Add PCI hotplug dependency to Kconfig
On 19/6/19 11:28 pm, Frederic Barrat wrote: The PCI hotplug framework is used to update the devices when a new image is written to the FPGA. Signed-off-by: Frederic Barrat Acked-by: Andrew Donnellan --- drivers/misc/ocxl/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/misc/ocxl/Kconfig b/drivers/misc/ocxl/Kconfig index 7fb6d39d4c5a..13a5d9f30369 100644 --- a/drivers/misc/ocxl/Kconfig +++ b/drivers/misc/ocxl/Kconfig @@ -12,6 +12,7 @@ config OCXL tristate "OpenCAPI coherent accelerator support" depends on PPC_POWERNV && PCI && EEH select OCXL_BASE + select HOTPLUG_PCI_POWERNV default m help Select this option to enable the ocxl driver for Open -- Andrew Donnellan OzLabs, ADL Canberra a...@linux.ibm.com IBM Australia Limited
