Hi,
On Thu, Sep 12, 2019 at 06:15:33PM +0800, Yunsheng Lin wrote:
> When passing the return value of dev_to_node() to cpumask_of_node()
> without checking the node id if the node id is NUMA_NO_NODE, there is
> global-out-of-bounds detected by KASAN.
>
> From the discussion [1], NUMA_NO_NODE
Hi Qian,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on linus/master]
[cannot apply to v5.3-rc8 next-20190904]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
Add support for the scv instruction on POWER9 and later CPUs.
For now this implements the zeroth scv vector 'scv 0', as identical
to 'sc' system calls, with the exception that lr is not preserved, and
it is 64-bit only. There may yet be changes made to this ABI, so it's
for testing only.
This
The scv instruction causes an interrupt which can enter the kernel with
MSR[EE]=1, thus allowing interrupts to hit at any time. These must not
be taken as normal interrupts, because they come from MSR[PR]=0 context,
and yet the kernel stack is not yet set up and r13 is not set to the
PACA).
Treat
The difference between lite and regular returns is that the lite case
restores all NVGPRs, whereas lite skips that. This is quite clumsy
though, most interrupts want the NVGPRs saved for debugging, not to
modify in the caller, so the NVGPRs restore is not necessary most of
the time. Restore NVGPRs
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it,
System call entry and particularly exit code is beyond the limit of what
is reasonable to implement in asm.
This conversion moves all conditional branches out of the asm code,
except for the case that all GPRs should be restored at exit.
Null syscall test is about 5% faster after this patch,
powerpc has an optimisation where interrupts avoid saving the
non-volatile (or callee saved) registers to the interrupt stack frame if
they are not required.
Two problems with this are that an interrupt does not always know
whether it will need non-volatiles; and if it does need them, they can
The soft nmi handler does not reconcile interrupt state, so it should
not return via the normal ret_from_except path. Return like other NMIs,
using the EXCEPTION_RESTORE_REGS macro.
This becomes important when the scv interrupt is implemented, which
must handle soft-masked interrupts that have
Apart from SRESET, MCE, and syscall (hcall variant), the SRR type
interrupts are not escalated to hypervisor mode, so delivered to the OS.
When running PR KVM, the OS is the hypervisor, and the guest runs with
MSR[PR]=1, so these interrupts must test if a guest was running when
interrupted. These
A few of the non-standard handlers are left uncommented. Some more
description could be added to some.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/exceptions-64s.S | 391 ---
1 file changed, 353 insertions(+), 38 deletions(-)
diff --git
Remove more magic numbers and replace with nicely named bools.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/exceptions-64s.S | 68 +---
1 file changed, 32 insertions(+), 36 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S
The reduction in interrupt entry size allows some handlers to be
re-inlined.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/exceptions-64s.S | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S
The hdec interrupt handler is reported to sometimes fire in Linux if
KVM leaves it pending after a guest exists. This is harmless, so there
is a no-op handler for it.
The interrupt handler currently uses the regular kernel stack. Change
this to avoid touching the stack entirely.
This should be
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/exceptions-64s.S | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S
b/arch/powerpc/kernel/exceptions-64s.S
index abf26db36427..9fa71d51ecf4 100644
---
These are used infrequently enough they don't provide much help, so
inline them.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/exceptions-64s.S | 82 ++--
1 file changed, 28 insertions(+), 54 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S
Replace IEARLY=1 and IEARLY=2 with IBRANCH_COMMON, which controls if
the entry code branches to a common handler; and IREALMODE_COMMON,
which controls whether the common handler should remain in real mode.
These special cases no longer avoid loading the SRR registers, there
is no point as most of
This allows more code to be moved out of unrelocated regions. The system
call KVMTEST is changed to be open-coded and remain in the tramp area to
avoid having to move it to entry_64.S. The custom nature of the system
call entry code means the hcall case can be made more streamlined than
regular
As well as moving code out of the unrelocated vectors, this allows the
masked handlers to be moved to common code, and allows the soft_nmi
handler to be generated more like a regular handler.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/exceptions-64s.S | 106
The real mode interrupt entry points currently use rfid to branch to
the common handler in virtual mode. This is a significant amount of
code, and forces other code (notably the KVM test) to live in the
real mode handler.
In the interest of minimising the amount of code that runs unrelocated
move
Rather than using DAR=2 to select the i-side registers, add an
explicit option.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/exceptions-64s.S | 23 ---
1 file changed, 16 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/exceptions-64s.S | 55 +---
1 file changed, 26 insertions(+), 29 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S
b/arch/powerpc/kernel/exceptions-64s.S
index f318869607db..bef0c2eee7dc 100644
---
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/exceptions-64s.S | 51 +---
1 file changed, 24 insertions(+), 27 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S
b/arch/powerpc/kernel/exceptions-64s.S
index ba2dcd91aaaf..f318869607db 100644
---
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/exceptions-64s.S | 68
1 file changed, 30 insertions(+), 38 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S
b/arch/powerpc/kernel/exceptions-64s.S
index b5decc9a0cbf..ba2dcd91aaaf 100644
---
Aside from label names and BUG line numbers, the generated code change
is an additional HMI KVM handler added for the "late" KVM handler,
because early and late HMI generation is achieved by defining two
different interrupt types.
Signed-off-by: Nicholas Piggin
---
These don't provide a large amount of code sharing. Removing them
makes code easier to shuffle around. For example, some of the common
instructions will be moved into the common code gen macro.
No generated code change.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/exceptions-64s.S |
No generated code change.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/exceptions-64s.S | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S
b/arch/powerpc/kernel/exceptions-64s.S
index 591ae2a73e18..0e39e98ef719 100644
No generated code change.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/exceptions-64s.S | 24 +---
1 file changed, 17 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S
b/arch/powerpc/kernel/exceptions-64s.S
index
The code generation macro arguments are difficult to read, and
defaults can't easily be used.
This introduces a block where parameters can be set for interrupt
handler code generation by the subsequent macros, and adds the first
generation macro for interrupt entry.
One interrupt handler is
My interrupt entry patches have finally collided with syscall and
interrupt exit patches, so I'll merge the series. Most patches have
been seen already, however there have been a number of small changes
and fixes throughout the series.
The final two patches add support for 'scv' and 'rfscv'
Le 14/09/2019 à 16:34, Scott Wood a écrit :
On Fri, 2019-08-23 at 12:50 +, Christophe Leroy wrote:
On mpc83xx with a QE, IMMR is 2Mbytes.
On mpc83xx without a QE, IMMR is 1Mbytes.
Each driver will map a part of it to access the registers it needs.
Some driver will map the same part of
https://bugzilla.kernel.org/show_bug.cgi?id=204819
--- Comment #10 from Christophe Leroy (christophe.le...@c-s.fr) ---
No no, what I mean by 'manually fixed kernel_page_tables' is that I fixed the
file you attached so that it has the same values as what it would have had with
the patch applied.
On Fri, 2019-08-23 at 12:50 +, Christophe Leroy wrote:
> On mpc83xx with a QE, IMMR is 2Mbytes.
> On mpc83xx without a QE, IMMR is 1Mbytes.
> Each driver will map a part of it to access the registers it needs.
> Some driver will map the same part of IMMR as other drivers.
>
> In order to
On Tue, 2019-09-10 at 13:34 +0800, Jason Yan wrote:
> Hi Scott,
>
> On 2019/8/28 12:05, Scott Wood wrote:
> > On Fri, 2019-08-09 at 18:07 +0800, Jason Yan wrote:
> > > This series implements KASLR for powerpc/fsl_booke/32, as a security
> > > feature that deters exploit attempts relying on
On Thu, 2019-08-29 at 11:25 +, Madalin-cristian Bucur wrote:
> > -Original Message-
> > From: Scott Wood
> > Sent: Wednesday, August 28, 2019 7:19 AM
> > To: Valentin Longchamp ; Madalin-cristian Bucur
> >
> > Cc: linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org;
> >
https://bugzilla.kernel.org/show_bug.cgi?id=204819
--- Comment #9 from Erhard F. (erhar...@mailbox.org) ---
I can apply the patch but how do I apply the manually fixed kernel_page_tables?
Not quite sure how to proceed.
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On Tue, 03 Sep 2019 10:00:57 +1000
Michael Ellerman wrote:
> Michal Suchánek writes:
> > On Mon, 02 Sep 2019 12:03:12 +1000
> > Michael Ellerman wrote:
> >
> >> Michal Suchanek writes:
> >> > On bigendian ppc64 it is common to have 32bit legacy binaries but much
> >> > less so on
https://bugzilla.kernel.org/show_bug.cgi?id=204819
--- Comment #8 from Christophe Leroy (christophe.le...@c-s.fr) ---
You get:
Sep 13 17:43:49 T600 kernel: BUG: Unable to handle kernel data access at
0xfe205150
However this area is properly mapped RW:
0xfe205000-0xfe205fff 0x297d6000
https://bugzilla.kernel.org/show_bug.cgi?id=204819
--- Comment #7 from Christophe Leroy (christophe.le...@c-s.fr) ---
Created attachment 284961
--> https://bugzilla.kernel.org/attachment.cgi?id=284961=edit
Manually fixed kernel_page_tables
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https://bugzilla.kernel.org/show_bug.cgi?id=204819
--- Comment #6 from Christophe Leroy (christophe.le...@c-s.fr) ---
Aaarrgghhh ! kernel_page_tables addresses are wrong. Ok, I'll manage.
For next time, please apply
Le 03/09/2019 à 07:23, Alastair D'Silva a écrit :
From: Alastair D'Silva
When calling flush_icache_range with a size >4GB, we were masking
off the upper 32 bits, so we would incorrectly flush a range smaller
than intended.
This patch replaces the 32 bit shifts with 64 bit ones, so that
the
> -Original Message-
> From: Gustavo Pimentel
> Sent: 2019年9月12日 19:24
> To: Andrew Murray ; Xiaowei Bao
>
> Cc: robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; Leo
> Li ; kis...@ti.com; lorenzo.pieral...@arm.com; M.h.
> Lian ; Mingkai Hu ; Roy
> Zang ;
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