From: Alastair D'Silva
This operation takes a significant amount of time when hotplugging
large amounts of memory (~50 seconds with 890GB of persistent memory).
This was orignally in commit fb5924fddf9e
("powerpc/mm: Flush cache on memory hot(un)plug") to support memtrace,
but the flush on add
From: Alastair D'Silva
When presented with large amounts of memory being hotplugged
(in my test case, ~890GB), the call to flush_dcache_range takes
a while (~50 seconds), triggering RCU stalls.
This patch breaks up the call into 1GB chunks, calling
cond_resched() inbetween to allow the
From: Alastair D'Silva
Similar to commit 22e9c88d486a
("powerpc/64: reuse PPC32 static inline flush_dcache_range()")
this patch converts the following ASM symbols to C:
flush_icache_range()
__flush_dcache_icache()
__flush_dcache_icache_phys()
This was done as we discovered a
From: Alastair D'Silva
This patch adds helpers to retrieve icache sizes, and renames the existing
helpers to make it clear that they are for dcache.
Signed-off-by: Alastair D'Silva
---
arch/powerpc/include/asm/cache.h | 29 +++
From: Alastair D'Silva
When calling __kernel_sync_dicache with a size >4GB, we were masking
off the upper 32 bits, so we would incorrectly flush a range smaller
than intended.
This patch replaces the 32 bit shifts with 64 bit ones, so that
the full size is accounted for.
Signed-off-by:
From: Alastair D'Silva
When calling flush_icache_range with a size >4GB, we were masking
off the upper 32 bits, so we would incorrectly flush a range smaller
than intended.
This patch replaces the 32 bit shifts with 64 bit ones, so that
the full size is accounted for.
Signed-off-by: Alastair
From: Alastair D'Silva
This series addresses a few issues discovered in how we flush caches:
1. Flushes were truncated at 4GB, so larger flushes were incorrect.
2. Flushing the dcache in arch_add_memory was unnecessary
This series also converts much of the cache assembler to C, with the
aim of
Hi
> Just a small concern...
>
> On Thu, Sep 26, 2019 at 09:29:51AM +0800, Shengjiu Wang wrote:
> > static int fsl_asrc_dma_startup(struct snd_pcm_substream *substream)
> > {
> > +
> > + release_pair = false;
> > + ret = snd_soc_set_runtime_hwparams(substream,
> > + _imx_hardware);
>
>
On Mon, 2019-09-23 at 13:39 +0200, Frederic Barrat wrote:
>
>
> > diff --git a/drivers/misc/ocxl/link.c b/drivers/misc/ocxl/link.c
> > index 2874811a4398..9e303a5f4d85 100644
> > --- a/drivers/misc/ocxl/link.c
> > +++ b/drivers/misc/ocxl/link.c
> > @@ -738,7 +738,7 @@ int
The patch fixes a bug that FlexTimer cannot
wakeup system in deep sleep.
Signed-off-by: Biwen Li
---
Change in v4:
- update property name
fsl,ippdexpcr-alt-addr -> fsl,ippdexpcr1-alt-addr
Change in v3:
- update property name
fsl,rcpm-scfg ->
The 'fsl,ippdexpcr1-alt-addr' property is used to handle an errata A-008646
on LS1021A
Signed-off-by: Biwen Li
---
Change in v4:
- rename property name
fsl,ippdexpcr-alt-addr -> fsl,ippdexpcr1-alt-addr
Change in v3:
- rename property name
fsl,rcpm-scfg ->
Description:
- Reading configuration register RCPM_IPPDEXPCR1
always return zero
Workaround:
- Save register RCPM_IPPDEXPCR1's value to
register SCFG_SPARECR8.(uboot's psci also
need reading value from the register SCFG_SPARECR8
to set
> Caution: EXT Email
>
> On Tue, Sep 24, 2019 at 11:27 PM Biwen Li wrote:
> >
> > > > >
> > > > > > > > > > >
> > > > > > > > > > > The 'fsl,ippdexpcr-alt-addr' property is used to
> > > > > > > > > > > handle an errata
> > > > > > > > > > > A-008646 on LS1021A
> > > > > > > > > > >
> > > > > >
Just a small concern...
On Thu, Sep 26, 2019 at 09:29:51AM +0800, Shengjiu Wang wrote:
> static int fsl_asrc_dma_startup(struct snd_pcm_substream *substream)
> {
> +
> + release_pair = false;
> + ret = snd_soc_set_runtime_hwparams(substream, _imx_hardware);
This set_runtime_hwparams()
There is error "aplay: pcm_write:2023: write error: Input/output error"
on i.MX8QM/i.MX8QXP platform for S24_3LE format.
In i.MX8QM/i.MX8QXP, the DMA is EDMA, which don't support 24bit
sample, but we didn't add any constraint, that cause issues.
So we need to query the caps of dma, then update
When set the runtime hardware parameters, we may need to query
the capability of DMA to complete the parameters.
This patch is to Extract this operation from
dmaengine_pcm_set_runtime_hwparams function to a separate function
snd_dmaengine_pcm_refine_runtime_hwparams, that other components
which
snd_pcm_format_t is more formal than enum asrc_word_width, which has
two property, width and physical width, which is more accurate than
enum asrc_word_width. So it is better to use in(out)put_format
instead of in(out)put_word_width.
Signed-off-by: Shengjiu Wang
Acked-by: Nicolin Chen
---
The ASRC support 24bit/16bit/8bit input width, which is
data width, not slot width.
For the S20_3LE format, the data with is 20bit, slot width
is 24bit, if we set ASRMCR1n.IWD to be 24bits, the result
is the volume is lower than expected, it likes 24bit data
right shift 4 bits
So replace S20_3LE
This patch serial is to update the supported format for fsl_asrc
and fix some format issue.
Shengjiu Wang (4):
ASoC: fsl_asrc: Use in(out)put_format instead of in(out)put_word_width
ASoC: fsl_asrc: update supported sample format
ASoC: pcm_dmaengine: Extract
On Wed, Sep 25, 2019 at 06:31:54PM +0200, Peter Zijlstra wrote:
> On Wed, Sep 25, 2019 at 03:25:44PM +0200, Michal Hocko wrote:
> > I am sorry but I still do not understand why you consider this whack a
> > mole better then simply live with the fact that NUMA_NO_NODE is a
> > reality and that
On Wed, Sep 25, 2019 at 03:25:44PM +0200, Michal Hocko wrote:
> I am sorry but I still do not understand why you consider this whack a
> mole better then simply live with the fact that NUMA_NO_NODE is a
> reality and that using the full cpu mask is a reasonable answer to that.
Because it doesn't
On Wed, Sep 25, 2019 at 9:17 AM Adam Ford wrote:
> I tried cma=256M and noticed the cma dump at the beginning didn't
> change. Do we need to setup a reserved-memory node like
> imx6ul-ccimx6ulsom.dtsi did?
I don't think so.
Were you able to identify what was the exact commit that caused such
On Tue, Sep 24, 2019 at 11:27 PM Biwen Li wrote:
>
> > > >
> > > > > > > > > >
> > > > > > > > > > The 'fsl,ippdexpcr-alt-addr' property is used to handle
> > > > > > > > > > an errata
> > > > > > > > > > A-008646 on LS1021A
> > > > > > > > > >
> > > > > > > > > > Signed-off-by: Biwen Li
> > > >
On Wed 25-09-19 12:40:40, Peter Zijlstra wrote:
> On Tue, Sep 24, 2019 at 03:19:39PM +0200, Michal Hocko wrote:
>
> > > The below would get rid of the PMU and workqueue warnings with no
> > > side-effects (the device isn't used for anything except sysfs).
> >
> > Hardcoding to 0 is simply wrong,
On Wed, Sep 25, 2019 at 7:12 AM Fabio Estevam wrote:
>
> Hi Adam,
>
> On Wed, Sep 25, 2019 at 6:38 AM Adam Ford wrote:
>
> > I know it's rather late, but this patch broke the Etnaviv 3D graphics
> > in my i.MX6Q.
> >
> > When I try to use the 3D, it returns some errors and the dmesg log
> >
On Wed, Sep 25, 2019 at 10:36:41AM +0530, Bharata B Rao wrote:
> [The main change in this version is the introduction of new
> locking to prevent concurrent page-in and page-out calls. More
> details about this are present in patch 2/8]
>
> Hi,
>
> A pseries guest can be run as a secure guest on
On Wed, Sep 25, 2019 at 10:36:43AM +0530, Bharata B Rao wrote:
> Manage migration of pages betwen normal and secure memory of secure
> guest by implementing H_SVM_PAGE_IN and H_SVM_PAGE_OUT hcalls.
>
> H_SVM_PAGE_IN: Move the content of a normal page to secure page
> H_SVM_PAGE_OUT: Move the
Hi Adam,
On Wed, Sep 25, 2019 at 6:38 AM Adam Ford wrote:
> I know it's rather late, but this patch broke the Etnaviv 3D graphics
> in my i.MX6Q.
>
> When I try to use the 3D, it returns some errors and the dmesg log
> shows some memory allocation errors too:
> [3.682347] etnaviv etnaviv:
From: Juliet Kim
Date: Fri, 20 Sep 2019 16:11:21 -0400
> This series includes two fixes. The first improves reset code to allow
> linkwatch_event to proceed during reset. The second ensures that no more
> than one thread runs in reset at a time.
>
> v2:
> - Separate change param reset from
On 17/9/19 3:42 am, Alastair D'Silva wrote:
From: Alastair D'Silva
Add OPAL calls for LPC memory alloc/release
Signed-off-by: Alastair D'Silva
This needs rebasing, but apart from that.
Acked-by: Andrew Donnellan
---
arch/powerpc/include/asm/opal-api.h| 4 +++-
On Mon, Jan 21, 2019 at 2:05 AM Mike Rapoport wrote:
>
> Hi,
>
> Current memblock API is quite extensive and, which is more annoying,
> duplicated. Except the low-level functions that allow searching for a free
> memory region and marking it as reserved, memblock provides three (well,
> two and a
On Tue, 2019-09-24 at 03:52:51 UTC, "Aneesh Kumar K.V" wrote:
> The store ordering vs tlbie issue mentioned in
> commit a5d4b5891c2f ("powerpc/mm: Fixup tlbie vs store ordering issue on
> POWER9") is fixed for Nimbus 2.3 and Cumulus 1.3 revisions. We don't need
> to apply the fixup if we are
On Fri, 2019-09-20 at 13:05:22 UTC, Laurent Dufour wrote:
> The PAPR document specifies the TLB Block Invalidate Characteristics which
> tells for each pair of segment base page size, actual page size, the size
> of the block the hcall H_BLOCK_REMOVE supports.
>
> These characteristics are loaded
On Wed, 2019-09-18 at 14:01:03 UTC, "Aneesh Kumar K.V" wrote:
> On failed task initialization due to memory allocation failures,
> we can call into destroy_context with process_tb entry set. This patch
> forces the process_tb entry to zero in destroy_context. With
> this patch, we lose the ability
On Tue, 2019-09-17 at 00:46:04 UTC, Alistair Popple wrote:
> Commit 388cc6e133132 ("KVM: PPC: Book3S HV: Support POWER6
> compatibility mode on POWER7") introduced new macros defining the PCR
> bits. When used from assembly files these definitions lead to build
> errors using older versions of
On Wed, 2019-09-11 at 22:31:55 UTC, Michael Roth wrote:
> On a 2-socket Power9 system with 32 cores/128 threads (SMT4) and 1TB
> of memory running the following guest configs:
...
> To handle both cases, this patch splits kvmppc_set_host_ipi() into
> separate set/clear functions, where we execute
On Wed, 2019-09-04 at 04:55:29 UTC, gromero wrote:
> From: Gustavo Romero
>
> Add TM selftest to check if FP or VEC register values from one process
> can leak into another process when both run on the same CPU.
>
> Signed-off-by: Gustavo Romero
> Signed-off-by: Michael Neuling
Applied to
On Tue, 2019-09-03 at 12:34:51 UTC, "Aneesh Kumar K.V" wrote:
> This simplifies the error handling and also enable us to switch to
> H_SCM_QUERY hcall in a later patch on H_OVERLAP error.
>
> We also do some kernel print formatting fixup in this patch.
>
> Signed-off-by: Aneesh Kumar K.V
On Wed, 2019-08-21 at 10:20:00 UTC, Christophe Leroy wrote:
> In a couple of places there is a need to select whether read-only
> protection of shadow pages is performed with PAGE_KERNEL_RO or with
> PAGE_READONLY.
>
> Add a helper to avoid duplicating the choice.
>
> Signed-off-by: Christophe
On Wed, Sep 25, 2019 at 05:14:20PM +0800, Yunsheng Lin wrote:
> From the discussion above, It seems making the node_to_cpumask_map()
> NUMA_NO_NODE aware is the most feasible way to move forwad.
That's still wrong.
On Tue, Sep 24, 2019 at 03:19:39PM +0200, Michal Hocko wrote:
> > The below would get rid of the PMU and workqueue warnings with no
> > side-effects (the device isn't used for anything except sysfs).
>
> Hardcoding to 0 is simply wrong, if the node0 is cpuless for example...
It doesn't
On 2019/9/24 21:19, Michal Hocko wrote:
> On Tue 24-09-19 14:59:36, Peter Zijlstra wrote:
>> On Tue, Sep 24, 2019 at 02:43:25PM +0200, Peter Zijlstra wrote:
>>> On Tue, Sep 24, 2019 at 02:25:00PM +0200, Michal Hocko wrote:
On Tue 24-09-19 14:09:43, Peter Zijlstra wrote:
>>>
> We can push
On Mon, 23 Sep 2019 17:44:00 +0200
Greg Kurz wrote:
> The XIVE VP is an internal structure which allow the XIVE interrupt
> controller to maintain the interrupt context state of vCPUs non
> dispatched on HW threads.
>
> When a guest is started, the XIVE KVM device allocates a block of
> XIVE
On 10.09.19 18:39, David Hildenbrand wrote:
> We can simply store the pages in a list (page->lru), no need for a
> separate data structure (+ complicated handling). This is how most
> other balloon drivers store allocated pages without additional tracking
> data.
>
> For the notifiers, use
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