Re: [PATCH 10/10] ocxl: Conditionally bind SCM devices to the generic OCXL driver
On Fri, Oct 25, 2019 at 03:47:05PM +1100, Alastair D'Silva wrote: > From: Alastair D'Silva > > This patch allows the user to bind OpenCAPI SCM devices to the generic OCXL > driver. This completely misses any explanation of why you'd want that. The what is rather obvious from the patch. > +config OCXL_SCM_GENERIC > + bool "Treat OpenCAPI Storage Class Memory as a generic OpenCAPI device" > + default n n is the default default.
Re: Onboard SD card doesn't work anymore after the 'mmc-v5.4-2' updates
On Fri, Oct 25, 2019 at 05:28:45PM -0500, Rob Herring wrote: > This doesn't work?: > > if (IS_ENABLED(CONFIG_PPC) || of_dma_is_coherent(dev->of_node)) > value |= ESDHC_DMA_SNOOP; > else > value &= ~ESDHC_DMA_SNOOP; > > While I said use the compatibles, using the kconfig symbol is easier > than sorting out which compatibles are PPC SoCs. Though if that's > already done elsewhere in the driver, you could set a flag and use > that here. I'd be surprised if this was the only difference between > ARM and PPC SoCs for this block. I think the right thing is a Kconfig variable that the architectures selects which says if OF is by default coherent or incoherent, and then use that in of_dma_is_coherent.
Re: [PATCH v2 0/1] pseries/hotplug: Change the default behaviour of cede_offline
"Gautham R. Shenoy" writes: > This is the v2 of the fix to change the default behaviour of > cede_offline. OK, but why keep the cede offline behavior at all? Can we remove it? I think doing so would allow us to remove all the code that temporarily onlines threads for partition migration.
Re: Onboard SD card doesn't work anymore after the 'mmc-v5.4-2' updates
On Wed, Oct 23, 2019 at 9:32 AM Russell King - ARM Linux admin wrote: > > On Wed, Oct 23, 2019 at 08:52:33AM -0500, Rob Herring wrote: > > > I think this should have been done the other way around and default to > > > coherent since most traditional OF platforms are coherent, and you > > > can't just require those DTs to change. > > > > You can blame me. This was really only intended for cases where > > coherency is configurable on a per peripheral basis and can't be > > determined in other ways. > > > > The simple solution here is simply to use the compatible string for > > the device to determine coherent or not. > > It really isn't that simple. This doesn't work?: if (IS_ENABLED(CONFIG_PPC) || of_dma_is_coherent(dev->of_node)) value |= ESDHC_DMA_SNOOP; else value &= ~ESDHC_DMA_SNOOP; While I said use the compatibles, using the kconfig symbol is easier than sorting out which compatibles are PPC SoCs. Though if that's already done elsewhere in the driver, you could set a flag and use that here. I'd be surprised if this was the only difference between ARM and PPC SoCs for this block. > There are two aspects to coherency, both of which must match: > > 1) The configuration of the device > 2) The configuration of the kernel's DMA API > > (1) is controlled by the driver, which can make the decision any way > it pleases. > > (2) on ARM64 is controlled depending on whether or not "dma-coherent" > is specified in the device tree, since ARM64 can have a mixture of > DMA coherent and non-coherent devices. > > A mismatch between (1) and (2) results in data corruption, potentially > eating your filesystem. So, it's very important that the two match. > > These didn't match for the LX2160A, but, due to the way CMA was working, > we sort of got away with it, but it was very dangerous as far as data > safety went. > > Then, a change to CMA happened which moved where it was located, which > caused a regression. Reverting the CMA changes didn't seem to be an > option, so another solution had to be found. > > I started a discussion on how best to solve this: > > https://archive.armlinux.org.uk/lurker/thread/20190919.041320.1e53541f.en.html > > and the solution that the discussion came out with was the one that has > been merged - which we now know caused a regression on PPC. > > Using compatible strings doesn't solve the issue: there is no way to > tell the DMA API from the driver that the device is coherent. The > only way to do that is via the "dma-coherent" property in DT on ARM64. > > To say that this is a mess is an under-statement, but we seem to have > ended up here because of a series of piece-meal changes that don't seem > to have been thought through enough. > > So, what's the right way to solve this, and ensure that the DMA API and > device match as far as their coherency expectations go? Revert all the > changes for sdhci-of-esdhc and CMA back to 5.0 or 5.1 state? The other option is similar to earlier in the thread and just add to of_dma_is_coherent(): /* Powerpc is normally cache coherent DMA */ if (IS_ENABLED(CONFIG_PPC) && !IS_ENABLED(CONFIG_NOT_COHERENT_CACHE)) return true; We could do the all the weak arch hooks, but that seems like overkill to me at this point. Rob
Re: [PATCH V2] ASoC: fsl_asrc: refine the setting of internal clock divider
On Fri, Oct 25, 2019 at 03:13:22PM +0800, Shengjiu Wang wrote:
> The output divider should align with the output sample
> rate, if use ideal sample rate, there will be a lot of overload,
> which would cause underrun.
>
> The maximum divider of asrc clock is 1024, but there is no
> judgement for this limitaion in driver, which may cause the divider
typo: "limitaion" => "limitation"
> setting not correct.
>
> For non-ideal ratio mode, the clock rate should divide the sample
> rate with no remainder, and the quotient should be less than 1024.
>
> Signed-off-by: Shengjiu Wang
And some comments inline. Please add my ack once they are fixed:
Acked-by: Nicolin Chen
Thanks
> diff --git a/sound/soc/fsl/fsl_asrc.c b/sound/soc/fsl/fsl_asrc.c
> index 0bf91a6f54b9..89cf333154c7 100644
> --- a/sound/soc/fsl/fsl_asrc.c
> +++ b/sound/soc/fsl/fsl_asrc.c
> @@ -259,8 +259,11 @@ static int fsl_asrc_set_ideal_ratio(struct fsl_asrc_pair
> *pair,
> * It configures those ASRC registers according to a configuration instance
> * of struct asrc_config which includes in/output sample rate, width, channel
> * and clock settings.
> + *
> + * Note:
> + * use_ideal_rate = true is need by some case which need higher performance.
I feel we can have a detailed one here and drop those inline comments, e.g.:
+ * Note:
+ * The ideal ratio configuration can work with a flexible clock rate setting.
+ * Using IDEAL_RATIO_RATE gives a faster converting speed but overloads ASRC.
+ * For a regular audio playback, the clock rate should not be slower than an
+ * clock rate aligning with the output sample rate; For a use case requiring
+ * faster conversion, set use_ideal_rate to have the faster speed.
> @@ -351,8 +355,10 @@ static int fsl_asrc_config_pair(struct fsl_asrc_pair
> *pair)
> /* We only have output clock for ideal ratio mode */
> clk = asrc_priv->asrck_clk[clk_index[ideal ? OUT : IN]];
>
> - div[IN] = clk_get_rate(clk) / inrate;
> - if (div[IN] == 0) {
> + clk_rate = clk_get_rate(clk);
> + rem[IN] = do_div(clk_rate, inrate);
> + div[IN] = (u32)clk_rate;
> + if (div[IN] == 0 || (!ideal && (div[IN] > 1024 || rem[IN] != 0))) {
Should have some comments to explain this like:
/*
* The divider range is [1, 1024], defined by the hardware. For non-
* ideal ratio configuration, clock rate has to be strictly aligned
* with the sample rate. For ideal ratio configuration, clock rates
* only result in different converting speeds. So remainder does not
* matter, as long as we keep the divider within its valid range.
*/
> pair_err("failed to support input sample rate %dHz by
> asrck_%x\n",
> inrate, clk_index[ideal ? OUT : IN]);
> return -EINVAL;
And move the min() behind this if-condition with no more comments:
+ div[IN] = min_t(u32, 1024, div[IN]);
> @@ -360,18 +366,29 @@ static int fsl_asrc_config_pair(struct fsl_asrc_pair
> *pair)
>
> clk = asrc_priv->asrck_clk[clk_index[OUT]];
>
> - /* Use fixed output rate for Ideal Ratio mode (INCLK_NONE) */
> - if (ideal)
> - div[OUT] = clk_get_rate(clk) / IDEAL_RATIO_RATE;
> + /*
> + * Output rate should be align with the out samplerate. If set too
> + * high output rate, there will be lots of Overload.
> + * But some case need higher performance, then we can use
> + * IDEAL_RATIO_RATE specifically for such case.
> + */
Can drop this since we have the detailed comments at the top.
> + clk_rate = clk_get_rate(clk);
> + if (ideal && use_ideal_rate)
> + rem[OUT] = do_div(clk_rate, IDEAL_RATIO_RATE);
> else
> - div[OUT] = clk_get_rate(clk) / outrate;
> + rem[OUT] = do_div(clk_rate, outrate);
> + div[OUT] = clk_rate;
>
> - if (div[OUT] == 0) {
And add before this if-condition:
/* Output divider has the same limitation as the input one */
> + if (div[OUT] == 0 || (!ideal && (div[OUT] > 1024 || rem[OUT] != 0))) {
> pair_err("failed to support output sample rate %dHz by
> asrck_%x\n",
> outrate, clk_index[OUT]);
> return -EINVAL;
> }
>
> + /* Divider range is [1, 1024] */
Can drop this too.
> + div[IN] = min_t(u32, 1024, div[IN]);
> + div[OUT] = min_t(u32, 1024, div[OUT]);
Re: [PATCH V2] ASoC: fsl_esai: Add spin lock to protect reset, stop and start
On Fri, Oct 25, 2019 at 03:13:53PM +0800, Shengjiu Wang wrote:
> xrun may happen at the end of stream, the
> trigger->fsl_esai_trigger_stop maybe called in the middle of
> fsl_esai_hw_reset, this may cause esai in wrong state
> after stop, and there may be endless xrun interrupt.
>
> This issue may also happen with trigger->fsl_esai_trigger_start.
>
> So Add spin lock to lock those functions.
>
> Fixes: 7ccafa2b3879 ("ASoC: fsl_esai: recover the channel swap after xrun")
> Signed-off-by: Shengjiu Wang
Some small comments inline. Once they are addressed, please add:
Acked-by: Nicolin Chen
Thanks
> ---
> Change in v2
> -add lock for fsl_esai_trigger_start.
>
> sound/soc/fsl/fsl_esai.c | 12
> 1 file changed, 12 insertions(+)
>
> diff --git a/sound/soc/fsl/fsl_esai.c b/sound/soc/fsl/fsl_esai.c
> index 37b14c48b537..9b28e2af26e4 100644
> --- a/sound/soc/fsl/fsl_esai.c
> +++ b/sound/soc/fsl/fsl_esai.c
> @@ -33,6 +33,7 @@
> * @fsysclk: system clock source to derive HCK, SCK and FS
> * @spbaclk: SPBA clock (optional, depending on SoC design)
> * @task: tasklet to handle the reset operation
> + * @lock: spin lock to handle reset and stop behavior
Should be "between hw_reset() and trigger()" now.
> * @fifo_depth: depth of tx/rx FIFO
> * @slot_width: width of each DAI slot
> * @slots: number of slots
> @@ -56,6 +57,7 @@ struct fsl_esai {
> struct clk *fsysclk;
> struct clk *spbaclk;
> struct tasklet_struct task;
> + spinlock_t lock; /* Protect reset and stop */
We can drop the comments here since you add it to the top.
Re: [PATCH v2 0/2] Enabling MSI for Microblaze
On Fri, Oct 25, 2019 at 08:10:36AM +0200, Michal Simek wrote: > Hi, > > these two patches come from discussion with Christoph, Bjorn, Palmer and > Waiman. The first patch was suggestion by Christoph here > https://lore.kernel.org/linux-riscv/20191008154604.ga7...@infradead.org/ > The second part was discussed > https://lore.kernel.org/linux-pci/mhng-5d9bcb53-225e-441f-86cc-b335624b3e7c@palmer-si-x1e/ > and > https://lore.kernel.org/linux-pci/20191017181937.7004-1-pal...@sifive.com/ > > Thanks, > Michal > > Changes in v2: > - Fix typo in commit message s/expect/except/ - Reported-by: Masahiro > > Michal Simek (1): > asm-generic: Make msi.h a mandatory include/asm header > > Palmer Dabbelt (1): > pci: Default to PCI_MSI_IRQ_DOMAIN > > arch/arc/include/asm/Kbuild | 1 - > arch/arm/include/asm/Kbuild | 1 - > arch/arm64/include/asm/Kbuild | 1 - > arch/mips/include/asm/Kbuild| 1 - > arch/powerpc/include/asm/Kbuild | 1 - > arch/riscv/include/asm/Kbuild | 1 - > arch/sparc/include/asm/Kbuild | 1 - > drivers/pci/Kconfig | 2 +- > include/asm-generic/Kbuild | 1 + > 9 files changed, 2 insertions(+), 8 deletions(-) I applied these to pci/msi for v5.5, thanks!
Re: [PATCH v9 2/8] powerpc/ima: add support to initialize ima policy rules
On 10/25/2019 10:02 AM, Nayna Jain wrote:
>> Is there any way to not use conditional compilation in
>> the above array definition? Maybe define different functions to get
>> "secure_rules" for when CONFIG_MODULE_SIG_FORCE is defined and when
>> it is not defined.
>
> How will you decide which function to be called ?
Define the array in the C file:
const char *const secure_rules_kernel_check[] = {
"appraise func=KEXEC_KERNEL_CHECK appraise_type=imasig|modsig",
NULL
};
const char *const secure_rules_kernel_module_check[] = {
"appraise func=KEXEC_KERNEL_CHECK appraise_type=imasig|modsig",
"appraise func=MODULE_CHECK appraise_type=imasig|modsig",
NULL
};
And, in the header file :
extern const char *const secure_rules_kernel_check;
extern const char *const secure_rules_kernel_module_check;
#ifdef CONFIG_MODULE_SIG_FORCE
const char *secure_rules() { return secure_rules_kernel_check; }
#else
const char *secure_rules() { return secure_rules_kernel_module_check;}
#endif // #ifdef CONFIG_MODULE_SIG_FORCE
If you want to avoid duplication, secure_rules_kernel_check and
secure_rules_kernel_module_check could be defined in separate C files
and conditionally compiled (in Makefile).
I was just trying to suggest the guidelines given in
"Section 21) Conditional Compilation" in coding-style.rst.
It says:
Whenever possible don't use preprocessor conditionals (#ifdef, #if) in
.c files;...
Feel free to do what you think is appropriate.
thanks,
-lakshmi
Re: [PATCH v9 7/8] ima: check against blacklisted hashes for files with modsig
On 10/24/19 12:48 PM, Lakshmi Ramasubramanian wrote:
On 10/23/2019 8:47 PM, Nayna Jain wrote:
+/*
+ * ima_check_blacklist - determine if the binary is blacklisted.
+ *
+ * Add the hash of the blacklisted binary to the measurement list,
based
+ * on policy.
+ *
+ * Returns -EPERM if the hash is blacklisted.
+ */
+int ima_check_blacklist(struct integrity_iint_cache *iint,
+ const struct modsig *modsig, int pcr)
+{
+ enum hash_algo hash_algo;
+ const u8 *digest = NULL;
+ u32 digestsize = 0;
+ int rc = 0;
+
+ if (!(iint->flags & IMA_CHECK_BLACKLIST))
+ return 0;
+
+ if (iint->flags & IMA_MODSIG_ALLOWED && modsig) {
+ ima_get_modsig_digest(modsig, &hash_algo, &digest,
&digestsize);
+
+ rc = is_binary_blacklisted(digest, digestsize);
+ if ((rc == -EPERM) && (iint->flags & IMA_MEASURE))
+ process_buffer_measurement(digest, digestsize,
+ "blacklisted-hash", NONE,
+ pcr);
+ }
The enum value "NONE" is being passed to process_buffer_measurement to
indicate that the check for required action based on ima policy is
already done by ima_check_blacklist. Not sure, but this can cause
confusion in the future when someone updates process_buffer_measurement.
As I explained in the response to other patch, the purpose is to
indicate that it is an auxiliary measurement record. By passing func as
NONE, it implies there is no explicit policy to be queried for the
template as it is an additional record for an existing policy and is to
use ima-buf template.
What type of confusion do you mean ?
Thanks & Regards,
- Nayna
Re: [PATCH v9 5/8] ima: make process_buffer_measurement() generic
On 10/25/2019 10:24 AM, Nayna Jain wrote:
On 10/24/19 10:20 AM, Lakshmi Ramasubramanian wrote:
On 10/23/19 8:47 PM, Nayna Jain wrote:
Hi Nayna,
+void process_buffer_measurement(const void *buf, int size,
+ const char *eventname, enum ima_hooks func,
+ int pcr)
{
int ret = 0;
struct ima_template_entry *entry = NULL;
+ if (func) {
+ security_task_getsecid(current, &secid);
+ action = ima_get_action(NULL, current_cred(), secid, 0, func,
+ &pcr, &template);
+ if (!(action & IMA_MEASURE))
+ return;
+ }
In your change set process_buffer_measurement is called with NONE for
the parameter func. So ima_get_action (the above if block) will not be
executed.
Wouldn't it better to update ima_get_action (and related functions) to
handle the ima policy (func param)?
The idea is to use ima-buf template for the auxiliary measurement
record. The auxiliary measurement record is an additional record to the
one already created based on the existing policy. When func is passed as
NONE, it represents it is an additional record. I am not sure what you
mean by updating ima_get_action, it is already handling the ima policy.
I was referring to using "func" in process_buffer_measurement to
determine ima action. In my opinion, process_buffer_measurement should
be generic.
ima_get_action() should instead determine the required ima action,
template, pcr, etc. based on "func" passed to it.
thanks,
-lakshmi
Re: [PATCH v9 5/8] ima: make process_buffer_measurement() generic
On 10/24/19 10:20 AM, Lakshmi Ramasubramanian wrote:
On 10/23/19 8:47 PM, Nayna Jain wrote:
Hi Nayna,
+void process_buffer_measurement(const void *buf, int size,
+ const char *eventname, enum ima_hooks func,
+ int pcr)
{
int ret = 0;
struct ima_template_entry *entry = NULL;
+ if (func) {
+ security_task_getsecid(current, &secid);
+ action = ima_get_action(NULL, current_cred(), secid, 0, func,
+ &pcr, &template);
+ if (!(action & IMA_MEASURE))
+ return;
+ }
In your change set process_buffer_measurement is called with NONE for
the parameter func. So ima_get_action (the above if block) will not be
executed.
Wouldn't it better to update ima_get_action (and related functions) to
handle the ima policy (func param)?
The idea is to use ima-buf template for the auxiliary measurement
record. The auxiliary measurement record is an additional record to the
one already created based on the existing policy. When func is passed as
NONE, it represents it is an additional record. I am not sure what you
mean by updating ima_get_action, it is already handling the ima policy.
Thanks & Regards,
- Nayna
Re: [PATCH v9 2/8] powerpc/ima: add support to initialize ima policy rules
On 10/24/19 12:35 PM, Lakshmi Ramasubramanian wrote:
On 10/23/2019 8:47 PM, Nayna Jain wrote:
+/*
+ * The "secure_rules" are enabled only on "secureboot" enabled systems.
+ * These rules verify the file signatures against known good values.
+ * The "appraise_type=imasig|modsig" option allows the known good
signature
+ * to be stored as an xattr or as an appended signature.
+ *
+ * To avoid duplicate signature verification as much as possible,
the IMA
+ * policy rule for module appraisal is added only if
CONFIG_MODULE_SIG_FORCE
+ * is not enabled.
+ */
+static const char *const secure_rules[] = {
+ "appraise func=KEXEC_KERNEL_CHECK appraise_type=imasig|modsig",
+#ifndef CONFIG_MODULE_SIG_FORCE
+ "appraise func=MODULE_CHECK appraise_type=imasig|modsig",
+#endif
+ NULL
+};
Is there any way to not use conditional compilation in the above array
definition? Maybe define different functions to get "secure_rules" for
when CONFIG_MODULE_SIG_FORCE is defined and when it is not defined.
How will you decide which function to be called ?
Thanks & Regards,
- Nayna
Re: [PATCH v9 1/8] powerpc: detect the secure boot mode of the system
On 10/24/19 12:26 PM, Lakshmi Ramasubramanian wrote:
On 10/23/2019 8:47 PM, Nayna Jain wrote:
This patch defines a function to detect the secure boot state of a
PowerNV system.
+bool is_ppc_secureboot_enabled(void)
+{
+ struct device_node *node;
+ bool enabled = false;
+
+ node = of_find_compatible_node(NULL, NULL, "ibm,secvar-v1");
+ if (!of_device_is_available(node)) {
+ pr_err("Cannot find secure variable node in device tree;
failing to secure state\n");
+ goto out;
Related to "goto out;" above:
Would of_find_compatible_node return NULL if the given node is not found?
If of_device_is_available returns false (say, because node is NULL or
it does not find the specified node) would it be correct to call
of_node_put?
of_node_put() handles NULL.
Thanks & Regards,
- Nayna
Re: [PATCH v9 3/8] powerpc: detect the trusted boot state of the system
On 10/24/19 12:38 PM, Lakshmi Ramasubramanian wrote:
On 10/23/2019 8:47 PM, Nayna Jain wrote:
+bool is_ppc_trustedboot_enabled(void)
+{
+ struct device_node *node;
+ bool enabled = false;
+
+ node = get_ppc_fw_sb_node();
+ enabled = of_property_read_bool(node, "trusted-enabled");
Can get_ppc_fw_sb_node return NULL?
Would of_property_read_bool handle the case when node is NULL?
Yes.
Thanks & Regards,
- Nayna
Re: Oxford Semiconductor Ltd OX16PCI954 - weird dmesg
On Fri, Oct 25, 2019 at 04:33:13PM +0200, Carlo Pisani wrote: > pci_bus :00: root bus resource [mem 0x5000-0x5fff] > pci_bus :00: root bus resource [io 0x1880-0x188f] > pci_bus :00: root bus resource [??? 0x flags 0x0] > pci_bus :00: No busn resource found for root bus, will use [bus 00-ff] > pci :00:00.0: [Firmware Bug]: reg 0x14: invalid BAR (can't size) > pci :00:00.0: [Firmware Bug]: reg 0x18: invalid BAR (can't size) > pci :00:04.0: BAR 0: assigned [mem 0x5000-0x5000] > pci :00:05.0: BAR 1: assigned [mem 0x5001-0x50010fff] > pci :00:05.0: BAR 3: assigned [mem 0x50011000-0x50011fff] > pci :00:0a.0: BAR 1: assigned [mem 0x50012000-0x50012fff] > pci :00:0a.0: BAR 3: assigned [mem 0x50013000-0x50013fff] > pci :00:02.0: BAR 0: assigned [io 0x1880-0x188000ff] > pci :00:02.0: BAR 1: assigned [mem 0x50014000-0x500140ff] > pci :00:03.0: BAR 0: assigned [io 0x18800400-0x188004ff] > pci :00:03.0: BAR 1: assigned [mem 0x50014100-0x500141ff] > pci :00:05.0: BAR 0: assigned [io 0x18800800-0x1880081f] > pci :00:05.0: BAR 2: assigned [io 0x18800820-0x1880083f] > pci :00:0a.0: BAR 0: assigned [io 0x18800840-0x1880085f] > pci :00:0a.0: BAR 2: assigned [io 0x18800860-0x1880087f] > > > 00:00.0 Non-VGA unclassified device: Integrated Device Technology, > Inc. Device > Subsystem: Device 0214:011d > Flags: bus master, 66MHz, medium devsel, latency 60, IRQ 140 > Memory at (32-bit, prefetchable) > I/O ports at > I/O ports at > > 00:02.0 Ethernet controller: VIA Technologies, Inc. VT6105/VT6106S > [Rhine-III] (rev 86) > Subsystem: AST Research Inc Device 086c > Flags: bus master, stepping, medium devsel, latency 64, IRQ 142 > I/O ports at 1880 [size=256] > Memory at 50014000 (32-bit, non-prefetchable) [size=256] > Capabilities: [40] Power Management version 2 > Kernel driver in use: via-rhine > > 00:03.0 Ethernet controller: VIA Technologies, Inc. VT6105/VT6106S > [Rhine-III] (rev 86) > Subsystem: AST Research Inc Device 086c > Flags: bus master, stepping, medium devsel, latency 64, IRQ 143 > I/O ports at 18800400 [size=256] > Memory at 50014100 (32-bit, non-prefetchable) [size=256] > Capabilities: [40] Power Management version 2 > Kernel driver in use: via-rhine > > 00:04.0 Network controller: Atheros Communications Inc. Device 0029 (rev 01) > Subsystem: Atheros Communications Inc. Device 2091 > Flags: bus master, 66MHz, medium devsel, latency 168, IRQ 142 > Memory at 5000 (32-bit, non-prefetchable) [size=64K] > Capabilities: [44] Power Management version 2 > Kernel driver in use: ath9k > > 00:05.0 Serial controller: Oxford Semiconductor Ltd OX16PCI954 (Quad > 16950 UART) function 0 (Uart) (rev 01) (prog-if 06 [) > Subsystem: Oxford Semiconductor Ltd Device > Flags: medium devsel, IRQ 143 > I/O ports at 18800800 [size=32] > Memory at 5001 (32-bit, non-prefetchable) [size=4K] > I/O ports at 18800820 [size=32] > Memory at 50011000 (32-bit, non-prefetchable) [size=4K] > Capabilities: [40] Power Management version 2 > Kernel driver in use: serial > > 00:05.1 Non-VGA unclassified device: Oxford Semiconductor Ltd > OX16PCI954 (Quad 16950 UART) function 0 (Disabled) (rev 01) > Subsystem: Oxford Semiconductor Ltd Device > Flags: medium devsel, IRQ 143 > I/O ports at [disabled] > I/O ports at [disabled] > I/O ports at [disabled] > Capabilities: [40] Power Management version 2 > > 00:0a.0 Serial controller: Oxford Semiconductor Ltd OX16PCI954 (Quad > 16950 UART) function 0 (Uart) (rev 01) (prog-if 06 [) > Subsystem: Oxford Semiconductor Ltd Device > Flags: medium devsel, IRQ 140 > I/O ports at 18800840 [size=32] > Memory at 50012000 (32-bit, non-prefetchable) [size=4K] > I/O ports at 18800860 [size=32] > Memory at 50013000 (32-bit, non-prefetchable) [size=4K] > Capabilities: [40] Power Management version 2 > Kernel driver in use: serial > > 00:0a.1 Non-VGA unclassified device: Oxford Semiconductor Ltd > OX16PCI954 (Quad 16950 UART) function 0 (Disabled) (rev 01) > Subsystem: Oxford Semiconductor Ltd Device > Flags: medium devsel, IRQ 140 > I/O ports at [disabled] > I/O ports at [disabled] > I/O ports at [disabled] > Capabilities: [40] Power Management version 2 > > > hi guys > I have a couple of miniPCI Oxford Semiconductor Ltd OX16PCI954 cards > installed, and the dmesg looks weird > > espeially these lines > pci_bus :00: root bus resource [mem 0x5000-0x5fff] > pci_bus :00: root bus resource [io 0x1880-0x188f] > pci_bus :00: root bus re
Re: [PATCH v5 4/4] powerpc: load firmware trusted keys/hashes into kernel keyring
On 10/24/19 5:58 PM, Nayna Jain wrote:
+
+/*
+ * Get a certificate list blob from the named secure variable.
+ */
+static __init void *get_cert_list(u8 *key, unsigned long keylen, uint64_t
*size)
+{
+ int rc;
+ void *db;
+
+ rc = secvar_ops->get(key, keylen, NULL, size);
+ if (rc) {
+ pr_err("Couldn't get size: %d\n", rc);
+ return NULL;
+ }
+
+ db = kmalloc(*size, GFP_KERNEL);
Is there a MIN\MAX limit on size that should be validated here before
memory allocation?
+ if (!db)
+ return NULL;
+
+ rc = secvar_ops->get(key, keylen, db, size);
+ if (rc) {
+ kfree(db);
+ pr_err("Error reading db var: %d\n", rc);
+ return NULL;
nit: set db to NULL and return from the end of the function.
+ }
+
+ return db;
+}
Re: [PATCH v5 2/4] powerpc: expose secure variables to userspace via sysfs
On 10/24/19 5:47 PM, Nayna Jain wrote:
+static ssize_t size_show(struct kobject *kobj, struct kobj_attribute *attr,
+char *buf)
+{
+ uint64_t dsize;
+ int rc;
+
+ rc = secvar_ops->get(kobj->name, strlen(kobj->name) + 1, NULL, &dsize);
+ if (rc) {
+ pr_err("Error retrieving variable size %d\n", rc);
+ return rc;
+ }
+
+ rc = sprintf(buf, "%llu\n", dsize);
+
+ return rc;
+}
nit: change it to "return sprintf(buf, "%llu\n", dsize);" instead.
+
+static ssize_t data_read(struct file *filep, struct kobject *kobj,
+struct bin_attribute *attr, char *buf, loff_t off,
+size_t count)
+{
+ uint64_t dsize;
+ char *data;
+ int rc;
+
+ rc = secvar_ops->get(kobj->name, strlen(kobj->name) + 1, NULL, &dsize);
+ if (rc) {
+ pr_err("Error getting variable size %d\n", rc);
+ return rc;
+ }
+ pr_debug("dsize is %llu\n", dsize);
+
+ data = kzalloc(dsize, GFP_KERNEL);
Is there any MAX\MIN limit on dsize that can be returned by secvar_ops?
Is it ok to not validate the dsize
+
+static ssize_t update_write(struct file *filep, struct kobject *kobj,
+ struct bin_attribute *attr, char *buf, loff_t off,
+ size_t count)
+{
+ int rc;
+
+ pr_debug("count is %ld\n", count);
+ rc = secvar_ops->set(kobj->name, strlen(kobj->name)+1, buf, count);
+ if (rc) {
+ pr_err("Error setting the variable %s\n", kobj->name);
+ return rc;
+ }
+
+ return count;
+}
Return value from this function can be a count (of bytes in buf?) or
error code. Could cause confusion.
+
+static int secvar_sysfs_load(void)
+{
+ char *name;
+ uint64_t namesize = 0;
+ struct kobject *kobj;
+ int rc;
+
+ name = kzalloc(NAME_MAX_SIZE, GFP_KERNEL);
+ if (!name)
+ return -ENOMEM;
+
+ do {
+ rc = secvar_ops->get_next(name, &namesize, NAME_MAX_SIZE);
+ if (rc) {
+ if (rc != -ENOENT)
+ pr_err("error getting secvar from firmware
%d\n",
+ rc);
+ break;
+ }
+
+ kobj = kzalloc(sizeof(*kobj), GFP_KERNEL);
+ if (!kobj)
+ return -ENOMEM;
Memory allocated for "name" is leaked in this case.
+
+ kobject_init(kobj, &secvar_ktype);
+
+ rc = kobject_add(kobj, &secvar_kset->kobj, "%s", name);
+ if (rc) {
+ pr_warn("kobject_add error %d for attribute: %s\n", rc,
+ name);
+ kobject_put(kobj);
+ kobj = NULL;
+ }
+
+ if (kobj)
+ kobject_uevent(kobj, KOBJ_ADD);
+
+ } while (!rc);
+
+ kfree(name);
+ return rc;
+}
Re: [PATCH v5 1/4] powerpc/powernv: Add OPAL API interface to access secure variable
On 10/24/19 5:47 PM, Nayna Jain wrote:
diff --git a/arch/powerpc/include/asm/opal-api.h
b/arch/powerpc/include/asm/opal-api.h
index 378e3997845a..c1f25a760eb1 100644
--- a/arch/powerpc/include/asm/opal-api.h
+++ b/arch/powerpc/include/asm/opal-api.h
@@ -211,7 +211,10 @@
#define OPAL_MPIPL_UPDATE 173
#define OPAL_MPIPL_REGISTER_TAG 174
#define OPAL_MPIPL_QUERY_TAG 175
-#define OPAL_LAST 175
+#define OPAL_SECVAR_GET176
+#define OPAL_SECVAR_GET_NEXT 177
+#define OPAL_SECVAR_ENQUEUE_UPDATE 178
+#define OPAL_LAST 178
Adjust indentation in the above #defines.
diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h
index a0cf8fba4d12..9986ac34b8e2 100644
--- a/arch/powerpc/include/asm/opal.h
+++ b/arch/powerpc/include/asm/opal.h
@@ -298,6 +298,13 @@ int opal_sensor_group_clear(u32 group_hndl, int token);
int opal_sensor_group_enable(u32 group_hndl, int token, bool enable);
int opal_nx_coproc_init(uint32_t chip_id, uint32_t ct);
+int opal_secvar_get(const char *key, uint64_t key_len, u8 *data,
+ uint64_t *data_size);
+int opal_secvar_get_next(const char *key, uint64_t *key_len,
+uint64_t key_buf_size);
+int opal_secvar_enqueue_update(const char *key, uint64_t key_len, u8 *data,
+ uint64_t data_size);
+
Fix alignment of the parameters in the 2nd line.
Same comment in a few other files in this change set.
+
+static int opal_get_variable(const char *key, uint64_t ksize,
+u8 *data, uint64_t *dsize)
+{
+ int rc;
+
+ if (!key || !dsize)
+ return -EINVAL;
+
+ *dsize = cpu_to_be64(*dsize);
+
+ rc = opal_secvar_get(key, ksize, data, dsize);
+
+ *dsize = be64_to_cpu(*dsize);
Is it ok to update dsize even if return code (rc) from opal_secvar_get
is an error? Just wanted to confirm.
+
+ *keylen = cpu_to_be64(*keylen);
+
+ rc = opal_secvar_get_next(key, keylen, keybufsize);
+
+ *keylen = be64_to_cpu(*keylen);
Same comment as above.
+
+ set_secvar_ops(&opal_secvar_ops);
Does this set function return status?
+
+ return 0;
+}
Re: [PATCH 1/5] crypto: nx - Improve debugfs_create_u{32,64}() handling for atomics
On Mon, Oct 21, 2019 at 04:51:45PM +0200, Geert Uytterhoeven wrote:
> Variables of type atomic{,64}_t can be used fine with
> debugfs_create_u{32,64}, when passing a pointer to the embedded counter.
> This allows to get rid of the casts, which prevented compiler checks.
>
> Signed-off-by: Geert Uytterhoeven
> ---
> drivers/crypto/nx/nx_debugfs.c | 18 +-
> 1 file changed, 9 insertions(+), 9 deletions(-)
Patch applied. Thanks.
--
Email: Herbert Xu
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
Re: [PATCH v2 0/3] crypto: powerpc - convert SPE AES algorithms to skcipher API
On Mon, Oct 14, 2019 at 07:45:14PM -0700, Eric Biggers wrote: > This series converts the glue code for the PowerPC SPE implementations > of AES-ECB, AES-CBC, AES-CTR, and AES-XTS from the deprecated > "blkcipher" API to the "skcipher" API. This is needed in order for the > blkcipher API to be removed. > > Patch 1-2 are fixes. Patch 3 is the actual conversion. > > Tested with: > > export ARCH=powerpc CROSS_COMPILE=powerpc-linux-gnu- > make mpc85xx_defconfig > cat >> .config << EOF > # CONFIG_MODULES is not set > # CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set > CONFIG_DEBUG_KERNEL=y > CONFIG_CRYPTO_MANAGER_EXTRA_TESTS=y > CONFIG_CRYPTO_AES=y > CONFIG_CRYPTO_CBC=y > CONFIG_CRYPTO_CTR=y > CONFIG_CRYPTO_ECB=y > CONFIG_CRYPTO_XTS=y > CONFIG_CRYPTO_AES_PPC_SPE=y > EOF > make olddefconfig > make -j32 > qemu-system-ppc -M mpc8544ds -cpu e500 -nographic \ > -kernel arch/powerpc/boot/zImage \ > -append cryptomgr.fuzz_iterations=1000 > > Note that xts-ppc-spe still fails the comparison tests due to the lack > of ciphertext stealing support. This is not addressed by this series. > > Changed since v1: > > - Split fixes into separate patches. > > - Made ppc_aes_setkey_skcipher() call ppc_aes_setkey(), rather than > creating a separate expand_key() function. This keeps the code > shorter. > > Eric Biggers (3): > crypto: powerpc - don't unnecessarily use atomic scatterwalk > crypto: powerpc - don't set ivsize for AES-ECB > crypto: powerpc - convert SPE AES algorithms to skcipher API > > arch/powerpc/crypto/aes-spe-glue.c | 389 - > crypto/Kconfig | 1 + > 2 files changed, 166 insertions(+), 224 deletions(-) All applied. Thanks. -- Email: Herbert Xu Home Page: http://gondor.apana.org.au/~herbert/ PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
Re: [PATCH -next 00/13] hwrng: use devm_platform_ioremap_resource() to simplify code
On Wed, Oct 16, 2019 at 06:46:08PM +0800, YueHaibing wrote: > devm_platform_ioremap_resource() internally have platform_get_resource() > and devm_ioremap_resource() in it. So instead of calling them separately > use devm_platform_ioremap_resource() directly. > > YueHaibing (13): > hwrng: atmel - use devm_platform_ioremap_resource() to simplify code > hwrng: bcm2835 - use devm_platform_ioremap_resource() to simplify code > hwrng: exynos - use devm_platform_ioremap_resource() to simplify code > hwrng: hisi - use devm_platform_ioremap_resource() to simplify code > hwrng: ks-sa - use devm_platform_ioremap_resource() to simplify code > hwrng: meson - use devm_platform_ioremap_resource() to simplify code > hwrng: npcm - use devm_platform_ioremap_resource() to simplify code > hwrng: omap - use devm_platform_ioremap_resource() to simplify code > hwrng: pasemi - use devm_platform_ioremap_resource() to simplify code > hwrng: pic32 - use devm_platform_ioremap_resource() to simplify code > hwrng: st - use devm_platform_ioremap_resource() to simplify code > hwrng: tx4939 - use devm_platform_ioremap_resource() to simplify code > hwrng: xgene - use devm_platform_ioremap_resource() to simplify code > > drivers/char/hw_random/atmel-rng.c | 4 +--- > drivers/char/hw_random/bcm2835-rng.c | 5 + > drivers/char/hw_random/exynos-trng.c | 4 +--- > drivers/char/hw_random/hisi-rng.c| 4 +--- > drivers/char/hw_random/ks-sa-rng.c | 4 +--- > drivers/char/hw_random/meson-rng.c | 4 +--- > drivers/char/hw_random/npcm-rng.c| 4 +--- > drivers/char/hw_random/omap-rng.c| 4 +--- > drivers/char/hw_random/pasemi-rng.c | 4 +--- > drivers/char/hw_random/pic32-rng.c | 4 +--- > drivers/char/hw_random/st-rng.c | 4 +--- > drivers/char/hw_random/tx4939-rng.c | 4 +--- > drivers/char/hw_random/xgene-rng.c | 4 +--- > 13 files changed, 13 insertions(+), 40 deletions(-) All applied. Thanks. -- Email: Herbert Xu Home Page: http://gondor.apana.org.au/~herbert/ PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
Oxford Semiconductor Ltd OX16PCI954 - weird dmesg
pci_bus :00: root bus resource [mem 0x5000-0x5fff] pci_bus :00: root bus resource [io 0x1880-0x188f] pci_bus :00: root bus resource [??? 0x flags 0x0] pci_bus :00: No busn resource found for root bus, will use [bus 00-ff] pci :00:00.0: [Firmware Bug]: reg 0x14: invalid BAR (can't size) pci :00:00.0: [Firmware Bug]: reg 0x18: invalid BAR (can't size) pci :00:04.0: BAR 0: assigned [mem 0x5000-0x5000] pci :00:05.0: BAR 1: assigned [mem 0x5001-0x50010fff] pci :00:05.0: BAR 3: assigned [mem 0x50011000-0x50011fff] pci :00:0a.0: BAR 1: assigned [mem 0x50012000-0x50012fff] pci :00:0a.0: BAR 3: assigned [mem 0x50013000-0x50013fff] pci :00:02.0: BAR 0: assigned [io 0x1880-0x188000ff] pci :00:02.0: BAR 1: assigned [mem 0x50014000-0x500140ff] pci :00:03.0: BAR 0: assigned [io 0x18800400-0x188004ff] pci :00:03.0: BAR 1: assigned [mem 0x50014100-0x500141ff] pci :00:05.0: BAR 0: assigned [io 0x18800800-0x1880081f] pci :00:05.0: BAR 2: assigned [io 0x18800820-0x1880083f] pci :00:0a.0: BAR 0: assigned [io 0x18800840-0x1880085f] pci :00:0a.0: BAR 2: assigned [io 0x18800860-0x1880087f] 00:00.0 Non-VGA unclassified device: Integrated Device Technology, Inc. Device Subsystem: Device 0214:011d Flags: bus master, 66MHz, medium devsel, latency 60, IRQ 140 Memory at (32-bit, prefetchable) I/O ports at I/O ports at 00:02.0 Ethernet controller: VIA Technologies, Inc. VT6105/VT6106S [Rhine-III] (rev 86) Subsystem: AST Research Inc Device 086c Flags: bus master, stepping, medium devsel, latency 64, IRQ 142 I/O ports at 1880 [size=256] Memory at 50014000 (32-bit, non-prefetchable) [size=256] Capabilities: [40] Power Management version 2 Kernel driver in use: via-rhine 00:03.0 Ethernet controller: VIA Technologies, Inc. VT6105/VT6106S [Rhine-III] (rev 86) Subsystem: AST Research Inc Device 086c Flags: bus master, stepping, medium devsel, latency 64, IRQ 143 I/O ports at 18800400 [size=256] Memory at 50014100 (32-bit, non-prefetchable) [size=256] Capabilities: [40] Power Management version 2 Kernel driver in use: via-rhine 00:04.0 Network controller: Atheros Communications Inc. Device 0029 (rev 01) Subsystem: Atheros Communications Inc. Device 2091 Flags: bus master, 66MHz, medium devsel, latency 168, IRQ 142 Memory at 5000 (32-bit, non-prefetchable) [size=64K] Capabilities: [44] Power Management version 2 Kernel driver in use: ath9k 00:05.0 Serial controller: Oxford Semiconductor Ltd OX16PCI954 (Quad 16950 UART) function 0 (Uart) (rev 01) (prog-if 06 [) Subsystem: Oxford Semiconductor Ltd Device Flags: medium devsel, IRQ 143 I/O ports at 18800800 [size=32] Memory at 5001 (32-bit, non-prefetchable) [size=4K] I/O ports at 18800820 [size=32] Memory at 50011000 (32-bit, non-prefetchable) [size=4K] Capabilities: [40] Power Management version 2 Kernel driver in use: serial 00:05.1 Non-VGA unclassified device: Oxford Semiconductor Ltd OX16PCI954 (Quad 16950 UART) function 0 (Disabled) (rev 01) Subsystem: Oxford Semiconductor Ltd Device Flags: medium devsel, IRQ 143 I/O ports at [disabled] I/O ports at [disabled] I/O ports at [disabled] Capabilities: [40] Power Management version 2 00:0a.0 Serial controller: Oxford Semiconductor Ltd OX16PCI954 (Quad 16950 UART) function 0 (Uart) (rev 01) (prog-if 06 [) Subsystem: Oxford Semiconductor Ltd Device Flags: medium devsel, IRQ 140 I/O ports at 18800840 [size=32] Memory at 50012000 (32-bit, non-prefetchable) [size=4K] I/O ports at 18800860 [size=32] Memory at 50013000 (32-bit, non-prefetchable) [size=4K] Capabilities: [40] Power Management version 2 Kernel driver in use: serial 00:0a.1 Non-VGA unclassified device: Oxford Semiconductor Ltd OX16PCI954 (Quad 16950 UART) function 0 (Disabled) (rev 01) Subsystem: Oxford Semiconductor Ltd Device Flags: medium devsel, IRQ 140 I/O ports at [disabled] I/O ports at [disabled] I/O ports at [disabled] Capabilities: [40] Power Management version 2 hi guys I have a couple of miniPCI Oxford Semiconductor Ltd OX16PCI954 cards installed, and the dmesg looks weird espeially these lines pci_bus :00: root bus resource [mem 0x5000-0x5fff] pci_bus :00: root bus resource [io 0x1880-0x188f] pci_bus :00: root bus resource [??? 0x flags 0x0] pci_bus :00: No busn resource found for root bus, will use [bus 00-ff] pci :00:00.0: [Firmware Bug]: reg 0x14: invalid BAR (can't size) pci :00:00.0: [Firmware Bug]: reg 0x18: invalid BAR (can't size) besides, I am experi
[PATCH AUTOSEL 4.4 04/16] powerpc/pseries/hvconsole: Fix stack overread via udbg
From: Daniel Axtens
[ Upstream commit 934bda59f286d0221f1a3ebab7f5156a996cc37d ]
While developing KASAN for 64-bit book3s, I hit the following stack
over-read.
It occurs because the hypercall to put characters onto the terminal
takes 2 longs (128 bits/16 bytes) of characters at a time, and so
hvc_put_chars() would unconditionally copy 16 bytes from the argument
buffer, regardless of supplied length. However, udbg_hvc_putc() can
call hvc_put_chars() with a single-byte buffer, leading to the error.
==
BUG: KASAN: stack-out-of-bounds in hvc_put_chars+0xdc/0x110
Read of size 8 at addr c23e7a90 by task swapper/0
CPU: 0 PID: 0 Comm: swapper Not tainted
5.2.0-rc2-next-20190528-02824-g048a6ab4835b #113
Call Trace:
dump_stack+0x104/0x154 (unreliable)
print_address_description+0xa0/0x30c
__kasan_report+0x20c/0x224
kasan_report+0x18/0x30
__asan_report_load8_noabort+0x24/0x40
hvc_put_chars+0xdc/0x110
hvterm_raw_put_chars+0x9c/0x110
udbg_hvc_putc+0x154/0x200
udbg_write+0xf0/0x240
console_unlock+0x868/0xd30
register_console+0x970/0xe90
register_early_udbg_console+0xf8/0x114
setup_arch+0x108/0x790
start_kernel+0x104/0x784
start_here_common+0x1c/0x534
Memory state around the buggy address:
c23e7980: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c23e7a00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f1 f1
>c23e7a80: f1 f1 01 f2 f2 f2 00 00 00 00 00 00 00 00 00 00
^
c23e7b00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c23e7b80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
==
Document that a 16-byte buffer is requred, and provide it in udbg.
Signed-off-by: Daniel Axtens
Signed-off-by: Michael Ellerman
Signed-off-by: Sasha Levin
---
arch/powerpc/platforms/pseries/hvconsole.c | 2 +-
drivers/tty/hvc/hvc_vio.c | 16 +++-
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/platforms/pseries/hvconsole.c
b/arch/powerpc/platforms/pseries/hvconsole.c
index 849b29b3e9ae0..954ef27128f22 100644
--- a/arch/powerpc/platforms/pseries/hvconsole.c
+++ b/arch/powerpc/platforms/pseries/hvconsole.c
@@ -62,7 +62,7 @@ EXPORT_SYMBOL(hvc_get_chars);
* @vtermno: The vtermno or unit_address of the adapter from which the data
* originated.
* @buf: The character buffer that contains the character data to send to
- * firmware.
+ * firmware. Must be at least 16 bytes, even if count is less than 16.
* @count: Send this number of characters.
*/
int hvc_put_chars(uint32_t vtermno, const char *buf, int count)
diff --git a/drivers/tty/hvc/hvc_vio.c b/drivers/tty/hvc/hvc_vio.c
index f575a9b5ede7b..1d671d058dcb0 100644
--- a/drivers/tty/hvc/hvc_vio.c
+++ b/drivers/tty/hvc/hvc_vio.c
@@ -122,6 +122,14 @@ static int hvterm_raw_get_chars(uint32_t vtermno, char
*buf, int count)
return got;
}
+/**
+ * hvterm_raw_put_chars: send characters to firmware for given vterm adapter
+ * @vtermno: The virtual terminal number.
+ * @buf: The characters to send. Because of the underlying hypercall in
+ * hvc_put_chars(), this buffer must be at least 16 bytes long, even if
+ * you are sending fewer chars.
+ * @count: number of chars to send.
+ */
static int hvterm_raw_put_chars(uint32_t vtermno, const char *buf, int count)
{
struct hvterm_priv *pv = hvterm_privs[vtermno];
@@ -234,6 +242,7 @@ static const struct hv_ops hvterm_hvsi_ops = {
static void udbg_hvc_putc(char c)
{
int count = -1;
+ unsigned char bounce_buffer[16];
if (!hvterm_privs[0])
return;
@@ -244,7 +253,12 @@ static void udbg_hvc_putc(char c)
do {
switch(hvterm_privs[0]->proto) {
case HV_PROTOCOL_RAW:
- count = hvterm_raw_put_chars(0, &c, 1);
+ /*
+* hvterm_raw_put_chars requires at least a 16-byte
+* buffer, so go via the bounce buffer
+*/
+ bounce_buffer[0] = c;
+ count = hvterm_raw_put_chars(0, bounce_buffer, 1);
break;
case HV_PROTOCOL_HVSI:
count = hvterm_hvsi_put_chars(0, &c, 1);
--
2.20.1
[PATCH AUTOSEL 4.9 05/20] powerpc/pseries/hvconsole: Fix stack overread via udbg
From: Daniel Axtens
[ Upstream commit 934bda59f286d0221f1a3ebab7f5156a996cc37d ]
While developing KASAN for 64-bit book3s, I hit the following stack
over-read.
It occurs because the hypercall to put characters onto the terminal
takes 2 longs (128 bits/16 bytes) of characters at a time, and so
hvc_put_chars() would unconditionally copy 16 bytes from the argument
buffer, regardless of supplied length. However, udbg_hvc_putc() can
call hvc_put_chars() with a single-byte buffer, leading to the error.
==
BUG: KASAN: stack-out-of-bounds in hvc_put_chars+0xdc/0x110
Read of size 8 at addr c23e7a90 by task swapper/0
CPU: 0 PID: 0 Comm: swapper Not tainted
5.2.0-rc2-next-20190528-02824-g048a6ab4835b #113
Call Trace:
dump_stack+0x104/0x154 (unreliable)
print_address_description+0xa0/0x30c
__kasan_report+0x20c/0x224
kasan_report+0x18/0x30
__asan_report_load8_noabort+0x24/0x40
hvc_put_chars+0xdc/0x110
hvterm_raw_put_chars+0x9c/0x110
udbg_hvc_putc+0x154/0x200
udbg_write+0xf0/0x240
console_unlock+0x868/0xd30
register_console+0x970/0xe90
register_early_udbg_console+0xf8/0x114
setup_arch+0x108/0x790
start_kernel+0x104/0x784
start_here_common+0x1c/0x534
Memory state around the buggy address:
c23e7980: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c23e7a00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f1 f1
>c23e7a80: f1 f1 01 f2 f2 f2 00 00 00 00 00 00 00 00 00 00
^
c23e7b00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c23e7b80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
==
Document that a 16-byte buffer is requred, and provide it in udbg.
Signed-off-by: Daniel Axtens
Signed-off-by: Michael Ellerman
Signed-off-by: Sasha Levin
---
arch/powerpc/platforms/pseries/hvconsole.c | 2 +-
drivers/tty/hvc/hvc_vio.c | 16 +++-
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/platforms/pseries/hvconsole.c
b/arch/powerpc/platforms/pseries/hvconsole.c
index 74da18de853af..73ec15cd27080 100644
--- a/arch/powerpc/platforms/pseries/hvconsole.c
+++ b/arch/powerpc/platforms/pseries/hvconsole.c
@@ -62,7 +62,7 @@ EXPORT_SYMBOL(hvc_get_chars);
* @vtermno: The vtermno or unit_address of the adapter from which the data
* originated.
* @buf: The character buffer that contains the character data to send to
- * firmware.
+ * firmware. Must be at least 16 bytes, even if count is less than 16.
* @count: Send this number of characters.
*/
int hvc_put_chars(uint32_t vtermno, const char *buf, int count)
diff --git a/drivers/tty/hvc/hvc_vio.c b/drivers/tty/hvc/hvc_vio.c
index b05dc50866279..8bab8b00d47d6 100644
--- a/drivers/tty/hvc/hvc_vio.c
+++ b/drivers/tty/hvc/hvc_vio.c
@@ -120,6 +120,14 @@ static int hvterm_raw_get_chars(uint32_t vtermno, char
*buf, int count)
return got;
}
+/**
+ * hvterm_raw_put_chars: send characters to firmware for given vterm adapter
+ * @vtermno: The virtual terminal number.
+ * @buf: The characters to send. Because of the underlying hypercall in
+ * hvc_put_chars(), this buffer must be at least 16 bytes long, even if
+ * you are sending fewer chars.
+ * @count: number of chars to send.
+ */
static int hvterm_raw_put_chars(uint32_t vtermno, const char *buf, int count)
{
struct hvterm_priv *pv = hvterm_privs[vtermno];
@@ -232,6 +240,7 @@ static const struct hv_ops hvterm_hvsi_ops = {
static void udbg_hvc_putc(char c)
{
int count = -1;
+ unsigned char bounce_buffer[16];
if (!hvterm_privs[0])
return;
@@ -242,7 +251,12 @@ static void udbg_hvc_putc(char c)
do {
switch(hvterm_privs[0]->proto) {
case HV_PROTOCOL_RAW:
- count = hvterm_raw_put_chars(0, &c, 1);
+ /*
+* hvterm_raw_put_chars requires at least a 16-byte
+* buffer, so go via the bounce buffer
+*/
+ bounce_buffer[0] = c;
+ count = hvterm_raw_put_chars(0, bounce_buffer, 1);
break;
case HV_PROTOCOL_HVSI:
count = hvterm_hvsi_put_chars(0, &c, 1);
--
2.20.1
[PATCH AUTOSEL 4.14 08/25] powerpc/pseries/hvconsole: Fix stack overread via udbg
From: Daniel Axtens
[ Upstream commit 934bda59f286d0221f1a3ebab7f5156a996cc37d ]
While developing KASAN for 64-bit book3s, I hit the following stack
over-read.
It occurs because the hypercall to put characters onto the terminal
takes 2 longs (128 bits/16 bytes) of characters at a time, and so
hvc_put_chars() would unconditionally copy 16 bytes from the argument
buffer, regardless of supplied length. However, udbg_hvc_putc() can
call hvc_put_chars() with a single-byte buffer, leading to the error.
==
BUG: KASAN: stack-out-of-bounds in hvc_put_chars+0xdc/0x110
Read of size 8 at addr c23e7a90 by task swapper/0
CPU: 0 PID: 0 Comm: swapper Not tainted
5.2.0-rc2-next-20190528-02824-g048a6ab4835b #113
Call Trace:
dump_stack+0x104/0x154 (unreliable)
print_address_description+0xa0/0x30c
__kasan_report+0x20c/0x224
kasan_report+0x18/0x30
__asan_report_load8_noabort+0x24/0x40
hvc_put_chars+0xdc/0x110
hvterm_raw_put_chars+0x9c/0x110
udbg_hvc_putc+0x154/0x200
udbg_write+0xf0/0x240
console_unlock+0x868/0xd30
register_console+0x970/0xe90
register_early_udbg_console+0xf8/0x114
setup_arch+0x108/0x790
start_kernel+0x104/0x784
start_here_common+0x1c/0x534
Memory state around the buggy address:
c23e7980: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c23e7a00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f1 f1
>c23e7a80: f1 f1 01 f2 f2 f2 00 00 00 00 00 00 00 00 00 00
^
c23e7b00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c23e7b80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
==
Document that a 16-byte buffer is requred, and provide it in udbg.
Signed-off-by: Daniel Axtens
Signed-off-by: Michael Ellerman
Signed-off-by: Sasha Levin
---
arch/powerpc/platforms/pseries/hvconsole.c | 2 +-
drivers/tty/hvc/hvc_vio.c | 16 +++-
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/platforms/pseries/hvconsole.c
b/arch/powerpc/platforms/pseries/hvconsole.c
index 74da18de853af..73ec15cd27080 100644
--- a/arch/powerpc/platforms/pseries/hvconsole.c
+++ b/arch/powerpc/platforms/pseries/hvconsole.c
@@ -62,7 +62,7 @@ EXPORT_SYMBOL(hvc_get_chars);
* @vtermno: The vtermno or unit_address of the adapter from which the data
* originated.
* @buf: The character buffer that contains the character data to send to
- * firmware.
+ * firmware. Must be at least 16 bytes, even if count is less than 16.
* @count: Send this number of characters.
*/
int hvc_put_chars(uint32_t vtermno, const char *buf, int count)
diff --git a/drivers/tty/hvc/hvc_vio.c b/drivers/tty/hvc/hvc_vio.c
index a1d272ac82bb4..c33150fcd9642 100644
--- a/drivers/tty/hvc/hvc_vio.c
+++ b/drivers/tty/hvc/hvc_vio.c
@@ -120,6 +120,14 @@ static int hvterm_raw_get_chars(uint32_t vtermno, char
*buf, int count)
return got;
}
+/**
+ * hvterm_raw_put_chars: send characters to firmware for given vterm adapter
+ * @vtermno: The virtual terminal number.
+ * @buf: The characters to send. Because of the underlying hypercall in
+ * hvc_put_chars(), this buffer must be at least 16 bytes long, even if
+ * you are sending fewer chars.
+ * @count: number of chars to send.
+ */
static int hvterm_raw_put_chars(uint32_t vtermno, const char *buf, int count)
{
struct hvterm_priv *pv = hvterm_privs[vtermno];
@@ -232,6 +240,7 @@ static const struct hv_ops hvterm_hvsi_ops = {
static void udbg_hvc_putc(char c)
{
int count = -1;
+ unsigned char bounce_buffer[16];
if (!hvterm_privs[0])
return;
@@ -242,7 +251,12 @@ static void udbg_hvc_putc(char c)
do {
switch(hvterm_privs[0]->proto) {
case HV_PROTOCOL_RAW:
- count = hvterm_raw_put_chars(0, &c, 1);
+ /*
+* hvterm_raw_put_chars requires at least a 16-byte
+* buffer, so go via the bounce buffer
+*/
+ bounce_buffer[0] = c;
+ count = hvterm_raw_put_chars(0, bounce_buffer, 1);
break;
case HV_PROTOCOL_HVSI:
count = hvterm_hvsi_put_chars(0, &c, 1);
--
2.20.1
[PATCH AUTOSEL 4.19 13/37] powerpc/pseries/hvconsole: Fix stack overread via udbg
From: Daniel Axtens
[ Upstream commit 934bda59f286d0221f1a3ebab7f5156a996cc37d ]
While developing KASAN for 64-bit book3s, I hit the following stack
over-read.
It occurs because the hypercall to put characters onto the terminal
takes 2 longs (128 bits/16 bytes) of characters at a time, and so
hvc_put_chars() would unconditionally copy 16 bytes from the argument
buffer, regardless of supplied length. However, udbg_hvc_putc() can
call hvc_put_chars() with a single-byte buffer, leading to the error.
==
BUG: KASAN: stack-out-of-bounds in hvc_put_chars+0xdc/0x110
Read of size 8 at addr c23e7a90 by task swapper/0
CPU: 0 PID: 0 Comm: swapper Not tainted
5.2.0-rc2-next-20190528-02824-g048a6ab4835b #113
Call Trace:
dump_stack+0x104/0x154 (unreliable)
print_address_description+0xa0/0x30c
__kasan_report+0x20c/0x224
kasan_report+0x18/0x30
__asan_report_load8_noabort+0x24/0x40
hvc_put_chars+0xdc/0x110
hvterm_raw_put_chars+0x9c/0x110
udbg_hvc_putc+0x154/0x200
udbg_write+0xf0/0x240
console_unlock+0x868/0xd30
register_console+0x970/0xe90
register_early_udbg_console+0xf8/0x114
setup_arch+0x108/0x790
start_kernel+0x104/0x784
start_here_common+0x1c/0x534
Memory state around the buggy address:
c23e7980: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c23e7a00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f1 f1
>c23e7a80: f1 f1 01 f2 f2 f2 00 00 00 00 00 00 00 00 00 00
^
c23e7b00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c23e7b80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
==
Document that a 16-byte buffer is requred, and provide it in udbg.
Signed-off-by: Daniel Axtens
Signed-off-by: Michael Ellerman
Signed-off-by: Sasha Levin
---
arch/powerpc/platforms/pseries/hvconsole.c | 2 +-
drivers/tty/hvc/hvc_vio.c | 16 +++-
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/platforms/pseries/hvconsole.c
b/arch/powerpc/platforms/pseries/hvconsole.c
index 74da18de853af..73ec15cd27080 100644
--- a/arch/powerpc/platforms/pseries/hvconsole.c
+++ b/arch/powerpc/platforms/pseries/hvconsole.c
@@ -62,7 +62,7 @@ EXPORT_SYMBOL(hvc_get_chars);
* @vtermno: The vtermno or unit_address of the adapter from which the data
* originated.
* @buf: The character buffer that contains the character data to send to
- * firmware.
+ * firmware. Must be at least 16 bytes, even if count is less than 16.
* @count: Send this number of characters.
*/
int hvc_put_chars(uint32_t vtermno, const char *buf, int count)
diff --git a/drivers/tty/hvc/hvc_vio.c b/drivers/tty/hvc/hvc_vio.c
index 59eaa620bf13a..80fd06fbd712a 100644
--- a/drivers/tty/hvc/hvc_vio.c
+++ b/drivers/tty/hvc/hvc_vio.c
@@ -107,6 +107,14 @@ static int hvterm_raw_get_chars(uint32_t vtermno, char
*buf, int count)
return got;
}
+/**
+ * hvterm_raw_put_chars: send characters to firmware for given vterm adapter
+ * @vtermno: The virtual terminal number.
+ * @buf: The characters to send. Because of the underlying hypercall in
+ * hvc_put_chars(), this buffer must be at least 16 bytes long, even if
+ * you are sending fewer chars.
+ * @count: number of chars to send.
+ */
static int hvterm_raw_put_chars(uint32_t vtermno, const char *buf, int count)
{
struct hvterm_priv *pv = hvterm_privs[vtermno];
@@ -219,6 +227,7 @@ static const struct hv_ops hvterm_hvsi_ops = {
static void udbg_hvc_putc(char c)
{
int count = -1;
+ unsigned char bounce_buffer[16];
if (!hvterm_privs[0])
return;
@@ -229,7 +238,12 @@ static void udbg_hvc_putc(char c)
do {
switch(hvterm_privs[0]->proto) {
case HV_PROTOCOL_RAW:
- count = hvterm_raw_put_chars(0, &c, 1);
+ /*
+* hvterm_raw_put_chars requires at least a 16-byte
+* buffer, so go via the bounce buffer
+*/
+ bounce_buffer[0] = c;
+ count = hvterm_raw_put_chars(0, bounce_buffer, 1);
break;
case HV_PROTOCOL_HVSI:
count = hvterm_hvsi_put_chars(0, &c, 1);
--
2.20.1
[PATCH AUTOSEL 4.19 11/37] KVM: PPC: Book3S HV: Fix lockdep warning when entering the guest
From: Alexey Kardashevskiy
[ Upstream commit 3309bec85e60d60d6394802cb8e183a4f4a72def ]
The trace_hardirqs_on() sets current->hardirqs_enabled and from here
the lockdep assumes interrupts are enabled although they are remain
disabled until the context switches to the guest. Consequent
srcu_read_lock() checks the flags in rcu_lock_acquire(), observes
disabled interrupts and prints a warning (see below).
This moves trace_hardirqs_on/off closer to __kvmppc_vcore_entry to
prevent lockdep from being confused.
DEBUG_LOCKS_WARN_ON(current->hardirqs_enabled)
WARNING: CPU: 16 PID: 8038 at kernel/locking/lockdep.c:4128
check_flags.part.25+0x224/0x280
[...]
NIP [c0185b84] check_flags.part.25+0x224/0x280
LR [c0185b80] check_flags.part.25+0x220/0x280
Call Trace:
[c03fec253710] [c0185b80] check_flags.part.25+0x220/0x280
(unreliable)
[c03fec253780] [c0187ea4] lock_acquire+0x94/0x260
[c03fec253840] [c0081a1e9768] kvmppc_run_core+0xa60/0x1ab0 [kvm_hv]
[c03fec253a10] [c0081a1ed944] kvmppc_vcpu_run_hv+0x73c/0xec0 [kvm_hv]
[c03fec253ae0] [c0081a1095dc] kvmppc_vcpu_run+0x34/0x48 [kvm]
[c03fec253b00] [c0081a1056bc] kvm_arch_vcpu_ioctl_run+0x2f4/0x400 [kvm]
[c03fec253b90] [c0081a0f3618] kvm_vcpu_ioctl+0x460/0x850 [kvm]
[c03fec253d00] [c041c4f4] do_vfs_ioctl+0xe4/0x930
[c03fec253db0] [c041ce04] ksys_ioctl+0xc4/0x110
[c03fec253e00] [c041ce78] sys_ioctl+0x28/0x80
[c03fec253e20] [c000b5a4] system_call+0x5c/0x70
Instruction dump:
419e0034 3d220004 39291730 8129 2f89 409e0020 3c82ffc6 3c62ffc5
3884be70 386329c0 4bf6ea71 6000 <0fe0> 3c62ffc6 3863be90 4801273d
irq event stamp: 1025
hardirqs last enabled at (1025): []
kvmppc_run_core+0xa20/0x1ab0 [kvm_hv]
hardirqs last disabled at (1024): []
kvmppc_run_core+0x650/0x1ab0 [kvm_hv]
softirqs last enabled at (0): []
copy_process.isra.4.part.5+0x5f0/0x1d00
softirqs last disabled at (0): [<>] (null)
---[ end trace 31180adcc848993e ]---
possible reason: unannotated irqs-off.
irq event stamp: 1025
hardirqs last enabled at (1025): []
kvmppc_run_core+0xa20/0x1ab0 [kvm_hv]
hardirqs last disabled at (1024): []
kvmppc_run_core+0x650/0x1ab0 [kvm_hv]
softirqs last enabled at (0): []
copy_process.isra.4.part.5+0x5f0/0x1d00
softirqs last disabled at (0): [<>] (null)
Fixes: 8b24e69fc47e ("KVM: PPC: Book3S HV: Close race with testing for signals
on guest entry", 2017-06-26)
Signed-off-by: Alexey Kardashevskiy
Signed-off-by: Paul Mackerras
Signed-off-by: Sasha Levin
---
arch/powerpc/kvm/book3s_hv.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index 3ae3e8d141e3e..dbfe32327212e 100644
--- a/arch/powerpc/kvm/book3s_hv.c
+++ b/arch/powerpc/kvm/book3s_hv.c
@@ -2993,25 +2993,26 @@ static noinline void kvmppc_run_core(struct
kvmppc_vcore *vc)
}
}
- /*
-* Interrupts will be enabled once we get into the guest,
-* so tell lockdep that we're about to enable interrupts.
-*/
- trace_hardirqs_on();
-
guest_enter_irqoff();
srcu_idx = srcu_read_lock(&vc->kvm->srcu);
this_cpu_disable_ftrace();
+ /*
+* Interrupts will be enabled once we get into the guest,
+* so tell lockdep that we're about to enable interrupts.
+*/
+ trace_hardirqs_on();
+
trap = __kvmppc_vcore_entry();
+ trace_hardirqs_off();
+
this_cpu_enable_ftrace();
srcu_read_unlock(&vc->kvm->srcu, srcu_idx);
- trace_hardirqs_off();
set_irq_happened(trap);
spin_lock(&vc->lock);
--
2.20.1
[PATCH v2 22/23] soc/fsl/qe/qe.h: remove include of asm/cpm.h
asm/cpm.h only exists on PPC, so this prevents use of this header on other platforms. Drivers that need asm/cpm.h (and are thus inherently PPC-specific) must include that explicitly. Signed-off-by: Rasmus Villemoes --- include/soc/fsl/qe/qe.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/soc/fsl/qe/qe.h b/include/soc/fsl/qe/qe.h index c1036d16ed03..3768c226490e 100644 --- a/include/soc/fsl/qe/qe.h +++ b/include/soc/fsl/qe/qe.h @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include -- 2.23.0
[PATCH v2 23/23] soc: fsl: qe: remove PPC32 dependency from CONFIG_QUICC_ENGINE
The core QE code now also builds for ARM, so replace the FSL_SOC && PPC32 dependencies by the more lax requirements OF && HAS_IOMEM. Signed-off-by: Rasmus Villemoes --- drivers/soc/fsl/qe/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/fsl/qe/Kconfig b/drivers/soc/fsl/qe/Kconfig index cfa4b2939992..0c5b8b8e46b6 100644 --- a/drivers/soc/fsl/qe/Kconfig +++ b/drivers/soc/fsl/qe/Kconfig @@ -5,7 +5,7 @@ config QUICC_ENGINE bool "QUICC Engine (QE) framework support" - depends on FSL_SOC && PPC32 + depends on OF && HAS_IOMEM select GENERIC_ALLOCATOR select CRC32 help -- 2.23.0
[PATCH v2 21/23] serial: ucc_uart.c: explicitly include asm/cpm.h
This driver uses #defines from asm/cpm.h, so instead of relying on some other header pulling that in, do that explicitly. Signed-off-by: Rasmus Villemoes --- drivers/tty/serial/ucc_uart.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/tty/serial/ucc_uart.c b/drivers/tty/serial/ucc_uart.c index a0555ae2b1ef..e2c998badf81 100644 --- a/drivers/tty/serial/ucc_uart.c +++ b/drivers/tty/serial/ucc_uart.c @@ -33,6 +33,7 @@ #include #include +#include /* * The GUMR flag for Soft UART. This would normally be defined in qe.h, -- 2.23.0
[PATCH v2 20/23] serial: make SERIAL_QE depend on PPC32
Currently SERIAL_QE depends on QUICC_ENGINE, which in turn depends on PPC32, so this doesn't add any extra dependency. However, the QUICC Engine IP block also exists on some arm boards, so this serves as preparation for removing the PPC32 dependency from QUICC_ENGINE and build the QE support in drivers/soc/fsl/qe, while preventing allmodconfig/randconfig failures due to SERIAL_QE not being supported yet. Signed-off-by: Rasmus Villemoes --- drivers/tty/serial/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 67a9eb3f94ce..78246f535809 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -1056,6 +1056,7 @@ config SERIAL_LANTIQ config SERIAL_QE tristate "Freescale QUICC Engine serial port support" depends on QUICC_ENGINE + depends on PPC32 select SERIAL_CORE select FW_LOADER help -- 2.23.0
[PATCH v2 19/23] net: ethernet: freescale: make UCC_GETH explicitly depend on PPC32
Currently, QUICC_ENGINE depends on PPC32, so this in itself does not change anything. In order to allow removing the PPC32 dependency from QUICC_ENGINE and avoid allmodconfig build failures, add this explicit dependency. Signed-off-by: Rasmus Villemoes --- drivers/net/ethernet/freescale/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/ethernet/freescale/Kconfig b/drivers/net/ethernet/freescale/Kconfig index 6a7e8993119f..97d27c7740d4 100644 --- a/drivers/net/ethernet/freescale/Kconfig +++ b/drivers/net/ethernet/freescale/Kconfig @@ -75,6 +75,7 @@ config FSL_XGMAC_MDIO config UCC_GETH tristate "Freescale QE Gigabit Ethernet" depends on QUICC_ENGINE + depends on PPC32 select FSL_PQ_MDIO select PHYLIB ---help--- -- 2.23.0
[PATCH v2 17/23] soc: fsl: qe: make qe_ic_cascade_* static
Now that the references from arch/powerpc/ are gone, these are only
referenced from inside qe_ic.c, so make them static.
Signed-off-by: Rasmus Villemoes
---
drivers/soc/fsl/qe/qe_ic.c | 6 +++---
include/soc/fsl/qe/qe_ic.h | 4
2 files changed, 3 insertions(+), 7 deletions(-)
diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/soc/fsl/qe/qe_ic.c
index 545eb67094d1..e20f1205c0df 100644
--- a/drivers/soc/fsl/qe/qe_ic.c
+++ b/drivers/soc/fsl/qe/qe_ic.c
@@ -402,7 +402,7 @@ unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
return irq_linear_revmap(qe_ic->irqhost, irq);
}
-void qe_ic_cascade_low(struct irq_desc *desc)
+static void qe_ic_cascade_low(struct irq_desc *desc)
{
struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
@@ -415,7 +415,7 @@ void qe_ic_cascade_low(struct irq_desc *desc)
chip->irq_eoi(&desc->irq_data);
}
-void qe_ic_cascade_high(struct irq_desc *desc)
+static void qe_ic_cascade_high(struct irq_desc *desc)
{
struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
@@ -428,7 +428,7 @@ void qe_ic_cascade_high(struct irq_desc *desc)
chip->irq_eoi(&desc->irq_data);
}
-void qe_ic_cascade_muxed_mpic(struct irq_desc *desc)
+static void qe_ic_cascade_muxed_mpic(struct irq_desc *desc)
{
struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
unsigned int cascade_irq;
diff --git a/include/soc/fsl/qe/qe_ic.h b/include/soc/fsl/qe/qe_ic.h
index 8ec21a3bd859..43e4ce95c6a0 100644
--- a/include/soc/fsl/qe/qe_ic.h
+++ b/include/soc/fsl/qe/qe_ic.h
@@ -67,8 +67,4 @@ void qe_ic_set_highest_priority(unsigned int virq, int high);
int qe_ic_set_priority(unsigned int virq, unsigned int priority);
int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int
high);
-void qe_ic_cascade_low(struct irq_desc *desc);
-void qe_ic_cascade_high(struct irq_desc *desc);
-void qe_ic_cascade_muxed_mpic(struct irq_desc *desc);
-
#endif /* _ASM_POWERPC_QE_IC_H */
--
2.23.0
[PATCH v2 18/23] soc: fsl: qe: remove unused qe_ic_set_* functions
There are no current callers of these functions, and they use the
ppc-specific virq_to_hw(). So removing them gets us one step closer to
building QE support for ARM.
If the functionality is ever actually needed, the code can be dug out
of git and then adapted to work on all architectures, but for future
reference please note that I believe qe_ic_set_priority is buggy: The
"priority < 4" should be "priority <= 4", and in the else branch 24
should be replaced by 28, at least if I'm reading the data sheet right.
Signed-off-by: Rasmus Villemoes
---
drivers/soc/fsl/qe/qe_ic.c | 94 --
include/soc/fsl/qe/qe_ic.h | 4 --
2 files changed, 98 deletions(-)
diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/soc/fsl/qe/qe_ic.c
index e20f1205c0df..58f4b4914f53 100644
--- a/drivers/soc/fsl/qe/qe_ic.c
+++ b/drivers/soc/fsl/qe/qe_ic.c
@@ -533,97 +533,3 @@ static int __init qe_ic_of_init(void)
return 0;
}
subsys_initcall(qe_ic_of_init);
-
-void qe_ic_set_highest_priority(unsigned int virq, int high)
-{
- struct qe_ic *qe_ic = qe_ic_from_irq(virq);
- unsigned int src = virq_to_hw(virq);
- u32 temp = 0;
-
- temp = qe_ic_read(qe_ic->regs, QEIC_CICR);
-
- temp &= ~CICR_HP_MASK;
- temp |= src << CICR_HP_SHIFT;
-
- temp &= ~CICR_HPIT_MASK;
- temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << CICR_HPIT_SHIFT;
-
- qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
-}
-
-/* Set Priority level within its group, from 1 to 8 */
-int qe_ic_set_priority(unsigned int virq, unsigned int priority)
-{
- struct qe_ic *qe_ic = qe_ic_from_irq(virq);
- unsigned int src = virq_to_hw(virq);
- u32 temp;
-
- if (priority > 8 || priority == 0)
- return -EINVAL;
- if (WARN_ONCE(src >= ARRAY_SIZE(qe_ic_info),
- "%s: Invalid hw irq number for QEIC\n", __func__))
- return -EINVAL;
- if (qe_ic_info[src].pri_reg == 0)
- return -EINVAL;
-
- temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].pri_reg);
-
- if (priority < 4) {
- temp &= ~(0x7 << (32 - priority * 3));
- temp |= qe_ic_info[src].pri_code << (32 - priority * 3);
- } else {
- temp &= ~(0x7 << (24 - priority * 3));
- temp |= qe_ic_info[src].pri_code << (24 - priority * 3);
- }
-
- qe_ic_write(qe_ic->regs, qe_ic_info[src].pri_reg, temp);
-
- return 0;
-}
-
-/* Set a QE priority to use high irq, only priority 1~2 can use high irq */
-int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high)
-{
- struct qe_ic *qe_ic = qe_ic_from_irq(virq);
- unsigned int src = virq_to_hw(virq);
- u32 temp, control_reg = QEIC_CICNR, shift = 0;
-
- if (priority > 2 || priority == 0)
- return -EINVAL;
- if (WARN_ONCE(src >= ARRAY_SIZE(qe_ic_info),
- "%s: Invalid hw irq number for QEIC\n", __func__))
- return -EINVAL;
-
- switch (qe_ic_info[src].pri_reg) {
- case QEIC_CIPZCC:
- shift = CICNR_ZCC1T_SHIFT;
- break;
- case QEIC_CIPWCC:
- shift = CICNR_WCC1T_SHIFT;
- break;
- case QEIC_CIPYCC:
- shift = CICNR_YCC1T_SHIFT;
- break;
- case QEIC_CIPXCC:
- shift = CICNR_XCC1T_SHIFT;
- break;
- case QEIC_CIPRTA:
- shift = CRICR_RTA1T_SHIFT;
- control_reg = QEIC_CRICR;
- break;
- case QEIC_CIPRTB:
- shift = CRICR_RTB1T_SHIFT;
- control_reg = QEIC_CRICR;
- break;
- default:
- return -EINVAL;
- }
-
- shift += (2 - priority) * 2;
- temp = qe_ic_read(qe_ic->regs, control_reg);
- temp &= ~(SIGNAL_MASK << shift);
- temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << shift;
- qe_ic_write(qe_ic->regs, control_reg, temp);
-
- return 0;
-}
diff --git a/include/soc/fsl/qe/qe_ic.h b/include/soc/fsl/qe/qe_ic.h
index 43e4ce95c6a0..d47eb231519e 100644
--- a/include/soc/fsl/qe/qe_ic.h
+++ b/include/soc/fsl/qe/qe_ic.h
@@ -63,8 +63,4 @@ static inline unsigned int qe_ic_get_high_irq(struct qe_ic
*qe_ic)
{ return 0; }
#endif /* CONFIG_QUICC_ENGINE */
-void qe_ic_set_highest_priority(unsigned int virq, int high);
-int qe_ic_set_priority(unsigned int virq, unsigned int priority);
-int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int
high);
-
#endif /* _ASM_POWERPC_QE_IC_H */
--
2.23.0
[PATCH v2 16/23] powerpc/85xx: remove mostly pointless mpc85xx_qe_init()
Since commit 302c059f2e7b (QE: use subsys_initcall to init qe),
mpc85xx_qe_init() has done nothing apart from possibly emitting a
pr_err(). As part of reducing the amount of QE-related code in
arch/powerpc/ (and eventually support QE on other architectures),
remove this low-hanging fruit.
Signed-off-by: Rasmus Villemoes
---
arch/powerpc/platforms/85xx/common.c | 23 ---
arch/powerpc/platforms/85xx/corenet_generic.c | 2 --
arch/powerpc/platforms/85xx/mpc85xx.h | 2 --
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 1 -
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 1 -
arch/powerpc/platforms/85xx/twr_p102x.c | 1 -
6 files changed, 30 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/common.c
b/arch/powerpc/platforms/85xx/common.c
index fe0606439b5a..a554b6d87cf7 100644
--- a/arch/powerpc/platforms/85xx/common.c
+++ b/arch/powerpc/platforms/85xx/common.c
@@ -86,29 +86,6 @@ void __init mpc85xx_cpm2_pic_init(void)
#endif
#ifdef CONFIG_QUICC_ENGINE
-void __init mpc85xx_qe_init(void)
-{
- struct device_node *np;
-
- np = of_find_compatible_node(NULL, NULL, "fsl,qe");
- if (!np) {
- np = of_find_node_by_name(NULL, "qe");
- if (!np) {
- pr_err("%s: Could not find Quicc Engine node\n",
- __func__);
- return;
- }
- }
-
- if (!of_device_is_available(np)) {
- of_node_put(np);
- return;
- }
-
- of_node_put(np);
-
-}
-
void __init mpc85xx_qe_par_io_init(void)
{
struct device_node *np;
diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c
b/arch/powerpc/platforms/85xx/corenet_generic.c
index 8c1bb3941642..27ac38f7e1a9 100644
--- a/arch/powerpc/platforms/85xx/corenet_generic.c
+++ b/arch/powerpc/platforms/85xx/corenet_generic.c
@@ -56,8 +56,6 @@ void __init corenet_gen_setup_arch(void)
swiotlb_detect_4g();
pr_info("%s board\n", ppc_md.name);
-
- mpc85xx_qe_init();
}
static const struct of_device_id of_device_ids[] = {
diff --git a/arch/powerpc/platforms/85xx/mpc85xx.h
b/arch/powerpc/platforms/85xx/mpc85xx.h
index fa23f9b0592c..cb84c5c56c36 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx.h
+++ b/arch/powerpc/platforms/85xx/mpc85xx.h
@@ -10,10 +10,8 @@ static inline void __init mpc85xx_cpm2_pic_init(void) {}
#endif /* CONFIG_CPM2 */
#ifdef CONFIG_QUICC_ENGINE
-extern void mpc85xx_qe_init(void);
extern void mpc85xx_qe_par_io_init(void);
#else
-static inline void __init mpc85xx_qe_init(void) {}
static inline void __init mpc85xx_qe_par_io_init(void) {}
#endif
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 4bc49e5ec0b6..fb05b4d5bf1e 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -237,7 +237,6 @@ static void __init mpc85xx_mds_qe_init(void)
{
struct device_node *np;
- mpc85xx_qe_init();
mpc85xx_qe_par_io_init();
mpc85xx_mds_reset_ucc_phys();
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index 14b5a61d49c1..80a80174768c 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -72,7 +72,6 @@ static void __init mpc85xx_rdb_setup_arch(void)
fsl_pci_assign_primary();
#ifdef CONFIG_QUICC_ENGINE
- mpc85xx_qe_init();
mpc85xx_qe_par_io_init();
#if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE)
if (machine_is(p1025_rdb)) {
diff --git a/arch/powerpc/platforms/85xx/twr_p102x.c
b/arch/powerpc/platforms/85xx/twr_p102x.c
index b099f5607120..9abb1e9f73c4 100644
--- a/arch/powerpc/platforms/85xx/twr_p102x.c
+++ b/arch/powerpc/platforms/85xx/twr_p102x.c
@@ -57,7 +57,6 @@ static void __init twr_p1025_setup_arch(void)
fsl_pci_assign_primary();
#ifdef CONFIG_QUICC_ENGINE
- mpc85xx_qe_init();
mpc85xx_qe_par_io_init();
#if IS_ENABLED(CONFIG_UCC_GETH) || IS_ENABLED(CONFIG_SERIAL_QE)
--
2.23.0
[PATCH v2 15/23] powerpc/83xx: remove mpc83xx_ipic_and_qe_init_IRQ
This is now exactly the same as mpc83xx_ipic_init_IRQ, so just use
that directly.
Signed-off-by: Rasmus Villemoes
---
arch/powerpc/platforms/83xx/km83xx.c | 2 +-
arch/powerpc/platforms/83xx/misc.c| 7 ---
arch/powerpc/platforms/83xx/mpc832x_mds.c | 2 +-
arch/powerpc/platforms/83xx/mpc832x_rdb.c | 2 +-
arch/powerpc/platforms/83xx/mpc836x_mds.c | 2 +-
arch/powerpc/platforms/83xx/mpc836x_rdk.c | 2 +-
arch/powerpc/platforms/83xx/mpc83xx.h | 5 -
7 files changed, 5 insertions(+), 17 deletions(-)
diff --git a/arch/powerpc/platforms/83xx/km83xx.c
b/arch/powerpc/platforms/83xx/km83xx.c
index 5c6227f7bc37..3d89569e9e71 100644
--- a/arch/powerpc/platforms/83xx/km83xx.c
+++ b/arch/powerpc/platforms/83xx/km83xx.c
@@ -177,7 +177,7 @@ define_machine(mpc83xx_km) {
.name = "mpc83xx-km-platform",
.probe = mpc83xx_km_probe,
.setup_arch = mpc83xx_km_setup_arch,
- .init_IRQ = mpc83xx_ipic_and_qe_init_IRQ,
+ .init_IRQ = mpc83xx_ipic_init_IRQ,
.get_irq= ipic_get_irq,
.restart= mpc83xx_restart,
.time_init = mpc83xx_time_init,
diff --git a/arch/powerpc/platforms/83xx/misc.c
b/arch/powerpc/platforms/83xx/misc.c
index 6935a5b9fbd1..1d8306eb2958 100644
--- a/arch/powerpc/platforms/83xx/misc.c
+++ b/arch/powerpc/platforms/83xx/misc.c
@@ -88,13 +88,6 @@ void __init mpc83xx_ipic_init_IRQ(void)
ipic_set_default_priority();
}
-#ifdef CONFIG_QUICC_ENGINE
-void __init mpc83xx_ipic_and_qe_init_IRQ(void)
-{
- mpc83xx_ipic_init_IRQ();
-}
-#endif /* CONFIG_QUICC_ENGINE */
-
static const struct of_device_id of_bus_ids[] __initconst = {
{ .type = "soc", },
{ .compatible = "soc", },
diff --git a/arch/powerpc/platforms/83xx/mpc832x_mds.c
b/arch/powerpc/platforms/83xx/mpc832x_mds.c
index 1c73af104d19..6fa5402ebf20 100644
--- a/arch/powerpc/platforms/83xx/mpc832x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc832x_mds.c
@@ -101,7 +101,7 @@ define_machine(mpc832x_mds) {
.name = "MPC832x MDS",
.probe = mpc832x_sys_probe,
.setup_arch = mpc832x_sys_setup_arch,
- .init_IRQ = mpc83xx_ipic_and_qe_init_IRQ,
+ .init_IRQ = mpc83xx_ipic_init_IRQ,
.get_irq= ipic_get_irq,
.restart= mpc83xx_restart,
.time_init = mpc83xx_time_init,
diff --git a/arch/powerpc/platforms/83xx/mpc832x_rdb.c
b/arch/powerpc/platforms/83xx/mpc832x_rdb.c
index 87f68ca06255..622c625d5ce4 100644
--- a/arch/powerpc/platforms/83xx/mpc832x_rdb.c
+++ b/arch/powerpc/platforms/83xx/mpc832x_rdb.c
@@ -219,7 +219,7 @@ define_machine(mpc832x_rdb) {
.name = "MPC832x RDB",
.probe = mpc832x_rdb_probe,
.setup_arch = mpc832x_rdb_setup_arch,
- .init_IRQ = mpc83xx_ipic_and_qe_init_IRQ,
+ .init_IRQ = mpc83xx_ipic_init_IRQ,
.get_irq= ipic_get_irq,
.restart= mpc83xx_restart,
.time_init = mpc83xx_time_init,
diff --git a/arch/powerpc/platforms/83xx/mpc836x_mds.c
b/arch/powerpc/platforms/83xx/mpc836x_mds.c
index 5b484da9533e..219a83ab6c00 100644
--- a/arch/powerpc/platforms/83xx/mpc836x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc836x_mds.c
@@ -208,7 +208,7 @@ define_machine(mpc836x_mds) {
.name = "MPC836x MDS",
.probe = mpc836x_mds_probe,
.setup_arch = mpc836x_mds_setup_arch,
- .init_IRQ = mpc83xx_ipic_and_qe_init_IRQ,
+ .init_IRQ = mpc83xx_ipic_init_IRQ,
.get_irq= ipic_get_irq,
.restart= mpc83xx_restart,
.time_init = mpc83xx_time_init,
diff --git a/arch/powerpc/platforms/83xx/mpc836x_rdk.c
b/arch/powerpc/platforms/83xx/mpc836x_rdk.c
index b7119e443920..b4aac2cde849 100644
--- a/arch/powerpc/platforms/83xx/mpc836x_rdk.c
+++ b/arch/powerpc/platforms/83xx/mpc836x_rdk.c
@@ -41,7 +41,7 @@ define_machine(mpc836x_rdk) {
.name = "MPC836x RDK",
.probe = mpc836x_rdk_probe,
.setup_arch = mpc836x_rdk_setup_arch,
- .init_IRQ = mpc83xx_ipic_and_qe_init_IRQ,
+ .init_IRQ = mpc83xx_ipic_init_IRQ,
.get_irq= ipic_get_irq,
.restart= mpc83xx_restart,
.time_init = mpc83xx_time_init,
diff --git a/arch/powerpc/platforms/83xx/mpc83xx.h
b/arch/powerpc/platforms/83xx/mpc83xx.h
index d343f6ce2599..f37d04332fc7 100644
--- a/arch/powerpc/platforms/83xx/mpc83xx.h
+++ b/arch/powerpc/platforms/83xx/mpc83xx.h
@@ -72,11 +72,6 @@ extern int mpc837x_usb_cfg(void);
extern int mpc834x_usb_cfg(void);
extern int mpc831x_usb_cfg(void);
extern void mpc83xx_ipic_init_IRQ(void);
-#ifdef CONFIG_QUICC_ENGINE
-extern void mpc83xx_ipic_and_qe_init_IRQ(void);
-#else
-#define mpc83xx_ipic_and_qe_init_IRQ mpc83xx_ipic_init_IRQ
-#endif /* CONFIG_QUICC_ENGINE */
#ifdef CONFIG_PCI
extern void mpc83xx_setup_pci(void);
--
[PATCH v2 11/23] soc: fsl: qe: rename qe_ic_cascade_low_mpic -> qe_ic_cascade_low
The qe_ic_cascade_{low,high}_mpic functions are now used as handlers
both when the interrupt parent is mpic as well as ipic, so remove the
_mpic suffix.
Signed-off-by: Rasmus Villemoes
---
arch/powerpc/platforms/83xx/misc.c| 2 +-
arch/powerpc/platforms/85xx/corenet_generic.c | 4 ++--
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 4 ++--
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 4 ++--
arch/powerpc/platforms/85xx/twr_p102x.c | 4 ++--
drivers/soc/fsl/qe/qe_ic.c| 4 ++--
include/soc/fsl/qe/qe_ic.h| 4 ++--
7 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/arch/powerpc/platforms/83xx/misc.c
b/arch/powerpc/platforms/83xx/misc.c
index 779791c0570f..835d082218ae 100644
--- a/arch/powerpc/platforms/83xx/misc.c
+++ b/arch/powerpc/platforms/83xx/misc.c
@@ -100,7 +100,7 @@ void __init mpc83xx_qe_init_IRQ(void)
if (!np)
return;
}
- qe_ic_init(np, 0, qe_ic_cascade_low_mpic, qe_ic_cascade_high_mpic);
+ qe_ic_init(np, 0, qe_ic_cascade_low, qe_ic_cascade_high);
of_node_put(np);
}
diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c
b/arch/powerpc/platforms/85xx/corenet_generic.c
index 7ee2c6628f64..2ed9e84ca03a 100644
--- a/arch/powerpc/platforms/85xx/corenet_generic.c
+++ b/arch/powerpc/platforms/85xx/corenet_generic.c
@@ -50,8 +50,8 @@ void __init corenet_gen_pic_init(void)
np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
if (np) {
- qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
- qe_ic_cascade_high_mpic);
+ qe_ic_init(np, 0, qe_ic_cascade_low,
+ qe_ic_cascade_high);
of_node_put(np);
}
}
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 5ca254256c47..24211a1787b2 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -288,8 +288,8 @@ static void __init mpc85xx_mds_qeic_init(void)
}
if (machine_is(p1021_mds))
- qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
- qe_ic_cascade_high_mpic);
+ qe_ic_init(np, 0, qe_ic_cascade_low,
+ qe_ic_cascade_high);
else
qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
of_node_put(np);
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index d3c540ee558f..093867879081 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -66,8 +66,8 @@ void __init mpc85xx_rdb_pic_init(void)
#ifdef CONFIG_QUICC_ENGINE
np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
if (np) {
- qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
- qe_ic_cascade_high_mpic);
+ qe_ic_init(np, 0, qe_ic_cascade_low,
+ qe_ic_cascade_high);
of_node_put(np);
} else
diff --git a/arch/powerpc/platforms/85xx/twr_p102x.c
b/arch/powerpc/platforms/85xx/twr_p102x.c
index 720b0c0f03ba..2e0fb23854c0 100644
--- a/arch/powerpc/platforms/85xx/twr_p102x.c
+++ b/arch/powerpc/platforms/85xx/twr_p102x.c
@@ -45,8 +45,8 @@ static void __init twr_p1025_pic_init(void)
#ifdef CONFIG_QUICC_ENGINE
np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
if (np) {
- qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
- qe_ic_cascade_high_mpic);
+ qe_ic_init(np, 0, qe_ic_cascade_low,
+ qe_ic_cascade_high);
of_node_put(np);
} else
pr_err("Could not find qe-ic node\n");
diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/soc/fsl/qe/qe_ic.c
index 0ff802816c0c..f3659c312e13 100644
--- a/drivers/soc/fsl/qe/qe_ic.c
+++ b/drivers/soc/fsl/qe/qe_ic.c
@@ -402,7 +402,7 @@ unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
return irq_linear_revmap(qe_ic->irqhost, irq);
}
-void qe_ic_cascade_low_mpic(struct irq_desc *desc)
+void qe_ic_cascade_low(struct irq_desc *desc)
{
struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
@@ -415,7 +415,7 @@ void qe_ic_cascade_low_mpic(struct irq_desc *desc)
chip->irq_eoi(&desc->irq_data);
}
-void qe_ic_cascade_high_mpic(struct irq_desc *desc)
+void qe_ic_cascade_high(struct irq_desc *desc)
{
struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
diff --git a/include/soc/fsl/qe/qe_ic.h b/include/soc/fsl/qe/qe_ic.h
index fb10a7606acc..3c8220cedd9a 100644
--- a/include/soc/fsl/qe/qe_ic.h
+++ b/include/soc/fsl/qe/qe_ic.h
@@ -74,8 +74,8 @@ void qe_ic_set_highest_priority(unsigned int
[PATCH v2 14/23] soc: fsl: qe: move calls of qe_ic_init out of arch/powerpc/
Having to call qe_ic_init() from platform-specific code makes it
awkward to allow building the QE drivers for ARM. It's also a needless
duplication of code, and slightly error-prone: Instead of the caller
needing to know the details of whether the QUICC Engine High and QUICC
Engine Low are actually the same interrupt (see e.g. the machine_is()
in mpc85xx_mds_qeic_init), just let the init function choose the
appropriate handlers after it has parsed the DT and figured it out. If
the two interrupts are distinct, use separate handlers, otherwise use
the handler which first checks the CHIVEC register (for the high
priority interrupts), then the CIVEC.
All existing callers pass 0 for flags, so continue to do that from the
new single caller. Later cleanups will remove that argument
from qe_ic_init and simplify the body, as well as make qe_ic_init into
a proper init function for an IRQCHIP_DECLARE, eliminating the need to
manually look up the fsl,qe-ic node.
Signed-off-by: Rasmus Villemoes
---
arch/powerpc/platforms/83xx/km83xx.c | 1 -
arch/powerpc/platforms/83xx/misc.c| 16 --
arch/powerpc/platforms/83xx/mpc832x_mds.c | 1 -
arch/powerpc/platforms/83xx/mpc832x_rdb.c | 1 -
arch/powerpc/platforms/83xx/mpc836x_mds.c | 1 -
arch/powerpc/platforms/83xx/mpc836x_rdk.c | 1 -
arch/powerpc/platforms/83xx/mpc83xx.h | 2 --
arch/powerpc/platforms/85xx/corenet_generic.c | 10 ---
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 27 -
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 17 ---
arch/powerpc/platforms/85xx/twr_p102x.c | 15 --
drivers/soc/fsl/qe/qe_ic.c| 29 +--
include/soc/fsl/qe/qe_ic.h| 7 -
13 files changed, 26 insertions(+), 102 deletions(-)
diff --git a/arch/powerpc/platforms/83xx/km83xx.c
b/arch/powerpc/platforms/83xx/km83xx.c
index 273145aed90a..5c6227f7bc37 100644
--- a/arch/powerpc/platforms/83xx/km83xx.c
+++ b/arch/powerpc/platforms/83xx/km83xx.c
@@ -34,7 +34,6 @@
#include
#include
#include
-#include
#include "mpc83xx.h"
diff --git a/arch/powerpc/platforms/83xx/misc.c
b/arch/powerpc/platforms/83xx/misc.c
index 835d082218ae..6935a5b9fbd1 100644
--- a/arch/powerpc/platforms/83xx/misc.c
+++ b/arch/powerpc/platforms/83xx/misc.c
@@ -14,7 +14,6 @@
#include
#include
#include
-#include
#include
#include
@@ -90,24 +89,9 @@ void __init mpc83xx_ipic_init_IRQ(void)
}
#ifdef CONFIG_QUICC_ENGINE
-void __init mpc83xx_qe_init_IRQ(void)
-{
- struct device_node *np;
-
- np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
- if (!np) {
- np = of_find_node_by_type(NULL, "qeic");
- if (!np)
- return;
- }
- qe_ic_init(np, 0, qe_ic_cascade_low, qe_ic_cascade_high);
- of_node_put(np);
-}
-
void __init mpc83xx_ipic_and_qe_init_IRQ(void)
{
mpc83xx_ipic_init_IRQ();
- mpc83xx_qe_init_IRQ();
}
#endif /* CONFIG_QUICC_ENGINE */
diff --git a/arch/powerpc/platforms/83xx/mpc832x_mds.c
b/arch/powerpc/platforms/83xx/mpc832x_mds.c
index b428835e5919..1c73af104d19 100644
--- a/arch/powerpc/platforms/83xx/mpc832x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc832x_mds.c
@@ -33,7 +33,6 @@
#include
#include
#include
-#include
#include "mpc83xx.h"
diff --git a/arch/powerpc/platforms/83xx/mpc832x_rdb.c
b/arch/powerpc/platforms/83xx/mpc832x_rdb.c
index 4588ce632484..87f68ca06255 100644
--- a/arch/powerpc/platforms/83xx/mpc832x_rdb.c
+++ b/arch/powerpc/platforms/83xx/mpc832x_rdb.c
@@ -22,7 +22,6 @@
#include
#include
#include
-#include
#include
#include
diff --git a/arch/powerpc/platforms/83xx/mpc836x_mds.c
b/arch/powerpc/platforms/83xx/mpc836x_mds.c
index 4a4efa906d35..5b484da9533e 100644
--- a/arch/powerpc/platforms/83xx/mpc836x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc836x_mds.c
@@ -41,7 +41,6 @@
#include
#include
#include
-#include
#include "mpc83xx.h"
diff --git a/arch/powerpc/platforms/83xx/mpc836x_rdk.c
b/arch/powerpc/platforms/83xx/mpc836x_rdk.c
index 9923059cb111..b7119e443920 100644
--- a/arch/powerpc/platforms/83xx/mpc836x_rdk.c
+++ b/arch/powerpc/platforms/83xx/mpc836x_rdk.c
@@ -17,7 +17,6 @@
#include
#include
#include
-#include
#include
#include
diff --git a/arch/powerpc/platforms/83xx/mpc83xx.h
b/arch/powerpc/platforms/83xx/mpc83xx.h
index 459145623334..d343f6ce2599 100644
--- a/arch/powerpc/platforms/83xx/mpc83xx.h
+++ b/arch/powerpc/platforms/83xx/mpc83xx.h
@@ -73,10 +73,8 @@ extern int mpc834x_usb_cfg(void);
extern int mpc831x_usb_cfg(void);
extern void mpc83xx_ipic_init_IRQ(void);
#ifdef CONFIG_QUICC_ENGINE
-extern void mpc83xx_qe_init_IRQ(void);
extern void mpc83xx_ipic_and_qe_init_IRQ(void);
#else
-static inline void __init mpc83xx_qe_init_IRQ(void) {}
#define mpc83xx_ipic_and_qe_init_IRQ mpc83xx_ipic_init_IRQ
#endif /* CONFIG_QUICC_ENGINE */
diff --git a/arch/powerpc
[PATCH v2 13/23] soc: fsl: qe: remove pointless sysfs registration in qe_ic.c
There's no point in registering with sysfs when that doesn't actually
allow any interaction with the device or driver (no uevents, no sysfs
files that provide information or allow configuration, no nothing).
Signed-off-by: Rasmus Villemoes
---
drivers/soc/fsl/qe/qe_ic.c | 31 ---
1 file changed, 31 deletions(-)
diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/soc/fsl/qe/qe_ic.c
index 61a40e40f3ae..6bd6d6fb9696 100644
--- a/drivers/soc/fsl/qe/qe_ic.c
+++ b/drivers/soc/fsl/qe/qe_ic.c
@@ -604,34 +604,3 @@ int qe_ic_set_high_priority(unsigned int virq, unsigned
int priority, int high)
return 0;
}
-
-static struct bus_type qe_ic_subsys = {
- .name = "qe_ic",
- .dev_name = "qe_ic",
-};
-
-static struct device device_qe_ic = {
- .id = 0,
- .bus = &qe_ic_subsys,
-};
-
-static int __init init_qe_ic_sysfs(void)
-{
- int rc;
-
- printk(KERN_DEBUG "Registering qe_ic with sysfs...\n");
-
- rc = subsys_system_register(&qe_ic_subsys, NULL);
- if (rc) {
- printk(KERN_ERR "Failed registering qe_ic sys class\n");
- return -ENODEV;
- }
- rc = device_register(&device_qe_ic);
- if (rc) {
- printk(KERN_ERR "Failed registering qe_ic sys device\n");
- return -ENODEV;
- }
- return 0;
-}
-
-subsys_initcall(init_qe_ic_sysfs);
--
2.23.0
[PATCH v2 12/23] soc: fsl: qe: drop assign-only high_active in qe_ic_init
high_active is only assigned to but never used. Remove it.
Signed-off-by: Rasmus Villemoes
---
drivers/soc/fsl/qe/qe_ic.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/soc/fsl/qe/qe_ic.c
index f3659c312e13..61a40e40f3ae 100644
--- a/drivers/soc/fsl/qe/qe_ic.c
+++ b/drivers/soc/fsl/qe/qe_ic.c
@@ -450,7 +450,7 @@ void __init qe_ic_init(struct device_node *node, unsigned
int flags,
{
struct qe_ic *qe_ic;
struct resource res;
- u32 temp = 0, ret, high_active = 0;
+ u32 temp = 0, ret;
ret = of_address_to_resource(node, 0, &res);
if (ret)
@@ -496,10 +496,8 @@ void __init qe_ic_init(struct device_node *node, unsigned
int flags,
temp |= CICR_GRTB;
/* choose destination signal for highest priority interrupt */
- if (flags & QE_IC_HIGH_SIGNAL) {
+ if (flags & QE_IC_HIGH_SIGNAL)
temp |= (SIGNAL_HIGH << CICR_HPIT_SHIFT);
- high_active = 1;
- }
qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
--
2.23.0
[PATCH v2 10/23] soc: fsl: qe: use qe_ic_cascade_{low, high}_mpic also on 83xx
The *_ipic and *_mpic handlers are almost identical - the only
difference is that the latter end with an unconditional
chip->irq_eoi() call. Since IPIC does not have ->irq_eoi, we can
reduce some code duplication by calling irq_eoi conditionally.
This is similar to what is already done in mpc8xxx_gpio_irq_cascade().
This leaves the functions slightly misnamed, but that will be fixed in
a subsequent patch.
Signed-off-by: Rasmus Villemoes
---
arch/powerpc/platforms/83xx/misc.c | 2 +-
drivers/soc/fsl/qe/qe_ic.c | 24
include/soc/fsl/qe/qe_ic.h | 2 --
3 files changed, 5 insertions(+), 23 deletions(-)
diff --git a/arch/powerpc/platforms/83xx/misc.c
b/arch/powerpc/platforms/83xx/misc.c
index f46d7bf3b140..779791c0570f 100644
--- a/arch/powerpc/platforms/83xx/misc.c
+++ b/arch/powerpc/platforms/83xx/misc.c
@@ -100,7 +100,7 @@ void __init mpc83xx_qe_init_IRQ(void)
if (!np)
return;
}
- qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
+ qe_ic_init(np, 0, qe_ic_cascade_low_mpic, qe_ic_cascade_high_mpic);
of_node_put(np);
}
diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/soc/fsl/qe/qe_ic.c
index a847b2672e90..0ff802816c0c 100644
--- a/drivers/soc/fsl/qe/qe_ic.c
+++ b/drivers/soc/fsl/qe/qe_ic.c
@@ -402,24 +402,6 @@ unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
return irq_linear_revmap(qe_ic->irqhost, irq);
}
-void qe_ic_cascade_low_ipic(struct irq_desc *desc)
-{
- struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
- unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
-
- if (cascade_irq != NO_IRQ)
- generic_handle_irq(cascade_irq);
-}
-
-void qe_ic_cascade_high_ipic(struct irq_desc *desc)
-{
- struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
- unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
-
- if (cascade_irq != NO_IRQ)
- generic_handle_irq(cascade_irq);
-}
-
void qe_ic_cascade_low_mpic(struct irq_desc *desc)
{
struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
@@ -429,7 +411,8 @@ void qe_ic_cascade_low_mpic(struct irq_desc *desc)
if (cascade_irq != NO_IRQ)
generic_handle_irq(cascade_irq);
- chip->irq_eoi(&desc->irq_data);
+ if (chip->irq_eoi)
+ chip->irq_eoi(&desc->irq_data);
}
void qe_ic_cascade_high_mpic(struct irq_desc *desc)
@@ -441,7 +424,8 @@ void qe_ic_cascade_high_mpic(struct irq_desc *desc)
if (cascade_irq != NO_IRQ)
generic_handle_irq(cascade_irq);
- chip->irq_eoi(&desc->irq_data);
+ if (chip->irq_eoi)
+ chip->irq_eoi(&desc->irq_data);
}
void qe_ic_cascade_muxed_mpic(struct irq_desc *desc)
diff --git a/include/soc/fsl/qe/qe_ic.h b/include/soc/fsl/qe/qe_ic.h
index f3492eb13052..fb10a7606acc 100644
--- a/include/soc/fsl/qe/qe_ic.h
+++ b/include/soc/fsl/qe/qe_ic.h
@@ -74,8 +74,6 @@ void qe_ic_set_highest_priority(unsigned int virq, int high);
int qe_ic_set_priority(unsigned int virq, unsigned int priority);
int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int
high);
-void qe_ic_cascade_low_ipic(struct irq_desc *desc);
-void qe_ic_cascade_high_ipic(struct irq_desc *desc);
void qe_ic_cascade_low_mpic(struct irq_desc *desc);
void qe_ic_cascade_high_mpic(struct irq_desc *desc);
void qe_ic_cascade_muxed_mpic(struct irq_desc *desc);
--
2.23.0
[PATCH v2 09/23] soc: fsl: qe: move qe_ic_cascade_* functions to qe_ic.c
These functions are only ever called through a function pointer, and
therefore it makes no sense for them to be "static inline" - gcc has
no choice but to emit a copy in each translation unit that takes the
address of one of these (currently various platform code under
arch/powerpc/). So move them into qe_ic.c and leave ordinary extern
declarations in the header file.
Signed-off-by: Rasmus Villemoes
---
drivers/soc/fsl/qe/qe_ic.c | 58 +++
include/soc/fsl/qe/qe_ic.h | 62 +++---
2 files changed, 63 insertions(+), 57 deletions(-)
diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/soc/fsl/qe/qe_ic.c
index 7b1870d2866a..a847b2672e90 100644
--- a/drivers/soc/fsl/qe/qe_ic.c
+++ b/drivers/soc/fsl/qe/qe_ic.c
@@ -402,6 +402,64 @@ unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
return irq_linear_revmap(qe_ic->irqhost, irq);
}
+void qe_ic_cascade_low_ipic(struct irq_desc *desc)
+{
+ struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
+ unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
+
+ if (cascade_irq != NO_IRQ)
+ generic_handle_irq(cascade_irq);
+}
+
+void qe_ic_cascade_high_ipic(struct irq_desc *desc)
+{
+ struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
+ unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
+
+ if (cascade_irq != NO_IRQ)
+ generic_handle_irq(cascade_irq);
+}
+
+void qe_ic_cascade_low_mpic(struct irq_desc *desc)
+{
+ struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
+ unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+
+ if (cascade_irq != NO_IRQ)
+ generic_handle_irq(cascade_irq);
+
+ chip->irq_eoi(&desc->irq_data);
+}
+
+void qe_ic_cascade_high_mpic(struct irq_desc *desc)
+{
+ struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
+ unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+
+ if (cascade_irq != NO_IRQ)
+ generic_handle_irq(cascade_irq);
+
+ chip->irq_eoi(&desc->irq_data);
+}
+
+void qe_ic_cascade_muxed_mpic(struct irq_desc *desc)
+{
+ struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
+ unsigned int cascade_irq;
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+
+ cascade_irq = qe_ic_get_high_irq(qe_ic);
+ if (cascade_irq == NO_IRQ)
+ cascade_irq = qe_ic_get_low_irq(qe_ic);
+
+ if (cascade_irq != NO_IRQ)
+ generic_handle_irq(cascade_irq);
+
+ chip->irq_eoi(&desc->irq_data);
+}
+
void __init qe_ic_init(struct device_node *node, unsigned int flags,
void (*low_handler)(struct irq_desc *desc),
void (*high_handler)(struct irq_desc *desc))
diff --git a/include/soc/fsl/qe/qe_ic.h b/include/soc/fsl/qe/qe_ic.h
index 714a9b890d8d..f3492eb13052 100644
--- a/include/soc/fsl/qe/qe_ic.h
+++ b/include/soc/fsl/qe/qe_ic.h
@@ -74,62 +74,10 @@ void qe_ic_set_highest_priority(unsigned int virq, int
high);
int qe_ic_set_priority(unsigned int virq, unsigned int priority);
int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int
high);
-static inline void qe_ic_cascade_low_ipic(struct irq_desc *desc)
-{
- struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
- unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
-
- if (cascade_irq != NO_IRQ)
- generic_handle_irq(cascade_irq);
-}
-
-static inline void qe_ic_cascade_high_ipic(struct irq_desc *desc)
-{
- struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
- unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
-
- if (cascade_irq != NO_IRQ)
- generic_handle_irq(cascade_irq);
-}
-
-static inline void qe_ic_cascade_low_mpic(struct irq_desc *desc)
-{
- struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
- unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
- struct irq_chip *chip = irq_desc_get_chip(desc);
-
- if (cascade_irq != NO_IRQ)
- generic_handle_irq(cascade_irq);
-
- chip->irq_eoi(&desc->irq_data);
-}
-
-static inline void qe_ic_cascade_high_mpic(struct irq_desc *desc)
-{
- struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
- unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
- struct irq_chip *chip = irq_desc_get_chip(desc);
-
- if (cascade_irq != NO_IRQ)
- generic_handle_irq(cascade_irq);
-
- chip->irq_eoi(&desc->irq_data);
-}
-
-static inline void qe_ic_cascade_muxed_mpic(struct irq_desc *desc)
-{
- struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
- unsigned int cascade_irq;
- struct irq_chip *chip = irq_desc_get_chip(desc);
-
- cascade_irq = qe_ic_get_high_irq(qe_ic);
- if (cascade_irq == NO_IRQ)
- cascade_irq = qe_ic_get_low_irq(qe_ic);
[PATCH v2 08/23] soc: fsl: qe: drop unneeded #includes
These includes are not actually needed, and asm/rheap.h and sysdev/fsl_soc.h are PPC-specific, hence prevent compiling QE for other architectures. Signed-off-by: Rasmus Villemoes --- drivers/soc/fsl/qe/qe.c| 5 - drivers/soc/fsl/qe/qe_io.c | 2 -- 2 files changed, 7 deletions(-) diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c index 0ddf83d8e3ce..48051a684458 100644 --- a/drivers/soc/fsl/qe/qe.c +++ b/drivers/soc/fsl/qe/qe.c @@ -26,13 +26,8 @@ #include #include #include -#include -#include -#include #include #include -#include -#include static void qe_snums_init(void); static int qe_sdma_init(void); diff --git a/drivers/soc/fsl/qe/qe_io.c b/drivers/soc/fsl/qe/qe_io.c index 776a2c9361e1..93ba17d250a3 100644 --- a/drivers/soc/fsl/qe/qe_io.c +++ b/drivers/soc/fsl/qe/qe_io.c @@ -18,8 +18,6 @@ #include #include -#include -#include #undef DEBUG -- 2.23.0
[PATCH v2 07/23] soc: fsl: qe: merge qe_ic.h into qe_ic.c
The local qe_ic.h header is only used by qe_ic.c, so merge its
contents into the .c file. This is preparation for moving the driver
to drivers/irqchip/. It also avoids confusion between this header and
the one at include/soc/fsl/qe/qe_ic.h, which is included from a number
of places (qe_ic.c among others).
Signed-off-by: Rasmus Villemoes
---
drivers/soc/fsl/qe/qe_ic.c | 91 ++-
drivers/soc/fsl/qe/qe_ic.h | 108 -
2 files changed, 90 insertions(+), 109 deletions(-)
delete mode 100644 drivers/soc/fsl/qe/qe_ic.h
diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/soc/fsl/qe/qe_ic.c
index d420492b4c23..7b1870d2866a 100644
--- a/drivers/soc/fsl/qe/qe_ic.c
+++ b/drivers/soc/fsl/qe/qe_ic.c
@@ -26,7 +26,96 @@
#include
#include
-#include "qe_ic.h"
+#define NR_QE_IC_INTS 64
+
+/* QE IC registers offset */
+#define QEIC_CICR 0x00
+#define QEIC_CIVEC 0x04
+#define QEIC_CRIPNR0x08
+#define QEIC_CIPNR 0x0c
+#define QEIC_CIPXCC0x10
+#define QEIC_CIPYCC0x14
+#define QEIC_CIPWCC0x18
+#define QEIC_CIPZCC0x1c
+#define QEIC_CIMR 0x20
+#define QEIC_CRIMR 0x24
+#define QEIC_CICNR 0x28
+#define QEIC_CIPRTA0x30
+#define QEIC_CIPRTB0x34
+#define QEIC_CRICR 0x3c
+#define QEIC_CHIVEC0x60
+
+/* Interrupt priority registers */
+#define CIPCC_SHIFT_PRI0 29
+#define CIPCC_SHIFT_PRI1 26
+#define CIPCC_SHIFT_PRI2 23
+#define CIPCC_SHIFT_PRI3 20
+#define CIPCC_SHIFT_PRI4 13
+#define CIPCC_SHIFT_PRI5 10
+#define CIPCC_SHIFT_PRI6 7
+#define CIPCC_SHIFT_PRI7 4
+
+/* CICR priority modes */
+#define CICR_GWCC 0x0004
+#define CICR_GXCC 0x0002
+#define CICR_GYCC 0x0001
+#define CICR_GZCC 0x0008
+#define CICR_GRTA 0x0020
+#define CICR_GRTB 0x0040
+#define CICR_HPIT_SHIFT8
+#define CICR_HPIT_MASK 0x0300
+#define CICR_HP_SHIFT 24
+#define CICR_HP_MASK 0x3f00
+
+/* CICNR */
+#define CICNR_WCC1T_SHIFT 20
+#define CICNR_ZCC1T_SHIFT 28
+#define CICNR_YCC1T_SHIFT 12
+#define CICNR_XCC1T_SHIFT 4
+
+/* CRICR */
+#define CRICR_RTA1T_SHIFT 20
+#define CRICR_RTB1T_SHIFT 28
+
+/* Signal indicator */
+#define SIGNAL_MASK3
+#define SIGNAL_HIGH2
+#define SIGNAL_LOW 0
+
+struct qe_ic {
+ /* Control registers offset */
+ u32 __iomem *regs;
+
+ /* The remapper for this QEIC */
+ struct irq_domain *irqhost;
+
+ /* The "linux" controller struct */
+ struct irq_chip hc_irq;
+
+ /* VIRQ numbers of QE high/low irqs */
+ unsigned int virq_high;
+ unsigned int virq_low;
+};
+
+/*
+ * QE interrupt controller internal structure
+ */
+struct qe_ic_info {
+ /* Location of this source at the QIMR register */
+ u32 mask;
+
+ /* Mask register offset */
+ u32 mask_reg;
+
+ /*
+* For grouped interrupts sources - the interrupt code as
+* appears at the group priority register
+*/
+ u8 pri_code;
+
+ /* Group priority register offset */
+ u32 pri_reg;
+};
static DEFINE_RAW_SPINLOCK(qe_ic_lock);
diff --git a/drivers/soc/fsl/qe/qe_ic.h b/drivers/soc/fsl/qe/qe_ic.h
deleted file mode 100644
index 29b4d768e4a8..
--- a/drivers/soc/fsl/qe/qe_ic.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * drivers/soc/fsl/qe/qe_ic.h
- *
- * QUICC ENGINE Interrupt Controller Header
- *
- * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
- *
- * Author: Li Yang
- * Based on code from Shlomi Gridish
- */
-#ifndef _POWERPC_SYSDEV_QE_IC_H
-#define _POWERPC_SYSDEV_QE_IC_H
-
-#include
-
-#define NR_QE_IC_INTS 64
-
-/* QE IC registers offset */
-#define QEIC_CICR 0x00
-#define QEIC_CIVEC 0x04
-#define QEIC_CRIPNR0x08
-#define QEIC_CIPNR 0x0c
-#define QEIC_CIPXCC0x10
-#define QEIC_CIPYCC0x14
-#define QEIC_CIPWCC0x18
-#define QEIC_CIPZCC0x1c
-#define QEIC_CIMR 0x20
-#define QEIC_CRIMR 0x24
-#define QEIC_CICNR 0x28
-#define QEIC_CIPRTA0x30
-#define QEIC_CIPRTB0x34
-#define QEIC_CRICR 0x3c
-#define QEIC_CHIVEC0x60
-
-/* Interrupt priority registers */
-#define CIPCC_SHIFT_PRI0 29
-#define CIPCC_SHIFT_PRI1 26
-#define CIPCC_SHIFT_PRI2 23
-#define CIPCC_SHIFT_PRI3 20
-#define CIPCC_SHIFT_PRI4 13
-#define CIPCC_SHIFT_PRI5 10
-#define CIPCC_SHIFT_PRI6 7
-#define CIPCC_SHIFT_PRI7 4
-
-/* CICR priority modes */
-#define CICR_GWCC 0x
[PATCH v2 06/23] soc: fsl: qe: avoid tail comments in qe_ic.h
This is consistent with normal kernel coding style and the style used
in the struct definition above this one.
Signed-off-by: Rasmus Villemoes
---
drivers/soc/fsl/qe/qe_ic.h | 19 ++-
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/drivers/soc/fsl/qe/qe_ic.h b/drivers/soc/fsl/qe/qe_ic.h
index 9420378d9b6b..29b4d768e4a8 100644
--- a/drivers/soc/fsl/qe/qe_ic.h
+++ b/drivers/soc/fsl/qe/qe_ic.h
@@ -89,11 +89,20 @@ struct qe_ic {
* QE interrupt controller internal structure
*/
struct qe_ic_info {
- u32 mask; /* location of this source at the QIMR register. */
- u32 mask_reg; /* Mask register offset */
- u8 pri_code; /* for grouped interrupts sources - the interrupt
-code as appears at the group priority register */
- u32 pri_reg; /* Group priority register offset */
+ /* Location of this source at the QIMR register */
+ u32 mask;
+
+ /* Mask register offset */
+ u32 mask_reg;
+
+ /*
+* For grouped interrupts sources - the interrupt code as
+* appears at the group priority register
+*/
+ u8 pri_code;
+
+ /* Group priority register offset */
+ u32 pri_reg;
};
#endif /* _POWERPC_SYSDEV_QE_IC_H */
--
2.23.0
[PATCH v2 05/23] soc: fsl: qe: qe.c: guard use of pvr_version_is() with CONFIG_PPC32
Commit e5c5c8d23fef (soc/fsl/qe: only apply QE_General4 workaround on
affected SoCs) introduced use of pvr_version_is(), saying
The QE_General4 workaround is only valid for the MPC832x and MPC836x
SoCs. The other SoCs that embed a QUICC engine are not affected by this
hardware bug and thus can use the computed divisors (this was
successfully tested on the T1040).
I'm reading the above as saying that the errata does not apply to the
ARM-based SOCs with QUICC engine. In any case, use of pvr_version_is()
must be guarded by CONFIG_PPC32 before we can remove the PPC32
dependency from CONFIG_QUICC_ENGINE, so introduce qe_general4_errata()
to keep the necessary #ifdeffery localized to a trivial helper.
Signed-off-by: Rasmus Villemoes
---
drivers/soc/fsl/qe/qe.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c
index bcdec37b25ca..0ddf83d8e3ce 100644
--- a/drivers/soc/fsl/qe/qe.c
+++ b/drivers/soc/fsl/qe/qe.c
@@ -197,6 +197,14 @@ EXPORT_SYMBOL(qe_get_brg_clk);
#define PVR_VER_836x 0x8083
#define PVR_VER_832x 0x8084
+static bool qe_general4_errata(void)
+{
+#ifdef CONFIG_PPC32
+ return pvr_version_is(PVR_VER_836x) || pvr_version_is(PVR_VER_832x);
+#endif
+ return false;
+}
+
/* Program the BRG to the given sampling rate and multiplier
*
* @brg: the BRG, QE_BRG1 - QE_BRG16
@@ -223,7 +231,7 @@ int qe_setbrg(enum qe_clock brg, unsigned int rate,
unsigned int multiplier)
/* Errata QE_General4, which affects some MPC832x and MPC836x SOCs, says
that the BRG divisor must be even if you're not using divide-by-16
mode. */
- if (pvr_version_is(PVR_VER_836x) || pvr_version_is(PVR_VER_832x))
+ if (qe_general4_errata())
if (!div16 && (divisor & 1) && (divisor > 3))
divisor++;
--
2.23.0
[PATCH v2 03/23] soc: fsl: qe: avoid ppc-specific io accessors
In preparation for allowing to build QE support for architectures
other than PPC, replace the ppc-specific io accessors. Done via
$ spatch --sp-file io.cocci --in-place drivers/soc/fsl/qe/
where io.cocci is
@@
expression addr, val;
@@
- out_be32(addr, val)
+ iowrite32be(val, addr)
@@
expression addr;
@@
- in_be32(addr)
+ ioread32be(addr)
@@
expression addr, val;
@@
- out_be16(addr, val)
+ iowrite16be(val, addr)
@@
expression addr;
@@
- in_be16(addr)
+ ioread16be(addr)
@@
expression addr, val;
@@
- out_8(addr, val)
+ iowrite8(val, addr)
@@
expression addr;
@@
- in_8(addr)
+ ioread8(addr)
@@
expression addr, clr, set;
@@
- clrsetbits_be32(addr, clr, set)
+ qe_clrsetbits32(addr, clr, set)
@@
expression addr, clr, set;
@@
- clrsetbits_be16(addr, clr, set)
+ qe_clrsetbits16(addr, clr, set)
@@
expression addr, clr, set;
@@
- clrsetbits_8(addr, clr, set)
+ qe_clrsetbits8(addr, clr, set)
@@
expression addr, set;
@@
- setbits32(addr, set)
+ qe_setbits32(addr, set)
@@
expression addr, set;
@@
- setbits16(addr, set)
+ qe_setbits16(addr, set)
@@
expression addr, set;
@@
- setbits8(addr, set)
+ qe_setbits8(addr, set)
@@
expression addr, clr;
@@
- clrbits32(addr, clr)
+ qe_clrbits32(addr, clr)
@@
expression addr, clr;
@@
- clrbits16(addr, clr)
+ qe_clrbits16(addr, clr)
@@
expression addr, clr;
@@
- clrbits8(addr, clr)
+ qe_clrbits8(addr, clr)
Signed-off-by: Rasmus Villemoes
---
drivers/soc/fsl/qe/gpio.c | 30 +++
drivers/soc/fsl/qe/qe.c | 35 +-
drivers/soc/fsl/qe/qe_ic.c| 4 +-
drivers/soc/fsl/qe/qe_io.c| 40 +---
drivers/soc/fsl/qe/qe_tdm.c | 8 ++--
drivers/soc/fsl/qe/ucc.c | 16
drivers/soc/fsl/qe/ucc_fast.c | 70 ++-
drivers/soc/fsl/qe/ucc_slow.c | 38 +--
drivers/soc/fsl/qe/usb.c | 2 +-
9 files changed, 120 insertions(+), 123 deletions(-)
diff --git a/drivers/soc/fsl/qe/gpio.c b/drivers/soc/fsl/qe/gpio.c
index f0c29ed8f0ff..949a35ac253c 100644
--- a/drivers/soc/fsl/qe/gpio.c
+++ b/drivers/soc/fsl/qe/gpio.c
@@ -41,13 +41,13 @@ static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
container_of(mm_gc, struct qe_gpio_chip, mm_gc);
struct qe_pio_regs __iomem *regs = mm_gc->regs;
- qe_gc->cpdata = in_be32(®s->cpdata);
+ qe_gc->cpdata = ioread32be(®s->cpdata);
qe_gc->saved_regs.cpdata = qe_gc->cpdata;
- qe_gc->saved_regs.cpdir1 = in_be32(®s->cpdir1);
- qe_gc->saved_regs.cpdir2 = in_be32(®s->cpdir2);
- qe_gc->saved_regs.cppar1 = in_be32(®s->cppar1);
- qe_gc->saved_regs.cppar2 = in_be32(®s->cppar2);
- qe_gc->saved_regs.cpodr = in_be32(®s->cpodr);
+ qe_gc->saved_regs.cpdir1 = ioread32be(®s->cpdir1);
+ qe_gc->saved_regs.cpdir2 = ioread32be(®s->cpdir2);
+ qe_gc->saved_regs.cppar1 = ioread32be(®s->cppar1);
+ qe_gc->saved_regs.cppar2 = ioread32be(®s->cppar2);
+ qe_gc->saved_regs.cpodr = ioread32be(®s->cpodr);
}
static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
@@ -56,7 +56,7 @@ static int qe_gpio_get(struct gpio_chip *gc, unsigned int
gpio)
struct qe_pio_regs __iomem *regs = mm_gc->regs;
u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
- return !!(in_be32(®s->cpdata) & pin_mask);
+ return !!(ioread32be(®s->cpdata) & pin_mask);
}
static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
@@ -74,7 +74,7 @@ static void qe_gpio_set(struct gpio_chip *gc, unsigned int
gpio, int val)
else
qe_gc->cpdata &= ~pin_mask;
- out_be32(®s->cpdata, qe_gc->cpdata);
+ iowrite32be(qe_gc->cpdata, ®s->cpdata);
spin_unlock_irqrestore(&qe_gc->lock, flags);
}
@@ -101,7 +101,7 @@ static void qe_gpio_set_multiple(struct gpio_chip *gc,
}
}
- out_be32(®s->cpdata, qe_gc->cpdata);
+ iowrite32be(qe_gc->cpdata, ®s->cpdata);
spin_unlock_irqrestore(&qe_gc->lock, flags);
}
@@ -255,11 +255,11 @@ void qe_pin_set_dedicated(struct qe_pin *qe_pin)
spin_lock_irqsave(&qe_gc->lock, flags);
if (second_reg) {
- clrsetbits_be32(®s->cpdir2, mask2, sregs->cpdir2 & mask2);
- clrsetbits_be32(®s->cppar2, mask2, sregs->cppar2 & mask2);
+ qe_clrsetbits32(®s->cpdir2, mask2, sregs->cpdir2 & mask2);
+ qe_clrsetbits32(®s->cppar2, mask2, sregs->cppar2 & mask2);
} else {
- clrsetbits_be32(®s->cpdir1, mask2, sregs->cpdir1 & mask2);
- clrsetbits_be32(®s->cppar1, mask2, sregs->cppar1 & mask2);
+ qe_clrsetbits32(®s->cpdir1, mask2, sregs->cpdir1 & mask2);
+ qe_clrsetbits32(®s->cppar1, mask2, sregs->cppar1 & mask2);
}
if (sregs->cpdata & mask1)
@@ -267,8 +267,8 @@ void qe_pin_set_dedicated(struct qe_pin *qe_pin)
else
qe_gc->cpdata &= ~mask1;
- out_be32(®s->cpdata, qe_gc->cpdata);
-
[PATCH v2 04/23] soc: fsl: qe: replace spin_event_timeout by readx_poll_timeout_atomic
In preparation for allowing QE to be built for architectures other
than ppc, use the generic readx_poll_timeout_atomic() helper from
iopoll.h rather than the ppc-only spin_event_timeout().
Signed-off-by: Rasmus Villemoes
---
drivers/soc/fsl/qe/qe.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c
index 60bf047001be..bcdec37b25ca 100644
--- a/drivers/soc/fsl/qe/qe.c
+++ b/drivers/soc/fsl/qe/qe.c
@@ -22,6 +22,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -108,7 +109,8 @@ int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32
cmd_input)
{
unsigned long flags;
u8 mcn_shift = 0, dev_shift = 0;
- u32 ret;
+ u32 val;
+ int ret;
spin_lock_irqsave(&qe_lock, flags);
if (cmd == QE_RESET) {
@@ -135,13 +137,12 @@ int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol,
u32 cmd_input)
}
/* wait for the QE_CR_FLG to clear */
- ret = spin_event_timeout((ioread32be(&qe_immr->cp.cecr) & QE_CR_FLG) ==
0,
-100, 0);
- /* On timeout (e.g. failure), the expression will be false (ret == 0),
- otherwise it will be true (ret == 1). */
+ ret = readx_poll_timeout_atomic(ioread32be, &qe_immr->cp.cecr, val,
+ (val & QE_CR_FLG) == 0, 0, 100);
+ /* On timeout, ret is -ETIMEDOUT, otherwise it will be 0. */
spin_unlock_irqrestore(&qe_lock, flags);
- return ret == 1;
+ return ret == 0;
}
EXPORT_SYMBOL(qe_issue_cmd);
--
2.23.0
[PATCH v2 02/23] soc: fsl: qe: drop volatile qualifier of struct qe_ic::regs
The actual io accessors (e.g. in_be32) implicitly add a volatile
qualifier to their address argument. Remove volatile from the struct
definition and the qe_ic_(read/write) helpers, in preparation for
switching from the ppc-specific io accessors to generic ones.
Signed-off-by: Rasmus Villemoes
---
drivers/soc/fsl/qe/qe_ic.c | 4 ++--
drivers/soc/fsl/qe/qe_ic.h | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/soc/fsl/qe/qe_ic.c
index 9bac546998d3..791adcd121d1 100644
--- a/drivers/soc/fsl/qe/qe_ic.c
+++ b/drivers/soc/fsl/qe/qe_ic.c
@@ -171,12 +171,12 @@ static struct qe_ic_info qe_ic_info[] = {
},
};
-static inline u32 qe_ic_read(volatile __be32 __iomem * base, unsigned int reg)
+static inline u32 qe_ic_read(__be32 __iomem *base, unsigned int reg)
{
return in_be32(base + (reg >> 2));
}
-static inline void qe_ic_write(volatile __be32 __iomem * base, unsigned int
reg,
+static inline void qe_ic_write(__be32 __iomem *base, unsigned int reg,
u32 value)
{
out_be32(base + (reg >> 2), value);
diff --git a/drivers/soc/fsl/qe/qe_ic.h b/drivers/soc/fsl/qe/qe_ic.h
index 08c695672a03..9420378d9b6b 100644
--- a/drivers/soc/fsl/qe/qe_ic.h
+++ b/drivers/soc/fsl/qe/qe_ic.h
@@ -72,7 +72,7 @@
struct qe_ic {
/* Control registers offset */
- volatile u32 __iomem *regs;
+ u32 __iomem *regs;
/* The remapper for this QEIC */
struct irq_domain *irqhost;
--
2.23.0
[PATCH v2 01/23] soc: fsl: qe: remove space-before-tab
Signed-off-by: Rasmus Villemoes --- drivers/soc/fsl/qe/qe.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c index 417df7e19281..2a0e6e642776 100644 --- a/drivers/soc/fsl/qe/qe.c +++ b/drivers/soc/fsl/qe/qe.c @@ -378,8 +378,8 @@ static int qe_sdma_init(void) } out_be32(&sdma->sdebcr, (u32) sdma_buf_offset & QE_SDEBCR_BA_MASK); - out_be32(&sdma->sdmr, (QE_SDMR_GLB_1_MSK | - (0x1 << QE_SDMR_CEN_SHIFT))); + out_be32(&sdma->sdmr, (QE_SDMR_GLB_1_MSK | +(0x1 << QE_SDMR_CEN_SHIFT))); return 0; } -- 2.23.0
[PATCH v2 00/23] QUICC Engine support on ARM
There have been several attempts in the past few years to allow
building the QUICC engine drivers for platforms other than PPC. This
is yet another attempt.
In v2, I've fixed a few style issues. But more importantly, it now
contains enough to actually remove the PPC32 dependency from
CONFIG_QUICC_ENGINE, so that's what the last patch does.
I haven't found a way to address Christophe's concern over the
performance impact of using the (on powerpc) out-of-line iowrite32be
instead of out_be32. I could of course introduce some qe_ prefixed
helpers (similar to the already added qe_clrsetbits ones) and make
their definition dependent on PPC32 or not, but that seems to be a bit
ugly.
Rasmus Villemoes (23):
soc: fsl: qe: remove space-before-tab
soc: fsl: qe: drop volatile qualifier of struct qe_ic::regs
soc: fsl: qe: avoid ppc-specific io accessors
soc: fsl: qe: replace spin_event_timeout by readx_poll_timeout_atomic
soc: fsl: qe: qe.c: guard use of pvr_version_is() with CONFIG_PPC32
soc: fsl: qe: avoid tail comments in qe_ic.h
soc: fsl: qe: merge qe_ic.h into qe_ic.c
soc: fsl: qe: drop unneeded #includes
soc: fsl: qe: move qe_ic_cascade_* functions to qe_ic.c
soc: fsl: qe: use qe_ic_cascade_{low,high}_mpic also on 83xx
soc: fsl: qe: rename qe_ic_cascade_low_mpic -> qe_ic_cascade_low
soc: fsl: qe: drop assign-only high_active in qe_ic_init
soc: fsl: qe: remove pointless sysfs registration in qe_ic.c
soc: fsl: qe: move calls of qe_ic_init out of arch/powerpc/
powerpc/83xx: remove mpc83xx_ipic_and_qe_init_IRQ
powerpc/85xx: remove mostly pointless mpc85xx_qe_init()
soc: fsl: qe: make qe_ic_cascade_* static
soc: fsl: qe: remove unused qe_ic_set_* functions
net: ethernet: freescale: make UCC_GETH explicitly depend on PPC32
serial: make SERIAL_QE depend on PPC32
serial: ucc_uart.c: explicitly include asm/cpm.h
soc/fsl/qe/qe.h: remove include of asm/cpm.h
soc: fsl: qe: remove PPC32 dependency from CONFIG_QUICC_ENGINE
arch/powerpc/platforms/83xx/km83xx.c | 3 +-
arch/powerpc/platforms/83xx/misc.c| 23 --
arch/powerpc/platforms/83xx/mpc832x_mds.c | 3 +-
arch/powerpc/platforms/83xx/mpc832x_rdb.c | 3 +-
arch/powerpc/platforms/83xx/mpc836x_mds.c | 3 +-
arch/powerpc/platforms/83xx/mpc836x_rdk.c | 3 +-
arch/powerpc/platforms/83xx/mpc83xx.h | 7 -
arch/powerpc/platforms/85xx/common.c | 23 --
arch/powerpc/platforms/85xx/corenet_generic.c | 12 -
arch/powerpc/platforms/85xx/mpc85xx.h | 2 -
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 28 --
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 18 --
arch/powerpc/platforms/85xx/twr_p102x.c | 16 -
drivers/net/ethernet/freescale/Kconfig| 1 +
drivers/soc/fsl/qe/Kconfig| 2 +-
drivers/soc/fsl/qe/gpio.c | 30 +-
drivers/soc/fsl/qe/qe.c | 59 ++--
drivers/soc/fsl/qe/qe_ic.c| 289 ++
drivers/soc/fsl/qe/qe_ic.h| 99 --
drivers/soc/fsl/qe/qe_io.c| 42 ++-
drivers/soc/fsl/qe/qe_tdm.c | 8 +-
drivers/soc/fsl/qe/ucc.c | 16 +-
drivers/soc/fsl/qe/ucc_fast.c | 70 ++---
drivers/soc/fsl/qe/ucc_slow.c | 38 +--
drivers/soc/fsl/qe/usb.c | 2 +-
drivers/tty/serial/Kconfig| 1 +
drivers/tty/serial/ucc_uart.c | 1 +
include/soc/fsl/qe/qe.h | 1 -
include/soc/fsl/qe/qe_ic.h| 69 -
29 files changed, 299 insertions(+), 573 deletions(-)
delete mode 100644 drivers/soc/fsl/qe/qe_ic.h
--
2.23.0
[REVIEW PATCH v5 2/3] arch: wire-up close_range()
This wires up the close_range() syscall into all arches at once. Suggested-by: Arnd Bergmann Signed-off-by: Christian Brauner Reviewed-by: Oleg Nesterov Acked-by: Arnd Bergmann Acked-by: Michael Ellerman (powerpc) Cc: Jann Horn Cc: David Howells Cc: Dmitry V. Levin Cc: Linus Torvalds Cc: Al Viro Cc: Florian Weimer Cc: linux-...@vger.kernel.org Cc: linux-al...@vger.kernel.org Cc: linux-arm-ker...@lists.infradead.org Cc: linux-i...@vger.kernel.org Cc: linux-m...@lists.linux-m68k.org Cc: linux-m...@vger.kernel.org Cc: linux-par...@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org Cc: linux-s...@vger.kernel.org Cc: linux...@vger.kernel.org Cc: sparcli...@vger.kernel.org Cc: linux-xte...@linux-xtensa.org Cc: linux-a...@vger.kernel.org Cc: x...@kernel.org --- /* v2 */ not present /* v3 */ not present /* v4 */ introduced - Arnd Bergmann : - split into two patches: 1. add close_range() 2. add syscall to all arches at once - bump __NR_compat_syscalls in arch/arm64/include/asm/unistd.h /* v5 */ - Christian Brauner : --- arch/alpha/kernel/syscalls/syscall.tbl | 1 + arch/arm/tools/syscall.tbl | 1 + arch/arm64/include/asm/unistd.h | 2 +- arch/arm64/include/asm/unistd32.h | 2 ++ arch/ia64/kernel/syscalls/syscall.tbl | 1 + arch/m68k/kernel/syscalls/syscall.tbl | 1 + arch/microblaze/kernel/syscalls/syscall.tbl | 1 + arch/mips/kernel/syscalls/syscall_n32.tbl | 1 + arch/mips/kernel/syscalls/syscall_n64.tbl | 1 + arch/mips/kernel/syscalls/syscall_o32.tbl | 1 + arch/parisc/kernel/syscalls/syscall.tbl | 1 + arch/powerpc/kernel/syscalls/syscall.tbl| 1 + arch/s390/kernel/syscalls/syscall.tbl | 1 + arch/sh/kernel/syscalls/syscall.tbl | 1 + arch/sparc/kernel/syscalls/syscall.tbl | 1 + arch/x86/entry/syscalls/syscall_32.tbl | 1 + arch/x86/entry/syscalls/syscall_64.tbl | 1 + arch/xtensa/kernel/syscalls/syscall.tbl | 1 + include/uapi/asm-generic/unistd.h | 4 +++- 19 files changed, 22 insertions(+), 2 deletions(-) diff --git a/arch/alpha/kernel/syscalls/syscall.tbl b/arch/alpha/kernel/syscalls/syscall.tbl index 728fe028c02c..f08906efa5ff 100644 --- a/arch/alpha/kernel/syscalls/syscall.tbl +++ b/arch/alpha/kernel/syscalls/syscall.tbl @@ -475,3 +475,4 @@ 543common fspick sys_fspick 544common pidfd_open sys_pidfd_open # 545 reserved for clone3 +546common close_range sys_close_range diff --git a/arch/arm/tools/syscall.tbl b/arch/arm/tools/syscall.tbl index 6da7dc4d79cc..f25716576d13 100644 --- a/arch/arm/tools/syscall.tbl +++ b/arch/arm/tools/syscall.tbl @@ -449,3 +449,4 @@ 433common fspick sys_fspick 434common pidfd_open sys_pidfd_open 435common clone3 sys_clone3 +436common close_range sys_close_range diff --git a/arch/arm64/include/asm/unistd.h b/arch/arm64/include/asm/unistd.h index 2629a68b8724..368761302768 100644 --- a/arch/arm64/include/asm/unistd.h +++ b/arch/arm64/include/asm/unistd.h @@ -38,7 +38,7 @@ #define __ARM_NR_compat_set_tls(__ARM_NR_COMPAT_BASE + 5) #define __ARM_NR_COMPAT_END(__ARM_NR_COMPAT_BASE + 0x800) -#define __NR_compat_syscalls 436 +#define __NR_compat_syscalls 437 #endif #define __ARCH_WANT_SYS_CLONE diff --git a/arch/arm64/include/asm/unistd32.h b/arch/arm64/include/asm/unistd32.h index 94ab29cf4f00..c1309f52c8ac 100644 --- a/arch/arm64/include/asm/unistd32.h +++ b/arch/arm64/include/asm/unistd32.h @@ -879,6 +879,8 @@ __SYSCALL(__NR_fspick, sys_fspick) __SYSCALL(__NR_pidfd_open, sys_pidfd_open) #define __NR_clone3 435 __SYSCALL(__NR_clone3, sys_clone3) +#define __NR_close_range 436 +__SYSCALL(__NR_close_range, sys_close_range) /* * Please add new compat syscalls above this comment and update diff --git a/arch/ia64/kernel/syscalls/syscall.tbl b/arch/ia64/kernel/syscalls/syscall.tbl index 36d5faf4c86c..151f4fd234be 100644 --- a/arch/ia64/kernel/syscalls/syscall.tbl +++ b/arch/ia64/kernel/syscalls/syscall.tbl @@ -356,3 +356,4 @@ 433common fspick sys_fspick 434common pidfd_open sys_pidfd_open # 435 reserved for clone3 +436common close_range sys_close_range diff --git a/arch/m68k/kernel/syscalls/syscall.tbl b/arch/m68k/kernel/syscalls/syscall.tbl index a88a285a0e5f..adff06c08d2f 100644 --- a/arch/m68k/kernel/syscalls/syscall.tbl +++ b/arch/m68k/kernel/syscalls/syscall.tbl @@ -435,3 +435,4 @@ 433common fspick sys_fspick 434common pidfd_open sys_pidfd_open # 435 reserved for clone3 +436common close_range sys_close_range diff --git a/arch/microblaze/kernel/syscalls/syscall.tbl b/arch/microblaze/kernel/syscalls/syscall.tbl index 09b0c
[PATCH trivial resend] powerpc/booke: Spelling s/date/data/
Caching dates is never a good idea ;-)
Fixes: e7affb1dba0e9068 ("powerpc/cache: add cache flush operation for various
e500")
Signed-off-by: Geert Uytterhoeven
---
arch/powerpc/kernel/cpu_setup_fsl_booke.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index 2b4f3ec0acf7d988..1d308780e0d31eb9 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -231,7 +231,7 @@ _GLOBAL(__setup_cpu_e5500)
blr
#endif
-/* flush L1 date cache, it can apply to e500v2, e500mc and e5500 */
+/* flush L1 data cache, it can apply to e500v2, e500mc and e5500 */
_GLOBAL(flush_dcache_L1)
mfmsr r10
wrteei 0
--
2.17.1
Re: [PATCH] powerpc/prom_init: Undo relocation before entering secure mode
Thiago Jung Bauermann writes:
> The ultravisor will do an integrity check of the kernel image but we
> relocated it so the check will fail. Restore the original image by
> relocating it back to the kernel virtual base address.
>
> This works because during build vmlinux is linked with an expected virtual
> runtime address of KERNELBASE.
>
> Fixes: 6a9c930bd775 ("powerpc/prom_init: Add the ESM call to prom_init")
> Signed-off-by: Thiago Jung Bauermann
> ---
> arch/powerpc/include/asm/elf.h | 3 +++
> arch/powerpc/kernel/prom_init.c| 11 +++
> arch/powerpc/kernel/prom_init_check.sh | 3 ++-
> 3 files changed, 16 insertions(+), 1 deletion(-)
This breaks the build when CONFIG_RELOCATABLE=n:
prom_init.c:(.init.text+0x3160): undefined reference to `relocate'
See http://kisskb.ellerman.id.au/kisskb/buildresult/14004234/
cheers
Re: [PATCH V7] mm/debug: Add tests validating architecture page table helpers
On 10/25/2019 02:22 PM, Christophe Leroy wrote:
>
>
> Le 25/10/2019 à 10:24, Anshuman Khandual a écrit :
>>
>>
>> On 10/25/2019 12:41 PM, Christophe Leroy wrote:
>>>
>>>
>>> Le 25/10/2019 à 07:52, Qian Cai a écrit :
> On Oct 24, 2019, at 11:45 PM, Anshuman Khandual
> wrote:
>
> Nothing specific. But just tested this with x86 defconfig with relevant
> configs
> which are required for this test. Not sure if it involved W=1.
No, it will not. It needs to run like,
make W=1 -j 64 2>/tmp/warns
>>>
>>> Are we talking about this peace of code ?
>>>
>>> +static unsigned long __init get_random_vaddr(void)
>>> +{
>>> + unsigned long random_vaddr, random_pages, total_user_pages;
>>> +
>>> + total_user_pages = (TASK_SIZE - FIRST_USER_ADDRESS) / PAGE_SIZE;
>>> +
>>> + random_pages = get_random_long() % total_user_pages;
>>> + random_vaddr = FIRST_USER_ADDRESS + random_pages * PAGE_SIZE;
>>> +
>>> + WARN_ON((random_vaddr > TASK_SIZE) ||
>>> + (random_vaddr < FIRST_USER_ADDRESS));
>>> + return random_vaddr;
>>> +}
>>> +
>>>
>>> ramdom_vaddr is unsigned,
>>> random_pages is unsigned and lower than total_user_pages
>>>
>>> So the max value random_vaddr can get is FIRST_USER_ADDRESS + ((TASK_SIZE -
>>> FIRST_USER_ADDRESS - 1) / PAGE_SIZE) * PAGE_SIZE = TASK_SIZE - 1
>>> And the min value random_vaddr can get is FIRST_USER_ADDRESS (that's when
>>> random_pages = 0)
>>
>> That's right.
>>
>>>
>>> So the WARN_ON() is just unneeded, isn't it ?
>>
>> It is just a sanity check on possible vaddr values before it's corresponding
>> page table mappings could be created. If it's worth to drop this in favor of
>> avoiding these unwanted warning messages on x86, will go ahead with it as it
>> is not super important.
>>
>
> But you are checking what ? That the compiler does calculation correctly or
> what ?
IIRC, probably this was for later if and when the vaddr calculation becomes
dependent on other factors rather than this simple arithmetic involving start
and end of process address space on a platform.
> As mentionned just above, based on the calculation done, what you are testing
> cannot happen, so I'm having a hard time understanding what kind of sanity
> check it can be.
You are right.
>
> Can you give an exemple of a situation which could trigger the warning ?
I was mistaken. We dont need those checks for now, hence will drop them next
time.
>
> Christophe
>
RE: [PATCH] powerpc/tools: Don't quote $objdump in scripts
From: Segher Boessenkool > Sent: 24 October 2019 18:29 > On Thu, Oct 24, 2019 at 11:47:30AM +1100, Michael Ellerman wrote: > > Some of our scripts are passed $objdump and then call it as > > "$objdump". This doesn't work if it contains spaces because we're > > using ccache, for example you get errors such as: > > > > ./arch/powerpc/tools/relocs_check.sh: line 48: ccache ppc64le-objdump: No > > such file or directory > > ./arch/powerpc/tools/unrel_branch_check.sh: line 26: ccache > > ppc64le-objdump: No such file or directory > > > > Fix it by not quoting the string when we expand it, allowing the shell > > to do the right thing for us. > > This breaks things for people with spaces in their paths. Why doesn't your > user use something like alias objdump="ccache ppc64le-objdump" , instead? Given that make doesn't handle spaces in filenames it is likely that a build will have terrible issues is there are spaces in any directory names. (It is a right PITA running make on a certain OS.) For command paths, spaces can be replaced by ? relying on shell globbing to restore the space. OTOH rather than alias, put the name of a script containing: #! /bin/sh exec ccache ppc64le-objdump "$@" into $objdump. David - Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK Registration No: 1397386 (Wales)
Re: [PATCH V7] mm/debug: Add tests validating architecture page table helpers
Le 25/10/2019 à 10:24, Anshuman Khandual a écrit :
On 10/25/2019 12:41 PM, Christophe Leroy wrote:
Le 25/10/2019 à 07:52, Qian Cai a écrit :
On Oct 24, 2019, at 11:45 PM, Anshuman Khandual
wrote:
Nothing specific. But just tested this with x86 defconfig with relevant configs
which are required for this test. Not sure if it involved W=1.
No, it will not. It needs to run like,
make W=1 -j 64 2>/tmp/warns
Are we talking about this peace of code ?
+static unsigned long __init get_random_vaddr(void)
+{
+ unsigned long random_vaddr, random_pages, total_user_pages;
+
+ total_user_pages = (TASK_SIZE - FIRST_USER_ADDRESS) / PAGE_SIZE;
+
+ random_pages = get_random_long() % total_user_pages;
+ random_vaddr = FIRST_USER_ADDRESS + random_pages * PAGE_SIZE;
+
+ WARN_ON((random_vaddr > TASK_SIZE) ||
+ (random_vaddr < FIRST_USER_ADDRESS));
+ return random_vaddr;
+}
+
ramdom_vaddr is unsigned,
random_pages is unsigned and lower than total_user_pages
So the max value random_vaddr can get is FIRST_USER_ADDRESS + ((TASK_SIZE -
FIRST_USER_ADDRESS - 1) / PAGE_SIZE) * PAGE_SIZE = TASK_SIZE - 1
And the min value random_vaddr can get is FIRST_USER_ADDRESS (that's when
random_pages = 0)
That's right.
So the WARN_ON() is just unneeded, isn't it ?
It is just a sanity check on possible vaddr values before it's corresponding
page table mappings could be created. If it's worth to drop this in favor of
avoiding these unwanted warning messages on x86, will go ahead with it as it
is not super important.
But you are checking what ? That the compiler does calculation correctly
or what ?
As mentionned just above, based on the calculation done, what you are
testing cannot happen, so I'm having a hard time understanding what kind
of sanity check it can be.
Can you give an exemple of a situation which could trigger the warning ?
Christophe
Re: [PATCH V7] mm/debug: Add tests validating architecture page table helpers
On 10/25/2019 12:41 PM, Christophe Leroy wrote:
>
>
> Le 25/10/2019 à 07:52, Qian Cai a écrit :
>>
>>
>>> On Oct 24, 2019, at 11:45 PM, Anshuman Khandual
>>> wrote:
>>>
>>> Nothing specific. But just tested this with x86 defconfig with relevant
>>> configs
>>> which are required for this test. Not sure if it involved W=1.
>>
>> No, it will not. It needs to run like,
>>
>> make W=1 -j 64 2>/tmp/warns
>>
>
> Are we talking about this peace of code ?
>
> +static unsigned long __init get_random_vaddr(void)
> +{
> + unsigned long random_vaddr, random_pages, total_user_pages;
> +
> + total_user_pages = (TASK_SIZE - FIRST_USER_ADDRESS) / PAGE_SIZE;
> +
> + random_pages = get_random_long() % total_user_pages;
> + random_vaddr = FIRST_USER_ADDRESS + random_pages * PAGE_SIZE;
> +
> + WARN_ON((random_vaddr > TASK_SIZE) ||
> + (random_vaddr < FIRST_USER_ADDRESS));
> + return random_vaddr;
> +}
> +
>
> ramdom_vaddr is unsigned,
> random_pages is unsigned and lower than total_user_pages
>
> So the max value random_vaddr can get is FIRST_USER_ADDRESS + ((TASK_SIZE -
> FIRST_USER_ADDRESS - 1) / PAGE_SIZE) * PAGE_SIZE = TASK_SIZE - 1
> And the min value random_vaddr can get is FIRST_USER_ADDRESS (that's when
> random_pages = 0)
That's right.
>
> So the WARN_ON() is just unneeded, isn't it ?
It is just a sanity check on possible vaddr values before it's corresponding
page table mappings could be created. If it's worth to drop this in favor of
avoiding these unwanted warning messages on x86, will go ahead with it as it
is not super important.
>
> Christophe
>
[Bug 205303] Compilation for PPC64 fails on warning in watchdog.o
https://bugzilla.kernel.org/show_bug.cgi?id=205303 A. Wilcox (awil...@adelielinux.org) changed: What|Removed |Added CC||awil...@adelielinux.org --- Comment #2 from A. Wilcox (awil...@adelielinux.org) --- This is because CONFIG_HARDLOCK_DETECTOR is on and CONFIG_NMI_IPI is off. CONFIG_HARDLOCK_DETECTOR pulls in CONFIG_PPC_WATCHDOG, which unconditionally uses smp_send_nmi_ipi (and I believe requires such to work properly). CONFIG_PPC_WATCHDOG doesn't depend on CONFIG_NMI_IPI which it probably should. And then CONFIG_HARDLOCK_DETECTOR_ARCH should probably depend on CONFIG_NMI_IPI or CONFIG_PPC_WATCHDOG. -- You are receiving this mail because: You are watching the assignee of the bug.
Re: [PATCH 00/10] Add support for OpenCAPI SCM devices
Hi Alastair,
On Fri, Oct 25, 2019 at 6:48 AM Alastair D'Silva wrote:
> From: Alastair D'Silva
>
> This series adds support for OpenCAPI SCM devices, exposing
> them as nvdimms so that we can make use of the existing
> infrastructure.
Thanks for your series!
The long CC list is a sign of get_maintainter.pl-considered-harmful.
Please trim it (by removing me, a.o. ;-) for next submission.
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
[PATCH V2] ASoC: fsl_esai: Add spin lock to protect reset, stop and start
xrun may happen at the end of stream, the
trigger->fsl_esai_trigger_stop maybe called in the middle of
fsl_esai_hw_reset, this may cause esai in wrong state
after stop, and there may be endless xrun interrupt.
This issue may also happen with trigger->fsl_esai_trigger_start.
So Add spin lock to lock those functions.
Fixes: 7ccafa2b3879 ("ASoC: fsl_esai: recover the channel swap after xrun")
Signed-off-by: Shengjiu Wang
---
Change in v2
-add lock for fsl_esai_trigger_start.
sound/soc/fsl/fsl_esai.c | 12
1 file changed, 12 insertions(+)
diff --git a/sound/soc/fsl/fsl_esai.c b/sound/soc/fsl/fsl_esai.c
index 37b14c48b537..9b28e2af26e4 100644
--- a/sound/soc/fsl/fsl_esai.c
+++ b/sound/soc/fsl/fsl_esai.c
@@ -33,6 +33,7 @@
* @fsysclk: system clock source to derive HCK, SCK and FS
* @spbaclk: SPBA clock (optional, depending on SoC design)
* @task: tasklet to handle the reset operation
+ * @lock: spin lock to handle reset and stop behavior
* @fifo_depth: depth of tx/rx FIFO
* @slot_width: width of each DAI slot
* @slots: number of slots
@@ -56,6 +57,7 @@ struct fsl_esai {
struct clk *fsysclk;
struct clk *spbaclk;
struct tasklet_struct task;
+ spinlock_t lock; /* Protect reset and stop */
u32 fifo_depth;
u32 slot_width;
u32 slots;
@@ -676,8 +678,10 @@ static void fsl_esai_hw_reset(unsigned long arg)
{
struct fsl_esai *esai_priv = (struct fsl_esai *)arg;
bool tx = true, rx = false, enabled[2];
+ unsigned long lock_flags;
u32 tfcr, rfcr;
+ spin_lock_irqsave(&esai_priv->lock, lock_flags);
/* Save the registers */
regmap_read(esai_priv->regmap, REG_ESAI_TFCR, &tfcr);
regmap_read(esai_priv->regmap, REG_ESAI_RFCR, &rfcr);
@@ -715,6 +719,8 @@ static void fsl_esai_hw_reset(unsigned long arg)
fsl_esai_trigger_start(esai_priv, tx);
if (enabled[rx])
fsl_esai_trigger_start(esai_priv, rx);
+
+ spin_unlock_irqrestore(&esai_priv->lock, lock_flags);
}
static int fsl_esai_trigger(struct snd_pcm_substream *substream, int cmd,
@@ -722,6 +728,7 @@ static int fsl_esai_trigger(struct snd_pcm_substream
*substream, int cmd,
{
struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
+ unsigned long lock_flags;
esai_priv->channels[tx] = substream->runtime->channels;
@@ -729,12 +736,16 @@ static int fsl_esai_trigger(struct snd_pcm_substream
*substream, int cmd,
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+ spin_lock_irqsave(&esai_priv->lock, lock_flags);
fsl_esai_trigger_start(esai_priv, tx);
+ spin_unlock_irqrestore(&esai_priv->lock, lock_flags);
break;
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+ spin_lock_irqsave(&esai_priv->lock, lock_flags);
fsl_esai_trigger_stop(esai_priv, tx);
+ spin_unlock_irqrestore(&esai_priv->lock, lock_flags);
break;
default:
return -EINVAL;
@@ -1002,6 +1013,7 @@ static int fsl_esai_probe(struct platform_device *pdev)
dev_set_drvdata(&pdev->dev, esai_priv);
+ spin_lock_init(&esai_priv->lock);
ret = fsl_esai_hw_init(esai_priv);
if (ret)
return ret;
--
2.21.0
[PATCH V2] ASoC: fsl_asrc: refine the setting of internal clock divider
The output divider should align with the output sample
rate, if use ideal sample rate, there will be a lot of overload,
which would cause underrun.
The maximum divider of asrc clock is 1024, but there is no
judgement for this limitaion in driver, which may cause the divider
setting not correct.
For non-ideal ratio mode, the clock rate should divide the sample
rate with no remainder, and the quotient should be less than 1024.
Signed-off-by: Shengjiu Wang
---
Change in v2
- remove p2p/m2m word
- use use_ideal_rate
sound/soc/fsl/fsl_asrc.c | 37 +++--
1 file changed, 27 insertions(+), 10 deletions(-)
diff --git a/sound/soc/fsl/fsl_asrc.c b/sound/soc/fsl/fsl_asrc.c
index 0bf91a6f54b9..89cf333154c7 100644
--- a/sound/soc/fsl/fsl_asrc.c
+++ b/sound/soc/fsl/fsl_asrc.c
@@ -259,8 +259,11 @@ static int fsl_asrc_set_ideal_ratio(struct fsl_asrc_pair
*pair,
* It configures those ASRC registers according to a configuration instance
* of struct asrc_config which includes in/output sample rate, width, channel
* and clock settings.
+ *
+ * Note:
+ * use_ideal_rate = true is need by some case which need higher performance.
*/
-static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair)
+static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair, bool
use_ideal_rate)
{
struct asrc_config *config = pair->config;
struct fsl_asrc *asrc_priv = pair->asrc_priv;
@@ -268,7 +271,8 @@ static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair)
enum asrc_word_width input_word_width;
enum asrc_word_width output_word_width;
u32 inrate, outrate, indiv, outdiv;
- u32 clk_index[2], div[2];
+ u32 clk_index[2], div[2], rem[2];
+ u64 clk_rate;
int in, out, channels;
int pre_proc, post_proc;
struct clk *clk;
@@ -351,8 +355,10 @@ static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair)
/* We only have output clock for ideal ratio mode */
clk = asrc_priv->asrck_clk[clk_index[ideal ? OUT : IN]];
- div[IN] = clk_get_rate(clk) / inrate;
- if (div[IN] == 0) {
+ clk_rate = clk_get_rate(clk);
+ rem[IN] = do_div(clk_rate, inrate);
+ div[IN] = (u32)clk_rate;
+ if (div[IN] == 0 || (!ideal && (div[IN] > 1024 || rem[IN] != 0))) {
pair_err("failed to support input sample rate %dHz by
asrck_%x\n",
inrate, clk_index[ideal ? OUT : IN]);
return -EINVAL;
@@ -360,18 +366,29 @@ static int fsl_asrc_config_pair(struct fsl_asrc_pair
*pair)
clk = asrc_priv->asrck_clk[clk_index[OUT]];
- /* Use fixed output rate for Ideal Ratio mode (INCLK_NONE) */
- if (ideal)
- div[OUT] = clk_get_rate(clk) / IDEAL_RATIO_RATE;
+ /*
+* Output rate should be align with the out samplerate. If set too
+* high output rate, there will be lots of Overload.
+* But some case need higher performance, then we can use
+* IDEAL_RATIO_RATE specifically for such case.
+*/
+ clk_rate = clk_get_rate(clk);
+ if (ideal && use_ideal_rate)
+ rem[OUT] = do_div(clk_rate, IDEAL_RATIO_RATE);
else
- div[OUT] = clk_get_rate(clk) / outrate;
+ rem[OUT] = do_div(clk_rate, outrate);
+ div[OUT] = clk_rate;
- if (div[OUT] == 0) {
+ if (div[OUT] == 0 || (!ideal && (div[OUT] > 1024 || rem[OUT] != 0))) {
pair_err("failed to support output sample rate %dHz by
asrck_%x\n",
outrate, clk_index[OUT]);
return -EINVAL;
}
+ /* Divider range is [1, 1024] */
+ div[IN] = min_t(u32, 1024, div[IN]);
+ div[OUT] = min_t(u32, 1024, div[OUT]);
+
/* Set the channel number */
channels = config->channel_num;
@@ -560,7 +577,7 @@ static int fsl_asrc_dai_hw_params(struct snd_pcm_substream
*substream,
config.output_sample_rate = rate;
}
- ret = fsl_asrc_config_pair(pair);
+ ret = fsl_asrc_config_pair(pair, false);
if (ret) {
dev_err(dai->dev, "fail to config asrc pair\n");
return ret;
--
2.21.0
Re: [PATCH V7] mm/debug: Add tests validating architecture page table helpers
Le 25/10/2019 à 07:52, Qian Cai a écrit :
On Oct 24, 2019, at 11:45 PM, Anshuman Khandual
wrote:
Nothing specific. But just tested this with x86 defconfig with relevant configs
which are required for this test. Not sure if it involved W=1.
No, it will not. It needs to run like,
make W=1 -j 64 2>/tmp/warns
Are we talking about this peace of code ?
+static unsigned long __init get_random_vaddr(void)
+{
+ unsigned long random_vaddr, random_pages, total_user_pages;
+
+ total_user_pages = (TASK_SIZE - FIRST_USER_ADDRESS) / PAGE_SIZE;
+
+ random_pages = get_random_long() % total_user_pages;
+ random_vaddr = FIRST_USER_ADDRESS + random_pages * PAGE_SIZE;
+
+ WARN_ON((random_vaddr > TASK_SIZE) ||
+ (random_vaddr < FIRST_USER_ADDRESS));
+ return random_vaddr;
+}
+
ramdom_vaddr is unsigned,
random_pages is unsigned and lower than total_user_pages
So the max value random_vaddr can get is FIRST_USER_ADDRESS +
((TASK_SIZE - FIRST_USER_ADDRESS - 1) / PAGE_SIZE) * PAGE_SIZE =
TASK_SIZE - 1
And the min value random_vaddr can get is FIRST_USER_ADDRESS (that's
when random_pages = 0)
So the WARN_ON() is just unneeded, isn't it ?
Christophe
