On Thu, Mar 30, 2023 at 4:30 PM Emil Abildgaard Svendsen <
e...@bang-olufsen.dk> wrote:
> Slot width should follow the physical width of the format instead of the
> data width.
>
> This is needed for formats like SNDRV_PCM_FMTBIT_S24_LE where physical
> width is 32 and data width is 24. By using
orion5x_defconfig clang
arm randconfig-c002-20230330 gcc
arm randconfig-r021-20230329 gcc
arm randconfig-r025-20230329 gcc
arm randconfig-r026-20230329 gcc
arm64allyesconfig
gcc
arm orion5x_defconfig clang
arm randconfig-c002-20230330 gcc
arm randconfig-r021-20230329 gcc
arm randconfig-r025-20230329 gcc
arm randconfig-r026-20230329 gcc
arm64
Hi Bjorn,
> But lpfc_aer_cleanup_state() is visible in the
> "lpfc_aer_state_cleanup" sysfs file, so removing it would break any
> userspace that uses it.
>
> If we can rely on the PCI core to clean up AER errors itself
> (admittedly, that might be a big "if"), maybe lpfc_aer_cleanup_state()
>
Rohan McLure writes:
> Anyone got time to review this one?
I was planning to pick it up, but it's going to conflict badly with the
set_ptes() series:
https://lore.kernel.org/all/20230315051444.3229621-1-wi...@infradead.org/
I thought that series was likely to go in soon, but I see it's still
Le 30/03/2023 à 12:03, Arnd Bergmann a écrit :
On Thu, Mar 30, 2023, at 09:48, Neil Armstrong wrote:
On 27/03/2023 14:13, Arnd Bergmann wrote:
From: Arnd Bergmann
The cache management operations for noncoherent DMA on ARMv6 work
in two different ways:
* When CONFIG_DMA_CACHE_RWFO is set,
Slot width should follow the physical width of the format instead of the
data width.
This is needed for formats like SNDRV_PCM_FMTBIT_S24_LE where physical
width is 32 and data width is 24. By using the physical width, data
won't get misaligned.
Signed-off-by: Emil Svendsen
---
On 27/03/2023 14:13, Arnd Bergmann wrote:
From: Arnd Bergmann
The cache management operations for noncoherent DMA on ARMv6 work
in two different ways:
* When CONFIG_DMA_CACHE_RWFO is set, speculative prefetches on in-flight
DMA buffers lead to data corruption when the prefetched data is
The pci_bus_for_each_resource() can hide the iterator loop since
it may be not used otherwise. With this, we may drop that iterator
variable definition.
Signed-off-by: Andy Shevchenko
Reviewed-by: Krzysztof Wilczyński
Acked-by: Dominik Brodowski
---
drivers/pcmcia/rsrc_nonstatic.c | 9
Refactor pci_bus_for_each_resource() in the same way as it's done in
pci_dev_for_each_resource() case. This will allow to hide iterator
inside the loop, where it's not used otherwise.
No functional changes intended.
Signed-off-by: Andy Shevchenko
Reviewed-by: Krzysztof Wilczyński
Reviewed-by:
The pci_bus_for_each_resource() can hide the iterator loop since
it may be not used otherwise. With this, we may drop that iterator
variable definition.
Signed-off-by: Andy Shevchenko
Reviewed-by: Krzysztof Wilczyński
Reviewed-by: Philippe Mathieu-Daudé
---
drivers/eisa/pci_eisa.c | 4 ++--
1
From: Conor Dooley
There's a bunch of bindings for (mostly l2) cache controllers
scattered to the four winds, move them to a common directory.
I renamed the freescale l2cache.txt file, as while that might make sense
when the parent dir is fsl, it's confusing after the move.
The two Marvell
There might be a confusion with the implementation of the
pci_bus_for_each_resources() due to side effect of Logical
OR. Document entire macro and explain how it works and why
the conditional needs to be like that.
Signed-off-by: Andy Shevchenko
---
include/linux/pci.h | 20
From: Mika Westerberg
Instead of open-coding it everywhere introduce a tiny helper that can be
used to iterate over each resource of a PCI device, and convert the most
obvious users into it.
While at it drop doubled empty line before pdev_sort_resources().
No functional changes intended.
kernel.h is being used as a dump for all kinds of stuff for a long time.
The COUNT_ARGS() and CONCATENATE() macros may be used in some places
without need of the full kernel.h dependency train with it.
Here is the attempt on cleaning it up by splitting out these macros().
Signed-off-by: Andy
Introduce pci_resource_n() and replace open-coded implementations of it
in pci.h.
Signed-off-by: Andy Shevchenko
Reviewed-by: Philippe Mathieu-Daudé
---
include/linux/pci.h | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/include/linux/pci.h
Provide two new helper macros to iterate over PCI device resources and
convert users.
Looking at it, refactor existing pci_bus_for_each_resource() and convert
users accordingly.
Note, the amount of lines grew due to the documentation update.
Changelog v8:
- fixed issue with
"Aneesh Kumar K.V" writes:
> platform device helper routines won't update the NUMA distance table
> while creating a platform device, even if the device is present on
> a NUMA node that doesn't have memory or CPU. This is especially true
> for pmem devices. If the target node of the pmem device
On Thu, Mar 30, 2023 at 05:51:57PM +0200, Laurent Dufour wrote:
> On 13/02/2023 16:40:50, Nathan Lynch wrote:
> > Michal Suchánek writes:
> >> On Mon, Feb 13, 2023 at 08:46:50AM -0600, Nathan Lynch wrote:
> >>> Laurent Dufour writes:
> When a new CPU is added, the kernel is activating all
On 13/02/2023 16:40:50, Nathan Lynch wrote:
> Michal Suchánek writes:
>> On Mon, Feb 13, 2023 at 08:46:50AM -0600, Nathan Lynch wrote:
>>> Laurent Dufour writes:
When a new CPU is added, the kernel is activating all its threads. This
leads to weird, but functional, result when adding
On Thu, Mar 30, 2023 at 09:24:21PM +0800, kernel test robot wrote:
>
> Greeting,
>
> FYI, we noticed various errors such like
> "i40e: probe of :3d:00.0 failed with error -12"
> due to commit (built with gcc-11):
>
> commit: d23d5938fd7ced817d6aa1ff86cd671ebbaebfc2 ("[PATCH v7 3/6] PCI:
On Mon, Mar 27, 2023 at 1:20 PM Arnd Bergmann wrote:
>
> From: Arnd Bergmann
>
> Now that all of these have consistent behavior, replace them with
> a single shared implementation of arch_sync_dma_for_device() and
> arch_sync_dma_for_cpu() and three parameters to pick how they should
> operate:
Hi Punit,
On 2023/3/30 21:15, Punit Agrawal wrote:
> Hi Yicong,
>
> Yicong Yang writes:
>
>> From: Barry Song
>>
>> on x86, batched and deferred tlb shootdown has lead to 90%
>> performance increase on tlb shootdown. on arm64, HW can do
>> tlb shootdown without software IPI. But sync tlbi is
On Mon, Mar 27, 2023 at 1:16 PM Arnd Bergmann wrote:
>
> From: Arnd Bergmann
>
> For a DMA_BIDIRECTIONAL transfer, the caches have to be cleaned
> first to let the device see data written by the CPU, and invalidated
> after the transfer to let the CPU see data written by the device.
>
> riscv
Hi Yicong,
Yicong Yang writes:
> From: Barry Song
>
> on x86, batched and deferred tlb shootdown has lead to 90%
> performance increase on tlb shootdown. on arm64, HW can do
> tlb shootdown without software IPI. But sync tlbi is still
> quite expensive.
>
> Even running a simplest program
On Mon, Mar 27, 2023 at 1:16 PM Arnd Bergmann wrote:
>
> From: Arnd Bergmann
>
> No other architecture intentionally writes back dirty cache lines into
> a buffer that a device has just finished writing into. If the cache is
> clean, this has no effect at all, but if a cacheline in the buffer
platform device helper routines won't update the NUMA distance table
while creating a platform device, even if the device is present on
a NUMA node that doesn't have memory or CPU. This is especially true
for pmem devices. If the target node of the pmem device is not online, we
find the nearest
On Mon, 27 Mar 2023 at 14:18, Arnd Bergmann wrote:
>
> From: Arnd Bergmann
>
> The cache management operations for noncoherent DMA on ARMv6 work
> in two different ways:
>
> * When CONFIG_DMA_CACHE_RWFO is set, speculative prefetches on in-flight
>DMA buffers lead to data corruption when
On 3/29/23 18:54, Arnaldo Carvalho de Melo wrote:
> Em Tue, Mar 28, 2023 at 09:21:49AM -0700, Ian Rogers escreveu:
>> On Tue, Mar 28, 2023 at 4:30 AM Kajol Jain wrote:
>>>
>>> Commit 3c22ba524304 ("perf vendor events powerpc: Update POWER9 events")
>>> added and updated power9 pmu json events.
The prefix architecture in ISA v3.1 introduces a prefixed bit in SRR1
for many types of synchronous interrupts which is set when the interrupt
is caused by a prefixed instruction.
This requires KVM to be able to set this bit when injecting interrupts
into a guest. Plumb through the SRR1 "flags"
Pass the hypervisor (H)SRR1[PREFIX] indication through to synchronous
interrupts injected into the guest.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kvm/book3s_64_mmu_radix.c | 13 +
arch/powerpc/kvm/book3s_hv.c | 27 +-
I missed this in my earlier review and testing, but I think we need
these in the prefix instruction enablement series before the final patch
that enables HFSCR[PREFIX] for guests.
Thanks,
Nick
Nicholas Piggin (2):
KVM: PPC: Permit SRR1 flags in more injected interrupt types
KVM: PPC: Book3S
On Thu, Mar 30, 2023, at 09:48, Neil Armstrong wrote:
> On 27/03/2023 14:13, Arnd Bergmann wrote:
>> From: Arnd Bergmann
>>
>> The cache management operations for noncoherent DMA on ARMv6 work
>> in two different ways:
>>
>> * When CONFIG_DMA_CACHE_RWFO is set, speculative prefetches on
Le 28/03/2023 à 13:47, Michael Ellerman a écrit :
> "Nicholas Piggin" writes:
>> On Mon Mar 27, 2023 at 8:26 PM AEST, Christophe Leroy wrote:
> ...
>>>
>>> Now that thread.regs doesn't change anymore at each interrupt, it would
>>> probably be worth dropping it and falling back to
On Mon, Mar 27, 2023 at 2:16 PM Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> The cache management operations for noncoherent DMA on ARMv6 work
> in two different ways:
>
> * When CONFIG_DMA_CACHE_RWFO is set, speculative prefetches on in-flight
>DMA buffers lead to data corruption when
On Wed, Mar 29, 2023, at 22:48, Conor Dooley wrote:
> On Mon, Mar 27, 2023 at 02:13:04PM +0200, Arnd Bergmann wrote:
>> From: Arnd Bergmann
>>
>> No other architecture intentionally writes back dirty cache lines into
>> a buffer that a device has just finished writing into. If the cache is
>>
The ISA 3.1B hashst and hashchk instructions use a per-cpu SPR HASHKEYR
to hold a key used in the hash calculation. This key should be different
for each process to make it harder for a malicious process to recreate
valid hash values for a victim process.
Add support for storing a per-thread hash
Test the kernel DEXCR[NPHIE] interface and hashchk exception handling.
Introduces with it a DEXCR utils library for common DEXCR operations.
Volatile is used to prevent the compiler optimising away the signal
tests.
Signed-off-by: Benjamin Gray
---
v1: * Clean up dexcr makefile
*
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