From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
We will use that in the later patch to find the kvm ops handler
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/arm/kvm/arm.c | 5 +++--
arch/ia64/kvm/kvm-ia64.c | 5 +++--
arch/mips/kvm
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
This moves the kvmppc_ops callbacks to be a per VM entity. This
enables us to select HV and PR mode when creating a VM. We also
allow both kvm-hv and kvm-pr kernel module to be loaded. To
achieve this we move /dev/kvm ownership to kvm.ko
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
drop is_hv_enabled, because that should not be a callback property
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/kvm_ppc.h | 6 +-
arch/powerpc/kvm/book3s.c | 6 +++---
arch
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
Make required changes to get BOOKE configs to build with
the introduction of kvmppc_ops callback
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/kvm_ppc.h | 4 +--
arch/powerpc/kvm/44x.c
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
This patch moves PR related tracepoints to a separate header. This
enables in converting PR to a kernel module which will be done in
later patches
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/kvm
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
This help us to identify whether we are running with hypervisor mode KVM
enabled. The change is needed so that we can have both HV and PR kvm
enabled in the same kernel.
If both HV and PR KVM are included, interrupts come in to the HV
Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com writes:
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
Even though we have same value for linux PTE bits and hash PTE pits
use the hash pte bits wen updating hash pte
...
diff --git a/arch/powerpc/platforms/pseries/lpar.c
b/arch
Hi Alex,
Any update on this ?
-aneesh
Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com writes:
Hi All,
This patch series support enabling HV and PR KVM together in the same kernel.
We
extend machine property with new property kvm_type. A value of HV will
force HV
KVM and PR PR KVM
The below patch fix a compile issue with KVM_XICS. Please fold
diff --git a/arch/powerpc/kvm/book3s_xics.c b/arch/powerpc/kvm/book3s_xics.c
index cef3de9..c3c832b 100644
--- a/arch/powerpc/kvm/book3s_xics.c
+++ b/arch/powerpc/kvm/book3s_xics.c
@@ -840,6 +840,7 @@ int kvmppc_xics_hcall(struct
: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
powerpc: Reduce PTE table memory wastage
The above patch only implements the new layout for PPC64 so it doesn't
compile for PPC32 with a 64K page size. Ideally we should implement
the same layout for PPC32 however for the meantime this patch
Alexander Graf ag...@suse.de writes:
On 07.10.2013, at 18:47, Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
wrote:
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
Make required changes to get BOOKE configs to build with
the introduction of kvmppc_ops callback
Signed-off
Hi,
This patch series add support for numa faults on ppc64 architecture. We steal
the
_PAGE_COHERENCE bit and use that for indicating _PAGE_NUMA. We clear the
_PAGE_PRESENT bit
and also invalidate the hpte entry on setting _PAGE_NUMA. The next fault on that
page will be considered a numa fault.
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
We want to make sure we don't use these function when updating a pte
or pmd entry that have a valid hpte entry, because these functions
don't invalidate them. So limit the check to _PAGE_PRESENT bit.
Numafault core changes use these functions
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
Even though we have same value for linux PTE bits and hash PTE pits
use the hash pte bits wen updating hash pte
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/platforms/cell/beat_htab.c | 4 ++--
arch
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
change_prot_numa should work even if _PAGE_NUMA != _PAGE_PROTNONE.
On archs like ppc64 that don't use _PAGE_PROTNONE and also have
a separate page table outside linux pagetable, we just need to
make sure that when calling change_prot_numa we
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/pgtable-ppc64.h | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/pgtable-ppc64.h
b
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
Provide numa related functions for updating pmd entries.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/pgtable.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
Archs like ppc64 have different layout for pmd entries pointing to PTE
page. Hence add a separate function for modifying them
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/pgtable.h | 17
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
After commit e2b3d202d1dba8f3546ed28224ce485bc50010be we have the
below possible formats for pmd entry
(1) invalid (all zeroes)
(2) pointer to next table, as normal; bottom 6 bits == 0
(3) leaf pte for huge page, bottom two bits != 00
(4
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
We steal the _PAGE_COHERENCE bit and use that for indicating NUMA ptes.
This patch still disables the numa hinting using pmd entries. That
require further changes to pmd entry format which is done in later
patches.
Signed-off-by: Aneesh
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
Set memory coherence always on hash64 config. If
a platform cannot have memory coherence always set they
can infer that from _PAGE_NO_CACHE and _PAGE_WRITETHRU
like in lpar. So we dont' really need a separate bit
for tracking _PAGE_COHERENCE
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
We don't use PACATOC for PR. Avoid updating HOST_R2 with PR
KVM mode when both HV and PR are enabled in the kernel. Without this we
get the below crash
(qemu)
Unable to handle kernel paging request for data at address 0x8310
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
Don't try to compute these values.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
NOTE: I am not sure why we were originally computing dsisr and dar. So may be
we need a variant of this patch
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
This patch make sure we inherit the LE bit correctly in different case
so that we can run Little Endian distro in PR mode
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
This patch depends on the below two changes
1
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
arch/powerpc/platforms/wsp/wsp.c: In function ‘wsp_probe_devices’:
arch/powerpc/platforms/wsp/wsp.c:76:3: error: implicit declaration of function
‘of_address_to_resource’ [-Werror=implicit-function-declaration]
Signed-off-by: Aneesh Kumar
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
Even though we have same value for linux PTE bits and hash PTE pits
use the hash pte bits wen updating hash pte
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/platforms/cell/beat_htab.c | 4 ++--
arch
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
We want to make sure we don't use these function when updating a pte
or pmd entry that have a valid hpte entry, because these functions
don't invalidate them. So limit the check to _PAGE_PRESENT bit.
Numafault core changes use these functions
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
change_prot_numa should work even if _PAGE_NUMA != _PAGE_PROTNONE.
On archs like ppc64 that don't use _PAGE_PROTNONE and also have
a separate page table outside linux pagetable, we just need to
make sure that when calling change_prot_numa we
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
Set memory coherence always on hash64 config. If
a platform cannot have memory coherence always set they
can infer that from _PAGE_NO_CACHE and _PAGE_WRITETHRU
like in lpar. So we dont' really need a separate bit
for tracking _PAGE_COHERENCE
Hi,
This patch series add support for numa faults on ppc64 architecture. We steal
the
_PAGE_COHERENCE bit and use that for indicating _PAGE_NUMA. We clear the
_PAGE_PRESENT bit
and also invalidate the hpte entry on setting _PAGE_NUMA. The next fault on that
page will be considered a numa fault.
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
We steal the _PAGE_COHERENCE bit and use that for indicating NUMA ptes.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/pgtable.h | 66 +-
arch/powerpc/include
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
This patch make sure we inherit the LE bit correctly in different case
so that we can run Little Endian distro in PR mode
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
Changes from V1:
* Use LPCR bit to find whether
Adding Mel and Rik to cc:
Benjamin Herrenschmidt b...@au1.ibm.com writes:
On Mon, 2013-11-18 at 14:58 +0530, Aneesh Kumar K.V wrote:
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
change_prot_numa should work even if _PAGE_NUMA != _PAGE_PROTNONE.
On archs like ppc64 that don't use
Liu Ping Fan kernelf...@gmail.com writes:
To enable the do_numa_page(), we should not fix _PAGE_NUMA in
hash_page(), so bail out for the case of pte_numa().
Signed-off-by: Liu Ping Fan pingf...@linux.vnet.ibm.com
---
arch/powerpc/mm/hash_utils_64.c | 2 +-
1 file changed, 1 insertion(+),
Liu Ping Fan kernelf...@gmail.com writes:
The period check of _PAGE_NUMA can probably trigger the check on
the correctly placed page. For this case, we can just insert hpte and
do fast exception return.
I still don't understand why we need to handle numa faults in hash
page ? Are you trying
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
change_prot_numa should work even if _PAGE_NUMA != _PAGE_PROTNONE.
On archs like ppc64 that don't use _PAGE_PROTNONE and also have
a separate page table outside linux pagetable, we just need to
make sure that when calling change_prot_numa we
Cc: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: linux-stable sta...@vger.kernel.org # v3.10+
Signed-off-by: Hong H. Pham hong.p...@windriver.com
---
arch/powerpc/include/asm/pgalloc-32.h | 2 +-
arch/powerpc/include/asm/pgalloc-64.h
Benjamin Herrenschmidt b...@kernel.crashing.org writes:
On Sat, 2013-12-07 at 09:06 -0500, Hong H. Pham wrote:
diff --git a/arch/powerpc/include/asm/pgalloc-32.h
b/arch/powerpc/include/asm/pgalloc-32.h
index 27b2386..842846c 100644
--- a/arch/powerpc/include/asm/pgalloc-32.h
+++
from common header
Cc: Paul Mackerras pau...@samba.org
Cc: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: linux-stable sta...@vger.kernel.org # v3.10+
Signed-off-by: Hong H. Pham hong.p...@windriver.com
Reviewed-by: Aneesh Kumar K.V
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
We already checked need_resched. So we can call schedule directly
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
NOTE: This patch also work around a regression upstream w.r.t PR KVM
BUG: soft lockup - CPU#0 stuck
Alexander Graf ag...@suse.de writes:
On 10.12.2013, at 15:21, Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
wrote:
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
We already checked need_resched. So we can call schedule directly
Signed-off-by: Aneesh Kumar K.V aneesh.ku
Hi Alex,
Any update on this ? We need this to got into 3.13.
-aneesh
Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com writes:
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
We don't use PACATOC for PR. Avoid updating HOST_R2 with PR
KVM mode when both HV and PR are enabled
Alexander Graf ag...@suse.de writes:
On 11.11.2013, at 15:02, Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
wrote:
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
Don't try to compute these values.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
NOTE
Alexander Graf ag...@suse.de writes:
Am 19.12.2013 um 08:02 schrieb Aneesh Kumar K.V
aneesh.ku...@linux.vnet.ibm.com:
Alexander Graf ag...@suse.de writes:
On 11.11.2013, at 15:02, Aneesh Kumar K.V
aneesh.ku...@linux.vnet.ibm.com wrote:
From: Aneesh Kumar K.V aneesh.ku
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
Although it's optional IBM POWER cpus always had DAR value set on
alignment interrupt. So don't try to compute these values.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/kvm/book3s_emulate.c | 28
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
This patch fix the below crash
NIP [c004cee4] .__hash_page_thp+0x2a4/0x440
LR [c00439ac] .hash_page+0x18c/0x5e0
...
Call Trace:
[c00736103c40] [1b00] 0x1b00(unreliable)
[437908.479693
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
This patch fix the below crash
NIP [c004cee4] .__hash_page_thp+0x2a4/0x440
LR [c00439ac] .hash_page+0x18c/0x5e0
...
Call Trace:
[c00736103c40] [1b00] 0x1b00(unreliable)
[437908.479693
Kirill A. Shutemov kirill.shute...@linux.intel.com writes:
Aneesh Kumar K.V wrote:
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
This patch fix the below crash
NIP [c004cee4] .__hash_page_thp+0x2a4/0x440
LR [c00439ac] .hash_page+0x18c/0x5e0
...
Call Trace
Benjamin Herrenschmidt b...@kernel.crashing.org writes:
On Thu, 2014-01-02 at 16:22 +0530, Aneesh Kumar K.V wrote:
Just use config option directly:
if (new_ptl != old_ptl ||
IS_ENABLED(CONFIG_ARCH_THP_MOVE_PMD_ALWAYS_WITHDRAW))
I didn't like that. I found
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
This patch fix the below crash
NIP [c004cee4] .__hash_page_thp+0x2a4/0x440
LR [c00439ac] .hash_page+0x18c/0x5e0
...
Call Trace:
[c00736103c40] [1b00] 0x1b00(unreliable)
[437908.479693
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
This avoid mmu-hash64.h including pagetable-ppc64.h. That inclusion
cause issues like
CC arch/powerpc/kernel/asm-offsets.s
In file included from
/home/aneesh/linus/arch/powerpc/include/asm/mmu-hash64.h:23:0,
from
Benjamin Herrenschmidt b...@kernel.crashing.org writes:
On Mon, 2014-01-06 at 14:33 +0530, Aneesh Kumar K.V wrote:
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
This avoid mmu-hash64.h including pagetable-ppc64.h. That inclusion
cause issues like
I don't like this. We have
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
This patch fix the below crash
NIP [c004cee4] .__hash_page_thp+0x2a4/0x440
LR [c00439ac] .hash_page+0x18c/0x5e0
...
Call Trace:
[c00736103c40] [1b00] 0x1b00(unreliable)
[437908.479693
Benjamin Herrenschmidt b...@kernel.crashing.org writes:
On Mon, 2014-01-13 at 11:34 +0530, Aneesh Kumar K.V wrote:
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
This patch fix the below crash
Andrea, can you ack the generic bit please ?
Thanks !
Kirill A. Shutemov did ack
Li Zhong zh...@linux.vnet.ibm.com writes:
It seems that forward declaration couldn't work well with typedef, use
struct spinlock directly to avoiding following build errors:
In file included from include/linux/spinlock.h:81,
from include/linux/seqlock.h:35,
Liu Ping Fan kernelf...@gmail.com writes:
To make _PAGE_NUMA take effect, we should force the checking when
guest uses hypercall to setup hpte.
Signed-off-by: Liu Ping Fan pingf...@linux.vnet.ibm.com
---
arch/powerpc/kvm/book3s_hv_rm_mmu.c | 2 +-
1 file changed, 1 insertion(+), 1
Liu ping fan kernelf...@gmail.com writes:
On Thu, Jan 9, 2014 at 8:08 PM, Alexander Graf ag...@suse.de wrote:
On 11.12.2013, at 09:47, Liu Ping Fan kernelf...@gmail.com wrote:
This series is based on Aneesh's series [PATCH -V2 0/5] powerpc: mm: Numa
faults support for ppc64
For this
Liu ping fan kernelf...@gmail.com writes:
On Mon, Jan 20, 2014 at 11:45 PM, Aneesh Kumar K.V
aneesh.ku...@linux.vnet.ibm.com wrote:
Liu ping fan kernelf...@gmail.com writes:
On Thu, Jan 9, 2014 at 8:08 PM, Alexander Graf ag...@suse.de wrote:
On 11.12.2013, at 09:47, Liu Ping Fan kernelf
Kumar K.V aneesh.ku...@linux.vnet.ibm.com
When we mark pte with _PAGE_NUMA we already call
mmu_notifier_invalidate_range_start and
mmu_notifier_invalidate_range_end, which will mark existing guest hpte
entry as HPTE_V_ABSENT. Now we need to do that when we are inserting new
guest hpte entries
Paul Mackerras pau...@samba.org writes:
On Mon, Jan 20, 2014 at 03:48:36PM +0100, Alexander Graf wrote:
On 15.01.2014, at 07:36, Liu ping fan kernelf...@gmail.com wrote:
On Thu, Jan 9, 2014 at 8:08 PM, Alexander Graf ag...@suse.de wrote:
On 11.12.2013, at 09:47, Liu Ping Fan
Alexander Graf ag...@suse.de writes:
On 21.01.2014, at 10:42, Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
wrote:
Liu Ping Fan kernelf...@gmail.com writes:
To make sure that on host, the pages marked with _PAGE_NUMA result in a
fault
when guest access them, we should force
Alexander Graf ag...@suse.de writes:
On 27.01.2014, at 11:28, Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
wrote:
Alexander Graf ag...@suse.de writes:
On 21.01.2014, at 10:42, Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
wrote:
Liu Ping Fan kernelf...@gmail.com writes
Although it's optional IBM POWER cpus always had DAR value set on
alignment interrupt. So don't try to compute these values.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
Changes from V2:
* Depend on cpu feature flag to decide whether to use fault_dsir or not
arch/powerpc
This patch make sure we inherit the LE bit correctly in different case
so that we can run Little Endian distro in PR mode
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
Changes from V2:
* Move H_SET_MODE to qemu
arch/powerpc/include/asm/kvm_host.h | 1 +
arch/powerpc
: b3084f4db3aeb991c507ca774337c7e7893ed04f
for 3.11 stable series
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/Kconfig | 3 +++
arch/powerpc/platforms/Kconfig.cputype | 1 +
mm/huge_memory.c | 12
3 files changed, 16 insertions(+)
diff --git
: b3084f4db3aeb991c507ca774337c7e7893ed04f
for 3.12 stable series
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/Kconfig | 3 +++
arch/powerpc/platforms/Kconfig.cputype | 1 +
mm/huge_memory.c | 12
3 files changed, 16 insertions(+)
diff --git
'spinlock_t'
/root/linux-next/arch/powerpc/include/asm/pgtable-ppc64.h:563: note: previous
declaration of 'spinlock_t' was here
build fix for upstream SHA1: b3084f4db3aeb991c507ca774337c7e7893ed04f
for 3.13 stable series
Signed-off-by: Li Zhong zh...@linux.vnet.ibm.com
Signed-off-by: Aneesh Kumar
for 3.13 stable series
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
Acked-by: Kirill A. Shutemov kirill.shute...@linux.intel.com
Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org
---
arch/powerpc/include/asm/pgtable-ppc64.h | 14 ++
include/asm-generic
Hello,
This patch series implements PR KVM support for POWER8 platform
-aneesh
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
We definitely don't need to emulate mtspr, because both the registers
are hypervisor resource.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/kvm_book3s.h | 2 --
arch/powerpc/include/asm/kvm_host.h | 4 ++--
arch/powerpc/kvm/book3s_emulate.c
virtual time base register is a per vm register and need to saved
and restored on vm exit and entry. Writing to VTB is not allowed
in the privileged mode.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/kvm_host.h | 1 +
arch/powerpc/include/asm
Since PR KVM doesn't support SMT yet, we always return 0.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/kvm/book3s_emulate.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/powerpc/kvm/book3s_emulate.c
b/arch/powerpc/kvm/book3s_emulate.c
index
We don't have SMT support yet, hence we should not find a doorbell
message generated
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/kvm/book3s_emulate.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/powerpc/kvm/book3s_emulate.c
b
Since we don't support SMT yet, we should always find zero in
Directed privileged doorbell exception state register.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/kvm/book3s_emulate.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/powerpc/kvm
At this point we allow all the supported facilities except EBB. So
forward the interrupt to guest as illegal instruction.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/kvm_asm.h | 4 +++-
arch/powerpc/kvm/book3s.c | 4
arch/powerpc
to emulate the support. Currently
all but EBB is disabled. We still don't support performance monitoring
in PR guest.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/kvm_book3s_asm.h | 1 +
arch/powerpc/include/asm/kvm_host.h | 1 +
arch/powerpc/kernel
Runtime disable transactional memory feature looking at pa-features
device tree entry. We need to do this so that we can run a kernel
built with TM config in PR mode. For PR guest we provide a device
tree entry with TM feature disabled in pa-features
Signed-off-by: Aneesh Kumar K.V aneesh.ku
We ignore write to these registers now
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/kvm/book3s_emulate.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/powerpc/kvm/book3s_emulate.c
b/arch/powerpc/kvm/book3s_emulate.c
index bf6b11021250
Writing to IC is not allowed in the privileged mode.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/kvm_host.h | 1 +
arch/powerpc/kvm/book3s_emulate.c | 3 +++
arch/powerpc/kvm/book3s_pr.c| 2 ++
3 files changed, 6 insertions(+)
diff
header
from within !ASSEMBLY seems to fix it up in an acceptable way.
Cc: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
Cc: Kirill A. Shutemov kirill.shute...@linux.intel.com
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com
Paul Gortmaker paul.gortma...@windriver.com writes:
On 14-01-28 12:28 PM, Aneesh Kumar K.V wrote:
Paul Gortmaker paul.gortma...@windriver.com writes:
Commit b3084f4db3aeb991c507ca774337c7e7893ed04f (powerpc/thp: Fix
crash on mremap) added a typedef struct spinlock spinlock_t;
which on gcc
Greg KH g...@kroah.com writes:
On Thu, Jan 30, 2014 at 09:57:36AM +1100, Benjamin Herrenschmidt wrote:
On Wed, 2014-01-29 at 10:45 -0800, Greg KH wrote:
On Tue, Jan 28, 2014 at 05:52:42PM +0530, Aneesh Kumar K.V wrote:
From: Li Zhong zh...@linux.vnet.ibm.com
It seems that forward
Greg KH g...@kroah.com writes:
On Thu, Jan 30, 2014 at 11:08:52PM +0530, Aneesh Kumar K.V wrote:
Greg KH g...@kroah.com writes:
On Thu, Jan 30, 2014 at 09:57:36AM +1100, Benjamin Herrenschmidt wrote:
On Wed, 2014-01-29 at 10:45 -0800, Greg KH wrote:
On Tue, Jan 28, 2014 at 05:52:42PM
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
This patch fix the below crash
NIP [c004cee4] .__hash_page_thp+0x2a4/0x440
LR [c00439ac] .hash_page+0x18c/0x5e0
...
Call Trace:
[c00736103c40] [1b00] 0x1b00(unreliable)
[437908.479693
'spinlock_t'
/root/linux-next/arch/powerpc/include/asm/pgtable-ppc64.h:563: note: previous
declaration of 'spinlock_t' was here
upstream sha1:fd120dc2e205d2318a8b47d6d8098b789e3af67d
for 3.13 stable series
Signed-off-by: Li Zhong zh...@linux.vnet.ibm.com
Signed-off-by: Aneesh Kumar K.V aneesh.ku
Alexander Graf ag...@suse.de writes:
On 01/28/2014 05:44 PM, Aneesh Kumar K.V wrote:
We definitely don't need to emulate mtspr, because both the registers
are hypervisor resource.
This patch description doesn't cover what the patch actually does. It
changes the implementation from always
Paul Mackerras pau...@samba.org writes:
On Tue, Jan 28, 2014 at 10:14:07PM +0530, Aneesh Kumar K.V wrote:
virtual time base register is a per vm register and need to saved
and restored on vm exit and entry. Writing to VTB is not allowed
in the privileged mode.
...
+#ifdef
Alexander Graf ag...@suse.de writes:
On 01/28/2014 05:44 PM, Aneesh Kumar K.V wrote:
Writing to IC is not allowed in the privileged mode.
This is not a patch description.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/kvm_host.h | 1
Paul Mackerras pau...@samba.org writes:
On Tue, Jan 28, 2014 at 10:14:12PM +0530, Aneesh Kumar K.V wrote:
We allow priv-mode update of this. The guest value is saved in fscr,
and the value actually used is saved in shadow_fscr. shadow_fscr
only contains values that are allowed by the host
Alexander Graf ag...@suse.de writes:
On 01/28/2014 05:44 PM, Aneesh Kumar K.V wrote:
At this point we allow all the supported facilities except EBB. So
forward the interrupt to guest as illegal instruction.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
This patch fix the below crash
NIP [c004cee4] .__hash_page_thp+0x2a4/0x440
LR [c00439ac] .hash_page+0x18c/0x5e0
...
Call Trace:
[c00736103c40] [1b00] 0x1b00(unreliable)
[437908.479693
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
We will use this later to set the _PAGE_NUMA bit.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/hugetlb.h | 2 +-
arch/powerpc/include/asm/pgtable-ppc64.h | 26
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
So move it within the if loop
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
mm/mprotect.c | 21 +++--
1 file changed, 7 insertions(+), 14 deletions(-)
diff --git a/mm/mprotect.c b/mm/mprotect.c
index
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
Archs like ppc64 doesn't do tlb flush in set_pte/pmd functions. ppc64 also
doesn't implement
flush_tlb_range. ppc64 require the tlb flushing to be batched within ptl locks.
The reason
to do that is to ensure that the hash page table
Hello,
This patch series fix random application crashes observed on ppc64 with numa
balancing enabled. Without the patch we see crashes like
anacron[14551]: unhandled signal 11 at 0041 nip 3cfd54b4 lr
3cfd5464 code 30001
anacron[14599]: unhandled signal 11 at
Greg KH gre...@linuxfoundation.org writes:
On Fri, Feb 07, 2014 at 07:21:57PM +0530, Aneesh Kumar K.V wrote:
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
This patch fix the below crash
NIP [c004cee4] .__hash_page_thp+0x2a4/0x440
LR [c00439ac] .hash_page+0x18c
Benjamin Herrenschmidt b...@kernel.crashing.org writes:
On Tue, 2014-02-11 at 09:31 -0800, Greg KH wrote:
On Fri, Feb 07, 2014 at 07:21:57PM +0530, Aneesh Kumar K.V wrote:
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
This patch fix the below crash
NIP [c004cee4
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
We will use this later to set the _PAGE_NUMA bit.
Acked-by: Mel Gorman mgor...@suse.de
Acked-by: Rik van Riel r...@redhat.com
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/hugetlb.h | 2
Hello,
This patch series fix random application crashes observed on ppc64 with numa
balancing enabled. Without the patch we see crashes like
anacron[14551]: unhandled signal 11 at 0041 nip 3cfd54b4 lr
3cfd5464 code 30001
anacron[14599]: unhandled signal 11 at
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
So move it within the if loop
Acked-by: Mel Gorman mgor...@suse.de
Reviewed-by: Rik van Riel r...@redhat.com
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
mm/mprotect.c | 21 +++--
1 file changed, 7
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