On 06/24/2013 04:58 PM, Michael Ellerman wrote:
In power_pmu_enable() we can use the existing out label to reduce the
number of return paths.
Signed-off-by: Michael Ellerman mich...@ellerman.id.au
Reviewed-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/perf/core
On 06/27/2013 05:22 PM, Michael Ellerman wrote:
On Wed, 2013-06-26 at 15:28 +0530, Anshuman Khandual wrote:
@@ -117,6 +117,7 @@
(EVENT_UNIT_MASK EVENT_UNIT_SHIFT) | \
(EVENT_COMBINE_MASKEVENT_COMBINE_SHIFT) | \
(EVENT_MARKED_MASK
mich...@ellerman.id.au
Reviewed-by: Anshuman Khandual khand...@linux.vnet.ibm.com
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powerpc, perf: Add generic cache reference and cache miss events for POWER8 PMU
This enables generic cache reference and cache miss events on POWER8 systems by
utilizing raw PMU event codes for L1 cache reference and L1 cache miss events
respectively.
Signed-off-by: Anshuman Khandual khand
Hi Anshuman,
Which system did you test this on and what results did you see?
Tested this on a power8 system.
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On 07/10/2013 06:32 PM, Mahesh J Salgaonkar wrote:
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
During Machine Check interrupt on pseries platform, R3 generally points to
memory region inside RTAS (FWNMI) area. We see r3 corruption because when RTAS
delivers the machine check exception
On 07/15/2013 11:36 AM, Aneesh Kumar K.V wrote:
Anshuman Khandual khand...@linux.vnet.ibm.com writes:
On 07/10/2013 06:32 PM, Mahesh J Salgaonkar wrote:
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
During Machine Check interrupt on pseries platform, R3 generally points to
memory
On 07/18/2013 07:01 AM, Michael Neuling wrote:
POWER8 comes with two different PVRs. This patch enables the additional
PVR in the cputable.
The existing entry (PVR=0x4b) is renamed to POWER8E and the new entry
(PVR=0x4d) is given POWER8.
Hey Mikey,
Is there any feature or architectural
On 06/24/2013 12:50 PM, Michael Neuling wrote:
Anshuman Khandual khand...@linux.vnet.ibm.com wrote:
When the task moves around the system, the corresponding cpuhw
per cpu strcuture should be popullated with the BHRB filter
request value so that PMU could be configured appropriately
obj-$(CONFIG_PPC64) += copypage_64.o copyuser_64.o \
memcpy_64.o usercopy_64.o mem_64.o string.o \
-checksum_wrappers_64.o hweight_64.o \
+checksum_wrappers_64.o \
copyuser_power7.o
On 08/07/2013 03:08 PM, Mahesh J Salgaonkar wrote:
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
This patch splits the common exception prolog logic into two parts to
facilitate reuse of existing code in the next patch. The second part will
be reused in the machine check exception
On 08/07/2013 03:08 PM, Mahesh J Salgaonkar wrote:
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
Move machine check entry point into Linux. So far we were dependent on
firmware to decode MCE error details and handover the high level info to OS.
This patch introduces early machine check
of instructions.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
Reviewed-by: Stephane Eranian eran...@google.com
---
include/uapi/linux/perf_event.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
index
Enables conditional branch filter support for POWER8
utilizing MMCRA register based filter and also invalidates
a BHRB branch filter combination involving conditional
branches.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/perf/power8-pmu.c | 10 ++
1 file
This patch adds conditional branch filtering support,
enabling it for PERF_SAMPLE_BRANCH_COND in perf branch
stack sampling framework by utilizing an available
software filter X86_BR_JCC.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
Reviewed-by: Stephane Eranian eran...@google.com
Adding documentation support for conditional branch filter.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
Reviewed-by: Stephane Eranian eran...@google.com
---
tools/perf/Documentation/perf-record.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tools/perf
Adding perf record support for new branch stack filter criteria
PERF_SAMPLE_BRANCH_COND.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
tools/perf/builtin-record.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/perf/builtin-record.c b/tools/perf/builtin-record.c
) bctarl
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/perf_event_server.h | 2 +-
arch/powerpc/perf/core-book3s.c | 200 +--
arch/powerpc/perf/power8-pmu.c | 19 ++-
3 files changed, 198 insertions
# PERF_SAMPLE_BRANCH_ANY_RET
Changes in V2
--
(1) Enabled PPC64 SW branch filtering support
(2) Incorporated changes required for all previous comments
Anshuman Khandual (6
On 08/30/2013 05:18 PM, Stephane Eranian wrote:
2013/8/30 Anshuman Khandual khand...@linux.vnet.ibm.com
This patchset is the re-spin of the original branch stack sampling
patchset which introduced new PERF_SAMPLE_BRANCH_COND filter. This patchset
also enables SW based branch
On 09/10/2013 07:36 AM, Michael Ellerman wrote:
On Fri, 2013-08-30 at 09:54 +0530, Anshuman Khandual wrote:
This patchset is the re-spin of the original branch stack sampling
patchset which introduced new PERF_SAMPLE_BRANCH_COND filter. This patchset
also enables SW based branch filtering
On 09/14/2013 06:19 AM, Sukadev Bhattiprolu wrote:
We use helpers like GENERIC_EVENT_ATTR() to list the generic events in
sysfs. To avoid name collisions, GENERIC_EVENT_ATTR() requires the perf
event macros to start with PME.
We got all the raw event codes covered for P7 with the help of
On 09/14/2013 06:19 AM, Sukadev Bhattiprolu wrote:
On Power7, the DCACHE_SRC field in MMCRA register identifies the memory
hierarchy level (eg: L2, L3 etc) from which a data-cache miss for a
marked instruction was satisfied.
Use the 'perf_mem_data_src' object to export this hierarchy level
On 09/14/2013 06:19 AM, Sukadev Bhattiprolu wrote:
+static void power7_get_mem_data_src(union perf_mem_data_src *dsrc,
+ struct pt_regs *regs)
+{
+ u64 idx;
+ u64 mmcra = regs-dsisr;
+ u64 addr;
+ int ret;
+ unsigned int instr;
+
+ if (mmcra
On 08/30/2013 05:18 PM, Stephane Eranian wrote:
2013/8/30 Anshuman Khandual khand...@linux.vnet.ibm.com
This patchset is the re-spin of the original branch stack sampling
patchset which introduced new PERF_SAMPLE_BRANCH_COND filter. This patchset
also enables SW based branch
On 09/21/2013 12:11 PM, Anshuman Khandual wrote:
On 08/30/2013 05:18 PM, Stephane Eranian wrote:
2013/8/30 Anshuman Khandual khand...@linux.vnet.ibm.com
This patchset is the re-spin of the original branch stack sampling
patchset which introduced new PERF_SAMPLE_BRANCH_COND filter
On 09/21/2013 12:25 PM, Stephane Eranian wrote:
On Tue, Sep 10, 2013 at 4:06 AM, Michael Ellerman
mich...@ellerman.id.au wrote:
On Fri, 2013-08-30 at 09:54 +0530, Anshuman Khandual wrote:
This patchset is the re-spin of the original branch stack sampling
patchset which introduced
On 09/25/2013 07:49 AM, Michael Ellerman wrote:
On Mon, 2013-09-23 at 14:45 +0530, Anshuman Khandual wrote:
On 09/21/2013 12:25 PM, Stephane Eranian wrote:
On Tue, Sep 10, 2013 at 4:06 AM, Michael Ellerman
mich...@ellerman.id.au wrote:
On Fri, 2013-08-30 at 09:54 +0530, Anshuman Khandual
allows for a different implementation in the future
* if needed, as long as you only use the functions and not the variables
--
Anshuman Khandual
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Hey Ben,
Because its too minor a documentation fix, did not write any description.
Not sure how it works, I thought this would be clubbed with other incoming
documentation fix in the same area.
On Monday 14 May 2012 09:02 PM, Anshuman Khandual wrote:
diff --git a/arch/powerpc/include/asm
On Tuesday 26 June 2012 04:30 PM, Anton Blanchard wrote:
We want to access the MMCRA_SIHV and MMCRA_SIPR bits elsewhere so
create mmcra_sihv and mmcra_sipr which hide the differences between
the old and new layout of the bits.
Hey Anton,
Going further in this direction, we can actually
There are 4 options:
1. [not a kernel interface] use ptrace to execute the register changing
command inside the specified pid. The next context switch saves the new
value in the thread_struct. Dirty hack.
2. Add a new syscall which would receive pid + register value and do the
job. A bit
-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
Changes in V2:
- Fixed the compilation problem in 32 bit archs
- Selective inclusion of plapr_set_ciabr for required platforms
- Cleaned up the white space issues
v1: https://patchwork.ozlabs.org/patch/354108/
arch/powerpc/include/asm/xmon.h
On 05/23/2014 08:45 PM, Anshuman Khandual wrote:
This patch series adds five new ELF core note sections which can be
used with existing ptrace request PTRACE_GETREGSET/SETREGSET for accessing
various transactional memory and miscellaneous register sets on PowerPC
platform. Please find
the
system explicitly.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/opal.h| 45 +-
.../include/uapi/asm/opal_platform_events.h| 90 +++
arch/powerpc/platforms/powernv/Makefile| 2 +-
.../platforms/powernv/opal
the
system explicitly.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/opal.h| 45 +-
.../include/uapi/asm/opal_platform_events.h| 90 +++
arch/powerpc/platforms/powernv/Makefile| 2 +-
.../platforms/powernv/opal
the
system explicitly.
Reviewed-by: Neelesh Gupta neele...@linux.vnet.ibm.com
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
Changes in V2:
- Changed the function fetch_dpo_timeout
- Export opal_platform_events.h for user space consumption
arch/powerpc/include/asm/opal.h
On 07/24/2014 12:22 PM, Sam Bobroff wrote:
Outstanding Issues
==
(1) Running DSCR register value inside a transaction does not seem to be
saved
at thread.dscr when the process stops for ptrace examination.
Since this is fixed by
On 08/28/2014 03:05 AM, Sukadev Bhattiprolu wrote:
Anshuman Khandual [khand...@linux.vnet.ibm.com] wrote:
| This patch enables get and set of miscellaneous registers through ptrace
| PTRACE_GETREGSET/PTRACE_SETREGSET interface by implementing new powerpc
| specific register set REGSET_MISC
On 08/28/2014 03:05 AM, Sukadev Bhattiprolu wrote:
Anshuman Khandual [khand...@linux.vnet.ibm.com] wrote:
| This patch enables get and set of transactional memory related register
| sets through PTRACE_GETREGSET/PTRACE_SETREGSET interface by implementing
| four new powerpc specific register
documentation
- Changed the commit message
Changes in V2: (http://patchwork.ozlabs.org/patch/373114/)
- Fixed the compilation problem in 32 bit archs
- Selective inclusion of plapr_set_ciabr for required platforms
- Cleaned up the white space issues
Signed-off-by: Anshuman Khandual khand
this rtas based event, it will expose itself to a forced abrupt
shutdown initiated by the platform firmware. This patch fixes the situation.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/platforms/pseries/ras.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
On 10/09/2014 05:18 PM, Anshuman Khandual wrote:
This patch enables support for hardware instruction breakpoints
on POWER8 with the help of a new register CIABR (Completed
Instruction Address Breakpoint Register). With this patch, single
hardware instruction breakpoint can be added and cleared
PPR: 4 (PASSED)
success: tm_ptrace
Anshuman Khandual (8):
elf: Add new PowerPC specifc core note sections
powerpc, process: Add functions flush_tm_state, flush_tmregs_to_thread
powerpc, process: Merge functions __switch_to_tm and tm_reclaim_task
powerpc, ptrace: Enable fpr_(get
This patch creates a new function called flush_tm_state to flush
the existing transactional memory state from the thread. It also
creates a function called flush_tmregs_to_thread which will then
be used on subsequent patches in this series.
Signed-off-by: Anshuman Khandual khand
This patch adds four new core note sections for PowerPC transactional
memory and one core note section for general miscellaneous debug registers.
These addition of new elf core note sections extends the existing elf ABI
without affecting it in any manner.
Signed-off-by: Anshuman Khandual khand
This patch enables the fpr_get which gets the running value of all
the FPR registers and the fpr_set which sets the running value of
of all the FPR registers to accommodate in transaction ptrace
interface based requests.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch
This patch enables the vr_get which gets the running value of all
the VMX registers and the vr_set which sets the running value of
of all the VMX registers to accommodate in transaction ptrace
interface based requests.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc
core note types added previously in this regard.
(1) NT_PPC_TM_SPR
(2) NT_PPC_TM_CGPR
(3) NT_PPC_TM_CFPR
(4) NT_PPC_TM_CVMX
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/include/uapi/asm/elf.h | 2 +
arch/powerpc/kernel/ptrace.c
-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/include/uapi/asm/elf.h | 1 +
arch/powerpc/kernel/ptrace.c| 102
2 files changed, 103 insertions(+)
diff --git a/arch/powerpc/include/uapi/asm/elf.h
b/arch/powerpc/include/uapi/asm/elf.h
index
then compares the received values
against the expected values to verify whether it passed the test
or not.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
tools/testing/selftests/powerpc/tm/Makefile| 2 +-
tools/testing/selftests/powerpc/tm/tm-ptrace.c | 529
The function tm_reclaim_task is only called from the function
__switch_to_tm. This patch merges these two functions to make
it more readable without changing the functionality in any way.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/kernel/process.c | 20
On 11/11/2014 10:56 AM, Anshuman Khandual wrote:
This patch enables get and set of miscellaneous debug registers through
ptrace PTRACE_GETREGSET-PTRACE_SETREGSET interface by implementing new
powerpc specific register set REGSET_MISC support corresponding to the
new ELF core note NT_PPC_MISC
On 11/14/2014 03:30 PM, Denis Kirjanov wrote:
On 11/13/14, Anshuman Khandual khand...@linux.vnet.ibm.com wrote:
On 11/11/2014 10:56 AM, Anshuman Khandual wrote:
This patch enables get and set of miscellaneous debug registers through
ptrace PTRACE_GETREGSET-PTRACE_SETREGSET interface
On 11/19/2014 02:48 AM, Sukadev Bhattiprolu wrote:
Anshuman Khandual [khand...@linux.vnet.ibm.com] wrote:
| This patch enables get and set of transactional memory related register
| sets through PTRACE_GETREGSET-PTRACE_SETREGSET interface by implementing
| four new powerpc specific register
On 11/11/2014 10:56 AM, Anshuman Khandual wrote:
This patch creates a new function called flush_tm_state to flush
the existing transactional memory state from the thread. It also
creates a function called flush_tmregs_to_thread which will then
be used on subsequent patches in this series
On 11/22/2014 05:13 AM, Andrew Morton wrote:
On Tue, 11 Nov 2014 10:56:30 +0530 Anshuman Khandual
khand...@linux.vnet.ibm.com wrote:
This patch adds four new core note sections for PowerPC transactional
memory and one core note section for general miscellaneous debug registers
RN FPR[31]: 0 (PASSED)
Testing TM running MISC debug registers:
TM RN DSCR: 32 (PASSED)
TM RN TAR: 3c (PASSED)
TM RN PPR: 4 (PASSED)
success: tm_ptrace
Anshuman Khandual (7):
elf: Add new powerpc specifc core note sections
powerpc, process: Add the function flush_tmregs_to_thread
Morton a...@linux-foundation.org
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
include/uapi/linux/elf.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h
index ea9bf25..2260fc0 100644
--- a/include/uapi/linux/elf.h
+++ b
This patch creates a function flush_tmregs_to_thread which
will then be used by subsequent patches in this series. The
function checks for self tracing ptrace interface attempts
while in the TM context and logs appropriate warning message.
Signed-off-by: Anshuman Khandual khand
This patch enables the vr_get which gets the running value of all
the VMX registers and the vr_set which sets the running value of
of all the VMX registers to accommodate in transaction ptrace
interface based requests.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc
core note types added previously in this regard.
(1) NT_PPC_TM_SPR
(2) NT_PPC_TM_CGPR
(3) NT_PPC_TM_CFPR
(4) NT_PPC_TM_CVMX
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/include/uapi/asm/elf.h | 2 +
arch/powerpc/kernel/ptrace.c
-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/include/uapi/asm/elf.h | 1 +
arch/powerpc/kernel/ptrace.c| 123
2 files changed, 124 insertions(+)
diff --git a/arch/powerpc/include/uapi/asm/elf.h
b/arch/powerpc/include/uapi/asm/elf.h
index
then compares the received values
against the expected values to verify whether it has passed the
given test or not.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
tools/testing/selftests/powerpc/tm/Makefile| 2 +-
tools/testing/selftests/powerpc/tm/tm-ptrace.c | 542
This patch enables the fpr_get which gets the running value of all
the FPR registers and the fpr_set which sets the running value of
of all the FPR registers to accommodate in transaction ptrace
interface based requests.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch
breakpoints]:
$./perf record ls
[ perf record: Woken up 1 times to write data ]
[ perf record: Captured and wrote 0.001 MB perf.data (~61 samples) ]
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
Changes in V3:
- Moved the 'ciabr_used' early init inside 'cmds' function
- Some minor code
the
system explicitly.
Reviewed-by: Neelesh Gupta neele...@linux.vnet.ibm.com
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
Changes in V3:
- Rebased the patch against the mainline
Changes in V2:
- Changed the function fetch_dpo_timeout
- Export opal_platform_events.h for user space
On 11/25/2014 10:36 PM, Shuah Khan wrote:
On 11/25/2014 01:05 AM, Anshuman Khandual wrote:
This patch adds one more test case called 'tm-ptrace' targeting TM
related ptrace interface. This test creates one child process to
run some basic TM transactions and the parent process attaches
On 11/26/2014 01:55 PM, Michael Ellerman wrote:
On Tue, 2014-25-11 at 10:08:48 UTC, Anshuman Khandual wrote:
This patch enables support for hardware instruction breakpoints
on POWER8 with the help of a new register CIABR (Completed
Instruction Address Breakpoint Register). With this patch
register based HW instruction breakpoint.
Signed-off-by: Michael Ellerman m...@ellerman.id.au
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
Changes in V4:
- Moved the external function code block from xmon.h to xmon.c
- Reformatted the in-code documentation as kernel-doc format
- Re
On 12/01/2014 11:10 AM, Michael Ellerman wrote:
On Fri, 2014-28-11 at 04:36:42 UTC, Anshuman Khandual wrote:
This patch enables support for hardware instruction breakpoint in
xmon on POWER8 platform with the help of a new register called the
CIABR (Completed Instruction Address Breakpoint
On 12/01/2014 11:25 AM, Michael Ellerman wrote:
Drop BP_IABR_TE, which though used, does not do anything useful. Rename
BP_IABR to BP_CIABR. Renumber the flags.
Signed-off-by: Michael Ellerman m...@ellerman.id.au
---
arch/powerpc/xmon/xmon.c | 19 +--
1 file changed, 9
(PASSED)
TM RN PPR: 4 (PASSED)
success: tm_ptrace
Anshuman Khandual (9):
elf: Add new powerpc specifc core note sections
powerpc, process: Add the function flush_tmregs_to_thread
powerpc, ptrace: Enable fpr_(get/set) for transactional memory
powerpc, ptrace: Enable vr_(get/set
This patch creates a function flush_tmregs_to_thread which
will then be used by subsequent patches in this series. The
function checks for self tracing ptrace interface attempts
while in the TM context and logs appropriate warning message.
Signed-off-by: Anshuman Khandual khand
This patch enables the fpr_get which gets the running value of all
the FPR registers and the fpr_set which sets the running value of
of all the FPR registers to accommodate in transaction ptrace
interface based requests.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch
This patch enables the vr_get which gets the running value of all
the VMX registers and the vr_set which sets the running value of
of all the VMX registers to accommodate in transaction ptrace
interface based requests.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc
core note types added previously in this regard.
(1) NT_PPC_TM_SPR
(2) NT_PPC_TM_CGPR
(3) NT_PPC_TM_CFPR
(4) NT_PPC_TM_CVMX
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/include/uapi/asm/elf.h | 2 +
arch/powerpc/kernel/ptrace.c
-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/include/uapi/asm/elf.h | 1 +
arch/powerpc/kernel/ptrace.c| 131
2 files changed, 132 insertions(+)
diff --git a/arch/powerpc/include/uapi/asm/elf.h
b/arch/powerpc/include/uapi/asm/elf.h
index
then compares the received values
against the expected values to verify whether it has passed the
given test or not.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
tools/testing/selftests/powerpc/tm/Makefile| 2 +-
tools/testing/selftests/powerpc/tm/tm-ptrace.c | 542
This patch includes all the TM test binaries into the .gitignore
file listing in the same directory. This will make sure that GIT
ignores all of them while displaying status.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
tools/testing/selftests/powerpc/tm/.gitignore | 2 ++
1
This patch includes all of the powerpc test binaries into the
.gitignore file listing in their respective directories. This
will make sure that GIT ignores all of these test binaries while
displaying status.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
.../testing/selftests
On 11/25/2014 06:51 PM, Anshuman Khandual wrote:
This patch creates a new OPAL platform event character driver
which will give userspace clients the access to these events
and process them effectively. Following platforms events are
currently supported with this platform driver.
(1
Morton a...@linux-foundation.org
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
include/uapi/linux/elf.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h
index ea9bf25..2260fc0 100644
--- a/include/uapi/linux/elf.h
+++ b
% top libc-2.11.2.so[k] vfprintf
libc-2.11.2.so[k] vfprintf
0.92% top top [k] _init
[unknown] [k] 0x0fe037f4
Anshuman Khandual (5
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/perf/power8-pmu.c | 57 +-
1 file changed, 56 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/perf/power8-pmu.c b/arch/powerpc/perf/power8-pmu.c
index 106ae0b..153408c
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/perf_event_server.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/powerpc/include/asm/perf_event_server.h
b/arch/powerpc/include/asm/perf_event_server.h
index 57b42da..3f0c15c 100644
This patch adds new instructions support for reading various
BHRB entries and also clearing the BHRB buffer.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/ppc-opcode.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/powerpc/include/asm
This patch provides basic enablement for perf branch stack sampling framework
on POWER8 processor with a new PMU feature called BHRB (Branch History Rolling
Buffer).
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/perf/core-book3s.c | 96
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/perf/Makefile | 2 +-
arch/powerpc/perf/bhrb.S | 34 ++
2 files changed, 35 insertions(+), 1 deletion(-)
create mode 100644 arch/powerpc/perf/bhrb.S
diff --git a/arch/powerpc/perf
This patch adds new instructions support for reading various
BHRB entries and also clearing the BHRB buffer.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/ppc-opcode.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/powerpc/include/asm
This patch adds some new BHRB related generic functions, data and flags
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/perf_event_server.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/powerpc/include/asm/perf_event_server.h
b/arch
% top top [k] _init
[unknown] [k] 0x0fe037f4
Changes in V2
--
- Added copyright messages to the newly created files
- Modified couple of commit messages
Anshuman Khandual (5):
powerpc, perf: Add new BHRB related
Defines BHRB functions, data and flags for POWER8
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/perf/power8-pmu.c | 57 +-
1 file changed, 56 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/perf/power8-pmu.c b/arch
This patch adds the basic assembly code to read BHRB entries
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/perf/Makefile | 2 +-
arch/powerpc/perf/bhrb.S | 44
2 files changed, 45 insertions(+), 1 deletion(-)
create
This patch provides basic enablement for perf branch stack sampling framework
on POWER8 processor with a new PMU feature called BHRB (Branch History Rolling
Buffer).
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/perf/core-book3s.c | 96
On 04/16/2013 10:53 PM, Segher Boessenkool wrote:
+/* r3 = n (where n = [0-1023])
+ * The maximum number of BHRB entries supported with PPC_MFBHRBE
instruction
+ * is 1024. We have limited number of table entries here as POWER8
implements
+ * 32 BHRB entries.
+ */
+
+/* .global read_bhrb
On 04/17/2013 12:38 PM, Michael Ellerman wrote:
On Tue, Apr 16, 2013 at 09:24:10PM +0530, Anshuman Khandual wrote:
This patch provides basic enablement for perf branch stack sampling framework
on POWER8 processor with a new PMU feature called BHRB (Branch History
Rolling
Buffer).
Signed
On 04/17/2013 05:37 PM, Anshuman Khandual wrote:
On 04/17/2013 12:38 PM, Michael Ellerman wrote:
On Tue, Apr 16, 2013 at 09:24:10PM +0530, Anshuman Khandual wrote:
This patch provides basic enablement for perf branch stack sampling
framework
on POWER8 processor with a new PMU feature called
This patch populates BHRB specific data for power_pmu structure. It
also implements POWER8 specific BHRB filter and configuration functions.
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/perf/power8-pmu.c | 57 +-
1 file
This patch adds couple of generic functions to power_pmu structure
which would configure the BHRB and it's filters. It also adds
representation of the number of BHRB entries present on the PMU.
A new PMU flag PPMU_BHRB would indicate presence of BHRB feature.
Signed-off-by: Anshuman Khandual
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