[RFC 6/8] powerpc/prom: Simplify the logic while fetching SLB size

From: khand...@linux.vnet.ibm.com khand...@linux.vnet.ibm.com This patch just simplifies the existing code logic while fetching the SLB size property from the device tree. Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com --- arch/powerpc/kernel/prom.c | 12 +--- 1 file

[RFC 5/8] powerpc/slb: Add documentation to runtime patching of SLB encoding

From: khand...@linux.vnet.ibm.com khand...@linux.vnet.ibm.com This patch adds some documentation to 'patch_slb_encoding' function explaining about how it clears the existing immediate value in the given instruction and inserts a new one there. Signed-off-by: Anshuman Khandual khand

[RFC 4/8] powerpc/slb: Add some helper functions to improve modularization

) kernel_linear_vsid_flags: VSID flags for kernel linear mapping (4) kernel_virtual_vsid_flags: VSID flags for kernel virtual mapping Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com --- arch/powerpc/mm/slb.c | 87 ++- 1 file changed, 59

Re: [PATCH V3] powerpc/irq: Enable some more exceptions in /proc/interrupts interface

On 07/13/2015 01:46 PM, Anshuman Khandual wrote: This patch enables facility unavailable exceptions for generic facility, FPU, ALTIVEC and VSX in /proc/interrupts listing by incrementing their newly added IRQ statistical counters as and when these exceptions happen. This also adds couple

[PATCH V3] powerpc/irq: Enable some more exceptions in /proc/interrupts interface

-- Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com --- Changes in V3: - Changed the display string from ALTIVEC to AltiVec - Now captured Facility unavailable exceptions in the example Changes in V2: - Fixed some typos in the final

Re: [PATCH 4/5] powerpc/tm: Check for already reclaimed tasks

On 11/13/2015 10:27 AM, Michael Neuling wrote: > Currently we can hit a scenario where we'll tm_reclaim() twice. This > results in a TM bad thing exception because the second reclaim occurs > when not in suspend mode. > > The scenario in which this can happen is the following. We attempt to >

Re: [PATCH 1/5] powerpc: Print MSR TM bits in oops message

On 11/13/2015 10:27 AM, Michael Neuling wrote: > Print the MSR TM bits in oops messages. This appends them to the end > like this: > MSR: 800502823031 > > You get the TM[] only if at least one TM MSR bit is set. Inside the > TM[], E means Enabled (bit

[RFC] powerpc/numa: Use VPHN based node ID information on shared processor LPARs

ppc_md. setup_arch inside setup_arch during boot. Signed-off-by: Anshuman Khandual <khand...@linux.vnet.ibm.com> --- Before the change: # numactl -H available: 2 nodes (0,3) node 0 cpus: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 node 0 size: 0 MB

[PATCH] selfttest/powerpc: Add memory page migration tests

-by: Anshuman Khandual <khand...@linux.vnet.ibm.com> --- - Works for normal page migration on both 64K and 4K base pages - Works for 16MB huge page migration (64K) on Aneesh's V2 PTE changes tools/testing/selftests/powerpc/mm/Makefile| 14 +- .../selftests/powerpc/mm/hugepage-migra

Re: [RFC] powerpc/numa: Use VPHN based node ID information on shared processor LPARs

On 10/14/2015 02:49 PM, Michael Ellerman wrote: > On Wed, 2015-10-14 at 14:32 +0530, Anshuman Khandual wrote: >> On shared processor LPARs, H_HOME_NODE_ASSOCIATIVITY hcall provides the >> dynamic virtual-physical mapping for any given processor. Currently we >> use VPHN nod

Re: [PATCH V8 00/28] Add new powerpc specific ELF core notes

On 05/19/2015 08:37 PM, Anshuman Khandual wrote: > Test Result > --- > ptrace-ebbPASS > ptrace-gprPASS > ptrace-tm-gpr PASS > ptrace-tm-spd-gpr PASS > ptrace-tarFAIL > ptrace-tm-tar FAIL > ptrace-tm-sp

[PATCH V9 01/28] elf: Add powerpc specific core note sections

sets, EBB related register set etc. Addition of these new ELF core note sections extends the existing ELF ABI on powerpc arch without affecting it in any manner. Signed-off-by: Anshuman Khandual <khand...@linux.vnet.ibm.com> --- include/uapi/linux/elf.h | 12 1 file chang

[PATCH V9 08/28] powerpc, ptrace: Enable support for NT_PPC_CFPR

the get, set and active functions for this new register set added. Signed-off-by: Anshuman Khandual <khand...@linux.vnet.ibm.com> --- arch/powerpc/kernel/ptrace.c | 126 +++ 1 file changed, 126 insertions(+) diff --git a/arch/powerpc/kernel/ptrace.c

[PATCH V9 17/28] selftests, powerpc: Add ptrace tests for EBB

This patch adds ptrace interface test for EBB specific registers. This also adds some generic ptrace interface based helper functions to be used by other patches later on in the series. Signed-off-by: Anshuman Khandual <khand...@linux.vnet.ibm.com> --- tools/testing/selftests/powerpc/Ma

[PATCH V9 21/28] selftests, powerpc: Add ptrace tests for TAR, PPR, DSCR registers

This patch adds ptrace interface test for TAR, PPR, DSCR registers. This also adds ptrace interface based helper functions related to TAR, PPR, DSCR register access. Signed-off-by: Anshuman Khandual <khand...@linux.vnet.ibm.com> --- tools/testing/selftests/powerpc/ptrace/Makefile

[PATCH V9 24/28] selftests, powerpc: Add ptrace tests for VSX, VMX registers

This patch adds ptrace interface test for VSX, VMX registers. This also adds ptrace interface based helper functions related to VSX, VMX registers access. This also adds some assembly helper functions related to VSX and VMX registers. Signed-off-by: Anshuman Khandual <khand...@linux.vnet.ibm.

[PATCH V9 28/28] selftests, powerpc: Add .gitignore file for ptrace executables

This patch adds a .gitignore file for all the executables in the ptrace test directory thus making invisible with git status query. Signed-off-by: Anshuman Khandual <khand...@linux.vnet.ibm.com> --- tools/testing/selftests/powerpc/ptrace/.gitignore | 11 +++ 1 file changed, 11 inse

[PATCH V9 03/28] powerpc, ptrace: Enable in transaction NT_PRFPREG ptrace requests

if transaction is active. This patch makes these functions adapt to situations when the transaction is active. Signed-off-by: Anshuman Khandual <khand...@linux.vnet.ibm.com> --- arch/powerpc/kernel/ptrace.c | 93 ++-- 1 file changed, 89 insertions(+), 4 del

[PATCH V9 07/28] powerpc, ptrace: Enable support for NT_PPC_CGPR

the get, set and active functions for this new register set added. Signed-off-by: Anshuman Khandual <khand...@linux.vnet.ibm.com> --- arch/powerpc/kernel/ptrace.c | 222 +++ 1 file changed, 222 insertions(+) diff --git a/arch/powerpc/kernel/ptrace.c

[PATCH V9 10/28] powerpc, ptrace: Enable support for NT_PPC_CVSX

the get, set and active functions for this new register set added. Signed-off-by: Anshuman Khandual <khand...@linux.vnet.ibm.com> --- arch/powerpc/include/uapi/asm/elf.h | 1 + arch/powerpc/kernel/ptrace.c| 129 2 files changed, 130 insertions(+)

[PATCH V9 13/28] powerpc, ptrace: Enable support for NT_PPPC_TAR, NT_PPC_PPR, NT_PPC_DSCR

corresponding to the ELF core note sections added in this regad. It implements the get, set and active functions for all these new register sets added. Signed-off-by: Anshuman Khandual <khand...@linux.vnet.ibm.com> --- arch/powerpc/kernel/ptrace.c

[PATCH V9 19/28] selftests, powerpc: Add ptrace tests for GPR/FPR registers in TM

This patch adds ptrace interface test for GPR/FPR registers inside TM context. This adds ptrace interface based helper functions related to checkpointed GPR/FPR access. Signed-off-by: Anshuman Khandual <khand...@linux.vnet.ibm.com> --- tools/testing/selftests/powerpc/ptrace/Makefile

[PATCH V9 23/28] selftests, powerpc: Add ptrace tests for TAR, PPR, DSCR in suspended TM

This patch adds ptrace interface test for TAR, PPR, DSCR registers inside suspended TM context. Signed-off-by: Anshuman Khandual <khand...@linux.vnet.ibm.com> --- tools/testing/selftests/powerpc/ptrace/Makefile| 2 +- .../selftests/powerpc/ptrace/ptrace-tm-spd-tar.c

[PATCH V9 25/28] selftests, powerpc: Add ptrace tests for VSX, VMX registers in TM

This patch adds ptrace interface test for VSX, VMX registers inside TM context. This also adds ptrace interface based helper functions related to chckpointed VSX, VMX registers access. Signed-off-by: Anshuman Khandual <khand...@linux.vnet.ibm.com> --- tools/testing/selftests/powerpc/

[PATCH V9 27/28] selftests, powerpc: Add ptrace tests for TM SPR registers

This patch adds ptrace interface test for TM SPR registers. This also adds ptrace interface based helper functions related to TM SPR registers access. Signed-off-by: Anshuman Khandual <khand...@linux.vnet.ibm.com> --- tools/testing/selftests/powerpc/ptrace/Makefile| 2 +- .../sel

[PATCH V9 02/28] powerpc, process: Add the function flush_tmregs_to_thread

This patch creates a function flush_tmregs_to_thread which will then be used by subsequent patches in this series. The function checks for self tracing ptrace interface attempts while in the TM context and logs appropriate warning message. Signed-off-by: Anshuman Khandual <kh

[PATCH V9 05/28] powerpc, ptrace: Enable in transaction NT_PPC_VSX ptrace requests

if transaction is active. This patch makes these functions adapt to situations when the transaction is active. Signed-off-by: Anshuman Khandual <khand...@linux.vnet.ibm.com> --- arch/powerpc/kernel/ptrace.c | 64 1 file changed, 64 insertions(+) diff --git

[PATCH V9 12/28] powerpc, ptrace: Enable NT_PPC_TM_CTAR, NT_PPC_TM_CPPR, NT_PPC_TM_CDSCR

and REGSET_TM_CDSCR in powerpc corresponding to the ELF core note sections added. It implements the get, set and active functions for all these new register sets added. Signed-off-by: Anshuman Khandual <khand...@linux.vnet.ibm.com> --- arch/powerpc/kernel/ptrace.c

[PATCH V9 14/28] powerpc, ptrace: Enable support for EBB registers

. It also implements the get, set and active functions for this new register sets added. Signed-off-by: Anshuman Khandual <khand...@linux.vnet.ibm.com> --- arch/powerpc/include/uapi/asm/elf.h | 3 + arch/powerpc/kernel/ptrace.c| 147 2 files c

[PATCH V9 18/28] selftests, powerpc: Add ptrace tests for GPR/FPR registers

This patch adds ptrace interface test for GPR/FPR registers. This adds ptrace interface based helper functions related to GPR/FPR access and some assembly helper functions related to GPR/FPR registers. Signed-off-by: Anshuman Khandual <khand...@linux.vnet.ibm.com> --- tools/testing/sel

[PATCH V9 04/28] powerpc, ptrace: Enable in transaction NT_PPC_VMX ptrace requests

is active. This patch makes these functions adapt to situations when the transaction is active. Signed-off-by: Anshuman Khandual <khand...@linux.vnet.ibm.com> --- arch/powerpc/kernel/ptrace.c | 90 ++-- 1 file changed, 87 insertions(+), 3 deletions(-)

[PATCH V9 06/28] powerpc, ptrace: Adapt gpr32_get, gpr32_set functions for transaction

This patch splits gpr32_get, gpr32_set functions to accommodate in transaction ptrace requests implemented in patches later in the series. Signed-off-by: Anshuman Khandual <khand...@linux.vnet.ibm.com> --- arch/powerpc/kernel/ptrace.c | 64 +++-

[PATCH V9 09/28] powerpc, ptrace: Enable support for NT_PPC_CVMX

the get, set and active functions for this new register set added. Signed-off-by: Anshuman Khandual <khand...@linux.vnet.ibm.com> --- arch/powerpc/include/uapi/asm/elf.h | 1 + arch/powerpc/kernel/ptrace.c| 158 2 files changed, 159 insertions(+)

[PATCH V9 15/28] selftests, powerpc: Move 'reg.h' file outside of 'ebb' sub directory

This patch moves 'reg.h' file from pmu 'ebb' sub directory to the powerpc root directory to make all the register definitions and instructions available for tests present in other subsystems. Signed-off-by: Anshuman Khandual <khand...@linux.vnet.ibm.com> --- tools/testing/selftests/power

[PATCH V9 22/28] selftests, powerpc: Add ptrace tests for TAR, PPR, DSCR in TM

This patch adds ptrace interface test for TAR, PPR, DSCR registers inside TM context. This also adds ptrace interface based helper functions related to checkpointed TAR, PPR, DSCR register access. Signed-off-by: Anshuman Khandual <khand...@linux.vnet.ibm.com> --- tools/testing/selftests/p

[PATCH V9 00/28] Add new powerpc specific ELF core notes

/PTRACE_SETREGSET using the individual NT_PPC* core note type instead - Fixed couple of attribute values for REGSET_TM_CGPR register set - Renamed flush_tmreg_to_thread as flush_tmregs_to_thread - Fixed 32 bit checkpointed GPR support - Changed commit messages accordingly Anshuman Khandual (28): elf: Add

[PATCH V9 11/28] powerpc, ptrace: Enable support for TM SPR state

, set and active functions for this new register set added. Signed-off-by: Anshuman Khandual <khand...@linux.vnet.ibm.com> --- arch/powerpc/include/uapi/asm/elf.h | 1 + arch/powerpc/kernel/ptrace.c| 143 +++- 2 files changed, 143 insertions(+), 1 de

[PATCH V9 16/28] selftests, powerpc: Add more SPR numbers, TM & VMX instructions to 'reg.h'

This patch adds SPR number for TAR, PPR, DSCR special purpose registers. It also adds TM, VSX, VMX related instructions which will then be used by patches later in the series. Signed-off-by: Anshuman Khandual <khand...@linux.vnet.ibm.com> --- tools/testing/selftests/powerpc/reg.

[PATCH V9 20/28] selftests, powerpc: Add ptrace tests for GPR/FPR registers in suspended TM

This patch adds ptrace interface test for GPR/FPR registers inside suspended TM context. Signed-off-by: Anshuman Khandual <khand...@linux.vnet.ibm.com> --- tools/testing/selftests/powerpc/ptrace/Makefile| 2 +- .../selftests/powerpc/ptrace/ptrace-tm-spd-gpr.c

[PATCH V9 26/28] selftests, powerpc: Add ptrace tests for VSX, VMX registers in suspended TM

This patch adds ptrace interface test for VSX, VMX registers inside suspended TM context. Signed-off-by: Anshuman Khandual <khand...@linux.vnet.ibm.com> --- tools/testing/selftests/powerpc/ptrace/Makefile| 3 +- .../selftests/powerpc/ptrace/ptrace-tm-spd-vsx.c

Re: [RFC] powerpc/numa: Use VPHN based node ID information on shared processor LPARs

On 10/16/2015 07:54 AM, Michael Ellerman wrote: > On Wed, 2015-10-14 at 15:43 +0530, Anshuman Khandual wrote: >> On 10/14/2015 02:49 PM, Michael Ellerman wrote: >>> On Wed, 2015-10-14 at 14:32 +0530, Anshuman Khandual wrote: >>>> On shared processor LPARs, H_HOME_NOD

Re: [RFC] powerpc/numa: Use VPHN based node ID information on shared processor LPARs

On 10/16/2015 07:57 AM, Michael Ellerman wrote: > On Wed, 2015-10-14 at 14:32 +0530, Anshuman Khandual wrote: >> On shared processor LPARs, H_HOME_NODE_ASSOCIATIVITY hcall provides the >> dynamic virtual-physical mapping for any given processor. Currently we >> use VPHN nod

Re: [PATCH] selfttest/powerpc: Add memory page migration tests

On 10/15/2015 09:16 PM, Anshuman Khandual wrote: > This adds two tests for memory page migration. One for normal page > migration which works for both 4K or 64K base page size kernel and > the other one is for 16MB huge page migration which will work both > 4K or 64K base page siz

Re: [PATCH] selfttest/powerpc: Add memory page migration tests

On 10/16/2015 05:09 PM, Aneesh Kumar K.V wrote: > Anshuman Khandual <khand...@linux.vnet.ibm.com> writes: > >> On 10/15/2015 09:16 PM, Anshuman Khandual wrote: >>> This adds two tests for memory page migration. One for normal page >>> migration which works for

[PATCH] powerpc/irq: Enable facility unavailable exceptions in /proc/interrupts

--- Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com --- arch/powerpc/include/asm/hardirq.h | 4 arch/powerpc/kernel/exceptions-64s.S | 2 ++ arch/powerpc/kernel/irq.c| 23 +++ arch/powerpc/kernel/traps.c

[PATCH V2] powerpc/irq: Enable some more exceptions in /proc/interrupts interface

-- Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com --- Changes in V2: - Fixed some typos in the final /proc/interrupts output - Added support for alignment and program check exceptions arch/powerpc/include/asm/hardirq.h | 6

Re: [PATCH V2] powerpc/irq: Enable some more exceptions in /proc/interrupts interface

On 07/10/2015 12:40 PM, Michael Neuling wrote: What's the performance impact of this? If you run this test with --fp, --altivec or --vector what is the impact of adding this patch? http://ozlabs.org/~anton/junkcode/context_switch2.c eg ./context_switch2 --fp 0 0 Please find the

Re: [RESEND] Soft lockup after huge page offline attempt

On 09/02/2015 03:50 PM, Michael Neuling wrote: > On Wed, 2015-09-02 at 15:37 +0530, Anshuman Khandual wrote: >> Hello, >> >> Worked on a modified version of the following selftest >> test case in the kernel source. >> >> tools/testing/selftests/vm/hugepag

[RESEND] Soft lockup after huge page offline attempt

Hello, Worked on a modified version of the following selftest test case in the kernel source. tools/testing/selftests/vm/hugepage-mmap.c This modified test will try to do the following sequence of events in the same order. (1) Allocate 16 Huge TLB pages (16MB each) through mmap (2) mlock()

Re: [RFC] powerpc/hugetlb: Add warning message when gpage allocation request fails

On 09/14/2015 09:54 PM, Nishanth Aravamudan wrote: > On 14.09.2015 [18:59:25 +0530], Aneesh Kumar K.V wrote: >> > Anshuman Khandual <khand...@linux.vnet.ibm.com> writes: >> > >>> > > When a 16GB huge page is requested on POWER platform through kern

[RFC] powerpc/hugetlb: Add warning message when gpage allocation request fails

page not available [0.473417] HugeTLB registered 16 GB page size, pre-allocated 0 pages [0.473423] HugeTLB registered 16 MB page size, pre-allocated 16 pages Signed-off-by: Anshuman Khandual <khand...@linux.vnet.ibm.com> --- arch/powerpc/mm/hugetlbpage.c | 8 ++-- 1 file chan

Re: [1/5] powerpc/perf: Drop the branch sample when 'from' cannot be fetched

On 07/28/2015 08:38 AM, Anshuman Khandual wrote: > On 07/27/2015 09:49 AM, Michael Ellerman wrote: >> > On Tue, 2015-30-06 at 08:20:27 UTC, Anshuman Khandual wrote: >>> >> BHRB (Branch History Rolling Buffer) is a rolling buffer. Hence we >>> >> might en

Regarding DSISR value of 0xa410

Hey Ben/Michael, Why does 0xa410 value of DSISR called weird here ? What does this signify ? Just wondering if we can replace it with a meaningful macro instead. arch/powerpc/kernel/exceptions-64s.S /* * Hash table stuff */ .align 7 do_hash_page: std r3,_DAR(r1)

Re: [PATCH V2 19/31] powerpc/mm: Convert 4k hash insert to C

On 09/30/2015 07:57 AM, Aneesh Kumar K.V wrote: > Signed-off-by: Aneesh Kumar K.V > --- > arch/powerpc/mm/Makefile| 3 + > arch/powerpc/mm/hash64_64k.c| 202 + > arch/powerpc/mm/hash_low_64.S | 380 >

Re: [PATCH V2 19/31] powerpc/mm: Convert 4k hash insert to C

On 10/01/2015 01:48 AM, Benjamin Herrenschmidt wrote: > On Wed, 2015-09-30 at 17:37 +0530, Anshuman Khandual wrote: >>> + if (unlikely(old_pte & _PAGE_BUSY)) >>> + return 0; >>> + /* If PTE permissions don't match, take

Re: [PATCH V2 26/31] powerpc/mm: Remove the dependency on pte bit position in asm code

On 09/30/2015 07:57 AM, Aneesh Kumar K.V wrote: > We should not expect pte bit position in asm code. Simply > by moving part of that to C I guess this does not depend on the new code changes and can simply be part of the preparatory patches at the beginning.

Re: [PATCH 24/31] powerpc/mm: Convert __hash_page_64K to C

On 09/21/2015 12:10 PM, Aneesh Kumar K.V wrote: > Convert from asm to C > > Signed-off-by: Aneesh Kumar K.V > --- > arch/powerpc/include/asm/book3s/64/hash-64k.h | 3 +- > arch/powerpc/include/asm/book3s/64/hash.h | 1 + > arch/powerpc/mm/hash64_64k.c

[PATCH V11 05/10] powerpc/perf: Change the name of HW PMU branch filter tracking variable

-by: Anshuman Khandual <khand...@linux.vnet.ibm.com> --- arch/powerpc/perf/core-book3s.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c index 5a6fd9c..463ddd3 100644 --- a/arch/powerpc/perf/core-bo

[PATCH V11 02/10] powerpc/perf: Re organize PMU branch filter processing on POWER8

This patch does some code re-arrangements to make it clear that kernel ignores any separate privilege level branch filter request and does not support any combinations of HW PMU branch filters. Signed-off-by: Anshuman Khandual <khand...@linux.vnet.ibm.com> --- arch/powerpc/perf/power8-pmu.

[PATCH V11 00/10] powerpc/perf: Enable SW branch filters

ouple of spelling mistakes (6) Changed code documentation in multiple places Changes in V2 (https://lkml.org/lkml/2013/8/30/10) = (1) Enabled PPC64 SW branch filtering support (2) Incorporated changes required for all previous comments Anshuman Khandual (10): powerpc/perf: Change nam

[PATCH V11 08/10] powerpc/perf: Change POWER8 PMU configuration to work with SW filters

to meet those protocols. POWER8 PMU can only handle one HW based branch filter request at any point of time. For all other combinations PMU will pass it on to the SW. Signed-off-by: Anshuman Khandual <khand...@linux.vnet.ibm.com> --- arch/powerpc/perf/power8-pmu.

[PATCH V11 07/10] powerpc/perf: Enable SW filtering in branch stack sampling framework

all. Its the PMU code's responsibility to uphold this protocol to be able to conform to the overall OR semantic of perf branch stack sampling framework. Signed-off-by: Anshuman Khandual <khand...@linux.vnet.ibm.com> --- arch/powerpc/include/asm/perf_event_server.h | 7 +- arch/powerpc/per

[PATCH V11 10/10] selftests/powerpc: Add test for BHRB branch filters (HW & SW)

This patch adds a test for verifying that all the branch stack sampling filters supported on powerpc work correctly. It also adds some assembly helper functions in this regard. This patch extends the generic event description to handle kernel mapped ring buffers. Signed-off-by: Anshuman Khandual

[PATCH V11 09/10] powerpc/perf: Enable privilege mode SW branch filters

the privilege mode branch filters itself. Signed-off-by: Anshuman Khandual <khand...@linux.vnet.ibm.com> --- arch/powerpc/include/asm/perf_event_server.h | 3 +++ arch/powerpc/perf/core-book3s.c | 37 ++-- arch/powerpc/perf/power8-pmu.c | 13 +++

[PATCH V11 03/10] powerpc/perf: Restore privilege level filter support for BHRB

patch also changes 'check_excludes' for the same reason. Signed-off-by: Anshuman Khandual <khand...@linux.vnet.ibm.com> --- arch/powerpc/perf/core-book3s.c | 20 +++- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/arch/powerpc/perf/core-book3s.c b/arch/p

[PATCH V11 01/10] powerpc/perf: Change name & type of 'pred' in power_pmu_bhrb_read

the logical inversion process more meaningful and readable. Reported-by: Daniel Axtens <d...@axtens.net> Signed-off-by: Anshuman Khandual <khand...@linux.vnet.ibm.com> --- arch/powerpc/perf/core-book3s.c | 15 +-- 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/arch/

[PATCH V11 06/10] powerpc/lib: Add new branch analysis support functions

Generic powerpc branch analysis support added in the code patching library which will help the subsequent patch on SW based filtering of branch records in perf. Signed-off-by: Anshuman Khandual <khand...@linux.vnet.ibm.com> --- arch/powerpc/include/asm/code-patching.h | 15 arch/p

[PATCH V11 04/10] powerpc/perf: Re organize BHRB processing

This patch cleans up some existing indentation problem in code and re organizes the BHRB processing code with an helper function named 'update_branch_entry' making it more readable. This patch does not change any functionality. Signed-off-by: Anshuman Khandual <khand...@linux.vnet.ibm.

Re: [PATCH 00/19] Context switch improvements

On 10/29/2015 06:13 AM, Anton Blanchard wrote: > Here are various improvements to our context switch path. Some of the > highlights: > > - Group all mfsprs and mtsprs in __switch_to(), which gives us a > 10% improvement on POWER8. > > - Create giveup_all() and flush_all_to_thread() so we only

Re: [PATCH V6 20/35] powerpc/mm: Don't track subpage valid bit in pte_t

On 12/01/2015 09:06 AM, Aneesh Kumar K.V wrote: > This free up 11 bits in pte_t. In the later patch we also change > the pte_t format so that we can start supporting migration pte > at pmd level. We now track 4k subpage valid bit as below > > If we have _PAGE_COMBO set, we override the

Re: [PATCH 1/3] selftests/powerpc: Standardise TM calls

On 12/02/2015 09:10 AM, Michael Ellerman wrote: > On Tue, 2015-12-01 at 13:38 +0530, Anshuman Khandual wrote: >> > On 12/01/2015 10:38 AM, Rashmica Gupta wrote: >>> > > Currently tbegin, tend etc are written as opcodes or asm instructions. >>> > > So >

Re: [PATCH] selftests/powerpc: Add test to check if TAR is corrupted

On 12/02/2015 08:52 AM, Rashmica Gupta wrote: > If the transaction is aborted, the TAR should be rolled back to the > checkpointed value before the transaction began. And if it does not abort, it should continue to hold the changed (inside the transaction) TAR value after the transaction

Re: [RFC 0/3] Prototype PAPR hash page table resizing (guest side)

On 12/22/2015 10:44 AM, David Gibson wrote: > I've discussed with Paul and Ben previously the possibility of > extending PAPR to allow changing the size of a running guest's hash > page table (HPT). This would allow for much more flexible memory > hotplug, since the HPT wouldn't have to be sized

Re: [PATCH V5 21/31] powerpc/mm: make pte page hash index slot 8 bits

On 11/23/2015 03:52 PM, Aneesh Kumar K.V wrote: > Currently we use 4 bits for each slot and pack all the 16 slot > information related to a 64K linux page in a 64bit value. To do this > we use 16 bits of pte_t. Move the hash slot valid bit out of pte_t Looking into the existing function

Re: [PATCH V5 17/31] powerpc/booke: Move nohash headers (part 5)

On 11/23/2015 03:52 PM, Aneesh Kumar K.V wrote: > Acked-by: Scott Wood > Signed-off-by: Aneesh Kumar K.V This and some previous patches can use some amount of description in the commit message to make them clear. Now these first 17

Re: [PATCH V5 08/31] powerpc/mm: Drop pte-common.h from BOOK3S 64

On 11/23/2015 03:52 PM, Aneesh Kumar K.V wrote: > We copy only needed PTE bits define from pte-common.h to respective > hash related header. This should greatly simply later patches in which Will it be simplify > we are going to change the pte

Re: [PATCH V5 11/31] powerpc/mm: Move hash64 PTE bits from book3s/64/pgtable.h to hash.h

On 11/23/2015 03:52 PM, Aneesh Kumar K.V wrote: > +extern struct page *pmd_page(pmd_t pmd); > static inline pte_t pud_pte(pud_t pud) > { > return __pte(pud_val(pud)); > @@ -294,15 +115,14 @@ static inline void pgd_set(pgd_t *pgdp, unsigned long > val) > * Find an entry in a

Re: [PATCH V5 14/31] powerpc/booke: Move nohash headers (part 2)

Some sort of commit message enlisting what we copied from where and which all header file references have changed will be helpful here. On 11/23/2015 03:52 PM, Aneesh Kumar K.V wrote: > Acked-by: Scott Wood > Signed-off-by: Aneesh Kumar K.V

Re: [PATCH] powerpc/mm: Fix infinite loop in hash fault with 4K page size

re > happening on a 4K page at an address previously mapped by hugetlb. > > Signed-off-by: Aneesh Kumar K.V <aneesh.ku...@linux.vnet.ibm.com> Reviewed-by: Anshuman Khandual <khand...@linux.vnet.ibm.com> ___ Linuxppc-dev maili

Re: [PATCH 2/3] selftests/powerpc: Add test for forking inside transaction

On 12/01/2015 10:38 AM, Rashmica Gupta wrote: > +int test_fork(void) > +{ > + SKIP_IF(!have_htm()); > + > + asm __volatile__( > + "tbegin.;" > + "blt1f; " > + "li 0, 2;" /* fork syscall */ > + "sc ;" > + "tend.;" > +

Re: [PATCH 1/3] selftests/powerpc: Standardise TM calls

On 12/01/2015 10:38 AM, Rashmica Gupta wrote: > Currently tbegin, tend etc are written as opcodes or asm instructions. So > standardise these to asm instructions. I think the asm instructions can be used with only newer versions of GCC. But not sure, does it work with the older gcc as well ?

Re: [PATCH V5 26/31] powerpc/mm: Remove the dependency on pte bit position in asm code

On 11/23/2015 03:52 PM, Aneesh Kumar K.V wrote: > We should not expect pte bit position in asm code. Simply > by moving part of that to C There is a full stop missing in the second sentence. The commit message here does not tell about why we would want to process the page access flags or other

Re: [PATCH V5 28/31] powerpc/mm: Move WIMG update to helper.

On 11/23/2015 03:52 PM, Aneesh Kumar K.V wrote: > Only difference here is, we apply the WIMG mapping early, so rflags > passed to updatepp will also be changed. This patch can be folded back with the previous patch. ___ Linuxppc-dev mailing list

Re: [PATCH V5 23/31] powerpc/mm: Increase the width of #define

On 11/23/2015 03:52 PM, Aneesh Kumar K.V wrote: > No real change, only style changes If there are no real changes and it does not help upcoming patches in the series, should not it just follow patch 17 after all the header movement has been completed before we get down to real changes. IMHO the

Re: [PATCH] powerpc: Standardise on NR_syscalls rather than __NR_syscalls.

On 11/19/2015 02:45 PM, Denis Kirjanov wrote: > On 11/19/15, Rashmica Gupta wrote: >> > Most architectures use NR_syscalls as the #define for the number of >> > syscalls. >> > >> > We use __NR_syscalls, and then define NR_syscalls as __NR_syscalls. >> > >> > __NR_syscalls is

Re: [PATCH] powerpc: Remove unused function trace_syscall()

-off-by: Rashmica Gupta <rashm...@gmail.com> > > Reviewed-by: Andrew Donnellan <andrew.donnel...@au1.ibm.com> Reviewed-by: Anshuman Khandual <khand...@linux.vnet.ibm.com> ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev

Re: [PATCH] powerpc: Standardise on NR_syscalls rather than __NR_syscalls.

On 11/19/2015 11:34 AM, Rashmica Gupta wrote: > Most architectures use NR_syscalls as the #define for the number of syscalls. > > We use __NR_syscalls, and then define NR_syscalls as __NR_syscalls. > > __NR_syscalls is not used outside arch code, whereas NR_syscalls is. So as > NR_syscalls must

Re: [PATCH v2 2/3] selftests/powerpc: Add TM signal return test

On 11/20/2015 09:45 AM, Michael Neuling wrote: > Test the kernel's signal return code to ensure that it doesn't crash > when both the transactional and suspend MSR bits are set in the signal > context. > > Signed-off-by: Michael Neuling <mi...@neuling.org> Tested-by: Ans

Re: [PATCH v2 3/3] selftests/powerpc: Add TM signal with invalid stack test

On 11/20/2015 09:45 AM, Michael Neuling wrote: > Test the kernels signal generation code to ensure it can handle an > invalid stack pointer when transactional. > > Signed-off-by: Michael Neuling <mi...@neuling.org> Tested-by: Anshuman Khandual <khand.

Re: [PATCH] powerpc: Add rN aliases to the pt_regs_offset table.

On 11/21/2015 11:38 AM, Rashmica Gupta wrote: > It is common practice with powerpc to use 'rN' to refer to register 'N'. > However > when using the pt_regs_offset table we have to use 'gprN'. > > So add aliases such that both 'rN' and 'gprN' can be used. > > For example, we can currently do: >

[PATCH V2] selfttest/powerpc: Add memory page migration tests

-by: Anshuman Khandual <khand...@linux.vnet.ibm.com> --- Changes in V2: - Changed the script to accommodate review comments from Michael - Disabled huge page migration test till it is supported on POWER tools/testing/selftests/powerpc/mm/Makefile| 14 +- .../selftests/powerpc/mm/hu

Re: [PATCH V5 00/31] powerpc/mm: Update page table format for book3s 64

On 11/23/2015 03:52 PM, Aneesh Kumar K.V wrote: > Hi All, > > This patch series attempt to update book3s 64 linux page table format to > make it more flexible. Our current pte format is very restrictive and we > overload multiple pte bits. This is due to the non-availability of free bits > in

Re: [PATCH V5 02/31] powerpc/mm: move pte headers to book3s directory (part 2)

On 11/23/2015 03:52 PM, Aneesh Kumar K.V wrote: > diff --git a/arch/powerpc/include/asm/pte-hash64-4k.h > b/arch/powerpc/include/asm/book3s/64/hash-4k.h > similarity index 99% > rename from arch/powerpc/include/asm/pte-hash64-4k.h > rename to arch/powerpc/include/asm/book3s/64/hash-4k.h > index

Re: [PATCH V5 03/31] powerpc/mm: make a separate copy for book3s

On 11/23/2015 03:52 PM, Aneesh Kumar K.V wrote: > +++ b/arch/powerpc/include/asm/book3s/pgtable.h > @@ -0,0 +1,10 @@ > +#ifndef _ASM_POWERPC_BOOK3S_PGTABLE_H > +#define _ASM_POWERPC_BOOK3S_PGTABLE_H > + > +#ifdef CONFIG_PPC64 > +#include > +#else > +#include > +#endif > + > +#endif Just as

Re: [PATCH V5 05/31] powerpc/mm: Move hash specific pte width and other defines to book3s

On 11/23/2015 03:52 PM, Aneesh Kumar K.V wrote: > This further make a copy of pte defines to book3s/64/hash*.h. This > remove the dependency on ppc64-4k.h and ppc64-64k.h > These files are pgtable-ppc64-4k.h and pgtable-ppc64-64k.h instead. > Acked-by: Scott Wood >

Re: [PATCH V5 04/31] powerpc/mm: make a separate copy for book3s (part 2)

On 11/23/2015 03:52 PM, Aneesh Kumar K.V wrote: > Keep it seperate to make rebasing easier This is confusing considering the fact that we are in between some renaming/moving of header files, changing the references they had before and so on. Could you please elaborate a bit about what kind of

Re: [PATCH V10 00/28] Add new powerpc specific ELF core notes

On 06/03/2016 03:56 AM, Cyril Bur wrote: > On 1 June 2016 at 18:26, Anshuman Khandual <khand...@linux.vnet.ibm.com> > wrote: > >> On 05/31/2016 04:42 AM, Michael Ellerman wrote: >>> Hi Laurent, >>> >>> Sorry no. My next branch closed for 4.7 about 3

Re: [PATCH V10 00/28] Add new powerpc specific ELF core notes

On 05/31/2016 04:42 AM, Michael Ellerman wrote: > Hi Laurent, > > Sorry no. My next branch closed for 4.7 about 3 weeks ago. > > This series has been blocked for a long time on the gdb support, but that is > now working. However it still doesn't pass its own selftests, and I had some This

Re: [RFCv2 5/9] arch/powerpc: Split hash page table sizing heuristic into a helper

On 02/02/2016 06:34 AM, David Gibson wrote: > On Mon, Feb 01, 2016 at 12:34:32PM +0530, Anshuman Khandual wrote: >> On 01/29/2016 10:53 AM, David Gibson wrote: >>> htab_get_table_size() either retrieve the size of the hash page table (HPT) >>> from the device tree - if

Re: [RFCv2 6/9] pseries: Add hypercall wrappers for hash page table resizing

On 02/02/2016 06:28 AM, David Gibson wrote: > On Mon, Feb 01, 2016 at 12:41:31PM +0530, Anshuman Khandual wrote: >> On 01/29/2016 10:54 AM, David Gibson wrote: >>> This adds the hypercall numbers and wrapper functions for the hash page >>> table resizing hypercalls. >

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