to use 0x0001e in the group. Testcase uses such
combination all events in power10 which has alternative event.
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/event_code_tests/Makefile | 2 +-
.../event_alternatives_tests_p10.c| 109 ++
2 files changed, 110
and 0x200fa as group. Testcase uses such
combination for all events in power9 which has an
alternative event.
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/event_code_tests/Makefile | 2 +-
.../event_alternatives_tests_p9.c | 116 ++
2 files changed, 117
is only applicable on power9 DD2.1 and DD2.2 and
hence test adds checks to skip on other platforms.
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/event_code_tests/Makefile | 3 +-
.../blacklisted_events_test.c | 132 ++
2 files changed, 134 insertions(+), 1
Testcase for reserved bits in Monitor Mode
Control Register A (MMCRA) thresh_ctl bits.
For MMCRA[48:51]/[52:55]) Threshold Start/Stop,
0b/0b is reserved.
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/event_code_tests/Makefile | 2
"radix_scope_qual" bit 18 in Monitor
Mode Control Register 1 (MMCR1).
Testcase to ensure that using reserved bits in
event code should cause event_open to fail.
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/event_code_tests/Makefile | 2 +-
.../invalid_event_code_test.c
that using different sample bits in event code will fail
in event open for group of events
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/event_code_tests/Makefile | 3 +-
.../group_constraint_mmcra_sample_test.c | 54 +++
2 files changed, 56 insertions(+), 1 deletion(-)
c
event_open to fail. Input event
code in testcases uses these sampling bits along with
401e0 (PM_MRK_INST_CMPL).
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/event_code_tests/Makefile | 2 +-
...eserved_bits_mmcra_sample_elig_mode_test.c | 77 +++
2 files changed, 78 insertions
14242" (PM_DATA_RADIX_PROCESS_L2_PTE_FROM_L2) with radix_scope_qual
bit set for power10.
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/event_code_tests/Makefile | 2 +-
.../group_constraint_radix_scope_qual_test.c | 56 +++
2 files changed, 57 insertions(+), 1 deletion(-)
create mode 100644
too
Testcase for group constraint check when using events
with same PMC. Multiple events in a group asking for
same PMC should fail. Testcase uses "0x22C040" on PMC2
as leader and also subling which is expected to fail.
Using PMC1 for sibling event should pass the test.
Signed-off-by: Ath
-by: Athira Rajeev
---
.../powerpc/pmu/event_code_tests/Makefile | 2 +-
.../group_constraint_pmc_count_test.c | 70 +++
2 files changed, 71 insertions(+), 1 deletion(-)
create mode 100644
tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_pmc_count_test.c
have cache bit set. Testcase use three events,
ie, 600f4(cycles), 500fa(instructions), 22C040 with cache
bit (dc_ic) set to test this constraint check.
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/event_code_tests/Makefile | 2 +-
.../group_pmc56_exclude_constraints_test.c| 64
bits in event code for
500fa and 600f4 to check this scenario.
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/event_code_tests/Makefile | 2 +-
.../group_constraint_pmc56_test.c | 63 +++
2 files changed, 64 insertions(+), 1 deletion(-)
create mode 100644
tools
responding Makefiles in "selftests/powerpc"
and "event_code_tests" folder.
Signed-off-by: Athira Rajeev
---
tools/testing/selftests/powerpc/pmu/Makefile | 11 +--
.../selftests/powerpc/pmu/event_code_tests/Makefile | 9 +
2 files changed, 18 insertions(+), 2
From: Kajol Jain
The testcase uses "instructions" event to generate the
samples and fetch Monitor Mode Control Register A (MMCRA)
when overflow. Branch History Rolling Buffer(bhrb) disable bit
is part of MMCRA which need to be verified by perf interface.
Incase sample is not of branch type, bhrb
The testcase uses event code "0x21c040" to verify
the settings for different fields in Monitor Mode Control
Register 1 (MMCR1). The fields include PMCxSEL, PMCXCOMB
PMCxUNIT, cache. Checks if these fields are translated
correctly via perf interface to MMCR1
Signed-off-by: Ath
for invalid and valid branch
sample types. The branch types for testcase are picked
from "perf_branch_sample_type" in perf_event.h
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/sampling_tests/Makefile | 3 +-
.../pmu/sampling_tests/bhrb_filter_map_test.c | 105 +
tcase
uses software event cycles since software event will work even
in cases without PMU.
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/sampling_tests/Makefile | 2 +-
.../intr_regs_no_crash_wo_pmu_test.c | 57 +++
2 files changed, 58 insertions(+), 1 deletion(
uses software event cycles since software event is
available and can be used even in cases without PMU.
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/sampling_tests/Makefile | 2 +-
.../bhrb_no_crash_wo_pmu_test.c | 59 +++
2 files changed, 60 insertions(
o sampling
tests "misc.h" file. This can be used in next tests to
find event array size. Also update "include/reg.h" to
add macros to find minor and major version from PVR which
will be used in testcases.
Signed-off-by: Athira Rajeev
---
tools/testing/selftests/powerpc/in
From: Kajol Jain
The testcase uses "instructions" event to generate the
samples and fetch Monitor Mode Control Register A (MMCRA)
when overflow. Branch History Rolling Buffer(bhrb) disable bit
is part of MMCRA which need to be verified by perf interface.
Testcase checks if the bhrb disable bit
From: Kajol Jain
The testcase uses "instructions" event to check if the
Instruction filtering mode(IFM) bits are programmed correctly
for conditional branch type. Testcase checks if IFM bits is
programmed correctly to Monitor Mode Control Register A (MMCRA)
via perf interface for ISA v3.1
From: Kajol Jain
The testcase uses "instructions" event to check if the
Instruction filtering mode(IFM) bits are programmed correctly
for type any branch. Testcase checks if IFM bits is
programmed correctly to Monitor Mode Control Register A (MMCRA)
via perf interface.
Signed-off-by: Kajol Jain
From: Kajol Jain
The testcase uses "instructions" event to check if the
Instruction filtering mode(IFM) bits are programmed correctly
for indirect branch type. Testcase checks if IFM bits are
programmed correctly to Monitor Mode Control Register A (MMCRA)
via perf interface for ISA v3.1
From: Kajol Jain
Add support for sample type as PERF_SAMPLE_BRANCH_STACK in sampling
tests. This change is a precursor/helper for sampling testcases, that
test branck stack feature in perf interface.
Signed-off-by: Kajol Jain
---
.../powerpc/pmu/sampling_tests/misc.c | 21
From: Kajol Jain
The testcase uses event code 0x35340401e0 for load
only sampling, to verify the settings of thresh compare field
in Monitor Mode Control Register A (MMCRA: 9-18 bits for power9
and MMCRA: 8-18 bits for power10). Testcase checks if the thresh compare
field is programmed correctly
". The same could be used
in powerpc in future. Since currently we don't have the "caps"
support in powerpc, patch uses auxv information to detect platform
type and compat mode. But as placeholder utility function is added
considering possiblity of getting "caps"
From: Kajol Jain
In power10, threshold compare field is not part of the raw
event code and provided via event attribute config1.
Hence add the mask and shift bits based on event attribute
config1, to extract the threshold compare value for power10
Also add a new function called
c used pmu_name for generic compat pmu
as generic_compat_pmu. But latest version of patch to expose caps
in powerpc will use power_pmu->name. So change the pmu name in
misc code as GENERIC_COMPAT ( which is what pmu->name uses in driver
code).
Link to linuxppc-ci:
https://github.com/athi
= "GENERIC_COMPAT",
> + .name = "ISAv3",
Looks good.
Reviewed-by: Athira Rajeev
> .n_counter = MAX_PMU_COUNTERS,
> .add_fields = ISA207_ADD_FIELDS,
> .test_adder = ISA207_TEST_ADDER,
> --
> 2.35.1
>
d ("powerpc/perf: Fix PMU callbacks to clear pending PMI
before resetting an overflown PMC")
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/core-book3s.c | 35 ++---
1 file changed, 15 insertions(+), 20 deletions(-)
diff --git a/arch/powerpc/perf/core-book3
> On 14-May-2022, at 12:02 AM, Ian Rogers wrote:
>
> On Thu, May 12, 2022 at 11:16 PM Disha Goel
> wrote:
>>
>>
>>
>> -Original Message-
>> From: Athira Rajeev
>> To: a...@kernel.org, jo...@kernel.org
>> Cc: m...@ellerman.id.
> On 14-May-2022, at 12:03 AM, Ian Rogers wrote:
>
> On Thu, May 12, 2022 at 11:18 PM Disha Goel
> wrote:
>>
>>
>>
>> -Original Message-
>> From: Athira Rajeev
>> To: a...@kernel.org, jo...@kernel.org
>> Cc: m...@ellerman.id.
hv_24x7 and hv_gpci
having "?" in event format. Hence skip these events on powerpc
platform since values like partition_id, domain is specific
to system and event.
Fixes: 3d5ac9effcc6 ("perf test: Workload test of all PMUs")
Signed-off-by: Athira Rajeev
---
Changelog:
v2 -> v3
From: Kajol Jain
The testcase checks if the transalation of a generic hardware cache
event is done properly via perf interface. The hardware cache events
has type as PERF_TYPE_HW_CACHE and each event points to raw event
code id.
Testcase checks different combination of cache level,
cache event
From: Kajol Jain
Thresh select bits in the event code is used to program thresh_sel
field in Monitor Mode Control Register A (MMCRA: 45-47). When scheduling
events as a group, all events in that group should match value in these
bits. Otherwise event open for the sibling events will fail.
From: Kajol Jain
Thresh control bits in the event code is used to program thresh_ctl
field in Monitor Mode Control Register A (MMCRA: 48-55). When scheduling
events as a group, all events in that group should match value in these
bits. Otherwise event open for the sibling events will fail.
From: Kajol Jain
Unit and pmu bits in the event code is used to program unit and pmc
fields in Monitor Mode Control Register 1 (MMCR1). For power9 platform,
incase unit field value is within 6 to 9, one of the event in the group
should use PMC4. Otherwise event_open should fail for that group.
From: Kajol Jain
Thresh compare bits for a event is used to program thresh compare
field in Monitor Mode Control Register A (MMCRA: 9-18 bits for
power9 and MMCRA: 8-18 bits for power10). When scheduling events
as a group, all events in that group should match value in
thresh compare bits.
From: Kajol Jain
Data and instruction cache qualifier bits in the event code is
used to program cache select field in Monitor Mode Control
Register 1 (MMCR1: 16-17). When scheduling events as a group, all
events in that group should match value in these bits. Otherwise
event open for the sibling
From: Kajol Jain
In power10, L2L3 select bits in the event code is used to
program l2l3_sel field in Monitor Mode Control Register 0
(MMCR0: 56-60). When scheduling events as a group,
all events in that group should match value in these bits.
Otherwise event open for the sibling events will
in power9 are:
- PERF_COUNT_HW_BUS_CYCLES
- PERF_COUNT_HW_REF_CPU_CYCLES
Testcase does event open for valid and invalid generic
events to ensure event open works for all valid events
and fails for invalid events.
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/event_code_tests/Makefile | 2
to use 0x0001e in the group. Testcase uses such
combination all events in power10 which has alternative event.
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/event_code_tests/Makefile | 2 +-
.../event_alternatives_tests_p10.c| 109 ++
2 files changed, 110
and 0x200fa as group. Testcase uses such
combination for all events in power9 which has an
alternative event.
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/event_code_tests/Makefile | 2 +-
.../event_alternatives_tests_p9.c | 116 ++
2 files changed, 117
is only applicable on power9 DD2.1 and DD2.2 and
hence test adds checks to skip on other platforms.
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/event_code_tests/Makefile | 3 +-
.../blacklisted_events_test.c | 132 ++
2 files changed, 134 insertions(+), 1
Testcase for reserved bits in Monitor Mode
Control Register A (MMCRA) thresh_ctl bits.
For MMCRA[48:51]/[52:55]) Threshold Start/Stop,
0b/0b is reserved.
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/event_code_tests/Makefile | 2
"radix_scope_qual" bit 18 in Monitor
Mode Control Register 1 (MMCR1).
Testcase to ensure that using reserved bits in
event code should cause event_open to fail.
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/event_code_tests/Makefile | 2 +-
.../invalid_event_code_test.c
that using different sample bits in event code will fail
in event open for group of events
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/event_code_tests/Makefile | 3 +-
.../group_constraint_mmcra_sample_test.c | 54 +++
2 files changed, 56 insertions(+), 1 deletion(-)
c
event_open to fail. Input event
code in testcases uses these sampling bits along with
401e0 (PM_MRK_INST_CMPL).
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/event_code_tests/Makefile | 2 +-
...eserved_bits_mmcra_sample_elig_mode_test.c | 77 +++
2 files changed, 78 insertions
14242" (PM_DATA_RADIX_PROCESS_L2_PTE_FROM_L2) with radix_scope_qual
bit set for power10.
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/event_code_tests/Makefile | 2 +-
.../group_constraint_radix_scope_qual_test.c | 56 +++
2 files changed, 57 insertions(+), 1 deletion(-)
create mode 100644
too
Testcase for group constraint check when using events
with same PMC. Multiple events in a group asking for
same PMC should fail. Testcase uses "0x22C040" on PMC2
as leader and also subling which is expected to fail.
Using PMC1 for sibling event should pass the test.
Signed-off-by: Ath
-by: Athira Rajeev
---
.../powerpc/pmu/event_code_tests/Makefile | 2 +-
.../group_constraint_pmc_count_test.c | 70 +++
2 files changed, 71 insertions(+), 1 deletion(-)
create mode 100644
tools/testing/selftests/powerpc/pmu/event_code_tests/group_constraint_pmc_count_test.c
have cache bit set. Testcase use three events,
ie, 600f4(cycles), 500fa(instructions), 22C040 with cache
bit (dc_ic) set to test this constraint check.
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/event_code_tests/Makefile | 2 +-
.../group_pmc56_exclude_constraints_test.c| 64
bits in event code for
500fa and 600f4 to check this scenario.
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/event_code_tests/Makefile | 2 +-
.../group_constraint_pmc56_test.c | 63 +++
2 files changed, 64 insertions(+), 1 deletion(-)
create mode 100644
tools
responding Makefiles in "selftests/powerpc"
and "event_code_tests" folder.
Signed-off-by: Athira Rajeev
---
tools/testing/selftests/powerpc/pmu/Makefile | 11 +--
.../selftests/powerpc/pmu/event_code_tests/Makefile | 9 +
2 files changed, 18 insertions(+), 2
From: Kajol Jain
The testcase uses "instructions" event to generate the
samples and fetch Monitor Mode Control Register A (MMCRA)
when overflow. Branch History Rolling Buffer(bhrb) disable bit
is part of MMCRA which need to be verified by perf interface.
Incase sample is not of branch type, bhrb
The testcase uses event code "0x21c040" to verify
the settings for different fields in Monitor Mode Control
Register 1 (MMCR1). The fields include PMCxSEL, PMCXCOMB
PMCxUNIT, cache. Checks if these fields are translated
correctly via perf interface to MMCR1
Signed-off-by: Ath
for invalid and valid branch
sample types. The branch types for testcase are picked
from "perf_branch_sample_type" in perf_event.h
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/sampling_tests/Makefile | 3 +-
.../pmu/sampling_tests/bhrb_filter_map_test.c | 105 +
tcase
uses software event cycles since software event will work even
in cases without PMU.
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/sampling_tests/Makefile | 2 +-
.../intr_regs_no_crash_wo_pmu_test.c | 57 +++
2 files changed, 58 insertions(+), 1 deletion(
uses software event cycles since software event is
available and can be used even in cases without PMU.
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/sampling_tests/Makefile | 2 +-
.../bhrb_no_crash_wo_pmu_test.c | 59 +++
2 files changed, 60 insertions(
o sampling
tests "misc.h" file. This can be used in next tests to
find event array size. Also update "include/reg.h" to
add macros to find minor and major version from PVR which
will be used in testcases.
Signed-off-by: Athira Rajeev
---
tools/testing/selftests/powerpc/in
From: Kajol Jain
The testcase uses "instructions" event to generate the
samples and fetch Monitor Mode Control Register A (MMCRA)
when overflow. Branch History Rolling Buffer(bhrb) disable bit
is part of MMCRA which need to be verified by perf interface.
Testcase checks if the bhrb disable bit
From: Kajol Jain
The testcase uses "instructions" event to check if the
Instruction filtering mode(IFM) bits are programmed correctly
for conditional branch type. Testcase checks if IFM bits is
programmed correctly to Monitor Mode Control Register A (MMCRA)
via perf interface for ISA v3.1
From: Kajol Jain
The testcase uses "instructions" event to check if the
Instruction filtering mode(IFM) bits are programmed correctly
for type any branch. Testcase checks if IFM bits is
programmed correctly to Monitor Mode Control Register A (MMCRA)
via perf interface.
Signed-off-by: Kajol Jain
From: Kajol Jain
The testcase uses "instructions" event to check if the
Instruction filtering mode(IFM) bits are programmed correctly
for indirect branch type. Testcase checks if IFM bits are
programmed correctly to Monitor Mode Control Register A (MMCRA)
via perf interface for ISA v3.1
From: Kajol Jain
Add support for sample type as PERF_SAMPLE_BRANCH_STACK in sampling
tests. This change is a precursor/helper for sampling testcases, that
test branck stack feature in perf interface.
Signed-off-by: Kajol Jain
---
.../powerpc/pmu/sampling_tests/misc.c | 21
From: Kajol Jain
The testcase uses event code 0x35340401e0 for load
only sampling, to verify the settings of thresh compare field
in Monitor Mode Control Register A (MMCRA: 9-18 bits for power9
and MMCRA: 8-18 bits for power10). Testcase checks if the thresh compare
field is programmed correctly
". The same could be used
in powerpc in future. Since currently we don't have the "caps"
support in powerpc, patch uses auxv information to detect platform
type and compat mode. But as placeholder utility function is added
considering possiblity of getting "caps"
From: Kajol Jain
In power10, threshold compare field is not part of the raw
event code and provided via event attribute config1.
Hence add the mask and shift bits based on event attribute
config1, to extract the threshold compare value for power10
Also add a new function called
eneric_compat_pmu. But latest version of patch to expose caps
in powerpc will use power_pmu->name. So change the pmu name in
misc code as GENERIC_COMPAT ( which is what pmu->name uses in driver
code).
Link to linuxppc-ci:
https://github.com/athira-rajeev/linux-ci/actions?query=branch%3
Details is added about "caps" attribute group in the ABI documentation.
This is used to expose some of the PMU attributes in "caps"
directory under : /sys/bus/event_source/devices//. The dev/caps
will contain information about features that platform specific PMU
supports.
S
ok3s using "attr_update".
The information exposed currently:
- pmu_name : Underlying PMU name from the driver
Example result with power9 pmu:
# ls /sys/bus/event_source/devices/cpu/caps
pmu_name
# cat /sys/bus/event_source/devices/cpu/caps/pmu_name
POWER9
Signed-off-by: Athira Rajeev
> On 20-May-2022, at 12:15 AM, Ian Rogers wrote:
>
> On Thu, May 19, 2022 at 8:43 AM Athira Rajeev
> wrote:
>>
>> "perf all PMU test" picks the input events from
>> "perf list --raw-dump pmu" list and runs "perf stat -e&qu
> On 20-May-2022, at 3:06 AM, Ian Rogers wrote:
>
> On Thu, May 19, 2022 at 4:29 AM Athira Rajeev
> wrote:
>>
>>> On 19-May-2022, at 10:12 AM, Ian Rogers wrote:
>>>
>>> On Wed, May 18, 2022 at 1:55 AM Athira Rajeev
>>> wrote:
&g
ailing list.
>>
>> Link to the thresh_cmp fix patchset:
>> http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=298742
>>
>> Patch 13 of the patchset add selftest for mmcr1 pmcxsel/unit/cache fields,
>> which was initially dropeed from sampling test patchs
hv_24x7 and hv_gpci
having "?" in event format. Hence skip these events on powerpc
platform since values like partition_id, domain is specific
to system and event.
Fixes: 3d5ac9effcc6 ("perf test: Workload test of all PMUs")
Signed-off-by: Athira Rajeev
---
Changelog:
v1 -&g
> On 19-May-2022, at 10:12 AM, Ian Rogers wrote:
>
> On Wed, May 18, 2022 at 1:55 AM Athira Rajeev
> wrote:
>>
>> Add caps support under "/sys/bus/event_source/devices//"
>> for powerpc. This directory can be used to expose some of the
>&g
> On 18-May-2022, at 6:35 PM, Michael Ellerman wrote:
>
> Athira Rajeev writes:
>> "perf all PMU test" picks the input events from
>> "perf list --raw-dump pmu" list and runs "perf stat -e"
>> for each of the event in the list. In ca
hv_24x7 and hv_gpci
having "?" in event format. Hence skip these events on powerpc
platform since values like partition_id, domain is specific
to system and event.
Fixes: 3d5ac9effcc6 ("perf test: Workload test of all PMUs")
Signed-off-by: Athira Rajeev
---
tools/perf/tes
Add ABI documentation for "caps" attribute group.
Some of the platform specific PMU features can be exposed
in "caps" attribute group/directory:
/sys/bus/event_source/devices//
Signed-off-by: Athira Rajeev
---
.../sysfs-bus-event_source-devices-caps| 18 ++
ok3s using "attr_update".
The information exposed currently:
- pmu_name : Underlying PMU name from the driver
Example result with power9 pmu:
# ls /sys/bus/event_source/devices/cpu/caps
pmu_name
# cat /sys/bus/event_source/devices/cpu/caps/pmu_name
POWER9
Signed-off-by: Athira Rajeev
sys
>
> Result after the patch changes:
>
> [command]# perf stat -e "{r8735340401e0,r8734340101ec}" sleep 1
> Error:
> The sys_perf_event_open() syscall returned with 22 (Invalid argument)
> for event (r8735340401e0).
> /bin/dmesg | grep -i perf may provide additional
After the patch:
<<>>
42: BPF filter:
42.1: Basic BPF filtering : Skip
42.2: BPF pinning : Skip
42.3: BPF prologue generation : Skip
<<>>
Fixes: ba1fae431e74 ("perf test: Add 'perf test BPF'")
Signed-off-by: Athira
an't be fetched from topology info.
Skip the testcase in powerpc if physical_package_id returns -1
Signed-off-by: Athira Rajeev
---
Changelog:
v1 -> v2:
Addressed review comments from Arnaldo and Michael Ellerman.
skip the test in powerpc when physical_package_id is set to
-1.
Dropped patch 1
> On 06-May-2022, at 3:07 PM, Athira Rajeev wrote:
>
>
>
>> On 05-May-2022, at 10:51 PM, Arnaldo Carvalho de Melo
>> wrote:
>>
>> Em Thu, May 05, 2022 at 03:30:39PM +0530, Athira Rajeev escreveu:
>>> Perf BPF filter test fails in e
> On 06-May-2022, at 3:03 PM, Athira Rajeev wrote:
>
>
>
>> On 05-May-2022, at 10:54 PM, Arnaldo Carvalho de Melo
>> wrote:
>>
>> Em Thu, May 05, 2022 at 03:09:59PM +0530, Athira Rajeev escreveu:
>>> /proc/cpuinfo provides information abo
> On 06-May-2022, at 6:55 PM, Michael Ellerman wrote:
>
> Hi Athira,
>
> Some comments below :)
>
> Athira Rajeev writes:
>> Add caps support under "/sys/bus/event_source/devices//"
>> for powerpc. This directory can be used to expose some o
ep 1
>
> Performance counter stats for 'sleep 1':
>
> r35340401e0
> r34340101ec
>
> 1.001499607 seconds time elapsed
>
> 0.000204000 seconds user
> 0.00076 seconds sys
>
> Fixes: 82d2c16b350f7 ("powerpc/perf: Adds supp
> On 05-May-2022, at 10:51 PM, Arnaldo Carvalho de Melo wrote:
>
> Em Thu, May 05, 2022 at 03:30:39PM +0530, Athira Rajeev escreveu:
>> Perf BPF filter test fails in environment where "clang"
>> is not installed.
>>
>> Test
> On 05-May-2022, at 10:54 PM, Arnaldo Carvalho de Melo wrote:
>
> Em Thu, May 05, 2022 at 03:09:59PM +0530, Athira Rajeev escreveu:
>> /proc/cpuinfo provides information about type of processor, number
>> of CPU's etc. Reading /proc/cpuinfo file outputs useful informa
After the patch:
<<>>
42: BPF filter:
42.1: Basic BPF filtering : Skip
42.2: BPF pinning : Skip
42.3: BPF prologue generation : Skip
<<>>
Signed-off-by: Athira Rajeev
---
tools/perf/tests/bpf.c | 4 ++--
1 file changed, 2 in
an't be fetched from topology info.
Skip the testcase in powerpc for pSeries. Use the utility
function "cpuinfo_field" to check platform from /proc/cpuinfo.
Results:
After the patch:
# ./perf test 41
41: Session topology : Skip
Signed-off-by: Athira R
ssor information
from "cpuinfo" by other utilities/testcases.
Signed-off-by: Athira Rajeev
---
tools/perf/util/header.c | 53
tools/perf/util/header.h | 1 +
2 files changed, 54 insertions(+)
diff --git a/tools/perf/util/header.c b/tools/perf/util/h
neric function to return value for any entry from the
/proc/cpuinfo file which can be used commonly in future
usecases.
Patch 2 uses the newly added utility function to look for
platform and skip the test in pSeries platform for powerpc.
Athira Rajeev (2):
tools/perf: Add utility function to r
> On 04-May-2022, at 7:16 PM, kajoljain wrote:
>
>
>
> On 4/28/22 20:38, Athira Rajeev wrote:
>> /proc/cpuinfo provides information about type of processor, number
>> of CPU's etc. Reading /proc/cpuinfo file outputs useful information
>> by field name lik
an't be fetched from topology info.
Skip the testcase in powerpc for pSeries. Use the utility
function "cpuinfo_field" to check platform from /proc/cpuinfo.
Signed-off-by: Athira Rajeev
---
tools/perf/tests/topology.c | 17 +
1 file changed, 17 insertions(+)
diff --gi
ssor information
from "cpuinfo" by other utilities/testcases.
Signed-off-by: Athira Rajeev
---
tools/perf/util/header.c | 54
tools/perf/util/header.h | 1 +
2 files changed, 55 insertions(+)
diff --git a/tools/perf/util/header.c b/tools/perf/util/h
neric function to return value for any entry from the
/proc/cpuinfo file which can be used commonly in future
usecases.
Patch 2 uses the newly added utility function to look for
platform and skip the test in pSeries platform for powerpc.
Athira Rajeev (2):
tools/perf: Add utility function to r
r
Example result with power9 pmu:
# ls /sys/bus/event_source/devices/cpu/caps
pmu_name
# cat /sys/bus/event_source/devices/cpu/caps/pmu_name
power9
Signed-off-by: Athira Rajeev
Reviewed-by: Madhavan Srinivasan
---
arch/powerpc/perf/generic-compat-pmu.c | 20
arch/powerpc/pe
10 Performance Monitoring support")
Signed-off-by: Athira Rajeev
Reviewed-by: Madhavan Srinivasan
---
Changelog:
v1 -> v2:
Added Fixes tag and reworded commit message
Added Reviewed-by from Maddy
v2 -> v3:
Added info about what is the breakage with current
code.
arch/powerpc/p
the events are using PMC3 in this case, they are
multiplexed here.
<>
# perf stat -e r3e054,r300fc
^C
Performance counter stats for 'system wide':
1006948 r3e054
182 r300fc
<<>>
Fixes: 91e0bd1e6251 ("powerpc/perf: Add PM_LD_MISS_L1 and PM_BR_2PA
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