]
static struct cpumask watchdog_allowed_mask __read_mostly;
```
Signed-off-by: Balamuruhan S
---
kernel/watchdog.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/kernel/watchdog.c b/kernel/watchdog.c
index 5abb5b22ad13..33c9b8a3d51b 100644
--- a/kernel/watchdog.c
+++ b/kernel
]
static struct cpumask watchdog_allowed_mask __read_mostly;
```
Signed-off-by: Balamuruhan S
---
kernel/watchdog.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/kernel/watchdog.c b/kernel/watchdog.c
index 5abb5b22ad13..33c9b8a3d51b 100644
--- a/kernel/watchdog.c
+++ b/kernel
)
* Prefixed Store VSX Vector Paired (pstxvp)
Suggested-by: Ravi Bangoria
Signed-off-by: Balamuruhan S
---
arch/powerpc/lib/test_emulate_step.c | 252 +++
1 file changed, 252 insertions(+)
diff --git a/arch/powerpc/lib/test_emulate_step.c
b/arch/powerpc/lib
)
* Store VSX Vector Paired Indexed (stxvpx)
* Prefixed Store VSX Vector Paired (pstxvp)
Signed-off-by: Balamuruhan S
---
arch/powerpc/include/asm/ppc-opcode.h | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/powerpc/include/asm/ppc-opcode.h
b/arch/powerpc
add emulate_step() changes to support vsx vector paired storage
access instructions that provides octword operands loads/stores
between storage and set of 64 Vector Scalar Registers (VSRs).
Suggested-by: Ravi Bangoria
Suggested-by: Naveen N. Rao
Signed-off-by: Balamuruhan S
---
arch/powerpc
(plxvp)
* Store VSX Vector Paired (stxvp)
* Store VSX Vector Paired Indexed (stxvpx)
* Prefixed Store VSX Vector Paired (pstxvp)
Suggested-by: Naveen N. Rao
Signed-off-by: Balamuruhan S
---
arch/powerpc/lib/sstep.c | 45
1 file
branch.
Changes in v2:
-
* Fix suggestion from Sandipan, wrap ISA 3.1 instructions with
cpu_has_feature(CPU_FTR_ARCH_31) check.
* Rebase on latest powerpc next branch.
Balamuruhan S (4):
powerpc/sstep: support new VSX vector paired storage access
instructions
powerpc/sstep
dividend to cover -|divisor| < r <= 0 if
the dividend is negative for divde[.]
* normal case with proper dividend and divisor for both
divde[.] and divdeu[.]
Reviewed-by: Sandipan Das
Signed-off-by: Balamuruhan S
Acked-by: Naveen N. Rao
---
arch/power
This patch adds emulation support for divde, divdeu instructions,
* Divide Doubleword Extended (divde[.])
* Divide Doubleword Extended Unsigned (divdeu[.])
Reviewed-by: Sandipan Das
Signed-off-by: Balamuruhan S
Acked-by: Naveen N. Rao
---
arch/powerpc/lib/sstep.c | 13
include instruction opcodes for divde and divdeu as macros.
Reviewed-by: Sandipan Das
Signed-off-by: Balamuruhan S
Acked-by: Naveen N. Rao
---
arch/powerpc/include/asm/ppc-opcode.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/powerpc/include/asm/ppc-opcode.h
b/arch/powerpc
greatest stack
depth: 11824 bytes left
355356256: (355355821): Welcome to Buildroot
355376898: (355376463): buildroot login:
Balamuruhan S (3):
powerpc ppc-opcode: add divde and divdeu opcodes
powerpc sstep: add support for divde[.] and divdeu[.] instructions
powerpc test_emulate_step: add
)
* Prefixed Store VSX Vector Paired (pstxvp)
Signed-off-by: Balamuruhan S
---
arch/powerpc/include/asm/ppc-opcode.h | 7 +
arch/powerpc/lib/test_emulate_step.c | 273 ++
2 files changed, 280 insertions(+)
diff --git a/arch/powerpc/include/asm/ppc-opcode.h
b/arch
add instruction opcodes for new vsx vector paired instructions,
* Load VSX Vector Paired (lxvp)
* Load VSX Vector Paired Indexed (lxvpx)
* Store VSX Vector Paired (stxvp)
* Store VSX Vector Paired Indexed (stxvpx)
Signed-off-by: Balamuruhan S
---
arch/powerpc
add emulate_step() changes to support vsx vector paired storage
access instructions that provides octword operands loads/stores
between storage and set of 2 Vector Scalar Registers (VSRs).
Signed-off-by: Balamuruhan S
---
arch/powerpc/include/asm/sstep.h | 2 +-
arch/powerpc/lib/sstep.c
(plxvp)
* Store VSX Vector Paired (stxvp)
* Store VSX Vector Paired Indexed (stxvpx)
* Prefixed Store VSX Vector Paired (pstxvp)
Signed-off-by: Balamuruhan S
---
arch/powerpc/lib/sstep.c | 52
1 file changed, 52 insertions(+)
diff
:
-
* Fix suggestion from Sandipan, wrap ISA 3.1 instructions with
cpu_has_feature(CPU_FTR_ARCH_31) check.
* Rebase on latest powerpc next branch.
Balamuruhan S (4):
powerpc/sstep: support new VSX vector paired storage access
instructions
powerpc/sstep: support emulation for vsx
)
* Prefixed Store VSX Vector Paired (pstxvp)
Signed-off-by: Balamuruhan S
---
arch/powerpc/include/asm/ppc-opcode.h | 7 +
arch/powerpc/lib/test_emulate_step.c | 273 ++
2 files changed, 280 insertions(+)
diff --git a/arch/powerpc/include/asm/ppc-opcode.h
b/arch
add instruction opcodes for new vsx vector paired instructions,
* Load VSX Vector Paired (lxvp)
* Load VSX Vector Paired Indexed (lxvpx)
* Store VSX Vector Paired (stxvp)
* Store VSX Vector Paired Indexed (stxvpx)
Signed-off-by: Balamuruhan S
---
arch/powerpc
add emulate_step() changes to support vsx vector paired storage
access instructions that provides octword operands loads/stores
between storage and set of 64 Vector Scalar Registers (VSRs).
Signed-off-by: Balamuruhan S
---
arch/powerpc/include/asm/sstep.h | 2 +-
arch/powerpc/lib/sstep.c
, stxvp,
stxvpx, plxvpx, pstxvpx.
Emulation infrastructure doesn't have support for these instructions, to
operate with 32-byte storage access and to operate with 2 VSX registers.
This patch series enables the instruction emulation support and adds test
cases for them respectively.
Balamuruhan S (4
(plxvp)
* Store VSX Vector Paired (stxvp)
* Store VSX Vector Paired Indexed (stxvpx)
* Prefixed Store VSX Vector Paired (pstxvp)
Signed-off-by: Balamuruhan S
---
arch/powerpc/lib/sstep.c | 44
1 file changed, 44 insertions(+)
diff
retrieve prefix instruction operands RA and pc relative bit R values
using macros and adopt it in sstep.c and test_emulate_step.c.
Signed-off-by: Balamuruhan S
---
arch/powerpc/include/asm/sstep.h | 4
arch/powerpc/lib/sstep.c | 12 ++--
2 files changed, 10 insertions
add provision to declare test is a negative scenario, verify
whether emulation fails and avoid executing it.
Signed-off-by: Balamuruhan S
---
arch/powerpc/lib/test_emulate_step.c | 30 +++-
1 file changed, 21 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/lib
Few ppc instructions are encoded in test_emulate_step.c, consolidate
them and use it from ppc-opcode.h
Signed-off-by: Balamuruhan S
Acked-by: Naveen N. Rao
Tested-by: Naveen N. Rao
Acked-by: Sandipan Das
---
arch/powerpc/include/asm/ppc-opcode.h | 18 +++
arch/powerpc/lib
Introduce PPC_RAW_* macros to have all the bare encoding of ppc
instructions. Move `VSX_XX*()` and `TMRN()` macros up to reuse it.
Signed-off-by: Balamuruhan S
Acked-by: Naveen N. Rao
Tested-by: Naveen N. Rao
---
arch/powerpc/include/asm/ppc-opcode.h | 90 ---
1 file
rfc v2: https://lists.ozlabs.org/pipermail/linuxppc-dev/2020-April/209395.html
rfc v1: https://lists.ozlabs.org/pipermail/linuxppc-dev/2020-March/206494.html
Balamuruhan S (6):
powerpc/ppc-opcode: introduce PPC_RAW_* macros for base instruction
encoding
powerpc/ppc-opcode: move ppc instr
fix checkpatch.pl warnings by moving extern declaration from source
file to headerfile.
Signed-off-by: Balamuruhan S
---
arch/powerpc/include/asm/sstep.h | 2 ++
arch/powerpc/lib/test_emulate_step.c | 2 --
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include
retrieve prefix instruction operands RA and pc relative bit R values
using macros and adopt it in sstep.c and test_emulate_step.c.
Signed-off-by: Balamuruhan S
---
arch/powerpc/include/asm/sstep.h | 4
arch/powerpc/lib/sstep.c | 12 ++--
arch/powerpc/lib
testcases for `paddi` instruction to cover the negative case,
if R is equal to 1 and RA is not equal to 0, the instruction
form is invalid.
Signed-off-by: Balamuruhan S
---
arch/powerpc/lib/test_emulate_step.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/powerpc/lib
add provision to declare test is a negative scenario, verify
whether emulation fails and avoid executing it.
Signed-off-by: Balamuruhan S
---
arch/powerpc/lib/test_emulate_step.c | 46 ++--
1 file changed, 36 insertions(+), 10 deletions(-)
diff --git a/arch/powerpc/lib
On test failure, `pr_log()` prints 4 bytes instruction
irrespective of word/prefix instruction, fix it by printing
them appropriately.
Signed-off-by: Balamuruhan S
---
arch/powerpc/lib/test_emulate_step.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc
and the value SI is placed into register RT. So to assert the emulated
instruction with executed instruction, update nip of emulated pt_regs.
Signed-off-by: Balamuruhan S
---
arch/powerpc/lib/test_emulate_step.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/arch
This patchset adds support to test negative scenarios and adds testcase
for paddi with few fixes. It is based on powerpc/next and on top of
Jordan's tests for prefixed instructions patchset,
https://lists.ozlabs.org/pipermail/linuxppc-dev/2020-May/211394.html
Balamuruhan S (6):
powerpc
Lot of PPC_INST_* macros are used only ever in PPC_* macros, fold those
PPC_INST_* into PPC_RAW_* to avoid using PPC_INST_* accidentally.
Signed-off-by: Balamuruhan S
Acked-by: Naveen N. Rao
Tested-by: Naveen N. Rao
---
arch/powerpc/include/asm/ppc-opcode.h | 381 +-
1
Wrap existing stringify macros to reuse raw instruction encoding macros that
are newly added.
Signed-off-by: Balamuruhan S
Acked-by: Naveen N. Rao
Tested-by: Naveen N. Rao
---
arch/powerpc/include/asm/ppc-opcode.h | 220 +-
1 file changed, 71 insertions(+), 149
move macro definitions of powerpc instructions from bpf_jit.h to ppc-opcode.h
and adopt the users of the macros accordingly. `PPC_MR()` is defined twice in
bpf_jit.h, remove the duplicate one.
Signed-off-by: Balamuruhan S
Acked-by: Naveen N. Rao
Tested-by: Naveen N. Rao
---
arch/powerpc
remove duplicate macro definitions from bpf_jit.h and reuse the macros from
ppc-opcode.h
Signed-off-by: Balamuruhan S
Acked-by: Naveen N. Rao
Tested-by: Naveen N. Rao
---
arch/powerpc/net/bpf_jit.h| 18 +-
arch/powerpc/net/bpf_jit32.h | 10 +-
arch/powerpc
Few ppc instructions are encoded in test_emulate_step.c, consolidate
them and use it from ppc-opcode.h
Signed-off-by: Balamuruhan S
Acked-by: Naveen N. Rao
Tested-by: Naveen N. Rao
---
arch/powerpc/include/asm/ppc-opcode.h | 35 ++
arch/powerpc/lib/test_emulate_step.c | 155
Introduce PPC_RAW_* macros to have all the bare encoding of ppc
instructions. Move `VSX_XX*()` and `TMRN()` macros up to reuse it.
Signed-off-by: Balamuruhan S
Acked-by: Naveen N. Rao
Tested-by: Naveen N. Rao
---
arch/powerpc/include/asm/ppc-opcode.h | 183 --
1 file
https://lists.ozlabs.org/pipermail/linuxppc-dev/2020-April/209395.html
rfc v1: https://lists.ozlabs.org/pipermail/linuxppc-dev/2020-March/206494.html
Balamuruhan S (6):
powerpc/ppc-opcode: introduce PPC_RAW_* macros for base instruction
encoding
powerpc/ppc-opcode: move ppc instruction en
On Thu, 2020-04-30 at 17:27 +0530, Naveen N. Rao wrote:
> Michael Ellerman wrote:
> > "Naveen N. Rao" writes:
> > > Michael Ellerman wrote:
> > > > Balamuruhan S writes:
> > > > > Avoid redefining macros to encode ppc instructions instead r
ajor changes:
> - Completely replacing store_inst() with patch_instruction() in
> xmon
> - Improve implementation of mread_instr() to not use mread().
> - Base the series on top of
> https://patchwork.ozlabs.org/patch/1232619/ as this will effect
> kprob
Avoid redefining macros to encode ppc instructions instead reuse it from
ppc-opcode.h, Makefile changes are necessary to compile memcmp_64.S with
__ASSEMBLY__ defined from selftests.
Signed-off-by: Balamuruhan S
---
.../selftests/powerpc/stringloops/Makefile| 34
Wrap existing stringify macros to reuse raw instruction encoding macros that
are newly added.
Signed-off-by: Balamuruhan S
---
arch/powerpc/include/asm/ppc-opcode.h | 220 +-
1 file changed, 71 insertions(+), 149 deletions(-)
diff --git a/arch/powerpc/include/asm/ppc
Lot of PPC_INST_* macros are used only ever in PPC_* macros, fold those
PPC_INST_* into PPC_RAW_* to avoid using PPC_INST_* accidentally.
Signed-off-by: Balamuruhan S
---
arch/powerpc/include/asm/ppc-opcode.h | 381 +-
1 file changed, 125 insertions(+), 256 deletions
move macro definitions of powerpc instructions from bpf_jit.h to ppc-opcode.h
and adopt the users of the macros accordingly. `PPC_MR()` is defined twice in
bpf_jit.h, remove the duplicate one.
Signed-off-by: Balamuruhan S
---
arch/powerpc/include/asm/ppc-opcode.h | 139 +
arch
remove duplicate macro definitions from bpf_jit.h and reuse the macros from
ppc-opcode.h
Signed-off-by: Balamuruhan S
---
arch/powerpc/net/bpf_jit.h| 18 +-
arch/powerpc/net/bpf_jit32.h | 10 +-
arch/powerpc/net/bpf_jit64.h | 4 ++--
arch/powerpc/net
Introduce PPC_RAW_* macros to have all the bare encoding of ppc
instructions. Move `VSX_XX*()` and `TMRN()` macros up to reuse it.
Signed-off-by: Balamuruhan S
---
arch/powerpc/include/asm/ppc-opcode.h | 183 --
1 file changed, 175 insertions(+), 8 deletions(-)
diff
Few ppc instructions are encoded in test_emulate_step.c, consolidate
them and use it from ppc-opcode.h
Signed-off-by: Balamuruhan S
---
arch/powerpc/include/asm/ppc-opcode.h | 35 ++
arch/powerpc/lib/test_emulate_step.c | 155 ++
2 files changed, 91 insertions
ichael on overall suggestions/improvements.
I would request for review and suggestions to make it better.
v1: https://lists.ozlabs.org/pipermail/linuxppc-dev/2020-March/206494.html
Balamuruhan S (7):
powerpc/ppc-opcode: introduce PPC_RAW_* macros for base instruction
encoding
powerpc/ppc-opcode
On Wed, 2020-04-15 at 14:40 +1000, Jordan Niethe wrote:
> On Mon, Apr 13, 2020 at 10:04 PM Balamuruhan S wrote:
> > On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> > > For powerpc64, redefine the ppc_inst type so both word and prefixed
> > > instructions can b
On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> For powerpc64, redefine the ppc_inst type so both word and prefixed
> instructions can be represented. On powerpc32 the type will remain the
> same. Update places which had assumed instructions to be 4 bytes long.
>
> Signed-off-by:
On Wed, 2020-04-08 at 12:18 +1000, Jordan Niethe wrote:
> On Tue, Apr 7, 2020 at 9:31 PM Balamuruhan S wrote:
> > On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> > > Currently in xmon, mread() is used for reading instructions. In
> > > preparation for pr
On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> Currently in xmon, mread() is used for reading instructions. In
> preparation for prefixed instructions, create and use a new function,
> mread_instr(), especially for reading instructions.
>
> Signed-off-by: Jordan Niethe
> ---
> v5: New
On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> Currently all instructions have the same length, but in preparation for
> prefixed instructions introduce a function for returning instruction
> length.
>
> Signed-off-by: Jordan Niethe
> ---
> arch/powerpc/include/asm/inst.h | 5 +
>
On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> Define specific __get_user_instr() and __get_user_instr_inatomic()
> macros for reading instructions from user space.
>
> Signed-off-by: Jordan Niethe
> ---
> arch/powerpc/include/asm/uaccess.h | 5 +
> arch/powerpc/kernel/align.c
On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> Prefixed instructions will mean there are instructions of different
> length. As a result dereferencing a pointer to an instruction will not
> necessarily give the desired result. Introduce a function for reading
> instructions from memory
On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> Currently unsigned ints are used to represent instructions on powerpc.
> This has worked well as instructions have always been 4 byte words.
> However, a future ISA version will introduce some changes to
> instructions that mean this scheme
On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> Use a function for byte swapping instructions in preparation of a more
> complicated instruction type.
Reviewed-by: Balamuruhan S
>
> Signed-off-by: Jordan Niethe
> ---
> arch/powerpc/include/asm/inst.h | 5 +++
On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> In preparation for an instruction data type that can not be directly
> used with the '==' operator use functions for checking equality.
LGTM except one comment below, otherwise
Reviewed-by: Balamuruhan S
>
> Signed-of
On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> In preparation for using a data type for instructions that can not be
> directly used with the '>>' operator use a function for getting the op
> code of an instruction.
vecemu.c and sstep.c will need ppc_inst_opcode().
-- Bala
>
>
On Tue, 2020-04-07 at 16:35 +1000, Jordan Niethe wrote:
> On Tue, Apr 7, 2020 at 4:10 PM Balamuruhan S wrote:
> > On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> > > create_branch(), create_cond_branch() and translate_branch() return the
> > > instruction th
On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> To execute an instruction out of line after a breakpoint, the NIP is set
> to the address of struct bpt::instr. Here a copy of the instruction that
> was replaced with a breakpoint is kept, along with a trap so normal flow
> can be resumed
On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> In preparation for instructions having a more complex data type start
> using a macro, ppc_inst(), for making an instruction out of a u32. A
> macro is used so that instructions can be used as initializer elements.
> Currently this does
On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> create_branch(), create_cond_branch() and translate_branch() return the
> instruction that they create, or return 0 to signal an error. Seperate
s/seperate/separate
> these concerns in preparation for an instruction type that is not just
On Thu, 2020-04-02 at 12:34 +0530, Naveen N. Rao wrote:
> Michael Ellerman wrote:
> > "Naveen N. Rao" writes:
> > > Balamuruhan S wrote:
> > > > Few ppc instructions are encoded in test_emulate_step.c, consolidate
> > > > them to
> > >
dividend to cover -|divisor| < r <= 0 if
the dividend is negative for divde[.]
* normal case with proper dividend and divisor for both
divde[.] and divdeu[.]
Reviewed-by: Sandipan Das
Signed-off-by: Balamuruhan S
Acked-by: Naveen N. Rao
---
arch/power
This patch adds emulation support for divde, divdeu instructions,
* Divide Doubleword Extended (divde[.])
* Divide Doubleword Extended Unsigned (divdeu[.])
Reviewed-by: Sandipan Das
Signed-off-by: Balamuruhan S
Acked-by: Naveen N. Rao
---
arch/powerpc/lib/sstep.c | 13
include instruction opcodes for divde and divdeu as macros.
Reviewed-by: Sandipan Das
Signed-off-by: Balamuruhan S
Acked-by: Naveen N. Rao
---
arch/powerpc/include/asm/ppc-opcode.h | 8
1 file changed, 8 insertions(+)
diff --git a/arch/powerpc/include/asm/ppc-opcode.h
b/arch
:
Balamuruhan S (3):
powerpc ppc-opcode: add divde and divdeu opcodes
powerpc sstep: add support for divde[.] and divdeu[.] instructions
powerpc test_emulate_step: add testcases for divde[.] and divdeu[.]
instructions
arch/powerpc/include/asm/ppc-opcode.h | 8 ++
arch/powerpc/lib
On Wed, 2020-04-01 at 16:26 +0530, Naveen N. Rao wrote:
> Balamuruhan S wrote:
> > add testcases for divde, divde., divdeu, divdeu. emulated
> > instructions to cover few scenarios,
> > * with same dividend and divisor to have undefine RT
>
On Fri, 2020-03-20 at 16:17 +1100, Jordan Niethe wrote:
> Currently unsigned ints are used to represent instructions on powerpc.
> This has worked well as instructions have always been 4 byte words.
> However, a future ISA version will introduce some changes to
> instructions that mean this scheme
On Fri, 2020-02-28 at 00:14 +, Christophe Leroy wrote:
> Drop a bunch of #ifdefs CONFIG_PPC64 that are not vital.
>
> Signed-off-by: Christophe Leroy
> ---
> arch/powerpc/include/asm/ptrace.h | 2 ++
> arch/powerpc/kernel/ptrace/ptrace.c | 18 +++---
> 2 files changed, 5
e70 vfs_write+0xd0/0x210
[c3be7dd0] c041126c ksys_write+0xdc/0x130
[c3be7e20] c000b9d0 system_call+0x5c/0x68
--- Exception: c01 (System Call) at 7fffa345e420
SP (70b08ab0) is in userspace
Signed-off-by: Balamuruhan S
---
arch/powerpc/xmon/xmon.c | 2 +-
1 f
On Fri, 2020-03-27 at 16:12 +0100, Christophe Leroy wrote:
>
> Le 27/03/2020 à 10:03, Balamuruhan S a écrit :
> > On Fri, 2020-03-27 at 07:48 +0100, Christophe Leroy wrote:
> > > Le 26/03/2020 à 07:15, Balamuruhan S a écrit :
> > > > Data Cache Block Invalidate (
On Fri, 2020-03-27 at 07:48 +0100, Christophe Leroy wrote:
>
> Le 26/03/2020 à 07:15, Balamuruhan S a écrit :
> > Data Cache Block Invalidate (dcbi) instruction was implemented back in
> > PowerPC
> > architecture version 2.03. It is obsolete and attempt to use of this
>
xdc/0x130
[c3be7e20] c000b9d0 system_call+0x5c/0x68
--- Exception: c01 (System Call) at 7fffa345e420
SP (70b08ab0) is in userspace
Signed-off-by: Balamuruhan S
---
arch/powerpc/xmon/xmon.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
---
changes in
On Tue, 2020-03-24 at 14:18 +1100, Jordan Niethe wrote:
> On Mon, Mar 23, 2020 at 10:13 PM Balamuruhan S wrote:
> > On Fri, 2020-03-20 at 16:18 +1100, Jordan Niethe wrote:
> > > In preparation for prefixed instructions where all instructions are no
> > > longer words,
On Tue, 2020-03-24 at 14:52 +1100, Michael Ellerman wrote:
> "Naveen N. Rao" writes:
> > Segher Boessenkool wrote:
> > > On Mon, Mar 23, 2020 at 04:55:48PM +0530, Balamuruhan S wrote:
> > > > Data Cache Block Invalidate (dcbi) instruction implemented in
On Mon, 2020-03-23 at 07:46 -0500, Segher Boessenkool wrote:
> On Mon, Mar 23, 2020 at 04:55:48PM +0530, Balamuruhan S wrote:
> > Data Cache Block Invalidate (dcbi) instruction implemented in 32-bit
> > designs prior to PowerPC architecture version 2.01 and got obsolete
> &
210
[c3be7dd0] c041126c ksys_write+0xdc/0x130
[c3be7e20] c000b9d0 system_call+0x5c/0x68
--- Exception: c01 (System Call) at 7fffa345e420
SP (70b08ab0) is in userspace
Signed-off-by: Balamuruhan S
---
arch/powerpc/xmon/xmon.c | 22 ++
1 file chan
On Fri, 2020-03-20 at 16:18 +1100, Jordan Niethe wrote:
> In preparation for prefixed instructions where all instructions are no
> longer words, use an accessor for getting a word instruction as a u32
> from the instruction data type.
>
> Signed-off-by: Jordan Niethe
> ---
> v4: New to series
>
On Fri, 2020-03-20 at 16:18 +1100, Jordan Niethe wrote:
> This adds emulation support for the following prefixed Fixed-Point
> Arithmetic instructions:
> * Prefixed Add Immediate (paddi)
>
> Signed-off-by: Jordan Niethe
Reviewed-by: Balamuruhan S
> ---
> v3: Since
Doubleword (pstxsd)
> * Prefixed Store VSX Scalar Single-Precision (pstxssp)
> * Prefixed Store VSX Vector [0|1] (pstxv, pstxv0, pstxv1)
>
> Signed-off-by: Jordan Niethe
LGTM,
Reviewed-by: Balamuruhan S
> ---
> v2: - Combine all load/store patches
> - Fix the name of Type
On Mon, 2020-03-23 at 18:00 +1000, Nicholas Piggin wrote:
> Jordan Niethe's on March 20, 2020 3:18 pm:
> > Prefixed instructions will mean there are instructions of different
> > length. As a result dereferencing a pointer to an instruction will not
> > necessarily give the desired result.
On Fri, 2020-03-20 at 16:17 +1100, Jordan Niethe wrote:
> In preparation for using a data type for instructions that can not be
> directly used with the '>>' operator use a function for getting the op
> code of an instruction.
we need to adopt this in sstep.c and vecemu.c
-- Bala
>
>
On Fri, 2020-03-20 at 16:17 +1100, Jordan Niethe wrote:
> Currently unsigned ints are used to represent instructions on powerpc.
> This has worked well as instructions have always been 4 byte words.
> However, a future ISA version will introduce some changes to
> instructions that mean this scheme
On Fri, 2020-03-20 at 16:17 +1100, Jordan Niethe wrote:
> To execute an instruction out of line after a breakpoint, the NIP is
> set
> to the address of struct bpt::instr. Here a copy of the instruction
> that
> was replaced with a breakpoint is kept, along with a trap so normal
> flow
> can be
On Fri, 2020-03-20 at 16:17 +1100, Jordan Niethe wrote:
> To execute an instruction out of line after a breakpoint, the NIP is
> set
> to the address of struct bpt::instr. Here a copy of the instruction
> that
> was replaced with a breakpoint is kept, along with a trap so normal
> flow
> can be
use PPC_KVM_LD and PPC_KVM_STD to fix gcc warnings on redefinition as
we consolidate all ppc instruction encoding in ppc-opcode.h
Signed-off-by: Balamuruhan S
---
arch/powerpc/include/asm/kvm_asm.h| 8
arch/powerpc/kvm/booke_interrupts.S | 8
arch/powerpc/kvm
Few ppc instructions are encoded in test_emulate_step.c, consolidate them to
ppc-opcode.h, fix redefintion errors in bpf_jit caused due to this
consolidation.
Reuse the macros from ppc-opcode.h
Signed-off-by: Balamuruhan S
---
arch/powerpc/include/asm/ppc-opcode.h | 34 ++
arch/powerpc
Avoid redefining macros to encode ppc instructions instead reuse it from
ppc-opcode.h, Makefile changes are necessary to compile memcmp_64.S with
__ASSEMBLY__ defined from selftests.
Signed-off-by: Balamuruhan S
---
.../selftests/powerpc/stringloops/Makefile| 15 ++--
.../powerpc
Introduce PPC_ENCODE* macros to have all the bare encoding of ppc
instructions and use it wrapped with stringify_in_c() for raw
encoding in ppc-opcode.h.
Signed-off-by: Balamuruhan S
---
arch/powerpc/include/asm/ppc-opcode.h | 330 +-
1 file changed, 220 insertions
ile format elf64-powerpcle
---
> vmlinux_rfc: file format elf64-powerpcle
I would request for your review and suggestions to make it better.
Balamuruhan S (4):
powerpc ppc-opcode: consolidate PowerPC instruction macros
powerpc selftest: reuse ppc-opcode macros to avoid redundancy
power
)
Reviewed-by: Sandipan Das
Signed-off-by: Balamuruhan S
---
arch/powerpc/lib/test_emulate_step.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
---
changes in v2:
-
* squash the commits as per Christophe's review comment
diff --git a/arch/powerpc/lib/test_emulate
On Wed, 2020-03-11 at 08:01 +0100, Christophe Leroy wrote:
>
> Le 11/03/2020 à 07:14, Balamuruhan S a écrit :
> > ld instruction should have 14 bit immediate field (DS) concatenated
> > with
> > 0b00 on the right, encode it accordingly.
> >
> > Fixes: 4ceae137
ld instruction should have 14 bit immediate field (DS) concatenated with
0b00 on the right, encode it accordingly.
Fixes: 4ceae137bdab ("powerpc: emulate_step() tests for load/store
instructions")
Reviewed-by: Sandipan Das
Signed-off-by: Balamuruhan S
---
arch/powerpc/lib/test_emul
introduce macro `IMM_DS()` to encode DS form instructions with
14 bit immediate field.
Signed-off-by: Balamuruhan S
---
arch/powerpc/lib/test_emulate_step.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/lib/test_emulate_step.c
b/arch/powerpc/lib
dividend to cover -|divisor| < r <= 0 if
the dividend is negative for divde[.]
* normal case with proper dividend and divisor for both
divde[.] and divdeu[.]
Reviewed-by: Sandipan Das
Signed-off-by: Balamuruhan S
---
arch/powerpc/lib/test_emulate_step.c
This patch adds emulation support for divde, divdeu instructions,
* Divide Doubleword Extended (divde[.])
* Divide Doubleword Extended Unsigned (divdeu[.])
Reviewed-by: Sandipan Das
Signed-off-by: Balamuruhan S
---
arch/powerpc/lib/sstep.c | 13 -
1 file changed, 12
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