[PATCH v2 08/11] powerpc/8xx: Handle CR out of exception PROLOG/EPILOG

In order to be able to reduce scope during which CR is saved, we take CR saving/restoring out of exception PROLOG and EPILOG Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- v2: no change arch/powerpc/kernel/head_8xx.S | 10 +++--- 1 file changed, 7 insertions(+), 3 deletions

[PATCH v2 00/11] powerpc8xx: Further optimisation of TLB handling

11 - powerpc/8xx: Add support for TASK_SIZE greater than 0x8000 All changes have been successfully tested on MPC885 Signed-off-by: Christophe Leroy christophe.le...@c-s.fr Tested-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/include/asm/pgtable-ppc32.h | 4 + arch/powerpc

[PATCH v2 09/11] powerpc/8xx: dont save CR in SCRATCH registers

is restored Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- v2: removed the CPU6 specific handling of CR which was saving (only) 1 cycle but was making the code more difficult to maintain due to too many different cases arch/powerpc/kernel/head_8xx.S | 29

[PATCH v2 11/11] powerpc/8xx: Add support for TASK_SIZE greater than 0x80000000

By default, TASK_SIZE is set to 0x8000 for PPC_8xx, which is most likely sufficient for most cases. However, kernel configuration allows to set TASK_SIZE to another value, so the 8xx shall handle it. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- v2: no change arch/powerpc

[PATCH v2 06/11] powerpc/8xx: Remove duplicated code in set_context()

Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- v2: no change arch/powerpc/kernel/head_8xx.S | 10 -- 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index a485ad7..a1571b3 100644 --- a/arch

[PATCH v2 04/11] powerpc/8xx: Take benefit of aligned PGDIR

L1 base address is now aligned so we can insert L1 index into r11 directly and then preserve r10 Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- v2: no change arch/powerpc/kernel/head_8xx.S | 34 +++--- 1 file changed, 15 insertions(+), 19 deletions

[PATCH v2 02/11] powerpc/8xx: remove tests on PGDIR entry validity

, remove all those tests and let the 8xx handle it. This reduce the number of cycle when the entries are valid which is the case most of the time, and doesn't significantly increase the time for handling invalid entries. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- v2: no change arch

[PATCH v2] powerpc/8xx: reduce pressure on TLB due to context switches

. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- v1-v2: removed blank line and added comment arch/powerpc/mm/mmu_context_nohash.c | 43 +++- 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/mm/mmu_context_nohash.c b/arch/powerpc/mm

[PATCH v4 1/2] powerpc32: adds handling of _PAGE_RO

Some powerpc like the 8xx don't have a RW bit in PTE bits but a RO (Read Only) bit. This patch implements the handling of a _PAGE_RO flag to be used in place of _PAGE_RW Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- v2 is a complete rework of v1 v3: - cleared PTE can remain 0

[PATCH v4 2/2] powerpc/8xx: use _PAGE_RO instead of _PAGE_RW

On powerpc 8xx, in TLB entries, 0x400 bit is set to 1 for read-only pages and is set to 0 for RW pages. So we should use _PAGE_RO instead of _PAGE_RW Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- v2 is a complete rework compared to v1 v3: fixing pte_update() and comments v4

[PATCH] powerpc/8xx: reduce pressure on TLB due to context switches

. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/mm/mmu_context_nohash.c | 44 +++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/mm/mmu_context_nohash.c b/arch/powerpc/mm/mmu_context_nohash.c index 928ebe7..c648677

Re: embedding dtb file into kernel

Le 13/02/2015 18:41, K Richard Pixley a écrit : I'm having trouble figuring out how to embed a dtb file into my kernel. I'm thinking that there should be a standard, architecture independent facility for this akin to initramfs, yes? Could someone please either point me to the standard

[PATCH] powerpc/8xx: reduce pressure on TLB due to context switches

. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/mm/mmu_context_nohash.c | 44 +++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/mm/mmu_context_nohash.c b/arch/powerpc/mm/mmu_context_nohash.c index 928ebe7..c648677

[PATCH v2 04/17] crypto: talitos - Refactor the sg in/out chain allocation

This patch refactors the handling of the input and output data that is quite similar in several functions Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- drivers/crypto/talitos.c | 163 --- 1 file changed, 85 insertions(+), 78 deletions

[PATCH v2 06/17] crypto: talitos - Add talitos2.c to isolate SEC2 specific functions

scatterlists We move to talitos.h some of the helpers that are used by both talitos.c and talitos2.c Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- drivers/crypto/Kconfig| 4 + drivers/crypto/Makefile | 1 + drivers/crypto/talitos.c | 666

[PATCH v2 10/17] crypto: talitos - Move interrupt related macros in talitos2.h

Move interrupt related macros in talitos2.h as they are specific to SEC2 Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- drivers/crypto/talitos.c | 58 - drivers/crypto/talitos2.h | 60 +++ 2

[PATCH v2 14/17] crypto: talitos - Add a helper function to clear j_extent field

j_extent field is specific to SEC2 so we add a helper function to clear it so that SEC1 can redefine that function as nop Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- drivers/crypto/talitos.c | 2 +- drivers/crypto/talitos2.h | 5 + 2 files changed, 6 insertions(+), 1

[PATCH v2 17/17] crypto: talitos - Update DT bindings with SEC1

This patch updates the documentation by including SEC1 into SEC2/3 doc Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- Documentation/devicetree/bindings/crypto/fsl-sec2.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings

[PATCH v2 01/17] crypto: talitos - base address for Execution Units and macro for ISR masks

SEC1 and SEC2 have different EU base addresses, so define base addresses as #define SEC1 and SEC2 have different bit masks for ISR registers, so create a macro to define them Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- drivers/crypto/talitos.h | 85

[PATCH v2 02/17] crypto: talitos - Externalise specific SEC2 reset actions

During init and reset, some actions are different between SEC1 and SEC2 This patch isolates them in small helper functions that we will be able to redefine for SEC1 Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- drivers/crypto/talitos.c | 20 1 file changed, 16

[PATCH v2 08/17] crypto: talitos - Deport SEC2 error handling

SEC2 and SEC1 error handling will be different because so many bits are different. So we move error handling into talitos2.c Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- drivers/crypto/talitos.c | 103 +- drivers/crypto/talitos.h

[PATCH v2 12/17] crypto: talitos - Define compatible in talitos2.h instead of talitos.c

Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- drivers/crypto/talitos.c | 4 +--- drivers/crypto/talitos2.h | 2 ++ 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c index 8b627d0..0262e75 100644 --- a/drivers/crypto

[PATCH v2 11/17] crypto: talitos - Move hash chain handling into talitos2.h

Move hash chain handling into talitos2.h as only SEC2 has sg chaining capatibility Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- drivers/crypto/talitos.c | 34 -- drivers/crypto/talitos2.h | 34 ++ 2 files changed

[PATCH v2 13/17] crypto: talitos - move sg_count() helper into talitos.h

move sg_count() helper into talitos.h as it will be needed by SEC1 specific functions Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- drivers/crypto/talitos.c | 20 drivers/crypto/talitos.h | 21 + 2 files changed, 21 insertions(+), 20

[PATCH v2 03/17] crypto: talitos - Use zero entry to init descriptors ptrs to zero

Do use zero_entry value to init the descriptors ptrs to zero instead of writing 0 in each field Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- drivers/crypto/talitos.c | 8 ++-- 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/crypto/talitos.c b/drivers

[PATCH v2 05/17] crypto: talitos - isolate scatter/gather handling for ahash

SEC1 doesn't support scatter/gather, therefore this part of the code will have to be implemented differently for SEC1, so we isolate it in a small helper function Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- drivers/crypto/talitos.c | 29 +++-- 1 file

[PATCH v2 09/17] crypto: talitos - Move reset/init helpers into talitos2.h

Move reset/init helpers init talitos2.h as they are specific to SEC2 Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- drivers/crypto/talitos.c | 19 --- drivers/crypto/talitos2.h | 20 2 files changed, 20 insertions(+), 19 deletions(-) diff

[PATCH v2 16/17] crypto: talitos - SEC1 bugs on 0 data hash

SEC1 bugs on 0 data hash, so we submit an already padded block representing 0 data Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- drivers/crypto/talitos.c | 3 +++ drivers/crypto/talitos1.c | 21 + drivers/crypto/talitos1.h | 4 drivers/crypto/talitos2

[PATCH v2 0/17] crypto: talitos - Add support for SEC1

/17] crypto: talitos - Implementation of SEC1 [16/17] crypto: talitos - SEC1 bugs on 0 data hash [17/17] crypto: talitos - Update DT bindings with SEC1 Signed-off-by: Christophe Leroy christophe.le...@c-s.fr .../devicetree/bindings/crypto/fsl-sec2.txt| 5 +- drivers/crypto/Kconfig

[PATCH v2 07/17] crypto: talitos - Split talitos.h into 2 parts

In order to be able to manage differences between SEC1 and SEC2, we split talitos.h into two parts. talitos2.h will contain all parts that are specific to SEC2 and different on SEC1 Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- drivers/crypto/talitos.h | 163

[PATCH v2 15/17] crypto: talitos - Implementation of SEC1

are in addition * SEC1 doesn't support scatter/gather * SEC1 has a different descriptor structure We add a helper function for clearing the desc field in the descriptor as that field needs to be cleared on SEC1 and doesn't exist on SEC2. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr

[PATCH 5/8] tty: cpm_uart: replace CONFIG_8xx by CONFIG_CPM1

to handle compat with arch=ppc It looks like not many places still have that old CONFIG_8xx used, so it is likely to be a good time to get rid of it completely ? Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- drivers/tty/serial/Kconfig | 2 +- drivers/tty/serial/cpm_uart

[PATCH 1/8] powerpc: replace CONFIG_8xx by CONFIG_PPC_8xx

to handle compat with arch=ppc It looks like not many places still have that old CONFIG_8xx used, so it is likely to be a good time to get rid of it completely ? Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/Kconfig | 10 +- arch/powerpc

[PATCH 2/8] um: replace CONFIG_8xx by CONFIG_PPC_8xx

to handle compat with arch=ppc It looks like not many places still have that old CONFIG_8xx used, so it is likely to be a good time to get rid of it completely ? Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/um/sys-ppc/misc.S | 12 ++-- 1 file changed, 6 insertions(+), 6

[PATCH 3/8] video: replace CONFIG_8xx by CONFIG_PPC_8xx

to handle compat with arch=ppc It looks like not many places still have that old CONFIG_8xx used, so it is likely to be a good time to get rid of it completely ? Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- drivers/video/console/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1

[PATCH 7/8] isdn: replace CONFIG_8xx by CONFIG_PPC_8xx

to handle compat with arch=ppc It looks like not many places still have that old CONFIG_8xx used, so it is likely to be a good time to get rid of it completely ? Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- drivers/isdn/hardware/mISDN/Kconfig | 4 ++-- 1 file changed, 2 insertions

[PATCH 6/8] mtd: replace CONFIG_8xx by CONFIG_PPC_8xx

to handle compat with arch=ppc It looks like not many places still have that old CONFIG_8xx used, so it is likely to be a good time to get rid of it completely ? Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- drivers/mtd/maps/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion

[PATCH 4/8] net: freescale: replace CONFIG_8xx by CONFIG_PPC_8xx

to handle compat with arch=ppc It looks like not many places still have that old CONFIG_8xx used, so it is likely to be a good time to get rid of it completely ? Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- drivers/net/ethernet/freescale/fs_enet/mac-fec.c | 2 +- drivers/net/ethernet

[PATCH 0/8] powerpc/8xx: Getting rid of CONFIG_8xx

of CONFIG_8xx All but the last one are independant and can be applied in any order. Only the 8th one requires the first 7 patches to be applied. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/Kconfig | 10 +- arch/powerpc/Makefile

[PATCH 8/8] powerpc: get rid of CONFIG_8xx

to handle compat with arch=ppc It looks like not many places still have that old CONFIG_8xx used, so it is likely to be a good time to get rid of it completely ? Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/platforms/Kconfig.cputype | 5 - 1 file changed, 5 deletions

[PATCH 03/17] crypto: talitos - Use zero entry to init descriptors ptrs to zero

Do use zero_entry value to init the descriptors ptrs to zero instead of writing 0 in each field Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- drivers/crypto/talitos.c | 8 ++-- 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/crypto/talitos.c b/drivers

[PATCH 04/17] crypto: talitos - Refactor the sg in/out chain allocation

This patch refactors the handling of the input and output data that is quite similar in several functions Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- drivers/crypto/talitos.c | 163 --- 1 file changed, 85 insertions(+), 78 deletions

[PATCH 07/17] crypto: talitos - Split talitos.h into 2 parts

In order to be able to manage differences between SEC1 and SEC2, we split talitos.h into two parts. talitos2.h will contain all parts that are specific to SEC2 and different on SEC1 Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- drivers/crypto/talitos.h | 163

[PATCH 12/17] crypto: talitos - Define compatible in talitos2.h instead of talitos.c

Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- drivers/crypto/talitos.c | 4 +--- drivers/crypto/talitos2.h | 2 ++ 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c index 6c1f6f1..9f75ec9 100644 --- a/drivers/crypto

[PATCH 09/17] crypto: talitos - Move reset/init helpers into talitos2.h

Move reset/init helpers init talitos2.h as they are specific to SEC2 Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- drivers/crypto/talitos.c | 19 --- drivers/crypto/talitos2.h | 20 2 files changed, 20 insertions(+), 19 deletions(-) diff

[PATCH 01/17] crypto: talitos - base address for Execution Units and macro for ISR masks

SEC1 and SEC2 have different EU base addresses, so define base addresses as #define SEC1 and SEC2 have different bit masks for ISR registers, so create a macro to define them Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- drivers/crypto/talitos.h | 85

[PATCH 02/17] crypto: talitos - Externalise specific SEC2 reset actions

During init and reset, some actions are different between SEC1 and SEC2 This patch isolates them in small helper functions that we will be able to redefine for SEC1 Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- drivers/crypto/talitos.c | 20 1 file changed, 16

[PATCH 06/17] crypto: talitos - Add talitos2.c to isolate SEC2 specific functions

scatterlists We move to talitos.h some of the helpers that are used by both talitos.c and talitos2.c Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- drivers/crypto/Kconfig| 4 + drivers/crypto/Makefile | 1 + drivers/crypto/talitos.c | 666

[PATCH 05/17] crypto: talitos - isolate scatter/gather handling for ahash

SEC1 doesn't support scatter/gather, therefore this part of the code will have to be implemented differently for SEC1, so we isolate it in a small helper function Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- drivers/crypto/talitos.c | 29 +++-- 1 file

[PATCH 13/17] crypto: talitos - move sg_count() helper into talitos.h

move sg_count() helper into talitos.h as it will be needed by SEC1 specific functions Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- drivers/crypto/talitos.c | 20 drivers/crypto/talitos.h | 21 + 2 files changed, 21 insertions(+), 20

[PATCH 14/17] crypto: talitos - Add a helper function to clear j_extent field

j_extent field is specific to SEC2 so we add a helper function to clear it so that SEC1 can redefine that function as nop Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- drivers/crypto/talitos.c | 2 +- drivers/crypto/talitos2.h | 5 + 2 files changed, 6 insertions(+), 1

[PATCH 11/17] crypto: talitos - Move hash chain handling into talitos2.h

Move hash chain handling into talitos2.h as only SEC2 has sg chaining capatibility Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- drivers/crypto/talitos.c | 34 -- drivers/crypto/talitos2.h | 34 ++ 2 files changed

[PATCH 10/17] crypto: talitos - Move interrupt related macros in talitos2.h

Move interrupt related macros in talitos2.h as they are specific to SEC2 Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- drivers/crypto/talitos.c | 58 - drivers/crypto/talitos2.h | 60 +++ 2

[PATCH 17/17] crypto: talitos - Update DT bindings with SEC1

This patch updates the documentation by including SEC1 into SEC2/3 doc Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- Documentation/devicetree/bindings/crypto/fsl-sec2.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings

[PATCH 0/17] crypto: talitos - Add support for SEC1

[17/17] crypto: talitos - Update DT bindings with SEC1 Signed-off-by: Christophe Leroy christophe.le...@c-s.fr .../devicetree/bindings/crypto/fsl-sec2.txt| 5 +- drivers/crypto/Kconfig | 8 + drivers/crypto/Makefile| 2

[PATCH 15/17] crypto: talitos - Implementation of SEC1

are in addition * SEC1 doesn't support scatter/gather * SEC1 has a different descriptor structure We add a helper function for clearing the desc field in the descriptor as that field needs to be cleared on SEC1 and doesn't exist on SEC2. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr

[PATCH 16/17] crypto: talitos - SEC1 bugs on 0 data hash

SEC1 bugs on 0 data hash, so we submit an already padded block representing 0 data Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- drivers/crypto/talitos.c | 3 +++ drivers/crypto/talitos1.c | 21 + drivers/crypto/talitos1.h | 4 drivers/crypto/talitos2

[PATCH 08/17] crypto: talitos - Deport SEC2 error handling

SEC2 and SEC1 error handling will be different because so many bits are different. So we move error handling into talitos2.c Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- drivers/crypto/talitos.c | 103 +- drivers/crypto/talitos.h

[PATCH] spi: fsl-spi: use of_iomap() to map parameter ram on CPM1

UART: when the CPM is of type CPM1, we simply do an of_iomap() of the area provided via the device tree. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- drivers/spi/spi-fsl-cpm.c | 32 +++- 1 file changed, 15 insertions(+), 17 deletions(-) diff --git

[PATCH v3] spi: fsl-spi: use devm_ioremap_resource() to map parameter ram on CPM1

the same principle as for the CPM UART: when the CPM is of type CPM1, we simply do an devm_ioremap_resource() of the area provided via the device tree. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- v2: Use devm_ioremap_resource() instead of_iomap() v3: Replaced of_iomap

[PATCH v2] spi: fsl-spi: use of_iomap() to map parameter ram on CPM1

UART: when the CPM is of type CPM1, we simply do an of_iomap() of the area provided via the device tree. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- v2: Use devm_ioremap_resource() instead of_iomap() drivers/spi/spi-fsl-cpm.c | 35 ++- 1 file

[PATCH] spi: fsl-spi: fix devm_ioremap_resource() error case

devm_ioremap_resource() doesn't return NULL but an ERR_PTR on error. Reported-by: Jonas Gorsky j...@openwrt.org Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- drivers/spi/spi-fsl-cpm.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-fsl

[PATCH 01/11] powerpc/8xx: remove remaining unnecessary code in FixupDAR

Since commit 33fb845a6f01 (powerpc/8xx: Don't use MD_TWC for walk), MD_EPN and MD_TWC are not writen anymore in FixupDAR so saving r3 has become useless. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S | 6 -- 1 file changed, 6 deletions(-) diff

[PATCH 04/11] powerpc/8xx: Take benefit of aligned PGDIR

L1 base address is now aligned so we can insert L1 index into r11 directly and then preserve r10 Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S | 34 +++--- 1 file changed, 15 insertions(+), 19 deletions(-) diff --git

[PATCH 07/11] powerpc/8xx: macro for handling CPU15 errata

Having a macro will help keep clear code. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S | 18 -- 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index

[PATCH 06/11] powerpc/8xx: Remove duplicated code in set_context()

Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S | 10 -- 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index aa45225..b227902e 100644 --- a/arch/powerpc/kernel

[PATCH 05/11] powerpc/8xx: Optimise access to swapper_pg_dir

All accessed to PGD entries are done via 0(r11). By using lower part of swapper_pg_dir as load index to r11, we can remove the ori instruction. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S | 22 ++ 1 file changed, 10 insertions

[PATCH 10/11] powerpc/8xx: Use SPRG2 instead of DAR for saving r3

We now have SPRG2 available as in it not used anymore for saving CR, so we don't need to crash DAR anymore for saving r3 for CPU6 ERRATA handling. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S | 9 - 1 file changed, 4 insertions(+), 5

[PATCH RESEND v5 1/5] powerpc/8xx: macro for handling CPU15 errata

Having a macro will help keep clear code. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S | 18 -- 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index

[PATCH RESEND v5 0/5] powerpc8xx: Further optimisation of TLB handling

This patchset provides a further optimisation of TLB handling in the 8xx. Changes are: - Not saving registers like CR when not needed - Adding support to any TASK_SIZE Only the last patch of the set is changed compared to v4 Resending with proper From: this time. Christophe Leroy (5): powerpc

[PATCH RESEND v5 4/5] powerpc/8xx: Use SPRG2 instead of DAR for saving r3

We now have SPRG2 available as in it not used anymore for saving CR, so we don't need to crash DAR anymore for saving r3 for CPU6 ERRATA handling. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S | 9 - 1 file changed, 4 insertions(+), 5

[PATCH RESEND v5 3/5] powerpc/8xx: dont save CR in SCRATCH registers

is restored Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S | 29 +++-- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 5a69c5e..150d03f 100644

[PATCH RESEND v5 5/5] powerpc/8xx: Add support for TASK_SIZE greater than 0x80000000

most of the time it is equal to 0xC000 Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S | 25 +++-- 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index

[PATCH 00/11] powerpc8xx: Further optimisation of TLB handling

11 - powerpc/8xx: Add support for TASK_SIZE greater than 0x8000 All changes have been successfully tested on MPC885 Signed-off-by: Christophe Leroy christophe.le...@c-s.fr Tested-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/include/asm/page.h | 8 +++ arch

[PATCH 03/11] powerpc32: Use kmem_cache memory for PGDIR

When pages are not 4K, PGDIR table is allocated with kmalloc(). In order to optimise TLB handlers, aligned memory is needed. kmalloc() doesn't provide aligned memory blocks, so lets use a kmem_cache pool instead. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/include

[PATCH 02/11] powerpc/8xx: remove tests on PGDIR entry validity

, remove all those tests and let the 8xx handle it. This reduce the number of cycle when the entries are valid which is the case most of the time, and doesn't significantly increase the time for handling invalid entries. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel

[PATCH 08/11] powerpc/8xx: Handle CR out of exception PROLOG/EPILOG

In order to be able to reduce scope during which CR is saved, we take CR saving/restoring out of exception PROLOG and EPILOG Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S | 10 +++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git

[PATCH 09/11] powerpc/8xx: dont save CR in SCRATCH registers

for saving CR - Otherwise, we use r10, then we reload SRR0/MD_EPN into r10 when CR is restored Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S | 53 +- 1 file changed, 37 insertions(+), 16 deletions(-) diff --git

[PATCH 11/11] powerpc/8xx: Add support for TASK_SIZE greater than 0x80000000

By default, TASK_SIZE is set to 0x8000 for PPC_8xx, which is most likely sufficient for most cases. However, kernel configuration allows to set TASK_SIZE to another value, so the 8xx shall handle it. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S

[PATCH RESEND v5 2/5] powerpc/8xx: Handle CR out of exception PROLOG/EPILOG

In order to be able to reduce scope during which CR is saved, we take CR saving/restoring out of exception PROLOG and EPILOG Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S | 10 +++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git

[PATCH 1/3] powerpc/8xx: mark _PAGE_SHARED all types of kernel pages

All kernel pages have to be marked as shared in order to not perform CASID verification. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/include/asm/pte-8xx.h | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/pte-8xx.h b

[PATCH 2/3] powerpc/8xx: Handle PAGE_USER via APG bits

according to page definition) This removes the special 8xx handling in pte_update() Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/include/asm/pgtable-ppc32.h | 19 --- arch/powerpc/include/asm/pte-8xx.h | 27 +-- arch

[PATCH 3/3] powerpc/8xx: Implementation of PAGE_EXEC

definition) GP3 (11) = User, exec = 00 (all accesses performed as supervisor) Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/include/asm/cputable.h | 2 +- arch/powerpc/include/asm/mmu-8xx.h | 26 ++ arch/powerpc/include/asm/pte-8xx.h | 3

[PATCH 0/3] powerpc/8xx: Implementation of execute protection

This patchset implements execute protection on the 8xx. It also simplifies the handling of PAGE_USER and PAGE_RO, and adds a small fix to the kernel pages definition. This patchset goes on to of my previous patchset named [v5] powerpc8xx: Further optimisation of TLB handling Christophe Leroy (3

Re: [v2,2/2] powerpc32: add support for csum_add()

Le 25/03/2015 02:30, Scott Wood a écrit : On Tue, Feb 03, 2015 at 12:39:27PM +0100, LEROY Christophe wrote: The C version of csum_add() as defined in include/net/checksum.h gives the following assembly: 0: 7c 04 1a 14 add r0,r4,r3 4: 7c 64 00 10 subfc

Re: powerpc32: rearrange instructions order in ip_fast_csum()

Le 25/03/2015 02:22, Scott Wood a écrit : On Tue, Feb 03, 2015 at 12:39:27PM +0100, LEROY Christophe wrote: Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/lib/checksum_32.S | 10 +++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/powerpc

Re: [PATCH v2 1/2] powerpc32: put csum_tcpudp_magic inline

Le 25/03/2015 03:10, Scott Wood a écrit : On Tue, 2015-02-03 at 12:39 +0100, Christophe Leroy wrote: csum_tcpudp_magic() is only a few instructions, and does not modifies any other register than the returned result. So it is not worth having it as a separate function and suffer function

Re: [PATCH 3/4] powerpc32: memset(0): use cacheable_memzero

Le 14/05/2015 02:55, Scott Wood a écrit : On Tue, 2015-05-12 at 15:32 +0200, Christophe Leroy wrote: cacheable_memzero uses dcbz instruction and is more efficient than memset(0) when the destination is in RAM This patch renames memset as generic_memset, and defines memset as a prolog

[PATCH v2 0/6] powerpc32: replace memcpy and memset by cacheable alternatives

This patchset implements use of cacheable versions of memset and memcpy since when the destination is not cacheable, memset_io and memcpy_toio are used. On MPC885, we observe a 7% rate increase on FTP transfer Christophe Leroy (6): powerpc: use memset_io() to clear CPM Muram Partially revert

[PATCH v2 2/6] Partially revert powerpc: Remove duplicate cacheable_memcpy/memzero functions

that we will overwrite. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/lib/copy_32.S | 127 + 1 file changed, 127 insertions(+) diff --git a/arch/powerpc/lib/copy_32.S b/arch/powerpc/lib/copy_32.S index 6813f80..55f19f9 100644

[PATCH v2 3/6] powerpc32: memset(0): use cacheable_memzero

() cacheable_memzero disappears as it is not referenced anywhere anymore Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/lib/copy_32.S | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/lib/copy_32.S b/arch/powerpc/lib/copy_32.S index 55f19f9

[PATCH v2 6/6] powerpc32: Few optimisations in memcpy

This patch adds a few optimisations in memcpy functions by using lbzu/stbu instead of lxb/stb and by re-ordering insn inside a loop to reduce latency due to loading Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/lib/copy_32.S | 10 +- 1 file changed, 5

[PATCH v2 1/6] powerpc: use memset_io() to clear CPM Muram

CPM muram is not cached, so use memset_io() instead of memset() Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/sysdev/cpm_common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/sysdev/cpm_common.c b/arch/powerpc/sysdev/cpm_common.c

[PATCH v2 4/6] powerpc32: Merge the new memset() with the old one

cacheable_memzero() which has become the new memset() and the old memset() are quite similar, so just merge them. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/lib/copy_32.S | 34 +++--- 1 file changed, 7 insertions(+), 27 deletions(-) diff

[PATCH v2 5/6] powerpc32: cacheable_memcpy becomes memcpy

approximatly 7% increase of the transfer rate on an FTP reception Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/lib/copy_32.S | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/powerpc/lib/copy_32.S b/arch/powerpc/lib/copy_32.S index 9262071

[PATCH 1/4] Partially revert powerpc: Remove duplicate cacheable_memcpy/memzero functions

that we will overwrite. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/lib/copy_32.S | 127 + 1 file changed, 127 insertions(+) diff --git a/arch/powerpc/lib/copy_32.S b/arch/powerpc/lib/copy_32.S index 6813f80..55f19f9 100644

[PATCH 0/4] powerpc32: use cacheable alternatives of memcpy and memset

This patchset implements use of cacheable versions of memset and memcpy when the len is greater than the cacheline size and the destination is in RAM. On MPC885, we observe a 7% rate increase on FTP transfer Christophe Leroy (4): Partially revert powerpc: Remove duplicate cacheable_memcpy

[PATCH 4/4] powerpc32: memcpy: use cacheable_memcpy

, we get approximatly 7% increase of the transfer rate on an FTP reception Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/lib/copy_32.S | 23 --- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/arch/powerpc/lib/copy_32.S b/arch/powerpc

[PATCH 2/4] powerpc32: swap r4 and r5 in cacheable_memzero

We swap r4 and r5, this avoids having to move the len contained in r4 into r5 Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/lib/copy_32.S | 29 ++--- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/arch/powerpc/lib/copy_32.S b

[PATCH 3/4] powerpc32: memset(0): use cacheable_memzero

back to generic_memcpy() Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/lib/copy_32.S | 15 ++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/lib/copy_32.S b/arch/powerpc/lib/copy_32.S index cbca76c..d8a9a86 100644 --- a/arch/powerpc

<    1   2   3   4   5   6   7   8   9   10   >