. If both are compiled in, feature
field is checked.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 3 +++
drivers/crypto/talitos.h | 17 +
2 files changed, 20 insertions(+)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index
talitos descriptor is slightly different for SEC1 and SEC2+, so
lets the helper function that fills the descriptor take into account
the type of SEC.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 105 ++-
1 file
SEC1 descriptor is a bit different to SEC2+ descriptor.
talitos_submit() will have to copy hdr field into hdr1 field and
send the descriptor starting at hdr1 up to next_desc.
For SEC2, it remains unchanged and next_desc is just ignored.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
SEC 1.0, 1.2 and 2.x+ have different EU base addresses, so we need to
define pointers for each EU in the driver private data structure.
The proper address is set by the probe function depending on the
SEC type, in order to provide access to the proper address.
Signed-off-by: Christophe Leroy
on SEC1.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 227 +++
drivers/crypto/talitos.h | 39 +---
2 files changed, 199 insertions(+), 67 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto
also adapt the max buffer size which is only 32k on SEC1 while it
is 64k on SEC2+
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 138 ++-
drivers/crypto/talitos.h | 3 +-
2 files changed, 103 insertions(+), 38
SEC1 bugs on 0 data hash, so we submit an already padded block representing 0
data
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto
We add a specific compatible for SEC1, to handle the differences
between SEC1 and SEC2+
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index
This patch updates the documentation by including SEC1 into SEC2/3 doc
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
Documentation/devicetree/bindings/crypto/fsl-sec2.txt | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings
time, talitos
driver shall support both SEC1 and SEC2+ at the same time.
Based on cryptodev-2.6 tree
Christophe Leroy (17):
crypto: talitos - Use zero entry to init descriptors ptrs to zero
crypto: talitos - Refactor the sg in/out chain allocation
crypto: talitos - talitos_ptr renamed ptr
Do use zero_entry value to init the descriptors ptrs to zero instead of
writing 0 in each field
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers
This patch refactors the handling of the input and output data that is quite
similar in several functions
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 159 ---
1 file changed, 81 insertions(+), 78 deletions
Do use zero_entry value to init the descriptors ptrs to zero instead of
writing 0 in each field
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers
Linux CodyingStyle recommends to use short variables for local
variables. ptr is just good enough for those 3 lines functions.
It helps keep single lines shorter than 80 characters.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 20 ++--
1
This patch enhances the talitos_desc struct with fields for SEC1.
SEC1 has only one header field, and has a 'next_desc' field in
addition.
This mixed descriptor will continue to fit SEC2, and for SEC1
we will recopy hdr value into hdr1 value in talitos_submit()
Signed-off-by: Christophe Leroy
time, talitos
driver shall support both SEC1 and SEC2+ at the same time.
Based on cryptodev-2.6 tree
Christophe Leroy (17):
crypto: talitos - Use zero entry to init descriptors ptrs to zero
crypto: talitos - Refactor the sg in/out chain allocation
crypto: talitos - talitos_ptr renamed ptr
This patch refactors the handling of the input and output data that is quite
similar in several functions
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 159 ---
1 file changed, 81 insertions(+), 78 deletions
This patch adds a helper function for reads and writes of the len
param of the talitos descriptor. This will help implement
SEC1 later.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 24 +---
1 file changed, 17 insertions(+), 7
map_single_talitos_ptr() is always called with extent == 0, so lets remove this
unused parameter
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 21 ++---
1 file changed, 10 insertions(+), 11 deletions(-)
diff --git a/drivers/crypto
j_extent field is specific to SEC2 so we add a helper function to clear it
so that SEC1 can redefine that function as nop
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers
This patch adds a CONFIG option to select SEC1, SEC2+ or both.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/Kconfig | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 800bf41..8a76a01 100644
Linux CodyingStyle recommends to use short variables for local
variables. ptr is just good enough for those 3 lines functions.
It helps keep single lines shorter than 80 characters.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 20 ++--
1
j_extent field is specific to SEC2 so we add a helper function to clear it
so that SEC1 can redefine that function as nop
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers
map_single_talitos_ptr() is always called with extent == 0, so lets remove this
unused parameter
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 21 ++---
1 file changed, 10 insertions(+), 11 deletions(-)
diff --git a/drivers/crypto
This patch adds a helper function for reads and writes of the len
param of the talitos descriptor. This will help implement
SEC1 later.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 24 +---
1 file changed, 17 insertions(+), 7
This patch enhances the talitos_desc struct with fields for SEC1.
SEC1 has only one header field, and has a 'next_desc' field in
addition.
This mixed descriptor will continue to fit SEC2, and for SEC1
we will recopy hdr value into hdr1 value in talitos_submit()
Signed-off-by: Christophe Leroy
This patch adds a CONFIG option to select SEC1, SEC2+ or both.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/Kconfig | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 800bf41..8a76a01 100644
. If both are compiled in, feature
field is checked.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 3 +++
drivers/crypto/talitos.h | 17 +
2 files changed, 20 insertions(+)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index
talitos descriptor is slightly different for SEC1 and SEC2+, so
lets the helper function that fills the descriptor take into account
the type of SEC.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 105 ++-
1 file
SEC1 descriptor is a bit different to SEC2+ descriptor.
talitos_submit() will have to copy hdr field into hdr1 field and
send the descriptor starting at hdr1 up to next_desc.
For SEC2, it remains unchanged and next_desc is just ignored.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
SEC 1.0, 1.2 and 2.x+ have different EU base addresses, so we need to
define pointers for each EU in the driver private data structure.
The proper address is set by the probe function depending on the
SEC type, in order to provide access to the proper address.
Signed-off-by: Christophe Leroy
on SEC1.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 227 +++
drivers/crypto/talitos.h | 39 +---
2 files changed, 199 insertions(+), 67 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto
also adapt the max buffer size which is only 32k on SEC1 while it
is 64k on SEC2+
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 138 ++-
drivers/crypto/talitos.h | 3 +-
2 files changed, 103 insertions(+), 38
SEC1 bugs on 0 data hash, so we submit an already padded block representing 0
data
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto
We add a specific compatible for SEC1, to handle the differences
between SEC1 and SEC2+
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index
This patch updates the documentation by including SEC1 into SEC2/3 doc
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
Documentation/devicetree/bindings/crypto/fsl-sec2.txt | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings
mmu_virtual_psize shall be set to MMU_PAGE_16K when 16k pages have
been selected
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/include/asm/mmu-8xx.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/powerpc/include/asm/mmu-8xx.h
b/arch/powerpc/include
I've got a MPC8323 RDB evaluation platform from freescale
kernel 4.0 doesn't boot
kernel 3.16 doesn't boot
kernel 3.15 boots ok
I disected the issue down to your commit of/fdt: Convert FDT functions
to use libfdt (e6a6928c3ea1d0195ed75a091e345696b916c09b)
Do you have an idea of what the issue
Le 06/06/2015 17:32, Rob Herring a écrit :
On Sat, Jun 6, 2015 at 6:20 AM, christophe leroy
christophe.le...@c-s.fr wrote:
I've got a MPC8323 RDB evaluation platform from freescale
kernel 4.0 doesn't boot
kernel 3.16 doesn't boot
kernel 3.15 boots ok
I disected the issue down to your commit
r7 and r8 which contains pointers to error feedback are used, so we stack them.
On a TCP benchmark using socklib on the loopback interface on which checksum
offload and scatter/gather have been deactivated, we get about 20% performance
increase.
Signed-off-by: Christophe Leroy christophe.le...@c
() which also exists on powerpc32
This patch renames arch/powerpc/lib/checksum_wrappers_64.c to
arch/powerpc/lib/checksum_wrappers.c and
makes it non-conditional to CONFIG_WORD_SIZE
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/include/asm/checksum.h | 9 ---
arch
.
Christophe Leroy (2):
powerpc32: checksum_wrappers_64 becomes checksum_wrappers
powerpc32: rewrite of csum_partial_copy_generic based of copy_tofrom_user
arch/powerpc/include/asm/checksum.h | 9 -
arch/powerpc/lib/Makefile | 3 +-
arch/powerpc/lib/checksum_32.S
r7 and r8 which contains pointers to error feedback are used, so we stack them.
On a TCP benchmark using socklib on the loopback interface on which checksum
offload and scatter/gather have been deactivated, we get about 20% performance
increase.
Signed-off-by: Christophe Leroy christophe.le...@c
() which also exists on powerpc32
This patch renames arch/powerpc/lib/checksum_wrappers_64.c to
arch/powerpc/lib/checksum_wrappers.c and
makes it non-conditional to CONFIG_WORD_SIZE
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
v2: no change, patch reformatted with format-patch -M -C
arch
.
v2 is just a new issue with format-patch -M -C, other changes.
Christophe Leroy (2):
powerpc32: checksum_wrappers_64 becomes checksum_wrappers
powerpc32: rewrite of csum_partial_copy_generic based of copy_tofrom_user
arch/powerpc/include/asm/checksum.h| 9 -
arch/powerpc
.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/lib/checksum_32.S | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/lib/checksum_32.S b/arch/powerpc/lib/checksum_32.S
index 9c48ee0..6fbadfe 100644
--- a/arch/powerpc/lib
The purpose of this patchset is to optimise csum_partial() on powerpc32.
In the first part, we remove some unneccessary instructions
In the second part, we partially unloop the main loop
Christophe Leroy (2):
Optimise a few instructions in csum_partial()
Optimise csum_partial() loop
arch
on the value of bit 31 and bit 30 of r4 instead of anding r4 with 3
then proceding on comparisons and substractions.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/lib/checksum_32.S | 37 +
1 file changed, 17 insertions(+), 20 deletions
On the 8xx, load latency is 2 cycles and taking branches also takes
2 cycles. So let's unroll the loop.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/lib/checksum_32.S | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/lib
.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/include/asm/checksum.h | 21 -
arch/powerpc/lib/checksum_32.S | 16
arch/powerpc/lib/checksum_64.S | 21 -
3 files changed, 12 insertions(+), 46 deletions(-)
diff
This patchset provides a few optimisations related to IP checksum functions.
Christophe Leroy (2):
powerpc: put csum_tcpudp_magic inline
powerpc: add support for csum_add()
arch/powerpc/include/asm/checksum.h | 37 -
arch/powerpc/lib/checksum_32.S
:clrldi r3,r3,32
0xc0001b10 +24:blr
include/net/checksum.h also offers the possibility to define an arch specific
function.
This patch provides a specific csum_add() inline function.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/include/asm/checksum.h | 16
: 9 Local timer interrupts for others
SPU: 0 Spurious interrupts
PMI: 0 Performance monitoring interrupts
MCE: 0 Machine check exceptions
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/sysdev/mpc8xx_pic.c | 2 +-
1 file changed, 1
rh_alloc() returns (unsigned long)-ERRxx on error, which may
result in overwriting memory outside the MURAM AREA.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/sysdev/cpm_common.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/sysdev
I'm trying to move the 3 microcode patches included in
arch/powerpc/sysdev/micropatch.c into the firmware directory in order to
use request_firmware() and then be able to add additional micropatch
that I need to relocate SMC2 on my MPC885.
I have written the below patch in order to test the
.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
v3: Only use lwzu for the last load as lwzu has undocumented
additional latency
arch/powerpc/lib/checksum_32.S | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/lib/checksum_32.S b
The purpose of this patchset is to optimise csum_partial() on powerpc32.
In the first part, we remove some unneccessary instructions
In the second part, we partially unloop the main loop
Christophe Leroy (2):
Optimise a few instructions in csum_partial()
Optimise csum_partial() loop
arch
on the value of bit 31 and bit 30 of r4 instead of anding r4 with 3
then proceding on comparisons and substractions.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/lib/checksum_32.S | 37 +
1 file changed, 17 insertions(+), 20 deletions
On the 8xx, load latency is 2 cycles and taking branches also takes
2 cycles. So let's unroll the loop.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
v2: Only use lwzu for the last load as lwzu has undocumented
additional latency
arch/powerpc/lib/checksum_32.S | 16
-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/net/ethernet/freescale/fs_enet/mac-fec.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/freescale/fs_enet/mac-fec.c
b/drivers/net/ethernet/freescale/fs_enet/mac-fec.c
index b34214e..016743e 100644
We are not interested in interrupts for partially transmitted frames,
we have to clear BD_ENET_TX_INTR explicitly otherwise it may remain
from a previously used descriptor.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/net/ethernet/freescale/fs_enet/fs_enet-main.c | 3
Now the noltlbs kernel parameter is also applicable to PPC8xx
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
Documentation/kernel-parameters.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/kernel-parameters.txt
b/Documentation/kernel
iounmap() cannot vunmap() area mapped by TLBCAMs either
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/mm/pgtable_32.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/mm/pgtable_32.c b/arch/powerpc/mm/pgtable_32.c
index 7692d1b
IMMR is now mapped at 0xff00 by page tables so it is not
anymore necessary to PIN TLBs
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/Kconfig.debug | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug
index
for that.
This patch adds a second 8M page to the initial mapping in order to
have 16M mapped regardless of CONFIG_PIN_TLB, like several other
32 bits PPC (40x, 601, ...)
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/kernel/head_8xx.S | 2 ++
arch/powerpc/mm/8xx_mmu.c | 4
clear_pages() is never used, and PPC32 is the only architecture
(still) having this function. Neither PPC64 nor any other
architecture has it.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/include/asm/page_32.h | 3 +--
arch/powerpc/kernel/misc_32.S | 7
ioremap_base is not initialised and is nowhere used so remove it
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/mm/mmu_decl.h | 1 -
arch/powerpc/mm/pgtable_32.c| 1 -
arch/powerpc/platforms/embedded6xx/mpc10x.h | 8
3 files
other miscellaneous improvements:
1/ Handling of CPU6 ERRATA directly in mtspr() C macro to reduce code
specific to PPC8xx
2/ Rewrite of a few non critical ASM functions in C
3/ Removal of some unused items
See related patches for details
Christophe Leroy (20):
powerpc/8xx: Save r3 all the time
increased to 313s
and the overall time spent in DTLB miss handler is 6.3s, which
represents 1% of the overall time and 2.2% of non-idle time.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/kernel/head_8xx.S | 30 ++-
arch/powerpc/mm/8xx_mmu.c | 83
Now we have a 8xx specific .c file for that so put it in there
as other powerpc variants do
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/mm/8xx_mmu.c | 17 +
arch/powerpc/mm/init_32.c | 19 ---
2 files changed, 17 insertions(+), 19
show IMMR area in startup memory layout
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/mm/mem.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index e1fe333..f987321 100644
--- a/arch/powerpc/mm/mem.c
+++ b/arch
MPC8xx has an ERRATA on the use of mtspr() for some registers
This patch includes the ERRATA handling directly into mtspr() macro
so that mtspr() users don't need to bother about that errata
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/include/asm/reg.h | 2
On PPC8xx, flushing instruction cache is performed by writing
in register SPRN_IC_CST. This registers suffers CPU6 ERRATA.
The patch rewrites the fonction in C so that CPU6 ERRATA will
be handled transparently
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/kernel
aligned) the same way.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/Kconfig.debug | 1 -
arch/powerpc/kernel/head_8xx.S | 10 +-
2 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug
index
hence yet another 10% reduction.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/include/asm/pgtable-ppc32.h | 5 +++
arch/powerpc/kernel/head_8xx.S | 57 ++--
arch/powerpc/mm/8xx_mmu.c| 50
Move 8xx SPRN defines into reg_8xx.h and add some missing ones
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/include/asm/mmu-8xx.h | 26 +-
arch/powerpc/include/asm/reg_8xx.h | 24
2 files changed, 37 insertions(+), 13
CPU6 ERRATA is now handled directly in mtspr(), so we can use the
standard set_dec() fonction in all cases.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/include/asm/time.h | 6 +-
arch/powerpc/kernel/head_8xx.S | 18 --
2 files changed, 1
There is no real need to have set_context() in assembly.
Now that we have mtspr() handling CPU6 ERRATA directly, we
can rewrite set_context() in C language for easier maintenance.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/kernel/head_8xx.S | 44
Commit 771168494719 ([POWERPC] Remove unused machine call outs)
removed the call to setup_io_mappings(), so remove the associated
progress line message
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/mm/init_32.c | 4
1 file changed, 4 deletions(-)
diff --git
We are spending between 40 and 160 cycles with a mean of 65 cycles in
the TLB handling routines (measured with mftbl) so make it more
simple althought it adds one instruction.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/kernel/head_8xx.S | 13 -
1 file
x_mapped_by_bats() and x_mapped_by_tlbcam() serve the same kind of
purpose, so lets group them into a single function.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/mm/pgtable_32.c | 33 ++---
1 file changed, 26 insertions(+), 7 deletions
We are spending between 40 and 160 cycles with a mean of 65 cycles
in the TLB handling routines (measured with mftbl) so make it more
simple althought it adds one instruction
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/kernel/head_8xx.S | 15 ---
1 file
but calling them
Signed-off-by: Christophe Leroy <christophe.le...@c-s.fr>
---
v2: new
v3: no change
arch/powerpc/include/asm/cacheflush.h | 52 ++--
arch/powerpc/kernel/misc_32.S | 65 ---
arch/powerpc/kernel/ppc_ksyms.c | 2
-by: Christophe Leroy <christophe.le...@c-s.fr>
---
v2: no change
v3: no change
arch/powerpc/include/asm/page_32.h | 17 ++---
arch/powerpc/kernel/misc_32.S | 16
arch/powerpc/kernel/ppc_ksyms_32.c | 1 -
3 files changed, 14 insertions(+), 20 deletions(-)
diff
This patch adds inline functions to use dcbz, dcbi, dcbf, dcbst
from C functions
Signed-off-by: Christophe Leroy <christophe.le...@c-s.fr>
---
v2: new
v3: no change
arch/powerpc/include/asm/cache.h | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/powerpc/inclu
Now we have a 8xx specific .c file for that so put it in there
as other powerpc variants do
Signed-off-by: Christophe Leroy <christophe.le...@c-s.fr>
---
v2: no change
v3: no change
arch/powerpc/mm/8xx_mmu.c | 17 +
arch/powerpc/mm/init_32.c | 19 ---
2
There is no real need to have set_context() in assembly.
Now that we have mtspr() handling CPU6 ERRATA directly, we
can rewrite set_context() in C language for easier maintenance.
Signed-off-by: Christophe Leroy <christophe.le...@c-s.fr>
---
v2: no change
v3: no change
arch/powerpc/
ioremap_base is not initialised and is nowhere used so remove it
Signed-off-by: Christophe Leroy <christophe.le...@c-s.fr>
---
v2: no change
v3: fix comment as well
arch/powerpc/include/asm/pgtable-ppc32.h| 2 +-
arch/powerpc/mm/mmu_decl.h | 1 -
arch/powe
is
selected.
Signed-off-by: Christophe Leroy <christophe.le...@c-s.fr>
---
v2: no change
v3: Automatic detection of available/needed memory instead of allocating 16M
for all.
arch/powerpc/kernel/head_8xx.S | 56 +++---
arch/powerpc/mm/8xx_mmu.c
This simplification helps the compiler. We now have only one test
instead of two, so it reduces the number of branches.
Signed-off-by: Christophe Leroy <christophe.le...@c-s.fr>
---
v2: new
v3: no change
arch/powerpc/mm/dma-noncoherent.c | 2 +-
1 file changed, 1 insertion(+), 1 de
CPU6 ERRATA is now handled directly in mtspr(), so we can use the
standard set_dec() fonction in all cases.
Signed-off-by: Christophe Leroy <christophe.le...@c-s.fr>
---
v2: no change
v3: no change
arch/powerpc/include/asm/time.h | 6 +-
arch/powerpc/kernel/head_8xx.S
Now the noltlbs kernel parameter is also applicable to PPC8xx
Signed-off-by: Christophe Leroy <christophe.le...@c-s.fr>
---
v2: no change
v3: no change
Documentation/kernel-parameters.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/kernel-parameters.
IMMR is now mapped by page tables so it is not
anymore necessary to PIN TLBs
Signed-off-by: Christophe Leroy <christophe.le...@c-s.fr>
---
v2: no change
v3: no change
arch/powerpc/Kconfig.debug | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/powerpc/Kconfig.debug b/arch/p
On PPC8xx, flushing instruction cache is performed by writing
in register SPRN_IC_CST. This registers suffers CPU6 ERRATA.
The patch rewrites the fonction in C so that CPU6 ERRATA will
be handled transparently
Signed-off-by: Christophe Leroy <christophe.le...@c-s.fr>
---
v2: no cha
Inlining of _dcache_range() functions has shown that the compiler
does the same thing a bit better with one insn less
Signed-off-by: Christophe Leroy <christophe.le...@c-s.fr>
---
v2: new
v3: no change
arch/powerpc/kernel/misc_32.S | 5 ++---
1 file changed, 2 insertions(+), 3 del
-by: Christophe Leroy <christophe.le...@c-s.fr>
---
v2: no change
v3: no change
arch/powerpc/kernel/head_8xx.S | 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 78c1eba..1557926 100644
---
Commit 771168494719 ("[POWERPC] Remove unused machine call outs")
removed the call to setup_io_mappings(), so remove the associated
progress line message
Signed-off-by: Christophe Leroy <christophe.le...@c-s.fr>
---
v2: no change
v3: no change
arch/powerpc/mm/init_32.c | 4
for mapping IMMR
Christophe Leroy (23):
powerpc/8xx: Save r3 all the time in DTLB miss handler
powerpc/8xx: Map linear kernel RAM with 8M pages
powerpc: Update documentation for noltlbs kernel parameter
powerpc/8xx: move setup_initial_memory_limit() into 8xx_mmu.c
powerpc32: Fix
IMMR is at 0xfa20 which
overlaps with VM ioremap area
This patch fixes the virtual address for remapping IMMR with the fixmap
regardless of the value of IMMR.
The size of IMMR area is 256kbytes (CPM at offset 0, security engine
at offset 128k) so a 512k page is enough
Signed-off-by: Christophe L
The fixmap related functions try to map kernel pages that are
already mapped through Large TLBs. pte_offset_kernel() has to
return NULL for LTLBs, otherwise the caller will try to access
level 2 table which doesn't exist
Signed-off-by: Christophe Leroy <christophe.le...@c-s.fr>
---
v3: New
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