).
The number of allocates pages depends on the max number of processes.
Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
---
drivers/misc/cxl/native.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/misc/cxl/native.c b/drivers/misc/cxl/native.c
index b
On 06/10/2015 08:19, Michael Ellerman wrote:
On Fri, 2015-10-02 at 16:01 +0200, Christophe Lombard wrote:
This moves the initialisation of the num_procs to before the SPA
allocation.
Why? What does it fix? I can't tell from the diff or the change log.
cheers
This moves the initialisation of the num_procs to before the SPA
allocation.
Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
---
drivers/misc/cxl/native.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/misc/cxl/native.c b/drivers/misc/cxl/na
@mpe since this patch introduces a new user API I'd appreciate it if you
could give this a bit extra scrutiny.
Excerpts from Frederic Barrat's message of 2016-02-07 00:29:01 +1100:
+Starts and controls flashing a new FPGA image. Partial
+reconfiguration is not supported (yet), so the
Excerpts from christophe lombard's message of 2016-02-16 07:53:54 +1100:
+void cxl_guest_reload_module(struct cxl *adapter)
+{
+struct platform_device *pdev;
+int afu;
+
+for (afu = 0; afu < adapter->slices; afu++)
+cxl_guest_remove_afu(adapter->afu[afu]);
Should we possibly
need to enter an error
recovery path.
Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
---
change from V1:
* Improved comments.
* Use a delayed queue work instead of our own kthread.
---
drivers/misc/cxl/cxl.h | 4 +++-
drivers/misc/cxl/guest.
of this patch is to interact with the external driver
(where the AFU is shown) even if no action is required. A kernel thread
is needed to check every x seconds the current state of the AFU to see
if we need to enter an error recovery path.
Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.
On 19/04/2016 04:40, Andrew Donnellan wrote:
On 18/04/16 23:05, Christophe Lombard wrote:
In the POWERVM environement, the PHYP CoherentAccel component manages
environment
the state of the Coherant Accelerator Processor Interface adapter and
Coherent
virtualizes CAPI resources, handles
-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
---
drivers/misc/cxl/pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
index 80a87ab..853925b 100644
--- a/drivers/misc/cxl/pci.c
+++ b/drivers/misc/cxl/pci.c
@@ -1323,6 +1323,7 @@ stat
.
Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
---
drivers/misc/cxl/native.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/misc/cxl/native.c b/drivers/misc/cxl/native.c
index 09505f4..8a3ce99 100644
--- a/drivers/misc/cxl/native.c
+++ b/drivers/mi
Point out the specific Coherent Accelerator Interface Architecture,
level 1, registers.
Code and functions specific to PSL8 (CAIA1) must be framed.
Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
---
drivers/misc/cxl/context.c | 28 +++-
drivers/misc/cxl
will be released when the context is detached.
The reference (use count) on the struct mm is not kept to avoid a
circular dependency if the process mmaps its cxl mmio and forget to
unmap before exiting.
Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
---
drivers/misc/cxl/api.c
The service layer API (in cxl.h) lists some low-level functions whose
implementation is different on PSL8, PSL9 and XSL. Each
environment implements its own functions, and the common code uses
them through function pointers, defined in cxl_service_layer_ops.
Signed-off-by: Christophe Lombard
If a valid mm_struct is found the memory context id is used for each
transaction associated with the process handle. The PSL uses the
context ID to find the corresponding process element.
Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
---
drivers/misc/cxl/context.c
will also be used for psl9.
Patches 4 restructure existing code, to easily add the psl
implementation.
Patch 5 and 6 rename and isolate implementation-specific code.
Patch 7 introduces the core of the PSL9-specific code.
Tested on Simulation environment.
Christophe Lombard (7):
cxl: Read vsec
Rename a few functions, changing the '_psl' suffix to '_psl8', to make
clear that the implementation is psl8 specific.
Those functions will have an equivalent implementation for the psl9 in
a later patch.
Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
---
drivers/misc/cxl
ative_register_serr_irq().
- ASB_Notify messages and Non-Blocking queues not supported
on DD1.
- Change the allocation of the apc machines.
Changelog[v2]
- Rebase to latest upstream.
- Integrate comments from Andrew Donnellan and Frederic Barrat.
Christophe Lombard (7):
cxl: Rea
If a valid mm_struct is found the memory context id is used for each
transaction associated with the process handle. The PSL uses the
context ID to find the corresponding process element.
Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
---
drivers/misc/cxl/context.c
will be released when the context is detached.
A reference on mm_users is not kept to avoid a circular dependency if
the process mmaps its cxl mmio and forget to unmap before exiting.
Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
---
drivers/misc/cxl/api.c | 17 +--
driver
Rename a few functions, changing the '_psl' suffix to '_psl8', to make
clear that the implementation is psl8 specific.
Those functions will have an equivalent implementation for the psl9 in
a later patch.
Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
---
drivers/misc/cxl
Identification Register (CXL_PSL_PID_TID_An)
is only used when attaching a dedicated process for PSL8 only. This
register goes away in CAIA2.
Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
---
drivers/misc/cxl/cxl.h| 13 +++--
drivers/misc/cxl/hcalls.
-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
---
drivers/misc/cxl/pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
index 91f6459..e82a207 100644
--- a/drivers/misc/cxl/pci.c
+++ b/drivers/misc/cxl/pci.c
@@ -1332,6 +1332,7 @@ stat
Point out the specific Coherent Accelerator Interface Architecture,
level 1, registers.
Code and functions specific to PSL8 (CAIA1) must be framed.
Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
---
drivers/misc/cxl/context.c | 28 +++-
drivers/misc/cxl
for the adapter and the afu.
- Traces.
Each environment implements its own functions, and the common code uses
them through function pointers, defined in cxl_service_layer_ops.
Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
---
drivers/misc/cxl/cxl.h
Le 30/03/2017 à 06:44, Andrew Donnellan a écrit :
On 29/03/17 02:14, Christophe Lombard wrote:
This series adds support for a cxl card which supports the Coherent
Accelerator Interface Architecture 2.0.
It requires IBM Power9 system and the Power Service Layer, version 9.
The PSL provides
Le 29/03/2017 à 02:21, Andrew Donnellan a écrit :
On 29/03/17 02:14, Christophe Lombard wrote:
The two fields pid and tid of the structure cxl_irq_info are only used
in the guest environment. To avoid confusion, it's not necessary
to fill the fields in the bare-metal environment. These two
Le 20/03/2017 à 17:26, Frederic Barrat a écrit :
Le 14/03/2017 à 12:08, Christophe Lombard a écrit :
Rename a few functions, changing the '_psl' suffix to '_psl8', to make
clear that the implementation is psl8 specific.
Those functions will have an equivalent implementation for the psl9
Le 21/03/2017 à 03:47, Andrew Donnellan a écrit :
On 14/03/17 22:08, Christophe Lombard wrote:
The first 3 patches are mostly cleanup and fixes, separating the
psl8-specific code from the code which will also be used for psl9.
Patches 4 restructure existing code, to easily add the psl
Le 03/04/2017 à 14:27, Frederic Barrat a écrit :
Le 28/03/2017 à 17:14, Christophe Lombard a écrit :
The two fields pid and tid of the structure cxl_irq_info are only used
in the guest environment. To avoid confusion, it's not necessary
to fill the fields in the bare-metal environment
Le 12/04/2017 à 04:11, Michael Ellerman a écrit :
Frederic Barrat <fbar...@linux.vnet.ibm.com> writes:
Le 07/04/2017 à 16:11, Christophe Lombard a écrit :
The new Coherent Accelerator Interface Architecture, level 2, for the
IBM POWER9 brings new content and features:
- POWER9 Service
nts from Andrew Donnellan and Frederic Barrat
Christophe Lombard (6):
cxl: Remove unused values in bare-metal environment.
cxl: Keep track of mm struct associated with a context
cxl: Update implementation service layer
cxl: Rename some psl8 specific functions
cxl: Isolate few psl8 speci
will be released when the context is detached.
The reference (use count) on the struct mm is not kept to avoid a
circular dependency if the process mmaps its cxl mmio and forget to
unmap before exiting.
Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
---
drivers/misc/cxl/api.c
for the adapter and the afu.
- Traces.
Each environment implements its own functions, and the common code uses
them through function pointers, defined in cxl_service_layer_ops.
Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
---
drivers/misc/cxl/cxl.h
.
Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
---
drivers/misc/cxl/native.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/misc/cxl/native.c b/drivers/misc/cxl/native.c
index 7ae7105..7257e8b 100644
--- a/drivers/misc/cxl/native.c
+++ b/drivers/mi
If a valid mm_struct is found the memory context id is used for each
transaction associated with the process handle. The PSL uses the
context ID to find the corresponding process element.
Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
---
drivers/misc/cxl/context.c
Rename a few functions, changing the '_psl' suffix to '_psl8', to make
clear that the implementation is psl8 specific.
Those functions will have an equivalent implementation for the psl9 in
a later patch.
Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
---
drivers/misc/cxl
Point out the specific Coherent Accelerator Interface Architecture,
level 1, registers.
Code and functions specific to PSL8 (CAIA1) must be framed.
Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
---
drivers/misc/cxl/context.c | 28 +++-
drivers/misc/cxl
Le 03/04/2017 à 14:39, Frederic Barrat a écrit :
Le 28/03/2017 à 17:14, Christophe Lombard a écrit :
The service layer API (in cxl.h) lists some low-level functions whose
implementation is different on PSL8, PSL9 and XSL:
- Init implementation for the adapter and the afu.
- Invalidate TLB/SLB
Le 03/04/2017 à 15:05, Frederic Barrat a écrit :
Le 28/03/2017 à 17:14, Christophe Lombard a écrit :
The new Coherent Accelerator Interface Architecture, level 2, for the
IBM POWER9 brings new content and features:
- POWER9 Service Layer
- Registers
- Radix mode
- Process element entry
Point out the specific Coherent Accelerator Interface Architecture,
level 1, registers.
Code and functions specific to PSL8 (CAIA1) must be framed.
Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
---
drivers/misc/cxl/context.c | 28 +++-
drivers/misc/cxl
Rename a few functions, changing the '_psl' suffix to '_psl8', to make
clear that the implementation is psl8 specific.
Those functions will have an equivalent implementation for the psl9 in
a later patch.
Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
---
drivers/misc/cxl
no longer useful.
Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
---
drivers/misc/cxl/api.c | 17 +--
drivers/misc/cxl/context.c | 21 +++--
drivers/misc/cxl/cxl.h | 10 --
drivers/misc/cxl/fault.c | 76 --
d
-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
---
drivers/misc/cxl/pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
index b27ea98..1f4c351 100644
--- a/drivers/misc/cxl/pci.c
+++ b/drivers/misc/cxl/pci.c
@@ -1332,6 +1332,7 @@ stat
ion of the apc machines.
Changelog[v2]
- Rebase to latest upstream.
- Integrate comments from Andrew Donnellan and Frederic Barrat.
Christophe Lombard (7):
cxl: Read vsec perst load image
cxl: Remove unused values in bare-metal environment.
cxl: Keep track of mm struct associated with a context
cxl
If a valid mm_struct is found the memory context id is used for each
transaction associated with the process handle. The PSL uses the
context ID to find the corresponding process element.
Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
---
Documentation/powerpc/cxl.txt
Process and Thread Identification Register
(CXL_PSL_PID_TID_An) is only used when attaching a dedicated process
for PSL8 only. This register goes away in CAIA2.
Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
---
drivers/misc/cxl/cxl.h| 20
drivers/mi
for the adapter and the afu.
- Traces.
Each environment implements its own functions, and the common code uses
them through function pointers, defined in cxl_service_layer_ops.
Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
---
drivers/misc/cxl/cxl.h
Le 07/08/2017 à 05:08, Michael Ellerman a écrit :
Hi Christophe,
I'm not across any of the details of this so hopefully most of these
comments aren't too stupid :)
Christophe Lombard <clomb...@linux.vnet.ibm.com> writes:
The POWER9 core supports a new feature: ASB_Notify which re
From: Christophe Lombard <christophe_lomb...@fr.ibm.cm>
The function is_page_fault(), for POWER9, lists the Translation Checkout
Responses where the page fault will be handled by copro_handle_mm_fault().
This list is too restrictive and not necessary.
This patches removes this restr
Le 05/08/2017 à 06:28, Benjamin Herrenschmidt a écrit :
On Fri, 2017-08-04 at 16:56 +0200, Christophe Lombard wrote:
The POWER9 core supports a new feature: ASB_Notify which requires the
support of the Special Purpose Register: TIDR.
The ASB_Notify command, generated by the AFU, will attempt
feature
(CPU_FTR_TIDR) is added to POWER9 system.
Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/cputable.h | 4 +++-
arch/powerpc/include/asm/emulated_ops.h | 2 ++
arch/powerpc/include/asm/ppc-opcode.h | 4
arch/powerpc/inclu
A previous set of patches "cxl: Add support for Coherent Accelerator
Interface Architecture 2.0" has introduced a new support for the CAPI
cards. These patches have been tested on Simulation environment and
quite a bit of them have been tested on real hardware.
This patch brings new fixes after a
A previous set of patches "cxl: Add support for Coherent Accelerator
Interface Architecture 2.0" has introduced a new support for the CAPI
cards. These patches have been tested on Simulation environment and
quite a bit of them have been tested on real hardware.
This patch brings new fixes after a
Le 15/06/2017 à 14:36, Frederic Barrat a écrit :
Salut Christophe,
A few comments below, nothing major...
Le 14/06/2017 à 15:29, Christophe Lombard a écrit :
This patch exports a in-kernel 'library' API which can be called by
other drivers to help interacting with an IBM XSL on a POWER9
, it implements the CAIA architecture, but has a number
of differences, mostly in it's implementation dependent registers.
The XSL also uses a special DMA cxl mode, which uses a slightly
different init sequence for the CAPP and PHB.
Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.
, it implements the CAIA architecture, but has a number
of differences, mostly in it's implementation dependent registers.
The XSL also uses a special DMA cxl mode, which uses a slightly
different init sequence for the CAPP and PHB.
Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.
Le 22/06/2017 à 13:20, Michael Ellerman a écrit :
Christophe Lombard <clomb...@linux.vnet.ibm.com> writes:
This patch exports a in-kernel 'library' API which can be called by
other drivers to help interacting with an IBM XSL on a POWER9 system.
The XSL (Translation Service
Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
---
Changelog[v4]
- Rebase to latest upstream.
- Add new Signed-off
- Update cxl_handle_mm_fault() and cxl_handle_page_fault()
Changelog[v3]
- Rebase to latest upstream.
- cxl_handle_mm_fault() is now exported. Remove ke
From: Christophe Lombard <christophe_lomb...@fr.ibm.cm>
This patch exports a in-kernel 'library' API which can be called by
other drivers to help interacting with an IBM XSL on a POWER9 system.
The XSL (Translation Service Layer) is a stripped down version of the
PSL (Power Service Layer
Reviewed-by: christophe lombard <clomb...@linux.vnet.ibm.com>
Le 06/06/2017 à 11:43, Frederic Barrat a écrit :
Fix error path if we can't copy user structure on CXL_IOCTL_START_WORK
ioctl. We shouldn't unlock the context status mutex as it was not
locked (yet).
Signed-off-by: Frederic
Le 09/06/2017 à 18:12, Frederic Barrat a écrit :
Salut Christophe,
It looks pretty good, but checkpatch complains about 1 or 2 items
worth fixing.
2 small remarks below.
Le 09/06/2017 à 12:09, Christophe Lombard a écrit :
A previous set of patches "cxl: Add support for Coh
Le 14/06/2017 à 07:01, Michael Ellerman a écrit :
Christophe Lombard <clomb...@linux.vnet.ibm.com> writes:
A previous set of patches "cxl: Add support for Coherent Accelerator
Interface Architecture 2.0" has introduced a new support for the CAPI
cards.
Which commit is that
of NULL pointer in cxllib_handle_fault().
- Reverse parameters when copro_handle_mm_fault() is called.
Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
---
This applies on top of this patch:
http://patchwork.ozlabs.org/patch/775322/
---
arch/powerpc/include/asm/opal-api.h
Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
---
drivers/misc/cxl/context.c | 6 +++---
drivers/misc/cxl/cxl.h | 18 +-
drivers/misc/cxl/fault.c | 23 +++
drivers/misc/cxl/main.c| 17 +
drivers/misc/cx
is trying to access is never
sent to the kernel for resolution.
This patch updates the loop on the memory pages to be handled.
Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
Fixes: 3ced8d730063 ("cxl: Export library to support IBM XSL");
---
drivers/misc/c
rrat <fbar...@linux.vnet.ibm.com>
Signed-off-by: Vaibhav Jain <vaib...@linux.vnet.ibm.com>
---
Thanks
Acked-by: Christophe Lombard<clomb...@linux.vnet.ibm.com>
rrat <fbar...@linux.vnet.ibm.com>
Signed-off-by: Vaibhav Jain <vaib...@linux.vnet.ibm.com>
Thanks
Acked-by: Christophe Lombard<clomb...@linux.vnet.ibm.com>
com>
---
Changelog:
[v2] -> As created a different function to dump the FIR register for PSL9 (Fred)
---
Thanks
Acked-by: Christophe Lombard<clomb...@linux.vnet.ibm.com>
features will be added soon:
- phb reset when switching to capi mode.
- cxllib update to support new functions.
Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
Acked-by: Frederic Barrat <fbar...@linux.vnet.ibm.com>
---
Changelog[v3]
- Update commit message
Changelog[v
s good.
Acked-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
, and the address the
adapter is trying to access is never sent to the kernel for resolution.
This patch reworks start address of the loop with an address aligned on
the page size. In this context, the last page is not missed.
Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
Le 26/09/2017 à 03:44, Vaibhav Jain a écrit :
Hi Christophe,
A minor nitpick
Christophe Lombard <clomb...@linux.vnet.ibm.com> writes:
+ for (dar = (addr & ~(page_size - 1)); dar < (addr + size); dar +=
page_size) {
+ if (dar < vma->vm_start || dar >
, and the address the
adapter is trying to access is never sent to the kernel for resolution.
This patch reworks start address of the loop with an address aligned on
the page size. In this context, the last page is not missed.
Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
Le 28/08/2017 à 06:15, Vaibhav Jain a écrit :
Make sure to set the valid-bit in software-state field of the
populated PE. This was earlier missing for dedicated mode AFUs, hence
was causing a PSL freeze when the AFU was activated.
Acked-by: Christophe Lombard <clomb...@linux.vnet.ibm.
Le 24/08/2017 à 09:09, Vaibhav Jain a écrit :
Hi Christophe,
Christophe Lombard <clomb...@linux.vnet.ibm.com> writes:
+ /* For debugging with trace arrays */
+ /* Configure RX trace 0 segmented mode */
+ cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x82000
Le 24/08/2017 à 07:24, Andrew Donnellan a écrit :
On 24/08/17 00:58, Christophe Lombard wrote:
The PSL initialization sequence has been updated to DD2.
This patch adapts to the changes, retaining compatibility with DD1.
Tests performed on some of the new hardware.
If we're retaining
The PSL initialization sequence has been updated to DD2.
This patch adapts to the changes, retaining compatibility with DD1.
Tests performed on some of the new hardware.
Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
---
drivers/misc/cxl/cxl.h | 2 ++
drivers/misc/cxl
-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
---
Changelog[v2]
- Rebase to latest upstream.
- Update the function is_page_fault()
---
drivers/misc/cxl/cxl.h | 2 ++
drivers/misc/cxl/fault.c | 15 ++-
drivers/misc/cxl/pci.c
| 38 ++
3 files changed, 42 insertions(+), 32 deletions(-)
Thanks
Acked-by: Christophe Lombard<clomb...@linux.vnet.ibm.com>
Le 23/11/2017 à 21:41, Benjamin Herrenschmidt a écrit :
On Thu, 2017-11-23 at 12:05 +0100, Christophe Lombard wrote:
The POWER9 core supports a new feature: ASB_Notify which requires the
support of the Special Purpose Register: TIDR.
The ASB_Notify command, generated by the AFU, will attempt
) for the current thread which
will be used in the process element entry.
Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
---
arch/powerpc/kernel/process.c | 2 ++
drivers/misc/cxl/api.c| 9 +
drivers/misc/cxl/context.c| 21 +
drivers/mi
Le 23/11/2017 à 15:16, Vaibhav Jain a écrit :
Hi Christophe,
Few review comments:
Christophe Lombard <clomb...@linux.vnet.ibm.com> writes:
+
+int cxl_context_thread_tidr(struct cxl_context *ctx, int assign)
+{
+ int rc = 0;
+
+ /* Clear any TIDR value assigned to the c
Le 27/11/2017 à 05:03, Michael Ellerman a écrit :
christophe lombard <clomb...@linux.vnet.ibm.com> writes:
Le 24/11/2017 à 14:02, Benjamin Herrenschmidt a écrit :
On Fri, 2017-11-24 at 11:14 +0100, christophe lombard wrote:
To my knowledge, there is no property (or similar), som
good for me
Thanks
Reviewed-by: Christophe Lombard clomb...@linux.vnet.ibm.com
Le 24/11/2017 à 14:02, Benjamin Herrenschmidt a écrit :
On Fri, 2017-11-24 at 11:14 +0100, christophe lombard wrote:
To my knowledge, there is no property (or similar), somewhere, that
indicating that the TIDR is supported or not.
For the time being, if I am not wrong, the only check we have
) for the current thread which
will be used in the process element entry.
A next patch will handle a new kind of "compatible" property in the
device-tree (PHB DT node) indicating which version of CAPI and which
features are supported, instead of handling PVR values.
Signed-off-by: Christop
) for the current thread which
will be used in the process element entry.
A next patch will handle a new kind of "compatible" property in the
device-tree (PHB DT node) indicating which version of CAPI and which
features are supported, instead of handling PVR values.
Signed-off-by: Christop
Le 20/12/2017 à 07:31, Vaibhav Jain a écrit :
Hi Christophe,
Thanks for the changes to the patch. Few minor review comments:
Thanks for the review.
Christophe Lombard <clomb...@linux.vnet.ibm.com> writes:
@@ -362,3 +363,17 @@ void cxl_context_mm_count_put(struct cxl_contex
Le 20/12/2017 à 09:46, Vaibhav Jain a écrit :
Hi Chritophe,
christophe lombard <clomb...@linux.vnet.ibm.com> writes:
Le 20/12/2017 à 07:31, Vaibhav Jain a écrit :
EINVAL might be a better return value instead of ENODEV in this case.
This return code has been already discussed (wi
Add support for future Coherent Accelerator device with an
ID of 0x060e.
Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
---
drivers/misc/cxl/pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
index 19969ee..5f5b9aa
) for the current thread which
will be used in the process element entry.
A next patch will handle a new kind of "compatible" property in the
device-tree (PHB DT node) indicating which version of CAPI and which
features are supported.
Signed-off-by: Christophe Lombard <clomb...@linux
kiboot prerequisites:
https://patchwork.ozlabs.org/patch/829294/
[1/2] phb4: set PHB CMPM registers for tunneled operations
https://patchwork.ozlabs.org/patch/829293/
[2/2] phb4: set PBCQ Tunnel BAR for tunneled operations
Looks good for me.
Acked-by: Christophe Lombard
) for the current thread which
will be used in the process element entry.
A next patch will handle a new kind of "compatible" property in the
device-tree (PHB DT node) indicating which version of CAPI and which
features are supported, instead of handling PVR values.
Signed-off-by: Christop
Le 24/03/2018 à 09:14, Benjamin Herrenschmidt a écrit :
On Fri, 2018-03-23 at 17:17 +0100, christophe lombard wrote:
Le 23/03/2018 à 03:14, Benjamin Herrenschmidt a écrit :
On Thu, 2018-03-22 at 17:37 +0100, Christophe Lombard wrote:
The cxl driver cannot disable the interrupt at the device
viewed-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
) for the current thread which
will be used in the process element entry.
Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
Reviewed-by: Philippe Bergheaud <fe...@linux.vnet.ibm.com>
---
Changelog[v7]
- Rebased to latest upstream.
- Added boolean: "need to allocate a
) for the current thread which
will be used in the process element entry.
Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
Reviewed-by: Philippe Bergheaud <fe...@linux.vnet.ibm.com>
---
Changelog[v6]
- Rebased to latest upstream.
- Updated the ioctl interface.
- Removed
3 files changed, 47 insertions(+), 7 deletions(-)
Acked-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
| 106 +
6 files changed, 118 insertions(+), 9 deletions(-)
Acked-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
Le 11/02/2018 à 18:10, Vaibhav Jain a écrit :
Thanks for reviewing the patch Christophe,
christophe lombard <clomb...@linux.vnet.ibm.com> writes:
+bool cxl_enable_psltrace = true;
+module_param_named(enable_psltrace, cxl_enable_psltrace, bool, 0600);
+MODULE_PARM_DESC(enable_psltrace, &q
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