on the current read/lseek method as it handles cases like
the buffer wrapping and overflowing.
Signed-off-by: Jordan Niethe
---
v2: ensure only whole pages can be mapped
---
arch/powerpc/platforms/powernv/opal.c | 12
1 file changed, 12 insertions(+)
diff --git a/arch/powerpc/platforms
3S PR: Don't include SPAPR TCE code on
non-pseries platforms")
Signed-off-by: Jordan Niethe
---
arch/powerpc/kvm/book3s_hv.c| 2 ++
arch/powerpc/kvm/book3s_hv_rmhandlers.S | 10 ++
2 files changed, 12 insertions(+)
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/p
Currently the opal log is globally readable. It is kernel policy to limit
the visibility of physical addresses / kernel pointers to root.
Given this and the fact the opal log may contain this information it would
be better to limit the readability to root.
Signed-off-by: Jordan Niethe
---
arch
-by: Jordan Niethe
---
arch/powerpc/platforms/powernv/opal.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/powerpc/platforms/powernv/opal.c
b/arch/powerpc/platforms/powernv/opal.c
index 2b0eca104f86..3cfc683bb060 100644
--- a/arch/powerpc/platforms/powernv/opal.c
+++ b/arch
On Tue, 2019-08-13 at 20:03 +1000, Paul Mackerras wrote:
> Escalation interrupts are interrupts sent to the host by the XIVE
> hardware when it has an interrupt to deliver to a guest VCPU but that
> VCPU is not running anywhere in the system. Hence we disable the
> escalation interrupt for the
On Wed, 2019-08-14 at 17:47 +0200, Cédric Le Goater wrote:
> Currently, the xmon 'dx' command calls OPAL to dump the XIVE state in
> the OPAL logs and also outputs some of the fields of the internal
> XIVE
> structures in Linux. The OPAL calls can only be done on baremetal
> (PowerNV) and they
Commit 2874c5fd2842 ("treewide: Replace GPLv2 boilerplate/reference with
SPDX - rule 152") left an empty comment in machdep.h, as the boilerplate
was the only text in the comment. Remove the empty comment.
Signed-off-by: Jordan Niethe
---
arch/powerpc/include/asm/machdep.h | 3 -
On Wed, 2019-08-07 at 13:44 +1000, Sam Bobroff wrote:
> From: Oliver O'Halloran
>
> Preparation for removing pci_dn from the powernv EEH code. The only
> thing we really use pci_dn for is to get the bdfn of the device for
> config space accesses, so adding that information to eeh_dev reduces
>
ive-regs.h
Signed-off-by: Jordan Niethe
---
arch/powerpc/sysdev/xive/common.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/sysdev/xive/common.c
b/arch/powerpc/sysdev/xive/common.c
index 1cdb39575eae..083f657091d7 100644
--- a/arch/powerpc/sysdev/xive/common.c
-off-by: Jordan Niethe
---
arch/powerpc/include/asm/reg.h | 3 +++
arch/powerpc/kernel/cpu_setup_power.S | 6 ++
arch/powerpc/kernel/dt_cpu_ftrs.c | 3 ++-
arch/powerpc/kvm/book3s_hv.c| 11 +++
arch/powerpc/kvm/book3s_hv_nested.c | 6 +++---
arch
pu feature
CPU_FTR_P9_RADIX_PREFETCH_BUG to indicate if the workarounds are needed.
Signed-off-by: Jordan Niethe
---
v2: Use a cpu feature instead of open coding the PVR check
---
arch/powerpc/include/asm/cputable.h | 6 --
arch/powerpc/kernel/dt_cpu_ftrs.c| 13 -
arch/p
In entry_64.S there are places that open code saving and restoring the
non-volatile registers. There are already macros for doing this so use
them.
Signed-off-by: Jordan Niethe
---
arch/powerpc/kernel/entry_64.S | 18 ++
1 file changed, 6 insertions(+), 12 deletions(-)
diff
The hsrr and n parameters are never used by the KVMTEST macro so remove
them.
Signed-off-by: Jordan Niethe
---
arch/powerpc/kernel/exceptions-64s.S | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S
b/arch/powerpc/kernel
The INT_KVM_HANDLER macro for system_reset is missing a comma so add it
to be consistent.
Signed-off-by: Jordan Niethe
---
arch/powerpc/kernel/exceptions-64s.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S
b/arch/powerpc/kernel
On Fri, Dec 13, 2019 at 2:19 AM Daniel Axtens wrote:
>
> KASAN support on Book3S is a bit tricky to get right:
>
> - It would be good to support inline instrumentation so as to be able to
>catch stack issues that cannot be caught with outline mode.
>
> - Inline instrumentation requires a
pu feature
CPU_FTR_P9_RADIX_PREFETCH_BUG to indicate if the workarounds are needed.
Signed-off-by: Jordan Niethe
---
v2: Use a cpu feature instead of open coding the PVR check
v3: Put parentheses around CPU_FTRS_POWER9_DD2_0 value
---
arch/powerpc/include/asm/cputable.h | 7 +--
arch/powe
by 8.
Prefixed instructions are not permitted to cross 64-byte boundaries. If
they do the alignment interrupt is invoked with SRR1 BOUNDARY bit set.
If this occurs send a SIGBUS to the offending process if in user mode.
If in kernel mode call bad_page_fault().
Signed-off-by: Jordan Niethe
---
arch
suffix is loaded too. Then print these in the form:
prefix:suffix
Xmon uses the disassembly routines from GNU binutils. These currently do
not support prefixed instructions so we will not disassemble the
prefixed instructions yet.
Signed-off-by: Jordan Niethe
---
arch/powerpc/xmon/xmon.c | 50
Doubleword (pld)
* Prefixed Store Byte (pstb)
* Prefixed Store Halfword (psth)
* Prefixed Store Word (pstw)
* Prefixed Store Doubleword (pstd)
* Prefixed Load Quadword (plq)
* Prefixed Store Quadword (pstq)
Signed-off-by: Jordan Niethe
---
arch/powerpc/lib/sstep.c | 110
This adds emulation support for the following prefixed Fixed-Point
Arithmetic instructions:
* Prefixed Add Immediate (paddi)
Signed-off-by: Jordan Niethe
---
arch/powerpc/lib/sstep.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
n() within facility_unavailable_exception().
However, when caused by a prefixed instructions the SRR1 PREFIXED bit is
set. Prepare for dealing with emulated prefixed instructions by checking
for this bit.
Signed-off-by: Jordan Niethe
---
arch/powerpc/kernel/traps.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/ar
from SRR1_ISI_N_OR_G -> SRR1_ISI_N_G_OR_CIP to reflected this new
role.
Signed-off-by: Jordan Niethe
---
arch/powerpc/include/asm/reg.h | 2 +-
arch/powerpc/kvm/book3s_hv_nested.c | 2 +-
arch/powerpc/kvm/book3s_hv_rm_mmu.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --
Currently when getting an instruction to emulate in
hw_breakpoint_handler() we do not load the suffix of a prefixed
instruction. Ensure we load the suffix if the instruction we need to
emulate is a prefixed instruction.
Signed-off-by: Jordan Niethe
---
arch/powerpc/kernel/hw_breakpoint.c | 8
mce_find_instr_ea_and_pfn analyses an instruction to determine the
effective address that caused the machine check. Update this to load and
pass the suffix to analyse_instr for prefixed instructions.
Signed-off-by: Jordan Niethe
---
arch/powerpc/kernel/mce_power.c | 6 --
1 file changed, 4
are emulated or
analysed - this is just making it possible to do so.
Signed-off-by: Jordan Niethe
---
arch/powerpc/include/asm/ppc-opcode.h | 3 +++
arch/powerpc/include/asm/sstep.h | 8 +--
arch/powerpc/include/asm/uaccess.h| 30 +++
arch/powerpc/kernel/align.c
Store VSX Scalar Single-Precision (pstxssp)
* Prefixed Store VSX Vector [0|1] (pstxv, pstxv0, pstxv1)
Signed-off-by: Jordan Niethe
---
arch/powerpc/lib/sstep.c | 42
1 file changed, 42 insertions(+)
diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib
This adds emulation support for the follow prefixed floating-point
load/stores:
* Prefixed Load Floating-Point Single (plfs)
* Prefixed Load Floating-Point Double (plfd)
* Prefixed Store Floating-Point Single (pstfs)
* Prefixed Store Floating-Point Double (pstfd)
Signed-off-by: Jordan
.
No support for disassembling prefixed instructions.
Signed-off-by: Jordan Niethe
---
arch/powerpc/xmon/xmon.c | 82 ++--
1 file changed, 71 insertions(+), 11 deletions(-)
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index f47bd843dc52
.
Signed-off-by: Jordan Niethe
---
arch/powerpc/include/asm/kprobes.h | 5 +--
arch/powerpc/kernel/kprobes.c| 46 +---
arch/powerpc/kernel/optprobes.c | 31 +++
arch/powerpc/kernel/optprobes_head.S | 6
4 files changed, 62 insertions
Uprobes can execute instructions out of line. Increase the size of the
buffer used for this so that this works for prefixed instructions. Take
into account the length of prefixed instructions when fixing up the nip.
Signed-off-by: Jordan Niethe
---
arch/powerpc/include/asm/uprobes.h | 18
and stores. So this patch is probably not needed but
it might be preferable to use analyse_instr() rather than open coding
the test anyway.
Signed-off-by: Jordan Niethe
---
arch/powerpc/mm/fault.c | 39 +++
1 file changed, 11 insertions(+), 28 deletions(-)
diff
Add the bit definition for when the cause of an alignment exception is a
prefixed instruction that crosses a 64-byte boundary.
Signed-off-by: Jordan Niethe
---
arch/powerpc/include/asm/reg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc
emulation to support them. Then the places where prefixed instructions
might need to be emulated are updated.
A future series will add prefixed instruction support to guests running
in KVM.
Alistair Popple (1):
powerpc: Enable Prefixed Instructions
Jordan Niethe (17):
powerpc: Add BOUNDARY SRR1 bit
Add the bit definition for exceptions caused by prefixed instructions.
Signed-off-by: Jordan Niethe
---
arch/powerpc/include/asm/reg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 6f9fcc3d4c82..0a6d39fb4769 100644
From: Alistair Popple
Prefix instructions have their own FSCR bit which needs to enabled via
a CPU feature. The kernel will save the FSCR for problem state but it
needs to be enabled initially.
Signed-off-by: Alistair Popple
---
arch/powerpc/include/asm/reg.h| 3 +++
refetching for the hypervisor with that PID value.
In Power9 DD2.2 the cpu behaviour was modified to fix this. When
accessing Quadrant 0 in hypervisor mode with LPID != 0 prefetching will
not be performed. This means that we can get rid of the workarounds for
Power9 DD2.2 and later revisions.
Signed-off-
Fix by making sure r0 is 0 before storing it to kvmppc_vcore->in_guest.
Fixes: 13c7bb3c57dc ("powerpc/64s: Set reserved PCR bits")
Reported-by: Alexey Kardashevskiy
Signed-off-by: Jordan Niethe
---
arch/powerpc/kvm/book3s_hv_rmhandlers.S | 1 +
1 file changed, 1 insertion(+
On Wed, Dec 18, 2019 at 7:23 PM Daniel Axtens wrote:
>
> Jordan Niethe writes:
>
> > Add the bit definition for exceptions caused by prefixed instructions.
> >
> > Signed-off-by: Jordan Niethe
> > ---
> > arch/powerpc/include/asm/reg.h | 1 +
> >
On Wed, Dec 18, 2019 at 7:35 PM Daniel Axtens wrote:
>
> Jordan Niethe writes:
>
> > Currently all instructions are a single word long. A future ISA version
> > will include prefixed instructions which have a double word length. The
> > functions used for analysing
On Thu, Dec 19, 2019 at 1:15 AM Daniel Axtens wrote:
>
> Jordan Niethe writes:
>
> > Currently all instructions are a single word long. A future ISA version
> > will include prefixed instructions which have a double word length. The
> > functions used for analysing
On Tue, Feb 11, 2020 at 5:14 PM Christophe Leroy
wrote:
>
>
>
> Le 11/02/2020 à 06:33, Jordan Niethe a écrit :
> > Alignment interrupts can be caused by prefixed instructions accessing
> > memory. In the alignment handler the instruction that caused the
> > exc
On Tue, Feb 11, 2020 at 5:46 PM Christophe Leroy
wrote:
>
>
>
> Le 11/02/2020 à 06:33, Jordan Niethe a écrit :
> > A prefixed instruction is composed of a word prefix followed by a word
> > suffix. It does not make sense to be able to have a kprobe on the suffix
> >
On Tue, Feb 11, 2020 at 5:39 PM Christophe Leroy
wrote:
>
>
>
> Le 11/02/2020 à 06:33, Jordan Niethe a écrit :
> > Currently when xmon is dumping instructions it reads a word at a time
> > and then prints that instruction (either as a hex number or by
> > d
On Tue, Feb 11, 2020 at 5:32 PM Christophe Leroy
wrote:
>
>
>
> Le 11/02/2020 à 06:33, Jordan Niethe a écrit :
> > A prefixed instruction is composed of a word prefix and a word suffix.
> > It does not make sense to be able to have a breakpoint on the suffix of
> > a
On Tue, Feb 11, 2020 at 5:05 PM Christophe Leroy
wrote:
>
>
>
> Le 11/02/2020 à 06:33, Jordan Niethe a écrit :
> > This adds emulation support for the following prefixed integer
> > load/stores:
> >* Prefixed Load Byte and Zero (plbz)
> >* P
Uprobes can execute instructions out of line. Increase the size of the
buffer used for this so that this works for prefixed instructions. Take
into account the length of prefixed instructions when fixing up the nip.
Signed-off-by: Jordan Niethe
---
v2: - Fix typo
- Use macro for instruction
Currently when getting an instruction to emulate in
hw_breakpoint_handler() we do not load the suffix of a prefixed
instruction. Ensure we load the suffix if the instruction we need to
emulate is a prefixed instruction.
Signed-off-by: Jordan Niethe
---
v2: Rename sufx to suffix
---
arch/powerpc
are emulated or
analysed - this is just making it possible to do so.
Signed-off-by: Jordan Niethe
---
v2: - Move definition of __get_user_instr() and
__get_user_instr_inatomic() to "powerpc: Support prefixed instructions
in alignment handler."
- Use a macro for returning the length of an op
-Precision (plxssp)
* Prefixed Load VSX Vector [0|1] (plxv, plxv0, plxv1)
* Prefixed Store VSX Scalar Doubleword (pstxsd)
* Prefixed Store VSX Scalar Single-Precision (pstxssp)
* Prefixed Store VSX Vector [0|1] (pstxv, pstxv0, pstxv1)
Signed-off-by: Jordan Niethe
---
v2: - Combine all load/store
.
No support for disassembling prefixed instructions.
Signed-off-by: Jordan Niethe
---
v2: Rename sufx to suffix
---
arch/powerpc/xmon/xmon.c | 82 ++--
1 file changed, 71 insertions(+), 11 deletions(-)
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon
mce_find_instr_ea_and_pfn analyses an instruction to determine the
effective address that caused the machine check. Update this to load and
pass the suffix to analyse_instr for prefixed instructions.
Signed-off-by: Jordan Niethe
---
v2: - Rename sufx to suffix
---
arch/powerpc/kernel
n() within facility_unavailable_exception().
However, when caused by a prefixed instructions the SRR1 PREFIXED bit is
set. Prepare for dealing with emulated prefixed instructions by checking
for this bit.
Signed-off-by: Jordan Niethe
---
arch/powerpc/kernel/traps.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/ar
This adds emulation support for the following prefixed Fixed-Point
Arithmetic instructions:
* Prefixed Add Immediate (paddi)
Signed-off-by: Jordan Niethe
---
arch/powerpc/lib/sstep.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
by 8.
Prefixed instructions are not permitted to cross 64-byte boundaries. If
they do the alignment interrupt is invoked with SRR1 BOUNDARY bit set.
If this occurs send a SIGBUS to the offending process if in user mode.
If in kernel mode call bad_page_fault().
Signed-off-by: Jordan Niethe
---
v2
From: Alistair Popple
Prefix instructions have their own FSCR bit which needs to enabled via
a CPU feature. The kernel will save the FSCR for problem state but it
needs to be enabled initially.
Signed-off-by: Alistair Popple
---
arch/powerpc/include/asm/reg.h| 3 +++
werpc: Enable Prefixed Instructions
Jordan Niethe (12):
powerpc: Define new SRR1 bits for a future ISA version
powerpc sstep: Prepare to support prefixed instructions
powerpc sstep: Add support for prefixed load/stores
powerpc sstep: Add support for prefixed fixed-point arithmetic
pow
used to indicate that an ISI was due to the access being no-exec or
guarded. A future ISA version adds another purpose. It is also set if
there is an access in a cache-inhibited location for prefixed
instruction. Rename from SRR1_ISI_N_OR_G to SRR1_ISI_N_G_OR_CIP.
Signed-off-by: Jordan Niethe
.
Signed-off-by: Jordan Niethe
---
arch/powerpc/include/asm/kprobes.h | 5 +--
arch/powerpc/kernel/kprobes.c| 47 +---
arch/powerpc/kernel/optprobes.c | 32 ++-
arch/powerpc/kernel/optprobes_head.S | 6
4 files changed, 63 insertions
suffix is loaded too. Then print these in the form:
prefix:suffix
Xmon uses the disassembly routines from GNU binutils. These currently do
not support prefixed instructions so we will not disassemble the
prefixed instructions yet.
Signed-off-by: Jordan Niethe
---
v2: Rename sufx to suffix
(). Otherwise replace store_inst() with patch_instruction().
Signed-off-by: Jordan Niethe
---
arch/powerpc/xmon/xmon.c | 13 ++---
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index 897e512c6379..a673cf55641c 100644
--- a/arch
.
No support for disassembling prefixed instructions.
Signed-off-by: Jordan Niethe
---
v2: Rename sufx to suffix
v3: - Just directly use PPC_INST_NOP
- Typo: plac -> place
- Rename read_inst() to mread_inst(). Do not have it call mread().
---
arch/powerpc/xmon/xmon.c |
.
Signed-off-by: Jordan Niethe
---
v3: - Base on top of https://patchwork.ozlabs.org/patch/1232619/
- Change printing format to %x:%x
---
arch/powerpc/include/asm/kprobes.h | 5 ++--
arch/powerpc/kernel/kprobes.c| 43 +---
arch/powerpc/kernel/optprobes.c
suffix is loaded too. Then print these in the form:
prefix:suffix
Xmon uses the disassembly routines from GNU binutils. These currently do
not support prefixed instructions so we will not disassemble the
prefixed instructions yet.
Signed-off-by: Jordan Niethe
---
v2: Rename sufx to suffix
v3
used to indicate that an ISI was due to the access being no-exec or
guarded. A future ISA version adds another purpose. It is also set if
there is an access in a cache-inhibited location for prefixed
instruction. Rename from SRR1_ISI_N_OR_G to SRR1_ISI_N_G_OR_CIP.
Signed-off-by: Jordan Niethe
From: Alistair Popple
Prefix instructions have their own FSCR bit which needs to enabled via
a CPU feature. The kernel will save the FSCR for problem state but it
needs to be enabled initially.
Signed-off-by: Alistair Popple
---
arch/powerpc/include/asm/reg.h| 3 +++
Currently when getting an instruction to emulate in
hw_breakpoint_handler() we do not load the suffix of a prefixed
instruction. Ensure we load the suffix if the instruction we need to
emulate is a prefixed instruction.
Signed-off-by: Jordan Niethe
---
v2: Rename sufx to suffix
v3: Add __user
orted by Greg
Kurz did not work correctly.
Alistair Popple (1):
powerpc: Enable Prefixed Instructions
Jordan Niethe (13):
powerpc: Define new SRR1 bits for a future ISA version
powerpc sstep: Prepare to support prefixed instructions
powerpc sstep: Add support for prefixed load/stores
power
This adds emulation support for the following prefixed Fixed-Point
Arithmetic instructions:
* Prefixed Add Immediate (paddi)
Signed-off-by: Jordan Niethe
---
v3: Since we moved the prefixed loads/stores into the load/store switch
statement it no longer makes sense to have paddi in there, so
Uprobes can execute instructions out of line. Increase the size of the
buffer used for this so that this works for prefixed instructions. Take
into account the length of prefixed instructions when fixing up the nip.
Signed-off-by: Jordan Niethe
---
v2: - Fix typo
- Use macro for instruction
n() within facility_unavailable_exception().
However, when caused by a prefixed instructions the SRR1 PREFIXED bit is
set. Prepare for dealing with emulated prefixed instructions by checking
for this bit.
Signed-off-by: Jordan Niethe
---
arch/powerpc/kernel/traps.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/ar
by 8.
Prefixed instructions are not permitted to cross 64-byte boundaries. If
they do the alignment interrupt is invoked with SRR1 BOUNDARY bit set.
If this occurs send a SIGBUS to the offending process if in user mode.
If in kernel mode call bad_page_fault().
Signed-off-by: Jordan Niethe
---
v2
-Precision (plxssp)
* Prefixed Load VSX Vector [0|1] (plxv, plxv0, plxv1)
* Prefixed Store VSX Scalar Doubleword (pstxsd)
* Prefixed Store VSX Scalar Single-Precision (pstxssp)
* Prefixed Store VSX Vector [0|1] (pstxv, pstxv0, pstxv1)
Signed-off-by: Jordan Niethe
---
v2: - Combine all load/store
are emulated or
analysed - this is just making it possible to do so.
Signed-off-by: Jordan Niethe
---
v2: - Move definition of __get_user_instr() and
__get_user_instr_inatomic() to "powerpc: Support prefixed instructions
in alignment handler."
- Use a macro for returning the length of an op
mce_find_instr_ea_and_pfn analyses an instruction to determine the
effective address that caused the machine check. Update this to load and
pass the suffix to analyse_instr for prefixed instructions.
Signed-off-by: Jordan Niethe
---
v2: - Rename sufx to suffix
---
arch/powerpc/kernel
pare for dealing with emulated prefixed instructions by checking
> > for this bit.
> >
> > Signed-off-by: Jordan Niethe
>
> Oh you've got it here, I would just squash this together with the first
> patch.
Sure, I'll put them together. When you mentioned a couple more
On Fri, Feb 28, 2020 at 12:48 PM Nicholas Piggin wrote:
>
> Jordan Niethe's on February 27, 2020 10:58 am:
> > On Wed, Feb 26, 2020 at 6:18 PM Nicholas Piggin wrote:
> >>
> >> Jordan Niethe's on February 26, 2020 2:07 pm:
> >> > @@ -136,11 +148,14 @@ int arch_prepare_kprobe(struct kprobe *p)
>
On Wed, Feb 26, 2020 at 5:50 PM Nicholas Piggin wrote:
>
> Jordan Niethe's on February 26, 2020 2:07 pm:
> > From: Alistair Popple
> >
> > Prefix instructions have their own FSCR bit which needs to enabled via
> > a CPU feature. The kernel will save the FSCR for problem state but it
> > needs to
; Adding prefixed instructions complicates this as the bpt::instr[1] needs
> > to be used to hold the suffix. To deal with this make bpt::instr[] big
> > enough for three word instructions. bpt::instr[2] contains the trap,
> > and in the case of word instructions pad bpt::instr[1]
to xmon. In some places patch_instruction() is already
> > being using followed by store_inst(). In these cases just remove the
> > store_inst(). Otherwise replace store_inst() with patch_instruction().
> >
> > Signed-off-by: Jordan Niethe
> > ---
> > arch/p
On Wed, Feb 26, 2020 at 6:18 PM Nicholas Piggin wrote:
>
> Jordan Niethe's on February 26, 2020 2:07 pm:
> > @@ -136,11 +148,14 @@ int arch_prepare_kprobe(struct kprobe *p)
> > }
> >
> > if (!ret) {
> > - patch_instruction(p->ainsn.insn, *p->addr);
> > +
On Thu, Feb 27, 2020 at 6:14 PM Christophe Leroy
wrote:
>
>
>
> Le 27/02/2020 à 01:11, Jordan Niethe a écrit :
> > On Wed, Feb 26, 2020 at 6:10 PM Nicholas Piggin wrote:
> >>
> >> Jordan Niethe's on February 26, 2020 2:07 pm:
> >>> A prefixed ins
On Fri, Jan 10, 2020 at 9:38 PM Balamuruhan S wrote:
>
> On Tue, Nov 26, 2019 at 04:21:29PM +1100, Jordan Niethe wrote:
> > This adds emulation support for the following prefixed integer
> > load/stores:
> > * Prefixed Load Byte and Zero (plbz)
> > * Prefixe
On Sat, Jan 11, 2020 at 2:13 AM Balamuruhan S wrote:
>
> On Tue, Nov 26, 2019 at 04:21:29PM +1100, Jordan Niethe wrote:
> > This adds emulation support for the following prefixed integer
> > load/stores:
> > * Prefixed Load Byte and Zero (plbz)
> > * Prefixe
On Mon, Jan 13, 2020 at 10:30 PM Balamuruhan S wrote:
>
> On Tue, Nov 26, 2019 at 04:21:38PM +1100, Jordan Niethe wrote:
> > Uprobes can execute instructions out of line. Increase the size of the
> > buffer used for this so that this works for prefixed instructions. Tak
On Mon, Jan 13, 2020 at 5:18 PM Balamuruhan S wrote:
>
> On Tue, Nov 26, 2019 at 04:21:28PM +1100, Jordan Niethe wrote:
> > Currently all instructions are a single word long. A future ISA version
> > will include prefixed instructions which have a double word length. The
On Fri, Feb 7, 2020 at 7:16 PM Greg Kurz wrote:
>
> On Thu, 19 Dec 2019 01:11:33 +1100
> Daniel Axtens wrote:
>
> > Jordan Niethe writes:
> >
> > > A user-mode access to an address a long way below the stack pointer is
> > > only valid if the inst
On Tue, Feb 11, 2020 at 4:57 PM Christophe Leroy
wrote:
>
>
>
> Le 11/02/2020 à 06:33, Jordan Niethe a écrit :
> > Currently all instructions are a single word long. A future ISA version
> > will include prefixed instructions which have a double word length. The
> >
On Fri, Dec 20, 2019 at 4:17 PM Jordan Niethe wrote:
>
> On Thu, Dec 19, 2019 at 1:15 AM Daniel Axtens wrote:
> >
> > Jordan Niethe writes:
> >
> > > Currently all instructions are a single word long. A future ISA version
> > > will include prefixed in
On Thu, Apr 9, 2020 at 4:21 AM Segher Boessenkool
wrote:
>
> Hi!
>
> On Mon, Apr 06, 2020 at 06:09:20PM +1000, Jordan Niethe wrote:
> > +static inline int ppc_inst_opcode(u32 x)
> > +{
> > + return x >> 26;
> > +}
>
> Maybe you should hav
On Thu, Apr 9, 2020 at 3:04 PM Balamuruhan S wrote:
>
> On Wed, 2020-04-08 at 12:18 +1000, Jordan Niethe wrote:
> > On Tue, Apr 7, 2020 at 9:31 PM Balamuruhan S wrote:
> > > On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> > > > Currently in
On Thu, Apr 9, 2020 at 4:11 PM Christophe Leroy wrote:
>
>
>
> Le 06/04/2020 à 10:09, Jordan Niethe a écrit :
> > To execute an instruction out of line after a breakpoint, the NIP is set
> > to the address of struct bpt::instr. Here a copy of the instructi
On Thu, Apr 9, 2020 at 4:39 PM Christophe Leroy wrote:
>
>
>
> On 04/06/2020 08:09 AM, Jordan Niethe wrote:
> > A future revision of the ISA will introduce prefixed instructions. A
> > prefixed instruction is composed of a 4-byte prefix followed by a
> > 4-byte suf
On Mon, Apr 13, 2020 at 10:04 PM Balamuruhan S wrote:
>
> On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> > For powerpc64, redefine the ppc_inst type so both word and prefixed
> > instructions can be represented. On powerpc32 the type will remain the
> > same.
On Tue, Apr 7, 2020 at 8:30 PM Balamuruhan S wrote:
>
> On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> > Currently unsigned ints are used to represent instructions on powerpc.
> > This has worked well as instructions have always been 4 byte words.
> > Howev
On Tue, Apr 7, 2020 at 9:31 PM Balamuruhan S wrote:
>
> On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> > Currently in xmon, mread() is used for reading instructions. In
> > preparation for prefixed instructions, create and use a new function,
> > mread_instr()
On Tue, Apr 7, 2020 at 9:15 PM Balamuruhan S wrote:
>
> On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> > Currently all instructions have the same length, but in preparation for
> > prefixed instructions introduce a function for returning instruction
> > le
On Tue, Apr 7, 2020 at 8:48 PM Balamuruhan S wrote:
>
> On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> > Define specific __get_user_instr() and __get_user_instr_inatomic()
> > macros for reading instructions from user space.
> >
> > Signed-off-by: Jo
On Tue, Apr 7, 2020 at 4:10 PM Balamuruhan S wrote:
>
> On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> > create_branch(), create_cond_branch() and translate_branch() return the
> > instruction that they create, or return 0 to signal an error. Seperate
>
> s/
On Mon, Apr 6, 2020 at 6:22 PM Christophe Leroy wrote:
>
>
>
> Le 06/04/2020 à 10:09, Jordan Niethe a écrit :
> > In preparation for using a data type for instructions that can not be
> > directly used with the '>>' operator use a function for getting the
On Tue, Apr 7, 2020 at 4:40 PM Balamuruhan S wrote:
>
> On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> > In preparation for instructions having a more complex data type start
> > using a macro, ppc_inst(), for making an instruction out of a u32. A
&g
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