[PATCH] powerpc/powernv: Add mmap to opal export sysfs nodes

[Jordan Niethe]

The sysfs nodes created under /opal/exports/ do not currently support
mmap. Skiboot trace buffers are exported here with in the series
https://patchwork.ozlabs.org/cover/1073501/. Adding mmap support makes
it possible to use the functions for reading traces in external/trace.
This improves on the current read/lseek method as it handles cases like
the buffer wrapping and overflowing.

Signed-off-by: Jordan Niethe 
---
v2: ensure only whole pages can be mapped
---
 arch/powerpc/platforms/powernv/opal.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/arch/powerpc/platforms/powernv/opal.c 
b/arch/powerpc/platforms/powernv/opal.c
index 2b0eca104f86..3611b5b9c5d2 100644
--- a/arch/powerpc/platforms/powernv/opal.c
+++ b/arch/powerpc/platforms/powernv/opal.c
@@ -714,6 +714,15 @@ static ssize_t export_attr_read(struct file *fp, struct 
kobject *kobj,
   bin_attr->size);
 }
 
+static int export_attr_mmap(struct file *fp, struct kobject *kobj,
+   struct bin_attribute *attr,
+   struct vm_area_struct *vma)
+{
+   return remap_pfn_range(vma, vma->vm_start,
+  __pa(attr->private) >> PAGE_SHIFT,
+  attr->size, PAGE_READONLY);
+}
+
 /*
  * opal_export_attrs: creates a sysfs node for each property listed in
  * the device-tree under /ibm,opal/firmware/exports/
@@ -759,6 +768,9 @@ static void opal_export_attrs(void)
attr->attr.name = kstrdup(prop->name, GFP_KERNEL);
attr->attr.mode = 0400;
attr->read = export_attr_read;
+   /* Ensure only whole pages are mapped */
+   if (vals[0] % PAGE_SIZE == 0 && vals[1] % PAGE_SIZE == 0)
+   attr->mmap = export_attr_mmap;
attr->private = __va(vals[0]);
attr->size = vals[1];
 
-- 
2.20.1

[PATCH] KVM: PPC: Book3S HV: Fix build failure without IOMMU support

[Jordan Niethe]

Currently trying to build without IOMMU support will fail:

  (.text+0x1380): undefined reference to `kvmppc_h_get_tce'
  (.text+0x1384): undefined reference to `kvmppc_rm_h_put_tce'
  (.text+0x149c): undefined reference to `kvmppc_rm_h_stuff_tce'
  (.text+0x14a0): undefined reference to `kvmppc_rm_h_put_tce_indirect'

This happens because turning off IOMMU support will prevent
book3s_64_vio_hv.c from being built because it is only built when
SPAPR_TCE_IOMMU is set, which depends on IOMMU support.

Fix it using ifdefs for the undefined references.

Fixes: 76d837a4c0f9 ("KVM: PPC: Book3S PR: Don't include SPAPR TCE code on 
non-pseries platforms")
Signed-off-by: Jordan Niethe 
---
 arch/powerpc/kvm/book3s_hv.c|  2 ++
 arch/powerpc/kvm/book3s_hv_rmhandlers.S | 10 ++
 2 files changed, 12 insertions(+)

diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index 5a066fc299e1..94e50438e6a2 100644
--- a/arch/powerpc/kvm/book3s_hv.c
+++ b/arch/powerpc/kvm/book3s_hv.c
@@ -937,6 +937,7 @@ int kvmppc_pseries_do_hcall(struct kvm_vcpu *vcpu)
ret = kvmppc_h_set_xdabr(vcpu, kvmppc_get_gpr(vcpu, 4),
kvmppc_get_gpr(vcpu, 5));
break;
+#ifdef CONFIG_SPAPR_TCE_IOMMU
case H_GET_TCE:
ret = kvmppc_h_get_tce(vcpu, kvmppc_get_gpr(vcpu, 4),
kvmppc_get_gpr(vcpu, 5));
@@ -966,6 +967,7 @@ int kvmppc_pseries_do_hcall(struct kvm_vcpu *vcpu)
if (ret == H_TOO_HARD)
return RESUME_HOST;
break;
+#endif
case H_RANDOM:
if (!powernv_get_random_long(>arch.regs.gpr[4]))
ret = H_HARDWARE;
diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S 
b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
index 9b8d50a7cbaf..541b121477e4 100644
--- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
+++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
@@ -2264,8 +2264,13 @@ hcall_real_table:
.long   DOTSYM(kvmppc_h_clear_mod) - hcall_real_table
.long   DOTSYM(kvmppc_h_clear_ref) - hcall_real_table
.long   DOTSYM(kvmppc_h_protect) - hcall_real_table
+#ifdef CONFIG_SPAPR_TCE_IOMMU
.long   DOTSYM(kvmppc_h_get_tce) - hcall_real_table
.long   DOTSYM(kvmppc_rm_h_put_tce) - hcall_real_table
+#else
+   .long   0   /* 0x1c */
+   .long   0   /* 0x20 */
+#endif
.long   0   /* 0x24 - H_SET_SPRG0 */
.long   DOTSYM(kvmppc_h_set_dabr) - hcall_real_table
.long   0   /* 0x2c */
@@ -2343,8 +2348,13 @@ hcall_real_table:
.long   0   /* 0x12c */
.long   0   /* 0x130 */
.long   DOTSYM(kvmppc_h_set_xdabr) - hcall_real_table
+#ifdef CONFIG_SPAPR_TCE_IOMMU
.long   DOTSYM(kvmppc_rm_h_stuff_tce) - hcall_real_table
.long   DOTSYM(kvmppc_rm_h_put_tce_indirect) - hcall_real_table
+#else
+   .long   0   /* 0x138 */
+   .long   0   /* 0x13c */
+#endif
.long   0   /* 0x140 */
.long   0   /* 0x144 */
.long   0   /* 0x148 */
-- 
2.20.1

[PATCH] powerpc/powernv: Make opal log only readable by root

[Jordan Niethe]

Currently the opal log is globally readable. It is kernel policy to limit
the visibility of physical addresses / kernel pointers to root.
Given this and the fact the opal log may contain this information it would
be better to limit the readability to root.

Signed-off-by: Jordan Niethe 
---
 arch/powerpc/platforms/powernv/opal-msglog.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/powerpc/platforms/powernv/opal-msglog.c 
b/arch/powerpc/platforms/powernv/opal-msglog.c
index acd3206dfae3..06628c71cef6 100644
--- a/arch/powerpc/platforms/powernv/opal-msglog.c
+++ b/arch/powerpc/platforms/powernv/opal-msglog.c
@@ -98,7 +98,7 @@ static ssize_t opal_msglog_read(struct file *file, struct 
kobject *kobj,
 }
 
 static struct bin_attribute opal_msglog_attr = {
-   .attr = {.name = "msglog", .mode = 0444},
+   .attr = {.name = "msglog", .mode = 0400},
.read = opal_msglog_read
 };
 
-- 
2.20.1

[PATCH] powerpc/powernv: Add mmap to opal export sysfs nodes

[Jordan Niethe]

The sysfs nodes created under /opal/exports/ do not currently support
mmap. Skiboot trace buffers are not yet added to this location but
this is a suitable for them to be exported to. Adding mmap support makes
using these trace buffers more convenient. The state in the header of
the trace buffer is needed to ensure the read position has not been
overwritten. Thus the header of the buffer must be read, then the
read position itself. Using lseek/read to do this introduces a delay
that could result in incorrect reads if the read position is overwritten
after the header is read.

Signed-off-by: Jordan Niethe 
---
 arch/powerpc/platforms/powernv/opal.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/powerpc/platforms/powernv/opal.c 
b/arch/powerpc/platforms/powernv/opal.c
index 2b0eca104f86..3cfc683bb060 100644
--- a/arch/powerpc/platforms/powernv/opal.c
+++ b/arch/powerpc/platforms/powernv/opal.c
@@ -714,6 +714,15 @@ static ssize_t export_attr_read(struct file *fp, struct 
kobject *kobj,
   bin_attr->size);
 }
 
+static int export_attr_mmap(struct file *fp, struct kobject *kobj,
+   struct bin_attribute *attr,
+   struct vm_area_struct *vma)
+{
+   return remap_pfn_range(vma, vma->vm_start,
+   __pa(attr->private) >> PAGE_SHIFT,
+   attr->size, PAGE_READONLY);
+}
+
 /*
  * opal_export_attrs: creates a sysfs node for each property listed in
  * the device-tree under /ibm,opal/firmware/exports/
@@ -759,6 +768,7 @@ static void opal_export_attrs(void)
attr->attr.name = kstrdup(prop->name, GFP_KERNEL);
attr->attr.mode = 0400;
attr->read = export_attr_read;
+   attr->mmap = export_attr_mmap;
attr->private = __va(vals[0]);
attr->size = vals[1];
 
-- 
2.20.1

Re: [PATCH v2 1/3] KVM: PPC: Book3S HV: Fix race in re-enabling XIVE escalation interrupts

[Jordan Niethe]

On Tue, 2019-08-13 at 20:03 +1000, Paul Mackerras wrote:
> Escalation interrupts are interrupts sent to the host by the XIVE
> hardware when it has an interrupt to deliver to a guest VCPU but that
> VCPU is not running anywhere in the system.  Hence we disable the
> escalation interrupt for the VCPU being run when we enter the guest
> and re-enable it when the guest does an H_CEDE hypercall indicating
> it is idle.
> 
> It is possible that an escalation interrupt gets generated just as we
> are entering the guest.  In that case the escalation interrupt may be
> using a queue entry in one of the interrupt queues, and that queue
> entry may not have been processed when the guest exits with an
> H_CEDE.
> The existing entry code detects this situation and does not clear the
> vcpu->arch.xive_esc_on flag as an indication that there is a pending
> queue entry (if the queue entry gets processed, xive_esc_irq() will
> clear the flag).  There is a comment in the code saying that if the
> flag is still set on H_CEDE, we have to abort the cede rather than
> re-enabling the escalation interrupt, lest we end up with two
> occurrences of the escalation interrupt in the interrupt queue.
> 
> However, the exit code doesn't do that; it aborts the cede in the
> sense
> that vcpu->arch.ceded gets cleared, but it still enables the
> escalation
> interrupt by setting the source's PQ bits to 00.  Instead we need to
> set the PQ bits to 10, indicating that an interrupt has been
> triggered.
> We also need to avoid setting vcpu->arch.xive_esc_on in this case
> (i.e. vcpu->arch.xive_esc_on seen to be set on H_CEDE) because
> xive_esc_irq() will run at some point and clear it, and if we race
> with
> that we may end up with an incorrect result (i.e. xive_esc_on set
> when
> the escalation interrupt has just been handled).
> 
> It is extremely unlikely that having two queue entries would cause
> observable problems; theoretically it could cause queue overflow, but
> the CPU would have to have thousands of interrupts targetted to it
> for
> that to be possible.  However, this fix will also make it possible to
> determine accurately whether there is an unhandled escalation
> interrupt in the queue, which will be needed by the following patch.
> 
> Cc: sta...@vger.kernel.org # v4.16+
> Fixes: 9b9b13a6d153 ("KVM: PPC: Book3S HV: Keep XIVE escalation
> interrupt masked unless ceded")
> Signed-off-by: Paul Mackerras 
> ---
> v2: don't set xive_esc_on if we're not using a XIVE escalation
> interrupt.
> 
>  arch/powerpc/kvm/book3s_hv_rmhandlers.S | 36 +
> 
>  1 file changed, 23 insertions(+), 13 deletions(-)
> 
> diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
> b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
> index 337e644..2e7e788 100644
> --- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
> +++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
> @@ -2831,29 +2831,39 @@ kvm_cede_prodded:
>  kvm_cede_exit:
>   ld  r9, HSTATE_KVM_VCPU(r13)
>  #ifdef CONFIG_KVM_XICS
> - /* Abort if we still have a pending escalation */
> + /* are we using XIVE with single escalation? */
> + ld  r10, VCPU_XIVE_ESC_VADDR(r9)
> + cmpdi   r10, 0
> + beq 3f
> + li  r6, XIVE_ESB_SET_PQ_00
Would it make sense to put the above instruction down into the 4: label
instead? If we do not branch to 4, r6 is overwriten anyway. 
I think that would save a load when we do not branch to 4. Also it
would mean that you could use r5 everywhere instead of changing it to
r6? 
> + /*
> +  * If we still have a pending escalation, abort the cede,
> +  * and we must set PQ to 10 rather than 00 so that we don't
> +  * potentially end up with two entries for the escalation
> +  * interrupt in the XIVE interrupt queue.  In that case
> +  * we also don't want to set xive_esc_on to 1 here in
> +  * case we race with xive_esc_irq().
> +  */
>   lbz r5, VCPU_XIVE_ESC_ON(r9)
>   cmpwi   r5, 0
> - beq 1f
> + beq 4f
>   li  r0, 0
>   stb r0, VCPU_CEDED(r9)
> -1:   /* Enable XIVE escalation */
> - li  r5, XIVE_ESB_SET_PQ_00
> + li  r6, XIVE_ESB_SET_PQ_10
> + b   5f
> +4:   li  r0, 1
> + stb r0, VCPU_XIVE_ESC_ON(r9)
> + /* make sure store to xive_esc_on is seen before xive_esc_irq
> runs */
> + sync
> +5:   /* Enable XIVE escalation */
>   mfmsr   r0
>   andi.   r0, r0, MSR_DR  /* in real mode? */
>   beq 1f
> - ld  r10, VCPU_XIVE_ESC_VADDR(r9)
> - cmpdi   r10, 0
> - beq 3f
> - ldx r0, r10, r5
> + ldx r0, r10, r6
>   b   2f
>  1:   ld  r10, VCPU_XIVE_ESC_RADDR(r9)
> - cmpdi   r10, 0
> - beq 3f
> - ldcix   r0, r10, r5
> + ldcix   r0, r10, r6
>  2:   sync
> - li  r0, 1
> - stb r0, VCPU_XIVE_ESC_ON(r9)
>  #endif /* CONFIG_KVM_XICS */
>  3:   b   guest_exit_cont
>  

Re: [PATCH 1/3] powerpc/xmon: Check for HV mode when dumping XIVE info from OPAL

[Jordan Niethe]

On Wed, 2019-08-14 at 17:47 +0200, Cédric Le Goater wrote:
> Currently, the xmon 'dx' command calls OPAL to dump the XIVE state in
> the OPAL logs and also outputs some of the fields of the internal
> XIVE
> structures in Linux. The OPAL calls can only be done on baremetal
> (PowerNV) and they crash a pseries machine. Fix by checking the
> hypervisor feature of the CPU.
> 
> Signed-off-by: Cédric Le Goater 
> ---
>  arch/powerpc/xmon/xmon.c | 17 ++---
>  1 file changed, 10 insertions(+), 7 deletions(-)
> 
> diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
> index 14e56c25879f..25d4adccf750 100644
> --- a/arch/powerpc/xmon/xmon.c
> +++ b/arch/powerpc/xmon/xmon.c
> @@ -2534,13 +2534,16 @@ static void dump_pacas(void)
>  static void dump_one_xive(int cpu)
>  {
>   unsigned int hwid = get_hard_smp_processor_id(cpu);
> -
> - opal_xive_dump(XIVE_DUMP_TM_HYP, hwid);
> - opal_xive_dump(XIVE_DUMP_TM_POOL, hwid);
> - opal_xive_dump(XIVE_DUMP_TM_OS, hwid);
> - opal_xive_dump(XIVE_DUMP_TM_USER, hwid);
> - opal_xive_dump(XIVE_DUMP_VP, hwid);
> - opal_xive_dump(XIVE_DUMP_EMU_STATE, hwid);
> + bool hv = cpu_has_feature(CPU_FTR_HVMODE);
> +
> + if (hv) {
> + opal_xive_dump(XIVE_DUMP_TM_HYP, hwid);
> + opal_xive_dump(XIVE_DUMP_TM_POOL, hwid);
> + opal_xive_dump(XIVE_DUMP_TM_OS, hwid);
> + opal_xive_dump(XIVE_DUMP_TM_USER, hwid);
> + opal_xive_dump(XIVE_DUMP_VP, hwid);
> + opal_xive_dump(XIVE_DUMP_EMU_STATE, hwid);
> + }
>  
>   if (setjmp(bus_error_jmp) != 0) {
>   catch_memory_errors = 0;
dump_one_xive() / other xive functions are guarded by #ifdef
CONFIG_PPC_POWERNV in xmon.c aren't they? With this series would it be
that these guards can be removed?

[PATCH] powerpc: Remove empty comment

[Jordan Niethe]

Commit 2874c5fd2842 ("treewide: Replace GPLv2 boilerplate/reference with
SPDX - rule 152") left an empty comment in machdep.h, as the boilerplate
was the only text in the comment. Remove the empty comment.

Signed-off-by: Jordan Niethe 
---
 arch/powerpc/include/asm/machdep.h | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/arch/powerpc/include/asm/machdep.h 
b/arch/powerpc/include/asm/machdep.h
index c43d6eca9edd..ab6c94c650e7 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -3,9 +3,6 @@
 #define _ASM_POWERPC_MACHDEP_H
 #ifdef __KERNEL__
 
-/*
- */
-
 #include 
 #include 
 #include 
-- 
2.20.1

Re: [PATCH v4 7/9] powerpc/eeh: Add bdfn field to eeh_dev

[Jordan Niethe]

On Wed, 2019-08-07 at 13:44 +1000, Sam Bobroff wrote:
> From: Oliver O'Halloran 
> 
> Preparation for removing pci_dn from the powernv EEH code. The only
> thing we really use pci_dn for is to get the bdfn of the device for
> config space accesses, so adding that information to eeh_dev reduces
> the need to carry around the pci_dn.
> 
> Signed-off-by: Oliver O'Halloran 
> [SB: Re-wrapped commit message, fixed whitespace damage.]
> Signed-off-by: Sam Bobroff 
> ---
>  arch/powerpc/include/asm/eeh.h | 2 ++
>  arch/powerpc/include/asm/ppc-pci.h | 2 ++
>  arch/powerpc/kernel/eeh_dev.c  | 2 ++
>  3 files changed, 6 insertions(+)
> 
> diff --git a/arch/powerpc/include/asm/eeh.h
> b/arch/powerpc/include/asm/eeh.h
> index 7f9404a0c3bb..bbe0798f6624 100644
> --- a/arch/powerpc/include/asm/eeh.h
> +++ b/arch/powerpc/include/asm/eeh.h
> @@ -121,6 +121,8 @@ static inline bool eeh_pe_passed(struct eeh_pe
> *pe)
>  struct eeh_dev {
>   int mode;   /* EEH mode */
>   int class_code; /* Class code of the device 
> */
> + int bdfn;   /* bdfn of device (for cfg ops) */
> + struct pci_controller *controller;

The other members of the structure get a comment, maybe it would be
more consistant if this one did too?

>   int pe_config_addr; /* PE config address
> */
>   u32 config_space[16];   /* Saved PCI config space   
> */
>   int pcix_cap;   /* Saved PCIx capability
> */
> diff --git a/arch/powerpc/include/asm/ppc-pci.h
> b/arch/powerpc/include/asm/ppc-pci.h
> index cec2d6409515..72860de205a0 100644
> --- a/arch/powerpc/include/asm/ppc-pci.h
> +++ b/arch/powerpc/include/asm/ppc-pci.h
> @@ -74,6 +74,8 @@ static inline const char *eeh_driver_name(struct
> pci_dev *pdev)
>  
>  #endif /* CONFIG_EEH */
>  
> +#define PCI_BUSNO(bdfn) ((bdfn >> 8) & 0xff)
> +
>  #else /* CONFIG_PCI */
>  static inline void init_pci_config_tokens(void) { }
>  #endif /* !CONFIG_PCI */
> diff --git a/arch/powerpc/kernel/eeh_dev.c
> b/arch/powerpc/kernel/eeh_dev.c
> index c4317c452d98..7370185c7a05 100644
> --- a/arch/powerpc/kernel/eeh_dev.c
> +++ b/arch/powerpc/kernel/eeh_dev.c
> @@ -47,6 +47,8 @@ struct eeh_dev *eeh_dev_init(struct pci_dn *pdn)
>   /* Associate EEH device with OF node */
>   pdn->edev = edev;
>   edev->pdn = pdn;
> + edev->bdfn = (pdn->busno << 8) | pdn->devfn;
> + edev->controller = pdn->phb;
>  
>   return edev;
>  }

[PATCH] powerpc/xive: Update comment referencing magic loads from an ESB

[Jordan Niethe]

The comment above xive_esb_read() references magic loads from an ESB as
described xive.h. This has been inaccurate since commit 12c1f339cd49
("powerpc/xive: Move definition of ESB bits") which moved the
description. Update the comment to reference the new location of the
description in xive-regs.h

Signed-off-by: Jordan Niethe 
---
 arch/powerpc/sysdev/xive/common.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/powerpc/sysdev/xive/common.c 
b/arch/powerpc/sysdev/xive/common.c
index 1cdb39575eae..083f657091d7 100644
--- a/arch/powerpc/sysdev/xive/common.c
+++ b/arch/powerpc/sysdev/xive/common.c
@@ -185,7 +185,7 @@ static u32 xive_scan_interrupts(struct xive_cpu *xc, bool 
just_peek)
 
 /*
  * This is used to perform the magic loads from an ESB
- * described in xive.h
+ * described in xive-regs.h
  */
 static notrace u8 xive_esb_read(struct xive_irq_data *xd, u32 offset)
 {
-- 
2.20.1

[PATCH] PPC: Set reserved PCR bits

[Jordan Niethe]

Currently the reserved bits of the Processor Compatibility Register
(PCR) are cleared as per the Programming Note in Section 1.3.3 of the
ISA.  An update is planned for the ISA so that PCR reserved bits should
be set. Set the reserved bits of the PCR as required.

Acked-by: Alistair Popple 
Signed-off-by: Jordan Niethe 
---
 arch/powerpc/include/asm/reg.h  |  3 +++
 arch/powerpc/kernel/cpu_setup_power.S   |  6 ++
 arch/powerpc/kernel/dt_cpu_ftrs.c   |  3 ++-
 arch/powerpc/kvm/book3s_hv.c| 11 +++
 arch/powerpc/kvm/book3s_hv_nested.c |  6 +++---
 arch/powerpc/kvm/book3s_hv_rmhandlers.S | 10 ++
 6 files changed, 27 insertions(+), 12 deletions(-)

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 10caa145f98b..2e0815994f4d 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -475,6 +475,7 @@
 #define   PCR_VEC_DIS  (1ul << (63-0)) /* Vec. disable (bit NA since POWER8) */
 #define   PCR_VSX_DIS  (1ul << (63-1)) /* VSX disable (bit NA since POWER8) */
 #define   PCR_TM_DIS   (1ul << (63-2)) /* Trans. memory disable (POWER8) */
+#define   PCR_HIGH_BITS(PCR_VEC_DIS | PCR_VSX_DIS | PCR_TM_DIS)
 /*
  * These bits are used in the function kvmppc_set_arch_compat() to specify and
  * determine both the compatibility level which we want to emulate and the
@@ -483,6 +484,8 @@
 #define   PCR_ARCH_207 0x8 /* Architecture 2.07 */
 #define   PCR_ARCH_206 0x4 /* Architecture 2.06 */
 #define   PCR_ARCH_205 0x2 /* Architecture 2.05 */
+#define   PCR_LOW_BITS (PCR_ARCH_207 | PCR_ARCH_206 | PCR_ARCH_205)
+#define   PCR_MASK ~(PCR_HIGH_BITS | PCR_LOW_BITS) /* PCR Reserved Bits */
 #defineSPRN_HEIR   0x153   /* Hypervisor Emulated Instruction 
Register */
 #define SPRN_TLBINDEXR 0x154   /* P7 TLB control register */
 #define SPRN_TLBVPNR   0x155   /* P7 TLB control register */
diff --git a/arch/powerpc/kernel/cpu_setup_power.S 
b/arch/powerpc/kernel/cpu_setup_power.S
index 3239a9fe6c1c..a460298c7ddb 100644
--- a/arch/powerpc/kernel/cpu_setup_power.S
+++ b/arch/powerpc/kernel/cpu_setup_power.S
@@ -23,6 +23,7 @@ _GLOBAL(__setup_cpu_power7)
beqlr
li  r0,0
mtspr   SPRN_LPID,r0
+   LOAD_REG_IMMEDIATE(r0, PCR_MASK)
mtspr   SPRN_PCR,r0
mfspr   r3,SPRN_LPCR
li  r4,(LPCR_LPES1 >> LPCR_LPES_SH)
@@ -37,6 +38,7 @@ _GLOBAL(__restore_cpu_power7)
beqlr
li  r0,0
mtspr   SPRN_LPID,r0
+   LOAD_REG_IMMEDIATE(r0, PCR_MASK)
mtspr   SPRN_PCR,r0
mfspr   r3,SPRN_LPCR
li  r4,(LPCR_LPES1 >> LPCR_LPES_SH)
@@ -54,6 +56,7 @@ _GLOBAL(__setup_cpu_power8)
beqlr
li  r0,0
mtspr   SPRN_LPID,r0
+   LOAD_REG_IMMEDIATE(r0, PCR_MASK)
mtspr   SPRN_PCR,r0
mfspr   r3,SPRN_LPCR
ori r3, r3, LPCR_PECEDH
@@ -76,6 +79,7 @@ _GLOBAL(__restore_cpu_power8)
beqlr
li  r0,0
mtspr   SPRN_LPID,r0
+   LOAD_REG_IMMEDIATE(r0, PCR_MASK)
mtspr   SPRN_PCR,r0
mfspr   r3,SPRN_LPCR
ori r3, r3, LPCR_PECEDH
@@ -98,6 +102,7 @@ _GLOBAL(__setup_cpu_power9)
mtspr   SPRN_PSSCR,r0
mtspr   SPRN_LPID,r0
mtspr   SPRN_PID,r0
+   LOAD_REG_IMMEDIATE(r0, PCR_MASK)
mtspr   SPRN_PCR,r0
mfspr   r3,SPRN_LPCR
LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE  | 
LPCR_HEIC)
@@ -123,6 +128,7 @@ _GLOBAL(__restore_cpu_power9)
mtspr   SPRN_PSSCR,r0
mtspr   SPRN_LPID,r0
mtspr   SPRN_PID,r0
+   LOAD_REG_IMMEDIATE(r0, PCR_MASK)
mtspr   SPRN_PCR,r0
mfspr   r3,SPRN_LPCR
LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE | 
LPCR_HEIC)
diff --git a/arch/powerpc/kernel/dt_cpu_ftrs.c 
b/arch/powerpc/kernel/dt_cpu_ftrs.c
index 0e4c7c1f5c3e..7f2858e3e56a 100644
--- a/arch/powerpc/kernel/dt_cpu_ftrs.c
+++ b/arch/powerpc/kernel/dt_cpu_ftrs.c
@@ -102,7 +102,7 @@ static void __restore_cpu_cpufeatures(void)
if (hv_mode) {
mtspr(SPRN_LPID, 0);
mtspr(SPRN_HFSCR, system_registers.hfscr);
-   mtspr(SPRN_PCR, 0);
+   mtspr(SPRN_PCR, PCR_MASK);
}
mtspr(SPRN_FSCR, system_registers.fscr);
 
@@ -145,6 +145,7 @@ static void __init cpufeatures_setup_cpu(void)
mtspr(SPRN_HFSCR, 0);
}
mtspr(SPRN_FSCR, 0);
+   mtspr(SPRN_PCR, PCR_MASK);
 
/*
 * LPCR does not get cleared, to match behaviour with secondaries
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index 76b1801aa44a..fb1debaa5a7c 100644
--- a/arch/powerpc/kvm/book3s_hv.c
+++ b/arch/powerpc/kvm/book3s_hv.c
@@ -401,8 +401,11 @@ static int kvmppc_set_arch_compat(struct kvm_vcpu *vcpu, 
u32 arch_compat)
 
spin_lock(>lock);
vc->arch_compat = arch_compat;
-

[PATCH v2] powerpc/mm: Remove kvm radix prefetch workaround for Power9 DD2.2

[Jordan Niethe]

Commit a25bd72badfa ("powerpc/mm/radix: Workaround prefetch issue with
KVM") introduced a number of workarounds as coming out of a guest with
the mmu enabled would make the cpu would start running in hypervisor
state with the PID value from the guest. The cpu will then start
prefetching for the hypervisor with that PID value.

In Power9 DD2.2 the cpu behaviour was modified to fix this. When
accessing Quadrant 0 in hypervisor mode with LPID != 0 prefetching will
not be performed. This means that we can get rid of the workarounds for
Power9 DD2.2 and later revisions. Add a new cpu feature
CPU_FTR_P9_RADIX_PREFETCH_BUG to indicate if the workarounds are needed.

Signed-off-by: Jordan Niethe 
---
v2: Use a cpu feature instead of open coding the PVR check
---
 arch/powerpc/include/asm/cputable.h  |  6 --
 arch/powerpc/kernel/dt_cpu_ftrs.c| 13 -
 arch/powerpc/kvm/book3s_hv_rmhandlers.S  |  2 ++
 arch/powerpc/mm/book3s64/radix_pgtable.c |  6 +-
 arch/powerpc/mm/book3s64/radix_tlb.c |  3 +++
 5 files changed, 22 insertions(+), 8 deletions(-)

diff --git a/arch/powerpc/include/asm/cputable.h 
b/arch/powerpc/include/asm/cputable.h
index cf00ff0d121d..944a39c4c3a0 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -212,6 +212,7 @@ static inline void cpu_feature_keys_init(void) { }
 #define CPU_FTR_P9_TLBIE_STQ_BUG   LONG_ASM_CONST(0x4000)
 #define CPU_FTR_P9_TIDR
LONG_ASM_CONST(0x8000)
 #define CPU_FTR_P9_TLBIE_ERAT_BUG  LONG_ASM_CONST(0x0001)
+#define CPU_FTR_P9_RADIX_PREFETCH_BUG  LONG_ASM_CONST(0x0002)
 
 #ifndef __ASSEMBLY__
 
@@ -459,8 +460,9 @@ static inline void cpu_feature_keys_init(void) { }
CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \
CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | CPU_FTR_PKEY | \
CPU_FTR_P9_TLBIE_STQ_BUG | CPU_FTR_P9_TLBIE_ERAT_BUG | 
CPU_FTR_P9_TIDR)
-#define CPU_FTRS_POWER9_DD2_0 CPU_FTRS_POWER9
-#define CPU_FTRS_POWER9_DD2_1 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1)
+#define CPU_FTRS_POWER9_DD2_0 CPU_FTRS_POWER9 | CPU_FTR_P9_RADIX_PREFETCH_BUG
+#define CPU_FTRS_POWER9_DD2_1 (CPU_FTRS_POWER9 | CPU_FTR_P9_RADIX_PREFETCH_BUG 
| \
+  CPU_FTR_POWER9_DD2_1)
 #define CPU_FTRS_POWER9_DD2_2 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1 | \
   CPU_FTR_P9_TM_HV_ASSIST | \
   CPU_FTR_P9_TM_XER_SO_BUG)
diff --git a/arch/powerpc/kernel/dt_cpu_ftrs.c 
b/arch/powerpc/kernel/dt_cpu_ftrs.c
index 180b3a5d1001..182b4047c1ef 100644
--- a/arch/powerpc/kernel/dt_cpu_ftrs.c
+++ b/arch/powerpc/kernel/dt_cpu_ftrs.c
@@ -727,17 +727,20 @@ static __init void cpufeatures_cpu_quirks(void)
/*
 * Not all quirks can be derived from the cpufeatures device tree.
 */
-   if ((version & 0xefff) == 0x004e0200)
-   ; /* DD2.0 has no feature flag */
-   else if ((version & 0xefff) == 0x004e0201)
+   if ((version & 0xefff) == 0x004e0200) {
+   /* DD2.0 has no feature flag */
+   cur_cpu_spec->cpu_features |= CPU_FTR_P9_RADIX_PREFETCH_BUG;
+   } else if ((version & 0xefff) == 0x004e0201) {
cur_cpu_spec->cpu_features |= CPU_FTR_POWER9_DD2_1;
-   else if ((version & 0xefff) == 0x004e0202) {
+   cur_cpu_spec->cpu_features |= CPU_FTR_P9_RADIX_PREFETCH_BUG;
+   } else if ((version & 0xefff) == 0x004e0202) {
cur_cpu_spec->cpu_features |= CPU_FTR_P9_TM_HV_ASSIST;
cur_cpu_spec->cpu_features |= CPU_FTR_P9_TM_XER_SO_BUG;
cur_cpu_spec->cpu_features |= CPU_FTR_POWER9_DD2_1;
-   } else if ((version & 0x) == 0x004e)
+   } else if ((version & 0x) == 0x004e) {
/* DD2.1 and up have DD2_1 */
cur_cpu_spec->cpu_features |= CPU_FTR_POWER9_DD2_1;
+   }
 
if ((version & 0x) == 0x004e) {
cur_cpu_spec->cpu_features &= ~(CPU_FTR_DAWR);
diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S 
b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
index faebcbb8c4db..72b08bb17200 100644
--- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
+++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
@@ -1793,6 +1793,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
tlbsync
ptesync
 
+BEGIN_FTR_SECTION
/* Radix: Handle the case where the guest used an illegal PID */
LOAD_REG_ADDR(r4, mmu_base_pid)
lwz r3, VCPU_GUEST_PID(r9)
@@ -1822,6 +1823,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
addir7,r7,0x1000
bdnz1b
ptesync
+END_FTR_SECTION_IFSET(CPU_FTR_P9_RADIX_PREFETCH_BUG)
 
 2:
 #endif /* CONFIG_PPC_RADIX_MMU */
diff --git a/arch/powerpc/mm/book3s64/radix_pgtable.c 
b/arch/powerpc/mm/book3s64/radix_pgtabl

[PATCH] powerpc/64: Use {SAVE,REST}_NVGPRS macros

[Jordan Niethe]

In entry_64.S there are places that open code saving and restoring the
non-volatile registers. There are already macros for doing this so use
them.

Signed-off-by: Jordan Niethe 
---
 arch/powerpc/kernel/entry_64.S | 18 ++
 1 file changed, 6 insertions(+), 12 deletions(-)

diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index 6467bdab8d40..457b86c13c19 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -591,8 +591,7 @@ _GLOBAL(_switch)
std r0,16(r1)
stdur1,-SWITCH_FRAME_SIZE(r1)
/* r3-r13 are caller saved -- Cort */
-   SAVE_8GPRS(14, r1)
-   SAVE_10GPRS(22, r1)
+   SAVE_NVGPRS(r1)
std r0,_NIP(r1) /* Return to switch caller */
mfcrr23
std r23,_CCR(r1)
@@ -716,8 +715,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
mtcrf   0xFF,r6
 
/* r3-r13 are destroyed -- Cort */
-   REST_8GPRS(14, r1)
-   REST_10GPRS(22, r1)
+   REST_NVGPRS(r1)
 
/* convert old thread to its task_struct for return value */
addir3,r3,-THREAD
@@ -1149,8 +1147,7 @@ _GLOBAL(enter_rtas)
 */
SAVE_GPR(2, r1) /* Save the TOC */
SAVE_GPR(13, r1)/* Save paca */
-   SAVE_8GPRS(14, r1)  /* Save the non-volatiles */
-   SAVE_10GPRS(22, r1) /* ditto */
+   SAVE_NVGPRS(r1) /* Save the non-volatiles */
 
mfcrr4
std r4,_CCR(r1)
@@ -1257,8 +1254,7 @@ rtas_restore_regs:
/* relocation is on at this point */
REST_GPR(2, r1) /* Restore the TOC */
REST_GPR(13, r1)/* Restore paca */
-   REST_8GPRS(14, r1)  /* Restore the non-volatiles */
-   REST_10GPRS(22, r1) /* ditto */
+   REST_NVGPRS(r1) /* Restore the non-volatiles */
 
GET_PACA(r13)
 
@@ -1292,8 +1288,7 @@ _GLOBAL(enter_prom)
 */
SAVE_GPR(2, r1)
SAVE_GPR(13, r1)
-   SAVE_8GPRS(14, r1)
-   SAVE_10GPRS(22, r1)
+   SAVE_NVGPRS(r1)
mfcrr10
mfmsr   r11
std r10,_CCR(r1)
@@ -1337,8 +1332,7 @@ _GLOBAL(enter_prom)
/* Restore other registers */
REST_GPR(2, r1)
REST_GPR(13, r1)
-   REST_8GPRS(14, r1)
-   REST_10GPRS(22, r1)
+   REST_NVGPRS(r1)
ld  r4,_CCR(r1)
mtcrr4
 
-- 
2.17.1

[PATCH 1/2] powerpc/64s/exception: Remove unused parameters from KVMTEST macro

[Jordan Niethe]

The hsrr and n parameters are never used by the KVMTEST macro so remove
them.

Signed-off-by: Jordan Niethe 
---
 arch/powerpc/kernel/exceptions-64s.S | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/powerpc/kernel/exceptions-64s.S 
b/arch/powerpc/kernel/exceptions-64s.S
index d0018dd17e0a..8bcf562242a2 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -210,7 +210,7 @@ END_FTR_SECTION_NESTED(ftr,ftr,943)
 #define kvmppc_interrupt kvmppc_interrupt_pr
 #endif
 
-.macro KVMTEST name, hsrr, n
+.macro KVMTEST name
lbz r10,HSTATE_IN_GUEST(r13)
cmpwi   r10,0
bne \name\()_kvm
@@ -284,7 +284,7 @@ END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948)
 .endm
 
 #else
-.macro KVMTEST name, hsrr, n
+.macro KVMTEST name
 .endm
 .macro KVM_HANDLER name, vec, hsrr, area, skip
 .endm
@@ -431,7 +431,7 @@ END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948)
SAVE_CTR(r10, \area\())
mfcrr9
.if \kvm
-   KVMTEST \name \hsrr \vec
+   KVMTEST \name
.endif
.if \bitmask
lbz r10,PACAIRQSOFTMASK(r13)
@@ -1444,7 +1444,7 @@ EXC_VIRT_NONE(0x4b00, 0x100)
GET_PACA(r13)
std r10,PACA_EXGEN+EX_R10(r13)
INTERRUPT_TO_KERNEL
-   KVMTEST system_call EXC_STD 0xc00 /* uses r10, branch to 
system_call_kvm */
+   KVMTEST system_call /* uses r10, branch to system_call_kvm */
mfctr   r9
 #else
mr  r9,r13
@@ -1811,7 +1811,7 @@ EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x100)
andis.  r10,r10,(HSRR1_DENORM)@h /* denorm? */
bne+denorm_assist
 #endif
-   KVMTEST denorm_exception_hv, EXC_HV 0x1500
+   KVMTEST denorm_exception_hv
INT_SAVE_SRR_AND_JUMP denorm_common, EXC_HV, 1
 EXC_REAL_END(denorm_exception_hv, 0x1500, 0x100)
 
-- 
2.17.1

[PATCH 2/2] powerpc/64s/exception: Add missing comma to INT_KVM_HANDLER macro for system_reset

[Jordan Niethe]

The INT_KVM_HANDLER macro for system_reset is missing a comma so add it
to be consistent.

Signed-off-by: Jordan Niethe 
---
 arch/powerpc/kernel/exceptions-64s.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/powerpc/kernel/exceptions-64s.S 
b/arch/powerpc/kernel/exceptions-64s.S
index 8bcf562242a2..528c893deefd 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -828,7 +828,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
 */
 EXC_REAL_END(system_reset, 0x100, 0x100)
 EXC_VIRT_NONE(0x4100, 0x100)
-INT_KVM_HANDLER system_reset 0x100, EXC_STD, PACA_EXNMI, 0
+INT_KVM_HANDLER system_reset, 0x100, EXC_STD, PACA_EXNMI, 0
 
 #ifdef CONFIG_PPC_P7_NAP
 TRAMP_REAL_BEGIN(system_reset_idle_wake)
-- 
2.17.1

Re: [PATCH v3 3/3] powerpc: Book3S 64-bit "heavyweight" KASAN support

[Jordan Niethe]

On Fri, Dec 13, 2019 at 2:19 AM Daniel Axtens  wrote:
>
> KASAN support on Book3S is a bit tricky to get right:
>
>  - It would be good to support inline instrumentation so as to be able to
>catch stack issues that cannot be caught with outline mode.
>
>  - Inline instrumentation requires a fixed offset.
>
>  - Book3S runs code in real mode after booting. Most notably a lot of KVM
>runs in real mode, and it would be good to be able to instrument it.
>
>  - Because code runs in real mode after boot, the offset has to point to
>valid memory both in and out of real mode.
>
>[For those not immersed in ppc64, in real mode, the top nibble or 2 bits
>(depending on radix/hash mmu) of the address is ignored. The linear
>mapping is placed at 0xc000. This means that a pointer to
>part of the linear mapping will work both in real mode, where it will be
>interpreted as a physical address of the form 0x000..., and out of real
>mode, where it will go via the linear mapping.]
>

How does hash or radix mmu mode effect how many bits are ignored in real mode?

> One approach is just to give up on inline instrumentation. This way all
> checks can be delayed until after everything set is up correctly, and the
> address-to-shadow calculations can be overridden. However, the features and
> speed boost provided by inline instrumentation are worth trying to do
> better.
>
> If _at compile time_ it is known how much contiguous physical memory a
> system has, the top 1/8th of the first block of physical memory can be set
> aside for the shadow. This is a big hammer and comes with 3 big
> consequences:
>
>  - there's no nice way to handle physically discontiguous memory, so only
>the first physical memory block can be used.
>
>  - kernels will simply fail to boot on machines with less memory than
>specified when compiling.
>
>  - kernels running on machines with more memory than specified when
>compiling will simply ignore the extra memory.
>
> Implement and document KASAN this way. The current implementation is Radix
> only.
>
> Despite the limitations, it can still find bugs,
> e.g. http://patchwork.ozlabs.org/patch/1103775/
>
> At the moment, this physical memory limit must be set _even for outline
> mode_. This may be changed in a later series - a different implementation
> could be added for outline mode that dynamically allocates shadow at a
> fixed offset. For example, see https://patchwork.ozlabs.org/patch/795211/
>
> Suggested-by: Michael Ellerman 
> Cc: Balbir Singh  # ppc64 out-of-line radix version
> Cc: Christophe Leroy  # ppc32 version
> Signed-off-by: Daniel Axtens 
>
> ---
> Changes since v2:
>
>  - Address feedback from Christophe around cleanups and docs.
>  - Address feedback from Balbir: at this point I don't have a good solution
>for the issues you identify around the limitations of the inline 
> implementation
>but I think that it's worth trying to get the stack instrumentation 
> support.
>I'm happy to have an alternative and more flexible outline mode - I had
>envisoned this would be called 'lightweight' mode as it imposes fewer 
> restrictions.
>I've linked to your implementation. I think it's best to add it in a 
> follow-up series.
>  - Made the default PHYS_MEM_SIZE_FOR_KASAN value 1024MB. I think most people 
> have
>guests with at least that much memory in the Radix 64s case so it's a much
>saner default - it means that if you just turn on KASAN without reading the
>docs you're much more likely to have a bootable kernel, which you will 
> never
>have if the value is set to zero! I'm happy to bikeshed the value if we 
> want.
>
> Changes since v1:
>  - Landed kasan vmalloc support upstream
>  - Lots of feedback from Christophe.
>
> Changes since the rfc:
>
>  - Boots real and virtual hardware, kvm works.
>
>  - disabled reporting when we're checking the stack for exception
>frames. The behaviour isn't wrong, just incompatible with KASAN.
>
>  - Documentation!
>
>  - Dropped old module stuff in favour of KASAN_VMALLOC.
>
> The bugs with ftrace and kuap were due to kernel bloat pushing
> prom_init calls to be done via the plt. Because we did not have
> a relocatable kernel, and they are done very early, this caused
> everything to explode. Compile with CONFIG_RELOCATABLE!
> ---
>  Documentation/dev-tools/kasan.rst |   8 +-
>  Documentation/powerpc/kasan.txt   | 112 +-
>  arch/powerpc/Kconfig  |   3 +
>  arch/powerpc/Kconfig.debug|  21 
>  arch/powerpc/Makefile |  11 ++
>  arch/powerpc/include/asm/book3s/64/hash.h |   4 +
>  arch/powerpc/include/asm/book3s/64/pgtable.h  |   7 ++
>  arch/powerpc/include/asm/book3s/64/radix.h|   5 +
>  arch/powerpc/include/asm/kasan.h  |  21 +++-
>  arch/powerpc/kernel/process.c |   8 ++
>  arch/powerpc/kernel/prom.c 

[PATCH v3] powerpc/mm: Remove kvm radix prefetch workaround for Power9 DD2.2

[Jordan Niethe]

Commit a25bd72badfa ("powerpc/mm/radix: Workaround prefetch issue with
KVM") introduced a number of workarounds as coming out of a guest with
the mmu enabled would make the cpu would start running in hypervisor
state with the PID value from the guest. The cpu will then start
prefetching for the hypervisor with that PID value.

In Power9 DD2.2 the cpu behaviour was modified to fix this. When
accessing Quadrant 0 in hypervisor mode with LPID != 0 prefetching will
not be performed. This means that we can get rid of the workarounds for
Power9 DD2.2 and later revisions. Add a new cpu feature
CPU_FTR_P9_RADIX_PREFETCH_BUG to indicate if the workarounds are needed.

Signed-off-by: Jordan Niethe 
---
v2: Use a cpu feature instead of open coding the PVR check
v3: Put parentheses around CPU_FTRS_POWER9_DD2_0 value
---
 arch/powerpc/include/asm/cputable.h  |  7 +--
 arch/powerpc/kernel/dt_cpu_ftrs.c| 13 -
 arch/powerpc/kvm/book3s_hv_rmhandlers.S  |  2 ++
 arch/powerpc/mm/book3s64/radix_pgtable.c |  6 +-
 arch/powerpc/mm/book3s64/radix_tlb.c |  3 +++
 5 files changed, 23 insertions(+), 8 deletions(-)

diff --git a/arch/powerpc/include/asm/cputable.h 
b/arch/powerpc/include/asm/cputable.h
index cf00ff0d121d..40a4d3c6fd99 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -212,6 +212,7 @@ static inline void cpu_feature_keys_init(void) { }
 #define CPU_FTR_P9_TLBIE_STQ_BUG   LONG_ASM_CONST(0x4000)
 #define CPU_FTR_P9_TIDR
LONG_ASM_CONST(0x8000)
 #define CPU_FTR_P9_TLBIE_ERAT_BUG  LONG_ASM_CONST(0x0001)
+#define CPU_FTR_P9_RADIX_PREFETCH_BUG  LONG_ASM_CONST(0x0002)
 
 #ifndef __ASSEMBLY__
 
@@ -459,8 +460,10 @@ static inline void cpu_feature_keys_init(void) { }
CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \
CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | CPU_FTR_PKEY | \
CPU_FTR_P9_TLBIE_STQ_BUG | CPU_FTR_P9_TLBIE_ERAT_BUG | 
CPU_FTR_P9_TIDR)
-#define CPU_FTRS_POWER9_DD2_0 CPU_FTRS_POWER9
-#define CPU_FTRS_POWER9_DD2_1 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1)
+#define CPU_FTRS_POWER9_DD2_0 (CPU_FTRS_POWER9 | CPU_FTR_P9_RADIX_PREFETCH_BUG)
+#define CPU_FTRS_POWER9_DD2_1 (CPU_FTRS_POWER9 | \
+  CPU_FTR_P9_RADIX_PREFETCH_BUG | \
+  CPU_FTR_POWER9_DD2_1)
 #define CPU_FTRS_POWER9_DD2_2 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1 | \
   CPU_FTR_P9_TM_HV_ASSIST | \
   CPU_FTR_P9_TM_XER_SO_BUG)
diff --git a/arch/powerpc/kernel/dt_cpu_ftrs.c 
b/arch/powerpc/kernel/dt_cpu_ftrs.c
index 180b3a5d1001..182b4047c1ef 100644
--- a/arch/powerpc/kernel/dt_cpu_ftrs.c
+++ b/arch/powerpc/kernel/dt_cpu_ftrs.c
@@ -727,17 +727,20 @@ static __init void cpufeatures_cpu_quirks(void)
/*
 * Not all quirks can be derived from the cpufeatures device tree.
 */
-   if ((version & 0xefff) == 0x004e0200)
-   ; /* DD2.0 has no feature flag */
-   else if ((version & 0xefff) == 0x004e0201)
+   if ((version & 0xefff) == 0x004e0200) {
+   /* DD2.0 has no feature flag */
+   cur_cpu_spec->cpu_features |= CPU_FTR_P9_RADIX_PREFETCH_BUG;
+   } else if ((version & 0xefff) == 0x004e0201) {
cur_cpu_spec->cpu_features |= CPU_FTR_POWER9_DD2_1;
-   else if ((version & 0xefff) == 0x004e0202) {
+   cur_cpu_spec->cpu_features |= CPU_FTR_P9_RADIX_PREFETCH_BUG;
+   } else if ((version & 0xefff) == 0x004e0202) {
cur_cpu_spec->cpu_features |= CPU_FTR_P9_TM_HV_ASSIST;
cur_cpu_spec->cpu_features |= CPU_FTR_P9_TM_XER_SO_BUG;
cur_cpu_spec->cpu_features |= CPU_FTR_POWER9_DD2_1;
-   } else if ((version & 0x) == 0x004e)
+   } else if ((version & 0x) == 0x004e) {
/* DD2.1 and up have DD2_1 */
cur_cpu_spec->cpu_features |= CPU_FTR_POWER9_DD2_1;
+   }
 
if ((version & 0x) == 0x004e) {
cur_cpu_spec->cpu_features &= ~(CPU_FTR_DAWR);
diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S 
b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
index faebcbb8c4db..72b08bb17200 100644
--- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
+++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
@@ -1793,6 +1793,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
tlbsync
ptesync
 
+BEGIN_FTR_SECTION
/* Radix: Handle the case where the guest used an illegal PID */
LOAD_REG_ADDR(r4, mmu_base_pid)
lwz r3, VCPU_GUEST_PID(r9)
@@ -1822,6 +1823,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
addir7,r7,0x1000
bdnz1b
ptesync
+END_FTR_SECTION_IFSET(CPU_FTR_P9_RADIX_PREFETCH_BUG)
 
 2:
 #endif /* CONFIG_PPC_RADIX_MMU *

[PATCH 10/18] powerpc: Support prefixed instructions in alignment handler

[Jordan Niethe]

Alignment interrupts can be caused by prefixed instructions accessing
memory. In the alignment handler the instruction that caused the
exception is loaded and attempted emulate. If the instruction is a
prefixed instruction load the prefix and suffix to emulate. After
emulating increment the NIP by 8.

Prefixed instructions are not permitted to cross 64-byte boundaries. If
they do the alignment interrupt is invoked with SRR1 BOUNDARY bit set.
If this occurs send a SIGBUS to the offending process if in user mode.
If in kernel mode call bad_page_fault().

Signed-off-by: Jordan Niethe 
---
 arch/powerpc/kernel/align.c |  8 +---
 arch/powerpc/kernel/traps.c | 17 -
 2 files changed, 21 insertions(+), 4 deletions(-)

diff --git a/arch/powerpc/kernel/align.c b/arch/powerpc/kernel/align.c
index 245e79792a01..53493404c25c 100644
--- a/arch/powerpc/kernel/align.c
+++ b/arch/powerpc/kernel/align.c
@@ -293,7 +293,7 @@ static int emulate_spe(struct pt_regs *regs, unsigned int 
reg,
 
 int fix_alignment(struct pt_regs *regs)
 {
-   unsigned int instr;
+   unsigned int instr, sufx;
struct instruction_op op;
int r, type;
 
@@ -303,13 +303,15 @@ int fix_alignment(struct pt_regs *regs)
 */
CHECK_FULL_REGS(regs);
 
-   if (unlikely(__get_user(instr, (unsigned int __user *)regs->nip)))
+   if (unlikely(__get_user_instr(instr, sufx,
+(unsigned int __user *)regs->nip)))
return -EFAULT;
if ((regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE)) {
/* We don't handle PPC little-endian any more... */
if (cpu_has_feature(CPU_FTR_PPC_LE))
return -EIO;
instr = swab32(instr);
+   sufx = swab32(sufx);
}
 
 #ifdef CONFIG_SPE
@@ -334,7 +336,7 @@ int fix_alignment(struct pt_regs *regs)
if ((instr & 0xfc0006fe) == (PPC_INST_COPY & 0xfc0006fe))
return -EIO;
 
-   r = analyse_instr(, regs, instr, 0);
+   r = analyse_instr(, regs, instr, sufx);
if (r < 0)
return -EINVAL;
 
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 014ff0701f24..8e26f464 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -583,6 +583,8 @@ static inline int check_io_access(struct pt_regs *regs)
 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
 #define REASON_PRIVILEGED  ESR_PPR
 #define REASON_TRAPESR_PTR
+#define REASON_PREFIXED0
+#define REASON_BOUNDARY0
 
 /* single-step stuff */
 #define single_stepping(regs)  (current->thread.debug.dbcr0 & DBCR0_IC)
@@ -597,6 +599,8 @@ static inline int check_io_access(struct pt_regs *regs)
 #define REASON_ILLEGAL SRR1_PROGILL
 #define REASON_PRIVILEGED  SRR1_PROGPRIV
 #define REASON_TRAPSRR1_PROGTRAP
+#define REASON_PREFIXEDSRR1_PREFIXED
+#define REASON_BOUNDARYSRR1_BOUNDARY
 
 #define single_stepping(regs)  ((regs)->msr & MSR_SE)
 #define clear_single_step(regs)((regs)->msr &= ~MSR_SE)
@@ -1593,11 +1597,20 @@ void alignment_exception(struct pt_regs *regs)
 {
enum ctx_state prev_state = exception_enter();
int sig, code, fixed = 0;
+   unsigned long  reason;
 
/* We restore the interrupt state now */
if (!arch_irq_disabled_regs(regs))
local_irq_enable();
 
+   reason = get_reason(regs);
+
+   if (reason & REASON_BOUNDARY) {
+   sig = SIGBUS;
+   code = BUS_ADRALN;
+   goto bad;
+   }
+
if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT))
goto bail;
 
@@ -1606,7 +1619,8 @@ void alignment_exception(struct pt_regs *regs)
fixed = fix_alignment(regs);
 
if (fixed == 1) {
-   regs->nip += 4; /* skip over emulated instruction */
+   /* skip over emulated instruction */
+   regs->nip += (reason & REASON_PREFIXED) ? 8 : 4;
emulate_single_step(regs);
goto bail;
}
@@ -1619,6 +1633,7 @@ void alignment_exception(struct pt_regs *regs)
sig = SIGBUS;
code = BUS_ADRALN;
}
+bad:
if (user_mode(regs))
_exception(sig, regs, code, regs->dar);
else
-- 
2.20.1

[PATCH 13/18] powerpc/xmon: Dump prefixed instructions

[Jordan Niethe]

Currently when xmon is dumping instructions it reads a word at a time
and then prints that instruction (either as a hex number or by
disassembling it). For prefixed instructions it would be nice to show
its prefix and suffix as together. Use read_instr() so that if a prefix
is encountered its suffix is loaded too. Then print these in the form:
prefix:suffix
Xmon uses the disassembly routines from GNU binutils. These currently do
not support prefixed instructions so we will not disassemble the
prefixed instructions yet.

Signed-off-by: Jordan Niethe 
---
 arch/powerpc/xmon/xmon.c | 50 +++-
 1 file changed, 39 insertions(+), 11 deletions(-)

diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index 93259a06eadc..dc8b1c7b3e1b 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -2900,6 +2900,21 @@ prdump(unsigned long adrs, long ndump)
}
 }
 
+static bool instrs_are_equal(unsigned long insta, unsigned long sufxa,
+unsigned long instb, unsigned long sufxb)
+{
+   if (insta != instb)
+   return false;
+
+   if (!IS_PREFIX(insta) && !IS_PREFIX(instb))
+   return true;
+
+   if (IS_PREFIX(insta) && IS_PREFIX(instb))
+   return sufxa == sufxb;
+
+   return false;
+}
+
 typedef int (*instruction_dump_func)(unsigned long inst, unsigned long addr);
 
 static int
@@ -2908,12 +2923,11 @@ generic_inst_dump(unsigned long adr, long count, int 
praddr,
 {
int nr, dotted;
unsigned long first_adr;
-   unsigned int inst, last_inst = 0;
-   unsigned char val[4];
+   unsigned int inst, sufx, last_inst = 0, last_sufx = 0;
 
dotted = 0;
-   for (first_adr = adr; count > 0; --count, adr += 4) {
-   nr = mread(adr, val, 4);
+   for (first_adr = adr; count > 0; --count, adr += nr) {
+   nr = read_instr(adr, , );
if (nr == 0) {
if (praddr) {
const char *x = fault_chars[fault_type];
@@ -2921,8 +2935,9 @@ generic_inst_dump(unsigned long adr, long count, int 
praddr,
}
break;
}
-   inst = GETWORD(val);
-   if (adr > first_adr && inst == last_inst) {
+   if (adr > first_adr && instrs_are_equal(inst, sufx,
+   last_inst,
+   last_sufx)) {
if (!dotted) {
printf(" ...\n");
dotted = 1;
@@ -2931,11 +2946,24 @@ generic_inst_dump(unsigned long adr, long count, int 
praddr,
}
dotted = 0;
last_inst = inst;
-   if (praddr)
-   printf(REG"  %.8x", adr, inst);
-   printf("\t");
-   dump_func(inst, adr);
-   printf("\n");
+   last_sufx = sufx;
+   if (IS_PREFIX(inst)) {
+   if (praddr)
+   printf(REG"  %.8x:%.8x", adr, inst, sufx);
+   printf("\t");
+   /*
+* Just use this until binutils ppc disassembly
+* prints prefixed instructions.
+*/
+   printf("%.8x:%.8x", inst, sufx);
+   printf("\n");
+   } else {
+   if (praddr)
+   printf(REG"  %.8x", adr, inst);
+   printf("\t");
+   dump_func(inst, adr);
+   printf("\n");
+   }
}
return adr - first_adr;
 }
-- 
2.20.1

[PATCH 06/18] powerpc sstep: Add support for prefixed integer load/stores

[Jordan Niethe]

This adds emulation support for the following prefixed integer
load/stores:
  * Prefixed Load Byte and Zero (plbz)
  * Prefixed Load Halfword and Zero (plhz)
  * Prefixed Load Halfword Algebraic (plha)
  * Prefixed Load Word and Zero (plwz)
  * Prefixed Load Word Algebraic (plwa)
  * Prefixed Load Doubleword (pld)
  * Prefixed Store Byte (pstb)
  * Prefixed Store Halfword (psth)
  * Prefixed Store Word (pstw)
  * Prefixed Store Doubleword (pstd)
  * Prefixed Load Quadword (plq)
  * Prefixed Store Quadword (pstq)

Signed-off-by: Jordan Niethe 
---
 arch/powerpc/lib/sstep.c | 110 +++
 1 file changed, 110 insertions(+)

diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index ade3f5eba2e5..4f5ad1f602d8 100644
--- a/arch/powerpc/lib/sstep.c
+++ b/arch/powerpc/lib/sstep.c
@@ -187,6 +187,43 @@ static nokprobe_inline unsigned long xform_ea(unsigned int 
instr,
return ea;
 }
 
+/*
+ * Calculate effective address for a MLS:D-form / 8LS:D-form prefixed 
instruction
+ */
+static nokprobe_inline unsigned long mlsd_8lsd_ea(unsigned int instr,
+ unsigned int sufx,
+ const struct pt_regs *regs)
+{
+   int ra, prefix_r;
+   unsigned int  dd;
+   unsigned long ea, d0, d1, d;
+
+   prefix_r = instr & (1ul << 20);
+   ra = (sufx >> 16) & 0x1f;
+
+   d0 = instr & 0x3;
+   d1 = sufx & 0x;
+   d = (d0 << 16) | d1;
+
+   /*
+* sign extend a 34 bit number
+*/
+   dd = (unsigned int) (d >> 2);
+   ea = (signed int) dd;
+   ea = (ea << 2) | (d & 0x3);
+
+   if (!prefix_r && ra)
+   ea += regs->gpr[ra];
+   else if (!prefix_r && !ra)
+   ; /* Leave ea as is */
+   else if (prefix_r && !ra)
+   ea += regs->nip;
+   else if (prefix_r && ra)
+   ; /* Invalid form. Should already be checked for by caller! */
+
+   return ea;
+}
+
 /*
  * Return the largest power of 2, not greater than sizeof(unsigned long),
  * such that x is a multiple of it.
@@ -1166,6 +1203,7 @@ int analyse_instr(struct instruction_op *op, const struct 
pt_regs *regs,
  unsigned int instr, unsigned int sufx)
 {
unsigned int opcode, ra, rb, rc, rd, spr, u;
+   unsigned int sufxopcode, prefixtype, prefix_r;
unsigned long int imm;
unsigned long int val, val2;
unsigned int mb, me, sh;
@@ -2652,6 +2690,78 @@ int analyse_instr(struct instruction_op *op, const 
struct pt_regs *regs,
 
}
 
+/*
+ * Prefixed instructions
+ */
+   switch (opcode) {
+   case 1:
+   prefix_r = instr & (1ul << 20);
+   ra = (sufx >> 16) & 0x1f;
+   op->update_reg = ra;
+   rd = (sufx >> 21) & 0x1f;
+   op->reg = rd;
+   op->val = regs->gpr[rd];
+
+   sufxopcode = sufx >> 26;
+   prefixtype = (instr >> 24) & 0x3;
+   switch (prefixtype) {
+   case 0: /* Type 00  Eight-Byte Load/Store */
+   if (prefix_r && ra)
+   break;
+   op->ea = mlsd_8lsd_ea(instr, sufx, regs);
+   switch (sufxopcode) {
+   case 41:/* plwa */
+   op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 4);
+   break;
+   case 56:/* plq */
+   op->type = MKOP(LOAD, PREFIXED, 16);
+   break;
+   case 57:/* pld */
+   op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 8);
+   break;
+   case 60:/* stq */
+   op->type = MKOP(STORE, PREFIXED, 16);
+   break;
+   case 61:/* pstd */
+   op->type = MKOP(STORE, PREFIXED | SIGNEXT, 8);
+   break;
+   }
+   break;
+   case 1: /* Type 01 Modified Register-to-Register */
+   break;
+   case 2: /* Type 10 Modified Load/Store */
+   if (prefix_r && ra)
+   break;
+   op->ea = mlsd_8lsd_ea(instr, sufx, regs);
+   switch (sufxopcode) {
+   case 32:/* plwz */
+   op->type = MKOP(LOAD, PREFIXED, 4);
+   break;
+   case 34:/* plbz */
+   op->

[PATCH 09/18] powerpc sstep: Add support for prefixed fixed-point arithmetic

[Jordan Niethe]

This adds emulation support for the following prefixed Fixed-Point
Arithmetic instructions:
  * Prefixed Add Immediate (paddi)

Signed-off-by: Jordan Niethe 
---
 arch/powerpc/lib/sstep.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index 9ae8d177b67f..1bb0c79cb774 100644
--- a/arch/powerpc/lib/sstep.c
+++ b/arch/powerpc/lib/sstep.c
@@ -2776,6 +2776,10 @@ int analyse_instr(struct instruction_op *op, const 
struct pt_regs *regs,
break;
op->ea = mlsd_8lsd_ea(instr, sufx, regs);
switch (sufxopcode) {
+   case 14:/* paddi */
+   op->type = COMPUTE | PREFIXED;
+   op->val = op->ea;
+   goto compute_done;
case 32:/* plwz */
op->type = MKOP(LOAD, PREFIXED, 4);
break;
-- 
2.20.1

[PATCH 11/18] powerpc/traps: Check for prefixed instructions in facility_unavailable_exception()

[Jordan Niethe]

If prefixed instructions are made unavailable by the [H]FSCR, attempting
to use them will cause a facility unavailable exception. Add "PREFIX" to
the facility_strings[].

Currently there are no prefixed instructions that are actually emulated
by emulate_instruction() within facility_unavailable_exception().
However, when caused by a prefixed instructions the SRR1 PREFIXED bit is
set. Prepare for dealing with emulated prefixed instructions by checking
for this bit.

Signed-off-by: Jordan Niethe 
---
 arch/powerpc/kernel/traps.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 8e26f464..92057830b9b6 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -1726,6 +1726,7 @@ void facility_unavailable_exception(struct pt_regs *regs)
[FSCR_TAR_LG] = "TAR",
[FSCR_MSGP_LG] = "MSGP",
[FSCR_SCV_LG] = "SCV",
+   [FSCR_PREFIX_LG] = "PREFIX",
};
char *facility = "unknown";
u64 value;
-- 
2.20.1

[PATCH 04/18] powerpc: Rename Bit 35 of SRR1 to indicate new purpose

[Jordan Niethe]

Bit 35 of SRR1 is called SRR1_ISI_N_OR_G. This name comes from it being
used to indicate that an ISI was due to the access being no-exec or
guarded. A future ISA version adds another purpose. Now it is also set if there
is a access in a cache-inhibited location for prefixed instruction.
Rename from SRR1_ISI_N_OR_G -> SRR1_ISI_N_G_OR_CIP to reflected this new
role.

Signed-off-by: Jordan Niethe 
---
 arch/powerpc/include/asm/reg.h  | 2 +-
 arch/powerpc/kvm/book3s_hv_nested.c | 2 +-
 arch/powerpc/kvm/book3s_hv_rm_mmu.c | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 0a6d39fb4769..d3d8212603cb 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -750,7 +750,7 @@
 #define SPRN_SRR0  0x01A   /* Save/Restore Register 0 */
 #define SPRN_SRR1  0x01B   /* Save/Restore Register 1 */
 #define   SRR1_ISI_NOPT0x4000 /* ISI: Not found in hash */
-#define   SRR1_ISI_N_OR_G  0x1000 /* ISI: Access is no-exec or G */
+#define   SRR1_ISI_N_G_OR_CIP  0x1000 /* ISI: Access is no-exec or G or CI 
for a prefixed instruction */
 #define   SRR1_ISI_PROT0x0800 /* ISI: Other protection 
fault */
 #define   SRR1_WAKEMASK0x0038 /* reason for wakeup */
 #define   SRR1_WAKEMASK_P8 0x003c /* reason for wakeup on POWER8 and 9 
*/
diff --git a/arch/powerpc/kvm/book3s_hv_nested.c 
b/arch/powerpc/kvm/book3s_hv_nested.c
index cdf30c6eaf54..32798ee76f27 100644
--- a/arch/powerpc/kvm/book3s_hv_nested.c
+++ b/arch/powerpc/kvm/book3s_hv_nested.c
@@ -1169,7 +1169,7 @@ static int kvmhv_translate_addr_nested(struct kvm_vcpu 
*vcpu,
} else if (vcpu->arch.trap == BOOK3S_INTERRUPT_H_INST_STORAGE) {
/* Can we execute? */
if (!gpte_p->may_execute) {
-   flags |= SRR1_ISI_N_OR_G;
+   flags |= SRR1_ISI_N_G_OR_CIP;
goto forward_to_l1;
}
} else {
diff --git a/arch/powerpc/kvm/book3s_hv_rm_mmu.c 
b/arch/powerpc/kvm/book3s_hv_rm_mmu.c
index 220305454c23..b53a9f1c1a46 100644
--- a/arch/powerpc/kvm/book3s_hv_rm_mmu.c
+++ b/arch/powerpc/kvm/book3s_hv_rm_mmu.c
@@ -1260,7 +1260,7 @@ long kvmppc_hpte_hv_fault(struct kvm_vcpu *vcpu, unsigned 
long addr,
status &= ~DSISR_NOHPTE;/* DSISR_NOHPTE == SRR1_ISI_NOPT */
if (!data) {
if (gr & (HPTE_R_N | HPTE_R_G))
-   return status | SRR1_ISI_N_OR_G;
+   return status | SRR1_ISI_N_G_OR_CIP;
if (!hpte_read_permission(pp, slb_v & key))
return status | SRR1_ISI_PROT;
} else if (status & DSISR_ISSTORE) {
-- 
2.20.1

[PATCH 16/18] powerpc/hw_breakpoints: Initial support for prefixed instructions

[Jordan Niethe]

Currently when getting an instruction to emulate in
hw_breakpoint_handler() we do not load the suffix of a prefixed
instruction. Ensure we load the suffix if the instruction we need to
emulate is a prefixed instruction.

Signed-off-by: Jordan Niethe 
---
 arch/powerpc/kernel/hw_breakpoint.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/powerpc/kernel/hw_breakpoint.c 
b/arch/powerpc/kernel/hw_breakpoint.c
index f4530961998c..f7e1af8b9eae 100644
--- a/arch/powerpc/kernel/hw_breakpoint.c
+++ b/arch/powerpc/kernel/hw_breakpoint.c
@@ -240,15 +240,15 @@ dar_range_overlaps(unsigned long dar, int size, struct 
arch_hw_breakpoint *info)
 static bool stepping_handler(struct pt_regs *regs, struct perf_event *bp,
 struct arch_hw_breakpoint *info)
 {
-   unsigned int instr = 0;
+   unsigned int instr = 0, sufx = 0;
int ret, type, size;
struct instruction_op op;
unsigned long addr = info->address;
 
-   if (__get_user_inatomic(instr, (unsigned int *)regs->nip))
+   if (__get_user_instr_inatomic(instr, sufx, (unsigned int *)regs->nip))
goto fail;
 
-   ret = analyse_instr(, regs, instr, 0);
+   ret = analyse_instr(, regs, instr, sufx);
type = GETTYPE(op.type);
size = GETSIZE(op.type);
 
@@ -272,7 +272,7 @@ static bool stepping_handler(struct pt_regs *regs, struct 
perf_event *bp,
return false;
}
 
-   if (!emulate_step(regs, instr, 0))
+   if (!emulate_step(regs, instr, sufx))
goto fail;
 
return true;
-- 
2.20.1

[PATCH 17/18] powerpc: Add prefix support to mce_find_instr_ea_and_pfn()

[Jordan Niethe]

mce_find_instr_ea_and_pfn analyses an instruction to determine the
effective address that caused the machine check. Update this to load and
pass the suffix to analyse_instr for prefixed instructions.

Signed-off-by: Jordan Niethe 
---
 arch/powerpc/kernel/mce_power.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/kernel/mce_power.c b/arch/powerpc/kernel/mce_power.c
index d862bb549158..68e81fcbdf07 100644
--- a/arch/powerpc/kernel/mce_power.c
+++ b/arch/powerpc/kernel/mce_power.c
@@ -365,7 +365,7 @@ static int mce_find_instr_ea_and_phys(struct pt_regs *regs, 
uint64_t *addr,
 * in real-mode is tricky and can lead to recursive
 * faults
 */
-   int instr;
+   int instr, sufx = 0;
unsigned long pfn, instr_addr;
struct instruction_op op;
struct pt_regs tmp = *regs;
@@ -374,7 +374,9 @@ static int mce_find_instr_ea_and_phys(struct pt_regs *regs, 
uint64_t *addr,
if (pfn != ULONG_MAX) {
instr_addr = (pfn << PAGE_SHIFT) + (regs->nip & ~PAGE_MASK);
instr = *(unsigned int *)(instr_addr);
-   if (!analyse_instr(, , instr, 0)) {
+   if (IS_PREFIX(instr))
+   sufx = *(unsigned int *)(instr_addr + 4);
+   if (!analyse_instr(, , instr, sufx)) {
pfn = addr_to_pfn(regs, op.ea);
*addr = op.ea;
*phys_addr = (pfn << PAGE_SHIFT);
-- 
2.20.1

[PATCH 05/18] powerpc sstep: Prepare to support prefixed instructions

[Jordan Niethe]

Currently all instructions are a single word long. A future ISA version
will include prefixed instructions which have a double word length. The
functions used for analysing and emulating instructions need to be
modified so that they can handle these new instruction types.

A prefixed instruction is a word prefix followed by a word suffix. All
prefixes uniquely have the primary op-code 1. Suffixes may be valid word
instructions or instructions that only exist as suffixes.

In handling prefixed instructions it will be convenient to treat the
suffix and prefix as separate words. To facilitate this modify
analyse_instr() and emulate_step() to take a take a suffix as a
parameter. For word instructions it does not matter what is passed in
here - it will be ignored.

We also define a new flag, PREFIXED, to be used in instruction_op:type.
This flag will indicate when emulating an analysed instruction if the
NIP should be advanced by word length or double word length.

The callers of analyse_instr() and emulate_step() will need their own
changes to be able to support prefixed instructions. For now modify them
to pass in 0 as a suffix.

Note that at this point no prefixed instructions are emulated or
analysed - this is just making it possible to do so.

Signed-off-by: Jordan Niethe 
---
 arch/powerpc/include/asm/ppc-opcode.h |  3 +++
 arch/powerpc/include/asm/sstep.h  |  8 +--
 arch/powerpc/include/asm/uaccess.h| 30 +++
 arch/powerpc/kernel/align.c   |  2 +-
 arch/powerpc/kernel/hw_breakpoint.c   |  4 ++--
 arch/powerpc/kernel/kprobes.c |  2 +-
 arch/powerpc/kernel/mce_power.c   |  2 +-
 arch/powerpc/kernel/optprobes.c   |  2 +-
 arch/powerpc/kernel/uprobes.c |  2 +-
 arch/powerpc/kvm/emulate_loadstore.c  |  2 +-
 arch/powerpc/lib/sstep.c  | 12 ++-
 arch/powerpc/lib/test_emulate_step.c  | 30 +--
 arch/powerpc/xmon/xmon.c  |  4 ++--
 13 files changed, 71 insertions(+), 32 deletions(-)

diff --git a/arch/powerpc/include/asm/ppc-opcode.h 
b/arch/powerpc/include/asm/ppc-opcode.h
index c1df75edde44..a1dfa4bdd22f 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -377,6 +377,9 @@
 #define PPC_INST_VCMPEQUD  0x10c7
 #define PPC_INST_VCMPEQUB  0x1006
 
+/* macro to check if a word is a prefix */
+#define IS_PREFIX(x) (((x) >> 26) == 1)
+
 /* macros to insert fields into opcodes */
 #define ___PPC_RA(a)   (((a) & 0x1f) << 16)
 #define ___PPC_RB(b)   (((b) & 0x1f) << 11)
diff --git a/arch/powerpc/include/asm/sstep.h b/arch/powerpc/include/asm/sstep.h
index 769f055509c9..6d4cb602e231 100644
--- a/arch/powerpc/include/asm/sstep.h
+++ b/arch/powerpc/include/asm/sstep.h
@@ -89,6 +89,9 @@ enum instruction_type {
 #define VSX_LDLEFT 4   /* load VSX register from left */
 #define VSX_CHECK_VEC  8   /* check MSR_VEC not MSR_VSX for reg >= 32 */
 
+/* Prefixed flag, ORed in with type */
+#define PREFIXED   0x800
+
 /* Size field in type word */
 #define SIZE(n)((n) << 12)
 #define GETSIZE(w) ((w) >> 12)
@@ -132,7 +135,7 @@ union vsx_reg {
  * otherwise.
  */
 extern int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
-unsigned int instr);
+unsigned int instr, unsigned int sufx);
 
 /*
  * Emulate an instruction that can be executed just by updating
@@ -149,7 +152,8 @@ void emulate_update_regs(struct pt_regs *reg, struct 
instruction_op *op);
  * 0 if it could not be emulated, or -1 for an instruction that
  * should not be emulated (rfid, mtmsrd clearing MSR_RI, etc.).
  */
-extern int emulate_step(struct pt_regs *regs, unsigned int instr);
+extern int emulate_step(struct pt_regs *regs, unsigned int instr,
+   unsigned int sufx);
 
 /*
  * Emulate a load or store instruction by reading/writing the
diff --git a/arch/powerpc/include/asm/uaccess.h 
b/arch/powerpc/include/asm/uaccess.h
index 15002b51ff18..bc585399e0c7 100644
--- a/arch/powerpc/include/asm/uaccess.h
+++ b/arch/powerpc/include/asm/uaccess.h
@@ -423,4 +423,34 @@ extern long __copy_from_user_flushcache(void *dst, const 
void __user *src,
 extern void memcpy_page_flushcache(char *to, struct page *page, size_t offset,
   size_t len);
 
+/*
+ * When reading an instruction iff it is a prefix, the suffix needs to be also
+ * loaded.
+ */
+#define __get_user_instr(x, y, ptr)\
+({ \
+   long __gui_ret = 0; \
+   y = 0;  \
+   __gui_ret = __get_user(x, ptr); \
+   if (!__gui_ret) {   \
+   if (IS_PREFIX(x))   \
+   

[PATCH 08/18] powerpc sstep: Add support for prefixed VSX load/stores

[Jordan Niethe]

This adds emulation support for the following prefixed VSX load/stores:
  * Prefixed Load VSX Scalar Doubleword (plxsd)
  * Prefixed Load VSX Scalar Single-Precision (plxssp)
  * Prefixed Load VSX Vector [0|1]  (plxv, plxv0, plxv1)
  * Prefixed Store VSX Scalar Doubleword (pstxsd)
  * Prefixed Store VSX Scalar Single-Precision (pstxssp)
  * Prefixed Store VSX Vector [0|1] (pstxv, pstxv0, pstxv1)

Signed-off-by: Jordan Niethe 
---
 arch/powerpc/lib/sstep.c | 42 
 1 file changed, 42 insertions(+)

diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index 9113b9a21ae9..9ae8d177b67f 100644
--- a/arch/powerpc/lib/sstep.c
+++ b/arch/powerpc/lib/sstep.c
@@ -2713,6 +2713,48 @@ int analyse_instr(struct instruction_op *op, const 
struct pt_regs *regs,
case 41:/* plwa */
op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 4);
break;
+   case 42:/* plxsd */
+   op->reg = rd + 32;
+   op->type = MKOP(LOAD_VSX, PREFIXED, 8);
+   op->element_size = 8;
+   op->vsx_flags = VSX_CHECK_VEC;
+   break;
+   case 43:/* plxssp */
+   op->reg = rd + 32;
+   op->type = MKOP(LOAD_VSX, PREFIXED, 4);
+   op->element_size = 8;
+   op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
+   break;
+   case 46:/* pstxsd */
+   op->reg = rd + 32;
+   op->type = MKOP(STORE_VSX, PREFIXED, 8);
+   op->element_size = 8;
+   op->vsx_flags = VSX_CHECK_VEC;
+   break;
+   case 47:/* pstxssp */
+   op->reg = rd + 32;
+   op->type = MKOP(STORE_VSX, PREFIXED, 4);
+   op->element_size = 8;
+   op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
+   break;
+   case 51:/* plxv1 */
+   op->reg += 32;
+
+   /* fallthru */
+   case 50:/* plxv0 */
+   op->type = MKOP(LOAD_VSX, PREFIXED, 16);
+   op->element_size = 16;
+   op->vsx_flags = VSX_CHECK_VEC;
+   break;
+   case 55:/* pstxv1 */
+   op->reg = rd + 32;
+
+   /* fallthru */
+   case 54:/* pstxv0 */
+   op->type = MKOP(STORE_VSX, PREFIXED, 16);
+   op->element_size = 16;
+   op->vsx_flags = VSX_CHECK_VEC;
+   break;
case 56:/* plq */
op->type = MKOP(LOAD, PREFIXED, 16);
break;
-- 
2.20.1

[PATCH 07/18] powerpc sstep: Add support for prefixed floating-point load/stores

[Jordan Niethe]

This adds emulation support for the follow prefixed floating-point
load/stores:
  * Prefixed Load Floating-Point Single (plfs)
  * Prefixed Load Floating-Point Double (plfd)
  * Prefixed Store Floating-Point Single (pstfs)
  * Prefixed Store Floating-Point Double (pstfd)

Signed-off-by: Jordan Niethe 
---
 arch/powerpc/lib/sstep.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index 4f5ad1f602d8..9113b9a21ae9 100644
--- a/arch/powerpc/lib/sstep.c
+++ b/arch/powerpc/lib/sstep.c
@@ -2755,6 +2755,18 @@ int analyse_instr(struct instruction_op *op, const 
struct pt_regs *regs,
case 44:/* psth */
op->type = MKOP(STORE, PREFIXED, 2);
break;
+   case 48:/* plfs */
+   op->type = MKOP(LOAD_FP, PREFIXED | FPCONV, 4);
+   break;
+   case 50:/* plfd */
+   op->type = MKOP(LOAD_FP, PREFIXED, 8);
+   break;
+   case 52:/* pstfs */
+   op->type = MKOP(STORE_FP, PREFIXED | FPCONV, 4);
+   break;
+   case 54:/* pstfd */
+   op->type = MKOP(STORE_FP, PREFIXED, 8);
+   break;
}
break;
case 3: /* Type 11 Modified Register-to-Register */
-- 
2.20.1

[PATCH 12/18] powerpc/xmon: Add initial support for prefixed instructions

[Jordan Niethe]

A prefixed instruction is composed of a word prefix and a word suffix.
It does not make sense to be able to have a breakpoint on the suffix of
a prefixed instruction, so make this impossible.

When leaving xmon_core() we check to see if we are currently at a
breakpoint. If this is the case, the breakpoint needs to be proceeded
from. Initially emulate_step() is tried, but if this fails then we need
to execute the saved instruction out of line. The NIP is set to the
address of bpt::instr[] for the current breakpoint.  bpt::instr[]
contains the instruction replaced by the breakpoint, followed by a trap
instruction.  After bpt::instr[0] is executed and we hit the trap we
enter back into xmon_bpt(). We know that if we got here and the offset
indicates we are at bpt::instr[1] then we have just executed out of line
so we can put the NIP back to the instruction after the breakpoint
location and continue on.

Adding prefixed instructions complicates this as the bpt::instr[1] needs
to be used to hold the suffix. To deal with this make bpt::instr[] big
enough for three word instructions.  bpt::instr[2] contains the trap,
and in the case of word instructions pad bpt::instr[1] with a noop.

No support for disassembling prefixed instructions.

Signed-off-by: Jordan Niethe 
---
 arch/powerpc/xmon/xmon.c | 82 ++--
 1 file changed, 71 insertions(+), 11 deletions(-)

diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index f47bd843dc52..93259a06eadc 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -97,7 +97,8 @@ static long *xmon_fault_jmp[NR_CPUS];
 /* Breakpoint stuff */
 struct bpt {
unsigned long   address;
-   unsigned intinstr[2];
+   /* Prefixed instructions can not cross 64-byte boundaries */
+   unsigned intinstr[3] __aligned(64);
atomic_tref_count;
int enabled;
unsigned long   pad;
@@ -113,6 +114,7 @@ static struct bpt bpts[NBPTS];
 static struct bpt dabr;
 static struct bpt *iabr;
 static unsigned bpinstr = 0x7fe8;  /* trap */
+static unsigned nopinstr = 0x6000; /* nop */
 
 #define BP_NUM(bp) ((bp) - bpts + 1)
 
@@ -120,6 +122,7 @@ static unsigned bpinstr = 0x7fe8;   /* trap */
 static int cmds(struct pt_regs *);
 static int mread(unsigned long, void *, int);
 static int mwrite(unsigned long, void *, int);
+static int read_instr(unsigned long, unsigned int *, unsigned int *);
 static int handle_fault(struct pt_regs *);
 static void byterev(unsigned char *, int);
 static void memex(void);
@@ -705,7 +708,8 @@ static int xmon_core(struct pt_regs *regs, int fromipi)
if ((regs->msr & (MSR_IR|MSR_PR|MSR_64BIT)) == (MSR_IR|MSR_64BIT)) {
bp = at_breakpoint(regs->nip);
if (bp != NULL) {
-   int stepped = emulate_step(regs, bp->instr[0], 0);
+   int stepped = emulate_step(regs, bp->instr[0],
+  bp->instr[1]);
if (stepped == 0) {
regs->nip = (unsigned long) >instr[0];
atomic_inc(>ref_count);
@@ -760,8 +764,8 @@ static int xmon_bpt(struct pt_regs *regs)
 
/* Are we at the trap at bp->instr[1] for some bp? */
bp = in_breakpoint_table(regs->nip, );
-   if (bp != NULL && offset == 4) {
-   regs->nip = bp->address + 4;
+   if (bp != NULL && (offset == 4 || offset == 8)) {
+   regs->nip = bp->address + offset;
atomic_dec(>ref_count);
return 1;
}
@@ -863,7 +867,8 @@ static struct bpt *in_breakpoint_table(unsigned long nip, 
unsigned long *offp)
return NULL;
off %= sizeof(struct bpt);
if (off != offsetof(struct bpt, instr[0])
-   && off != offsetof(struct bpt, instr[1]))
+   && off != offsetof(struct bpt, instr[1])
+   && off != offsetof(struct bpt, instr[2]))
return NULL;
*offp = off - offsetof(struct bpt, instr[0]);
return (struct bpt *) (nip - off);
@@ -880,9 +885,18 @@ static struct bpt *new_breakpoint(unsigned long a)
 
for (bp = bpts; bp < [NBPTS]; ++bp) {
if (!bp->enabled && atomic_read(>ref_count) == 0) {
+   /*
+* Prefixed instructions are two words, but regular
+* instructions are only one. Use a nop to pad out the
+* regular instructions so that we can place the trap
+* at the same plac. For prefixed instructions the nop
+* will get overwritten during insert_bpts().
+*/
bp->address = a;
-   bp->instr[1] = bpinstr;
+  

[PATCH 14/18] powerpc/kprobes: Support kprobes on prefixed instructions

[Jordan Niethe]

A prefixed instruction is composed of a word prefix followed by a word
suffix. It does not make sense to be able to have a kprobe on the suffix
of a prefixed instruction, so make this impossible.

Kprobes work by replacing an instruction with a trap and saving that
instruction to be single stepped out of place later. Currently there is
not enough space allocated to keep a prefixed instruction for single
stepping. Increase the amount of space allocated for holding the
instruction copy.

kprobe_post_handler() expects all instructions to be 4 bytes long which
means that it does not function correctly for prefixed instructions.
Add checks for prefixed instructions which will use a length of 8 bytes
instead.

For optprobes we normally patch in loading the instruction we put a
probe on into r4 before calling emulate_step(). We now make space and
patch in loading the suffix into r5 as well.

Signed-off-by: Jordan Niethe 
---
 arch/powerpc/include/asm/kprobes.h   |  5 +--
 arch/powerpc/kernel/kprobes.c| 46 +---
 arch/powerpc/kernel/optprobes.c  | 31 +++
 arch/powerpc/kernel/optprobes_head.S |  6 
 4 files changed, 62 insertions(+), 26 deletions(-)

diff --git a/arch/powerpc/include/asm/kprobes.h 
b/arch/powerpc/include/asm/kprobes.h
index 66b3f2983b22..1f03a1cacb1e 100644
--- a/arch/powerpc/include/asm/kprobes.h
+++ b/arch/powerpc/include/asm/kprobes.h
@@ -38,12 +38,13 @@ extern kprobe_opcode_t optprobe_template_entry[];
 extern kprobe_opcode_t optprobe_template_op_address[];
 extern kprobe_opcode_t optprobe_template_call_handler[];
 extern kprobe_opcode_t optprobe_template_insn[];
+extern kprobe_opcode_t optprobe_template_sufx[];
 extern kprobe_opcode_t optprobe_template_call_emulate[];
 extern kprobe_opcode_t optprobe_template_ret[];
 extern kprobe_opcode_t optprobe_template_end[];
 
-/* Fixed instruction size for powerpc */
-#define MAX_INSN_SIZE  1
+/* Prefixed instructions are two words */
+#define MAX_INSN_SIZE  2
 #define MAX_OPTIMIZED_LENGTH   sizeof(kprobe_opcode_t) /* 4 bytes */
 #define MAX_OPTINSN_SIZE   (optprobe_template_end - 
optprobe_template_entry)
 #define RELATIVEJUMP_SIZE  sizeof(kprobe_opcode_t) /* 4 bytes */
diff --git a/arch/powerpc/kernel/kprobes.c b/arch/powerpc/kernel/kprobes.c
index 7303fe3856cc..aa15b3480385 100644
--- a/arch/powerpc/kernel/kprobes.c
+++ b/arch/powerpc/kernel/kprobes.c
@@ -104,17 +104,30 @@ kprobe_opcode_t *kprobe_lookup_name(const char *name, 
unsigned int offset)
 
 int arch_prepare_kprobe(struct kprobe *p)
 {
+   int len;
int ret = 0;
+   struct kprobe *prev;
kprobe_opcode_t insn = *p->addr;
+   kprobe_opcode_t prfx = *(p->addr - 1);
 
+   preempt_disable();
if ((unsigned long)p->addr & 0x03) {
printk("Attempt to register kprobe at an unaligned address\n");
ret = -EINVAL;
} else if (IS_MTMSRD(insn) || IS_RFID(insn) || IS_RFI(insn)) {
printk("Cannot register a kprobe on rfi/rfid or mtmsr[d]\n");
ret = -EINVAL;
+   } else if (IS_PREFIX(prfx)) {
+   printk("Cannot register a kprobe on the second word of prefixed 
instruction\n");
+   ret = -EINVAL;
+   }
+   prev = get_kprobe(p->addr - 1);
+   if (prev && IS_PREFIX(*prev->ainsn.insn)) {
+   printk("Cannot register a kprobe on the second word of prefixed 
instruction\n");
+   ret = -EINVAL;
}
 
+
/* insn must be on a special executable page on ppc64.  This is
 * not explicitly required on ppc32 (right now), but it doesn't hurt */
if (!ret) {
@@ -124,14 +137,18 @@ int arch_prepare_kprobe(struct kprobe *p)
}
 
if (!ret) {
-   memcpy(p->ainsn.insn, p->addr,
-   MAX_INSN_SIZE * sizeof(kprobe_opcode_t));
+   if (IS_PREFIX(insn))
+   len = MAX_INSN_SIZE * sizeof(kprobe_opcode_t);
+   else
+   len = sizeof(kprobe_opcode_t);
+   memcpy(p->ainsn.insn, p->addr, len);
p->opcode = *p->addr;
flush_icache_range((unsigned long)p->ainsn.insn,
(unsigned long)p->ainsn.insn + sizeof(kprobe_opcode_t));
}
 
p->ainsn.boostable = 0;
+   preempt_enable_no_resched();
return ret;
 }
 NOKPROBE_SYMBOL(arch_prepare_kprobe);
@@ -216,10 +233,11 @@ NOKPROBE_SYMBOL(arch_prepare_kretprobe);
 static int try_to_emulate(struct kprobe *p, struct pt_regs *regs)
 {
int ret;
-   unsigned int insn = *p->ainsn.insn;
+   unsigned int insn = p->ainsn.insn[0];
+   unsigned int sufx = p->ainsn.insn[1];
 
/* regs->nip is also adjusted if emulate_step returns 1 */
-   ret = emulate_step(regs, insn, 0);
+   ret = emulate_step(regs

[PATCH 15/18] powerpc/uprobes: Add support for prefixed instructions

[Jordan Niethe]

Uprobes can execute instructions out of line. Increase the size of the
buffer used  for this so that this works for prefixed instructions. Take
into account the length of prefixed instructions when fixing up the nip.

Signed-off-by: Jordan Niethe 
---
 arch/powerpc/include/asm/uprobes.h | 18 ++
 arch/powerpc/kernel/uprobes.c  |  4 ++--
 2 files changed, 16 insertions(+), 6 deletions(-)

diff --git a/arch/powerpc/include/asm/uprobes.h 
b/arch/powerpc/include/asm/uprobes.h
index 2bbdf27d09b5..5b5e8a3d2f55 100644
--- a/arch/powerpc/include/asm/uprobes.h
+++ b/arch/powerpc/include/asm/uprobes.h
@@ -14,18 +14,28 @@
 
 typedef ppc_opcode_t uprobe_opcode_t;
 
+/*
+ * We have to ensure we have enought space for prefixed instructions, which
+ * are double the size of a word instruction, i.e. 8 bytes. However,
+ * sometimes it is simpler to treat a prefixed instruction like 2 word
+ * instructions.
+ */
 #define MAX_UINSN_BYTES4
-#define UPROBE_XOL_SLOT_BYTES  (MAX_UINSN_BYTES)
+#define UPROBE_XOL_SLOT_BYTES  (2 * MAX_UINSN_BYTES)
 
 /* The following alias is needed for reference from arch-agnostic code */
 #define UPROBE_SWBP_INSN   BREAKPOINT_INSTRUCTION
 #define UPROBE_SWBP_INSN_SIZE  4 /* swbp insn size in bytes */
 
 struct arch_uprobe {
+/*
+ * Ensure there is enough space for prefixed instructions. Prefixed
+ * instructions must not cross 64-byte boundaries.
+ */
union {
-   u32 insn;
-   u32 ixol;
-   };
+   uprobe_opcode_t insn[2];
+   uprobe_opcode_t ixol[2];
+   } __aligned(64);
 };
 
 struct arch_uprobe_task {
diff --git a/arch/powerpc/kernel/uprobes.c b/arch/powerpc/kernel/uprobes.c
index ab1077dc6148..cfcea6946f8b 100644
--- a/arch/powerpc/kernel/uprobes.c
+++ b/arch/powerpc/kernel/uprobes.c
@@ -111,7 +111,7 @@ int arch_uprobe_post_xol(struct arch_uprobe *auprobe, 
struct pt_regs *regs)
 * support doesn't exist and have to fix-up the next instruction
 * to be executed.
 */
-   regs->nip = utask->vaddr + MAX_UINSN_BYTES;
+   regs->nip = utask->vaddr + ((IS_PREFIX(auprobe->insn[0])) ? 8 : 4);
 
user_disable_single_step(current);
return 0;
@@ -173,7 +173,7 @@ bool arch_uprobe_skip_sstep(struct arch_uprobe *auprobe, 
struct pt_regs *regs)
 * emulate_step() returns 1 if the insn was successfully emulated.
 * For all other cases, we need to single-step in hardware.
 */
-   ret = emulate_step(regs, auprobe->insn, 0);
+   ret = emulate_step(regs, auprobe->insn[0], auprobe->insn[1]);
if (ret > 0)
return true;
 
-- 
2.20.1

[PATCH 18/18] powerpc/fault: Use analyse_instr() to check for store with updates to sp

[Jordan Niethe]

A user-mode access to an address a long way below the stack pointer is
only valid if the instruction is one that would update the stack pointer
to the address accessed. This is checked by directly looking at the
instructions op-code. As a result is does not take into account prefixed
instructions. Instead of looking at the instruction our self, use
analyse_instr() determine if this a store instruction that will update
the stack pointer.

Something to note is that there currently are not any store with update
prefixed instructions. Actually there is no plan for prefixed
update-form loads and stores. So this patch is probably not needed but
it might be preferable to use analyse_instr() rather than open coding
the test anyway.

Signed-off-by: Jordan Niethe 
---
 arch/powerpc/mm/fault.c | 39 +++
 1 file changed, 11 insertions(+), 28 deletions(-)

diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
index b5047f9b5dec..cb78b3ca1800 100644
--- a/arch/powerpc/mm/fault.c
+++ b/arch/powerpc/mm/fault.c
@@ -41,37 +41,17 @@
 #include 
 #include 
 #include 
+#include 
 
 /*
  * Check whether the instruction inst is a store using
  * an update addressing form which will update r1.
  */
-static bool store_updates_sp(unsigned int inst)
+static bool store_updates_sp(struct instruction_op *op)
 {
-   /* check for 1 in the rA field */
-   if (((inst >> 16) & 0x1f) != 1)
-   return false;
-   /* check major opcode */
-   switch (inst >> 26) {
-   case OP_STWU:
-   case OP_STBU:
-   case OP_STHU:
-   case OP_STFSU:
-   case OP_STFDU:
-   return true;
-   case OP_STD:/* std or stdu */
-   return (inst & 3) == 1;
-   case OP_31:
-   /* check minor opcode */
-   switch ((inst >> 1) & 0x3ff) {
-   case OP_31_XOP_STDUX:
-   case OP_31_XOP_STWUX:
-   case OP_31_XOP_STBUX:
-   case OP_31_XOP_STHUX:
-   case OP_31_XOP_STFSUX:
-   case OP_31_XOP_STFDUX:
+   if (GETTYPE(op->type) == STORE) {
+   if ((op->type & UPDATE) && (op->update_reg == 1))
return true;
-   }
}
return false;
 }
@@ -278,14 +258,17 @@ static bool bad_stack_expansion(struct pt_regs *regs, 
unsigned long address,
 
if ((flags & FAULT_FLAG_WRITE) && (flags & FAULT_FLAG_USER) &&
access_ok(nip, sizeof(*nip))) {
-   unsigned int inst;
+   unsigned int inst, sufx;
+   struct instruction_op op;
int res;
 
pagefault_disable();
-   res = __get_user_inatomic(inst, nip);
+   res = __get_user_instr_inatomic(inst, sufx, nip);
pagefault_enable();
-   if (!res)
-   return !store_updates_sp(inst);
+   if (!res) {
+   analyse_instr(, uregs, inst, sufx);
+   return !store_updates_sp();
+   }
*must_retry = true;
}
return true;
-- 
2.20.1

[PATCH 02/18] powerpc: Add BOUNDARY SRR1 bit for future ISA version

[Jordan Niethe]

Add the bit definition for when the cause of an alignment exception is a
prefixed instruction that crosses a 64-byte boundary.

Signed-off-by: Jordan Niethe 
---
 arch/powerpc/include/asm/reg.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 521ecbe35507..6f9fcc3d4c82 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -777,6 +777,7 @@
 #define   SRR1_PROGADDR0x0001 /* SRR0 contains subsequent 
addr */
 
 #define   SRR1_MCE_MCP 0x0008 /* Machine check signal caused 
interrupt */
+#define   SRR1_BOUNDARY0x1000 /* Prefixed instruction 
crosses 64-byte boundary */
 
 #define SPRN_HSRR0 0x13A   /* Save/Restore Register 0 */
 #define SPRN_HSRR1 0x13B   /* Save/Restore Register 1 */
-- 
2.20.1

[PATCH 00/18] Initial Prefixed Instruction support

[Jordan Niethe]

A future revision of the ISA will introduce prefixed instructions. A
prefixed instruction is composed of a 4-byte prefix followed by a
4-byte suffix.

All prefixes have the major opcode 1. A prefix will never be a valid
word instruction. A suffix may be an existing word instruction or a new
instruction.

The new instruction formats are:
* Eight-Byte Load/Store Instructions
* Eight-Byte Register-to-Register Instructions
* Modified Load/Store Instructions
* Modified Register-to-Register Instructions

This series enables prefixed instructions and extends the instruction
emulation to support them. Then the places where prefixed instructions
might need to be emulated are updated.

A future series will add prefixed instruction support to guests running
in KVM.

Alistair Popple (1):
  powerpc: Enable Prefixed Instructions

Jordan Niethe (17):
  powerpc: Add BOUNDARY SRR1 bit for future ISA version
  powerpc: Add PREFIXED SRR1 bit for future ISA version
  powerpc: Rename Bit 35 of SRR1 to indicate new purpose
  powerpc sstep: Prepare to support prefixed instructions
  powerpc sstep: Add support for prefixed integer load/stores
  powerpc sstep: Add support for prefixed floating-point load/stores
  powerpc sstep: Add support for prefixed VSX load/stores
  powerpc sstep: Add support for prefixed fixed-point arithmetic
  powerpc: Support prefixed instructions in alignment handler
  powerpc/traps: Check for prefixed instructions in
facility_unavailable_exception()
  powerpc/xmon: Add initial support for prefixed instructions
  powerpc/xmon: Dump prefixed instructions
  powerpc/kprobes: Support kprobes on prefixed instructions
  powerpc/uprobes: Add support for prefixed instructions
  powerpc/hw_breakpoints: Initial support for prefixed instructions
  powerpc: Add prefix support to mce_find_instr_ea_and_pfn()
  powerpc/fault: Use analyse_instr() to check for store with updates to
sp

 arch/powerpc/include/asm/kprobes.h|   5 +-
 arch/powerpc/include/asm/ppc-opcode.h |   3 +
 arch/powerpc/include/asm/reg.h|   7 +-
 arch/powerpc/include/asm/sstep.h  |   8 +-
 arch/powerpc/include/asm/uaccess.h|  30 +
 arch/powerpc/include/asm/uprobes.h|  18 ++-
 arch/powerpc/kernel/align.c   |   8 +-
 arch/powerpc/kernel/dt_cpu_ftrs.c |  23 
 arch/powerpc/kernel/hw_breakpoint.c   |   8 +-
 arch/powerpc/kernel/kprobes.c |  46 +--
 arch/powerpc/kernel/mce_power.c   |   6 +-
 arch/powerpc/kernel/optprobes.c   |  31 +++--
 arch/powerpc/kernel/optprobes_head.S  |   6 +
 arch/powerpc/kernel/traps.c   |  18 ++-
 arch/powerpc/kernel/uprobes.c |   4 +-
 arch/powerpc/kvm/book3s_hv_nested.c   |   2 +-
 arch/powerpc/kvm/book3s_hv_rm_mmu.c   |   2 +-
 arch/powerpc/kvm/emulate_loadstore.c  |   2 +-
 arch/powerpc/lib/sstep.c  | 180 +-
 arch/powerpc/lib/test_emulate_step.c  |  30 ++---
 arch/powerpc/mm/fault.c   |  39 ++
 arch/powerpc/xmon/xmon.c  | 132 +++
 22 files changed, 490 insertions(+), 118 deletions(-)

-- 
2.20.1

[PATCH 03/18] powerpc: Add PREFIXED SRR1 bit for future ISA version

[Jordan Niethe]

Add the bit definition for exceptions caused by prefixed instructions.

Signed-off-by: Jordan Niethe 
---
 arch/powerpc/include/asm/reg.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 6f9fcc3d4c82..0a6d39fb4769 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -778,6 +778,7 @@
 
 #define   SRR1_MCE_MCP 0x0008 /* Machine check signal caused 
interrupt */
 #define   SRR1_BOUNDARY0x1000 /* Prefixed instruction 
crosses 64-byte boundary */
+#define   SRR1_PREFIXED0x2000 /* Exception caused by 
prefixed instruction */
 
 #define SPRN_HSRR0 0x13A   /* Save/Restore Register 0 */
 #define SPRN_HSRR1 0x13B   /* Save/Restore Register 1 */
-- 
2.20.1

[PATCH 01/18] powerpc: Enable Prefixed Instructions

[Jordan Niethe]

From: Alistair Popple 

Prefix instructions have their own FSCR bit which needs to enabled via
a CPU feature. The kernel will save the FSCR for problem state but it
needs to be enabled initially.

Signed-off-by: Alistair Popple 
---
 arch/powerpc/include/asm/reg.h|  3 +++
 arch/powerpc/kernel/dt_cpu_ftrs.c | 23 +++
 2 files changed, 26 insertions(+)

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 0b7900f194c8..521ecbe35507 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -397,6 +397,7 @@
 #define SPRN_RWMR  0x375   /* Region-Weighting Mode Register */
 
 /* HFSCR and FSCR bit numbers are the same */
+#define FSCR_PREFIX_LG 13  /* Enable Prefix Instructions */
 #define FSCR_SCV_LG12  /* Enable System Call Vectored */
 #define FSCR_MSGP_LG   10  /* Enable MSGP */
 #define FSCR_TAR_LG8   /* Enable Target Address Register */
@@ -408,11 +409,13 @@
 #define FSCR_VECVSX_LG 1   /* Enable VMX/VSX  */
 #define FSCR_FP_LG 0   /* Enable Floating Point */
 #define SPRN_FSCR  0x099   /* Facility Status & Control Register */
+#define   FSCR_PREFIX  __MASK(FSCR_PREFIX_LG)
 #define   FSCR_SCV __MASK(FSCR_SCV_LG)
 #define   FSCR_TAR __MASK(FSCR_TAR_LG)
 #define   FSCR_EBB __MASK(FSCR_EBB_LG)
 #define   FSCR_DSCR__MASK(FSCR_DSCR_LG)
 #define SPRN_HFSCR 0xbe/* HV=1 Facility Status & Control Register */
+#define   HFSCR_PREFIX __MASK(FSCR_PREFIX_LG)
 #define   HFSCR_MSGP   __MASK(FSCR_MSGP_LG)
 #define   HFSCR_TAR__MASK(FSCR_TAR_LG)
 #define   HFSCR_EBB__MASK(FSCR_EBB_LG)
diff --git a/arch/powerpc/kernel/dt_cpu_ftrs.c 
b/arch/powerpc/kernel/dt_cpu_ftrs.c
index 180b3a5d1001..f5ca7dd8fbaf 100644
--- a/arch/powerpc/kernel/dt_cpu_ftrs.c
+++ b/arch/powerpc/kernel/dt_cpu_ftrs.c
@@ -553,6 +553,28 @@ static int __init feat_enable_large_ci(struct 
dt_cpu_feature *f)
return 1;
 }
 
+static int __init feat_enable_prefix(struct dt_cpu_feature *f)
+{
+   u64 fscr, hfscr;
+
+   if (f->usable_privilege & USABLE_HV) {
+   hfscr = mfspr(SPRN_HFSCR);
+   hfscr |= HFSCR_PREFIX;
+   mtspr(SPRN_HFSCR, hfscr);
+   }
+
+   if (f->usable_privilege & USABLE_OS) {
+   fscr = mfspr(SPRN_FSCR);
+   fscr |= FSCR_PREFIX;
+   mtspr(SPRN_FSCR, fscr);
+
+   if (f->usable_privilege & USABLE_PR)
+   current->thread.fscr |= FSCR_PREFIX;
+   }
+
+   return 1;
+}
+
 struct dt_cpu_feature_match {
const char *name;
int (*enable)(struct dt_cpu_feature *f);
@@ -626,6 +648,7 @@ static struct dt_cpu_feature_match __initdata
{"vector-binary128", feat_enable, 0},
{"vector-binary16", feat_enable, 0},
{"wait-v3", feat_enable, 0},
+   {"prefix-instructions", feat_enable_prefix, 0},
 };
 
 static bool __initdata using_dt_cpu_ftrs;
-- 
2.20.1

[PATCH] powerpc/mm: Remove kvm radix prefetch workaround for Power9 DD2.2

[Jordan Niethe]

Commit a25bd72badfa ("powerpc/mm/radix: Workaround prefetch issue with
KVM") introduced a number of workarounds as coming out of a guest with
the mmu enabled would make the cpu would start running in hypervisor
state with the PID value from the guest. The cpu will then start
prefetching for the hypervisor with that PID value.

In Power9 DD2.2 the cpu behaviour was modified to fix this. When
accessing Quadrant 0 in hypervisor mode with LPID != 0 prefetching will
not be performed. This means that we can get rid of the workarounds for
Power9 DD2.2 and later revisions.

Signed-off-by: Jordan Niethe 
---
 arch/powerpc/kvm/book3s_hv_rmhandlers.S  |  9 +
 arch/powerpc/mm/book3s64/radix_pgtable.c | 18 --
 arch/powerpc/mm/book3s64/radix_tlb.c |  5 +
 3 files changed, 26 insertions(+), 6 deletions(-)

diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S 
b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
index faebcbb8c4db..6bbc5fbc7ea9 100644
--- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
+++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
@@ -1793,6 +1793,15 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
tlbsync
ptesync
 
+   /* We do not need this work around from POWER9 DD2.2 and onwards */
+   mfspr   r3, SPRN_PVR
+   srwir6, r3, 16
+   cmpwi   cr0, r6, PVR_POWER9
+   bne cr0, 2f
+   andi.   r3, r3, 0xfff
+   cmpwi   cr0, r3, 0x202
+   bge cr0, 2f
+
/* Radix: Handle the case where the guest used an illegal PID */
LOAD_REG_ADDR(r4, mmu_base_pid)
lwz r3, VCPU_GUEST_PID(r9)
diff --git a/arch/powerpc/mm/book3s64/radix_pgtable.c 
b/arch/powerpc/mm/book3s64/radix_pgtable.c
index 6ee17d09649c..1f280124994e 100644
--- a/arch/powerpc/mm/book3s64/radix_pgtable.c
+++ b/arch/powerpc/mm/book3s64/radix_pgtable.c
@@ -312,6 +312,7 @@ static void __init radix_init_pgtable(void)
 {
unsigned long rts_field;
struct memblock_region *reg;
+   unsigned int pvr;
 
/* We don't support slb for radix */
mmu_slb_size = 0;
@@ -336,24 +337,29 @@ static void __init radix_init_pgtable(void)
}
 
/* Find out how many PID bits are supported */
+   pvr = mfspr(SPRN_PVR);
if (cpu_has_feature(CPU_FTR_HVMODE)) {
if (!mmu_pid_bits)
mmu_pid_bits = 20;
 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
/*
-* When KVM is possible, we only use the top half of the
-* PID space to avoid collisions between host and guest PIDs
-* which can cause problems due to prefetch when exiting the
-* guest with AIL=3
+* Before Power9 DD2.2, when KVM is possible, we only use the
+* top half of the PID space to avoid collisions between host
+* and guest PIDs which can cause problems due to prefetch when
+* exiting the guest with AIL=3
 */
-   mmu_base_pid = 1 << (mmu_pid_bits - 1);
+   if (PVR_VER(pvr) == PVR_POWER9 && ((0xfff & pvr) < 0x202))
+   mmu_base_pid = 1;
+   else
+   mmu_base_pid = 1 << (mmu_pid_bits - 1);
 #else
mmu_base_pid = 1;
 #endif
} else {
/* The guest uses the bottom half of the PID space */
if (!mmu_pid_bits)
-   mmu_pid_bits = 19;
+   mmu_pid_bits = (PVR_VER(pvr) == PVR_POWER9 &&
+   ((0xfff & pvr) < 0x202)) ? 19 : 20;
mmu_base_pid = 1;
}
 
diff --git a/arch/powerpc/mm/book3s64/radix_tlb.c 
b/arch/powerpc/mm/book3s64/radix_tlb.c
index 67af871190c6..cc86d8a88b86 100644
--- a/arch/powerpc/mm/book3s64/radix_tlb.c
+++ b/arch/powerpc/mm/book3s64/radix_tlb.c
@@ -1217,10 +1217,15 @@ void radix__flush_tlb_all(void)
 extern void radix_kvm_prefetch_workaround(struct mm_struct *mm)
 {
unsigned long pid = mm->context.id;
+   unsigned int pvr;
 
if (unlikely(pid == MMU_NO_CONTEXT))
return;
 
+   pvr = mfspr(SPRN_PVR);
+   if (PVR_VER(pvr) != PVR_POWER9 || ((0xfff & pvr) >= 0x202))
+   return;
+
/*
 * If this context hasn't run on that CPU before and KVM is
 * around, there's a slim chance that the guest on another
-- 
2.20.1

[PATCH] powerpc/kvm: Fix kvmppc_vcore->in_guest value in kvmhv_switch_to_host

[Jordan Niethe]

kvmhv_switch_to_host() in arch/powerpc/kvm/book3s_hv_rmhandlers.S needs
to set kvmppc_vcore->in_guest to 0 to signal secondary CPUs to continue.
This happens after resetting the PCR. Before commit 13c7bb3c57dc
("powerpc/64s: Set reserved PCR bits"), r0 would always be 0 before it
was stored to kvmppc_vcore->in_guest. However because of this change in
the commit:

/* Reset PCR */
ld  r0, VCORE_PCR(r5)
-   cmpdi   r0, 0
+   LOAD_REG_IMMEDIATE(r6, PCR_MASK)
+   cmpld   r0, r6
beq 18f
-   li  r0, 0
-   mtspr   SPRN_PCR, r0
+   mtspr   SPRN_PCR, r6
 18:
/* Signal secondary CPUs to continue */
stb r0,VCORE_IN_GUEST(r5)

We are no longer comparing r0 against 0 and loading it with 0 if it
contains something else. Hence when we store r0 to
kvmppc_vcore->in_guest, it might not be 0.  This means that secondary
CPUs will not be signalled to continue. Those CPUs get stuck and errors
like the following are logged:

KVM: CPU 1 seems to be stuck
KVM: CPU 2 seems to be stuck
KVM: CPU 3 seems to be stuck
KVM: CPU 4 seems to be stuck
KVM: CPU 5 seems to be stuck
KVM: CPU 6 seems to be stuck
KVM: CPU 7 seems to be stuck

This can be reproduced with:
$ for i in `seq 1 7` ; do chcpu -d $i ; done ;
$ taskset -c 0 qemu-system-ppc64 -smp 8,threads=8 \
   -M pseries,accel=kvm,kvm-type=HV -m 1G -nographic -vga none \
   -kernel vmlinux -initrd initrd.cpio.xz

Fix by making sure r0 is 0 before storing it to kvmppc_vcore->in_guest.

Fixes: 13c7bb3c57dc ("powerpc/64s: Set reserved PCR bits")
Reported-by: Alexey Kardashevskiy 
Signed-off-by: Jordan Niethe 
---
 arch/powerpc/kvm/book3s_hv_rmhandlers.S | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S 
b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
index 74a9cfe84aee..faebcbb8c4db 100644
--- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
+++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
@@ -1921,6 +1921,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
mtspr   SPRN_PCR, r6
 18:
/* Signal secondary CPUs to continue */
+   li  r0, 0
stb r0,VCORE_IN_GUEST(r5)
 19:lis r8,0x7fff   /* MAX_INT@h */
mtspr   SPRN_HDEC,r8
-- 
2.20.1

Re: [PATCH 03/18] powerpc: Add PREFIXED SRR1 bit for future ISA version

[Jordan Niethe]

On Wed, Dec 18, 2019 at 7:23 PM Daniel Axtens  wrote:
>
> Jordan Niethe  writes:
>
> > Add the bit definition for exceptions caused by prefixed instructions.
> >
> > Signed-off-by: Jordan Niethe 
> > ---
> >  arch/powerpc/include/asm/reg.h | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
> > index 6f9fcc3d4c82..0a6d39fb4769 100644
> > --- a/arch/powerpc/include/asm/reg.h
> > +++ b/arch/powerpc/include/asm/reg.h
> > @@ -778,6 +778,7 @@
> >
> >  #define   SRR1_MCE_MCP   0x0008 /* Machine check signal 
> > caused interrupt */
> >  #define   SRR1_BOUNDARY  0x1000 /* Prefixed instruction 
> > crosses 64-byte boundary */
> > +#define   SRR1_PREFIXED  0x2000 /* Exception caused by 
> > prefixed instruction */
>
> You could probably squash this with the previous patch, and maybe the
> next patch too.
>
> Regards,
> Daniel
>
> >
> >  #define SPRN_HSRR0   0x13A   /* Save/Restore Register 0 */
> >  #define SPRN_HSRR1   0x13B   /* Save/Restore Register 1 */
> > --
> > 2.20.1
Thanks, good idea.

Re: [PATCH 05/18] powerpc sstep: Prepare to support prefixed instructions

[Jordan Niethe]

On Wed, Dec 18, 2019 at 7:35 PM Daniel Axtens  wrote:
>
> Jordan Niethe  writes:
>
> > Currently all instructions are a single word long. A future ISA version
> > will include prefixed instructions which have a double word length. The
> > functions used for analysing and emulating instructions need to be
> > modified so that they can handle these new instruction types.
> >
> > A prefixed instruction is a word prefix followed by a word suffix. All
> > prefixes uniquely have the primary op-code 1. Suffixes may be valid word
> > instructions or instructions that only exist as suffixes.
> >
> > In handling prefixed instructions it will be convenient to treat the
> > suffix and prefix as separate words. To facilitate this modify
> > analyse_instr() and emulate_step() to take a take a suffix as a
> > parameter. For word instructions it does not matter what is passed in
> > here - it will be ignored.
> >
> > We also define a new flag, PREFIXED, to be used in instruction_op:type.
> > This flag will indicate when emulating an analysed instruction if the
> > NIP should be advanced by word length or double word length.
> >
> > The callers of analyse_instr() and emulate_step() will need their own
> > changes to be able to support prefixed instructions. For now modify them
> > to pass in 0 as a suffix.
> >
> > Note that at this point no prefixed instructions are emulated or
> > analysed - this is just making it possible to do so.
> >
> > Signed-off-by: Jordan Niethe 
> > ---
> >  arch/powerpc/include/asm/ppc-opcode.h |  3 +++
> >  arch/powerpc/include/asm/sstep.h  |  8 +--
> >  arch/powerpc/include/asm/uaccess.h| 30 +++
> >  arch/powerpc/kernel/align.c   |  2 +-
> >  arch/powerpc/kernel/hw_breakpoint.c   |  4 ++--
> >  arch/powerpc/kernel/kprobes.c |  2 +-
> >  arch/powerpc/kernel/mce_power.c   |  2 +-
> >  arch/powerpc/kernel/optprobes.c   |  2 +-
> >  arch/powerpc/kernel/uprobes.c |  2 +-
> >  arch/powerpc/kvm/emulate_loadstore.c  |  2 +-
> >  arch/powerpc/lib/sstep.c  | 12 ++-
> >  arch/powerpc/lib/test_emulate_step.c  | 30 +--
> >  arch/powerpc/xmon/xmon.c  |  4 ++--
> >  13 files changed, 71 insertions(+), 32 deletions(-)
> >
> > diff --git a/arch/powerpc/include/asm/ppc-opcode.h 
> > b/arch/powerpc/include/asm/ppc-opcode.h
> > index c1df75edde44..a1dfa4bdd22f 100644
> > --- a/arch/powerpc/include/asm/ppc-opcode.h
> > +++ b/arch/powerpc/include/asm/ppc-opcode.h
> > @@ -377,6 +377,9 @@
> >  #define PPC_INST_VCMPEQUD0x10c7
> >  #define PPC_INST_VCMPEQUB0x1006
> >
> > +/* macro to check if a word is a prefix */
> > +#define IS_PREFIX(x) (((x) >> 26) == 1)
> > +
> >  /* macros to insert fields into opcodes */
> >  #define ___PPC_RA(a) (((a) & 0x1f) << 16)
> >  #define ___PPC_RB(b) (((b) & 0x1f) << 11)
> > diff --git a/arch/powerpc/include/asm/sstep.h 
> > b/arch/powerpc/include/asm/sstep.h
> > index 769f055509c9..6d4cb602e231 100644
> > --- a/arch/powerpc/include/asm/sstep.h
> > +++ b/arch/powerpc/include/asm/sstep.h
> > @@ -89,6 +89,9 @@ enum instruction_type {
> >  #define VSX_LDLEFT   4   /* load VSX register from left */
> >  #define VSX_CHECK_VEC8   /* check MSR_VEC not MSR_VSX for reg 
> > >= 32 */
> >
> > +/* Prefixed flag, ORed in with type */
> > +#define PREFIXED 0x800
> > +
> >  /* Size field in type word */
> >  #define SIZE(n)  ((n) << 12)
> >  #define GETSIZE(w)   ((w) >> 12)
> > @@ -132,7 +135,7 @@ union vsx_reg {
> >   * otherwise.
> >   */
> >  extern int analyse_instr(struct instruction_op *op, const struct pt_regs 
> > *regs,
> > -  unsigned int instr);
> > +  unsigned int instr, unsigned int sufx);
> >
> >  /*
> >   * Emulate an instruction that can be executed just by updating
> > @@ -149,7 +152,8 @@ void emulate_update_regs(struct pt_regs *reg, struct 
> > instruction_op *op);
> >   * 0 if it could not be emulated, or -1 for an instruction that
> >   * should not be emulated (rfid, mtmsrd clearing MSR_RI, etc.).
> >   */
> > -extern int emulate_step(struct pt_regs *regs, unsigned int instr);
> > +extern int emulate_step(struct pt_regs *regs, unsigned int instr,
> > + unsigned int sufx);
> >
> >  /*
> >   * Emulate a load or 

Re: [PATCH 05/18] powerpc sstep: Prepare to support prefixed instructions

[Jordan Niethe]

On Thu, Dec 19, 2019 at 1:15 AM Daniel Axtens  wrote:
>
> Jordan Niethe  writes:
>
> > Currently all instructions are a single word long. A future ISA version
> > will include prefixed instructions which have a double word length. The
> > functions used for analysing and emulating instructions need to be
> > modified so that they can handle these new instruction types.
> >
> > A prefixed instruction is a word prefix followed by a word suffix. All
> > prefixes uniquely have the primary op-code 1. Suffixes may be valid word
> > instructions or instructions that only exist as suffixes.
> >
> > In handling prefixed instructions it will be convenient to treat the
> > suffix and prefix as separate words. To facilitate this modify
> > analyse_instr() and emulate_step() to take a take a suffix as a
> > parameter. For word instructions it does not matter what is passed in
> > here - it will be ignored.
> >
> > We also define a new flag, PREFIXED, to be used in instruction_op:type.
> > This flag will indicate when emulating an analysed instruction if the
> > NIP should be advanced by word length or double word length.
> >
> > The callers of analyse_instr() and emulate_step() will need their own
> > changes to be able to support prefixed instructions. For now modify them
> > to pass in 0 as a suffix.
> >
> > Note that at this point no prefixed instructions are emulated or
> > analysed - this is just making it possible to do so.
> >
> > Signed-off-by: Jordan Niethe 
> > ---
> >  arch/powerpc/include/asm/ppc-opcode.h |  3 +++
> >  arch/powerpc/include/asm/sstep.h  |  8 +--
> >  arch/powerpc/include/asm/uaccess.h| 30 +++
> >  arch/powerpc/kernel/align.c   |  2 +-
> >  arch/powerpc/kernel/hw_breakpoint.c   |  4 ++--
> >  arch/powerpc/kernel/kprobes.c |  2 +-
> >  arch/powerpc/kernel/mce_power.c   |  2 +-
> >  arch/powerpc/kernel/optprobes.c   |  2 +-
> >  arch/powerpc/kernel/uprobes.c |  2 +-
> >  arch/powerpc/kvm/emulate_loadstore.c  |  2 +-
> >  arch/powerpc/lib/sstep.c  | 12 ++-
> >  arch/powerpc/lib/test_emulate_step.c  | 30 +--
> >  arch/powerpc/xmon/xmon.c  |  4 ++--
> >  13 files changed, 71 insertions(+), 32 deletions(-)
> >
> > diff --git a/arch/powerpc/include/asm/ppc-opcode.h 
> > b/arch/powerpc/include/asm/ppc-opcode.h
> > index c1df75edde44..a1dfa4bdd22f 100644
> > --- a/arch/powerpc/include/asm/ppc-opcode.h
> > +++ b/arch/powerpc/include/asm/ppc-opcode.h
> > @@ -377,6 +377,9 @@
> >  #define PPC_INST_VCMPEQUD0x10c7
> >  #define PPC_INST_VCMPEQUB0x1006
> >
> > +/* macro to check if a word is a prefix */
> > +#define IS_PREFIX(x) (((x) >> 26) == 1)
> > +
> >  /* macros to insert fields into opcodes */
> >  #define ___PPC_RA(a) (((a) & 0x1f) << 16)
> >  #define ___PPC_RB(b) (((b) & 0x1f) << 11)
> > diff --git a/arch/powerpc/include/asm/sstep.h 
> > b/arch/powerpc/include/asm/sstep.h
> > index 769f055509c9..6d4cb602e231 100644
> > --- a/arch/powerpc/include/asm/sstep.h
> > +++ b/arch/powerpc/include/asm/sstep.h
> > @@ -89,6 +89,9 @@ enum instruction_type {
> >  #define VSX_LDLEFT   4   /* load VSX register from left */
> >  #define VSX_CHECK_VEC8   /* check MSR_VEC not MSR_VSX for reg 
> > >= 32 */
> >
> > +/* Prefixed flag, ORed in with type */
> > +#define PREFIXED 0x800
> > +
> >  /* Size field in type word */
> >  #define SIZE(n)  ((n) << 12)
> >  #define GETSIZE(w)   ((w) >> 12)
> > @@ -132,7 +135,7 @@ union vsx_reg {
> >   * otherwise.
> >   */
> >  extern int analyse_instr(struct instruction_op *op, const struct pt_regs 
> > *regs,
> > -  unsigned int instr);
> > +  unsigned int instr, unsigned int sufx);
> >
>
> I'm not saying this is necessarily better, but did you consider:
>
>  - making instr 64 bits and using masking and shifting macros to get the
>prefix and suffix?
>
>  - defining an instruction type/struct/union/whatever that contains both
>halves in one object?
>
> I'm happy to be told that it ends up being way, way uglier/worse/etc,
> but I just thought I'd ask.
>
> Regards,
> Daniel

It is a good question and something I thought and am not completely confident
that this approach is the best. Basically what I ended up thinking was that
the prefixed instructions were a bit of a special cas

Re: [PATCH v2 06/13] powerpc: Support prefixed instructions in alignment handler

[Jordan Niethe]

On Tue, Feb 11, 2020 at 5:14 PM Christophe Leroy
 wrote:
>
>
>
> Le 11/02/2020 à 06:33, Jordan Niethe a écrit :
> > Alignment interrupts can be caused by prefixed instructions accessing
> > memory. In the alignment handler the instruction that caused the
> > exception is loaded and attempted emulate. If the instruction is a
> > prefixed instruction load the prefix and suffix to emulate. After
> > emulating increment the NIP by 8.
> >
> > Prefixed instructions are not permitted to cross 64-byte boundaries. If
> > they do the alignment interrupt is invoked with SRR1 BOUNDARY bit set.
> > If this occurs send a SIGBUS to the offending process if in user mode.
> > If in kernel mode call bad_page_fault().
> >
> > Signed-off-by: Jordan Niethe 
> > ---
> > v2: - Move __get_user_instr() and __get_user_instr_inatomic() to this
> > commit (previously in "powerpc sstep: Prepare to support prefixed
> > instructions").
> >  - Rename sufx to suffix
> >  - Use a macro for calculating instruction length
> > ---
> >   arch/powerpc/include/asm/uaccess.h | 30 ++
> >   arch/powerpc/kernel/align.c|  8 +---
> >   arch/powerpc/kernel/traps.c| 21 -
> >   3 files changed, 55 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/powerpc/include/asm/uaccess.h 
> > b/arch/powerpc/include/asm/uaccess.h
> > index 2f500debae21..30f63a81c8d8 100644
> > --- a/arch/powerpc/include/asm/uaccess.h
> > +++ b/arch/powerpc/include/asm/uaccess.h
> > @@ -474,4 +474,34 @@ static __must_check inline bool 
> > user_access_begin(const void __user *ptr, size_t
> >   #define unsafe_copy_to_user(d, s, l, e) \
> >   unsafe_op_wrap(raw_copy_to_user_allowed(d, s, l), e)
> >
>
> Could it go close to other __get_user() and friends instead of being at
> the end of the file ?
Will do.
>
> > +/*
> > + * When reading an instruction iff it is a prefix, the suffix needs to be 
> > also
> > + * loaded.
> > + */
> > +#define __get_user_instr(x, y, ptr)  \
> > +({   \
> > + long __gui_ret = 0; \
> > + y = 0;  \
> > + __gui_ret = __get_user(x, ptr); \
> > + if (!__gui_ret) {   \
> > + if (IS_PREFIX(x))   \
>
> Does this apply to PPC32 ?
No, for now (and the foreseeable future) it will just affect 64s.
> If not, can we make sure IS_PREFIX is constant 0 on PPC32 so that the
> second read gets dropped at compile time ?
>
> Can we instead do :
>
> if (!__gui_ret && IS_PREFIX(x))
Will do.
>
> > + __gui_ret = __get_user(y, ptr + 1); \
> > + }   \
> > + \
> > + __gui_ret;  \
> > +})
> > +
> > +#define __get_user_instr_inatomic(x, y, ptr) \
> > +({   \
> > + long __gui_ret = 0; \
> > + y = 0;  \
> > + __gui_ret = __get_user_inatomic(x, ptr);\
> > + if (!__gui_ret) {   \
> > + if (IS_PREFIX(x))   \
>
> Same commments as above
>
> > + __gui_ret = __get_user_inatomic(y, ptr + 1);\
> > + }   \
> > + \
> > + __gui_ret;  \
> > +})
> > +
> >   #endif  /* _ARCH_POWERPC_UACCESS_H */
> > diff --git a/arch/powerpc/kernel/align.c b/arch/powerpc/kernel/align.c
> > index ba3bf5c3ab62..e42cfaa616d3 100644
> > --- a/arch/powerpc/kernel/align.c
> > +++ b/arch/powerpc/kernel/align.c
> > @@ -293,7 +293,7 @@ static int emulate_spe(struct pt_regs *regs, unsigned 
> > int reg,
> >
> >   int fix_alignment(struct pt_regs *regs)
> >   {
> > - unsigned int instr;
> > + unsigned int instr, suffix;
> >   struct instruction_op op;
> >   int r, type;
> >
> > @@ -303,13 +303,15 @@ int fix_alignment(struct pt_regs *regs)
> >*/
> >   CHECK_FULL_REGS(regs);
> >
> > - if (unlikely(__get_user(instr, (unsigned int __user *)regs->nip)))
> > + i

Re: [PATCH v2 10/13] powerpc/kprobes: Support kprobes on prefixed instructions

[Jordan Niethe]

On Tue, Feb 11, 2020 at 5:46 PM Christophe Leroy
 wrote:
>
>
>
> Le 11/02/2020 à 06:33, Jordan Niethe a écrit :
> > A prefixed instruction is composed of a word prefix followed by a word
> > suffix. It does not make sense to be able to have a kprobe on the suffix
> > of a prefixed instruction, so make this impossible.
> >
> > Kprobes work by replacing an instruction with a trap and saving that
> > instruction to be single stepped out of place later. Currently there is
> > not enough space allocated to keep a prefixed instruction for single
> > stepping. Increase the amount of space allocated for holding the
> > instruction copy.
> >
> > kprobe_post_handler() expects all instructions to be 4 bytes long which
> > means that it does not function correctly for prefixed instructions.
> > Add checks for prefixed instructions which will use a length of 8 bytes
> > instead.
> >
> > For optprobes we normally patch in loading the instruction we put a
> > probe on into r4 before calling emulate_step(). We now make space and
> > patch in loading the suffix into r5 as well.
> >
> > Signed-off-by: Jordan Niethe 
> > ---
> >   arch/powerpc/include/asm/kprobes.h   |  5 +--
> >   arch/powerpc/kernel/kprobes.c| 47 +---
> >   arch/powerpc/kernel/optprobes.c  | 32 ++-
> >   arch/powerpc/kernel/optprobes_head.S |  6 
> >   4 files changed, 63 insertions(+), 27 deletions(-)
> >
> > diff --git a/arch/powerpc/include/asm/kprobes.h 
> > b/arch/powerpc/include/asm/kprobes.h
> > index 66b3f2983b22..0d44ce8a3163 100644
> > --- a/arch/powerpc/include/asm/kprobes.h
> > +++ b/arch/powerpc/include/asm/kprobes.h
> > @@ -38,12 +38,13 @@ extern kprobe_opcode_t optprobe_template_entry[];
> >   extern kprobe_opcode_t optprobe_template_op_address[];
> >   extern kprobe_opcode_t optprobe_template_call_handler[];
> >   extern kprobe_opcode_t optprobe_template_insn[];
> > +extern kprobe_opcode_t optprobe_template_suffix[];
> >   extern kprobe_opcode_t optprobe_template_call_emulate[];
> >   extern kprobe_opcode_t optprobe_template_ret[];
> >   extern kprobe_opcode_t optprobe_template_end[];
> >
> > -/* Fixed instruction size for powerpc */
> > -#define MAX_INSN_SIZE1
> > +/* Prefixed instructions are two words */
> > +#define MAX_INSN_SIZE2
> >   #define MAX_OPTIMIZED_LENGTHsizeof(kprobe_opcode_t) /* 4 bytes */
> >   #define MAX_OPTINSN_SIZE(optprobe_template_end - 
> > optprobe_template_entry)
> >   #define RELATIVEJUMP_SIZE   sizeof(kprobe_opcode_t) /* 4 bytes */
> > diff --git a/arch/powerpc/kernel/kprobes.c b/arch/powerpc/kernel/kprobes.c
> > index 24a56f062d9e..b061deba4fe7 100644
> > --- a/arch/powerpc/kernel/kprobes.c
> > +++ b/arch/powerpc/kernel/kprobes.c
> > @@ -104,17 +104,30 @@ kprobe_opcode_t *kprobe_lookup_name(const char *name, 
> > unsigned int offset)
> >
> >   int arch_prepare_kprobe(struct kprobe *p)
> >   {
> > + int len;
> >   int ret = 0;
> > + struct kprobe *prev;
> >   kprobe_opcode_t insn = *p->addr;
> > + kprobe_opcode_t prefix = *(p->addr - 1);
> >
> > + preempt_disable();
> >   if ((unsigned long)p->addr & 0x03) {
> >   printk("Attempt to register kprobe at an unaligned 
> > address\n");
> >   ret = -EINVAL;
> >   } else if (IS_MTMSRD(insn) || IS_RFID(insn) || IS_RFI(insn)) {
> >   printk("Cannot register a kprobe on rfi/rfid or mtmsr[d]\n");
> >   ret = -EINVAL;
> > + } else if (IS_PREFIX(prefix)) {
> > + printk("Cannot register a kprobe on the second word of 
> > prefixed instruction\n");
> > + ret = -EINVAL;
> > + }
> > + prev = get_kprobe(p->addr - 1);
> > + if (prev && IS_PREFIX(*prev->ainsn.insn)) {
> > + printk("Cannot register a kprobe on the second word of 
> > prefixed instruction\n");
> > + ret = -EINVAL;
> >   }
> >
> > +
> >   /* insn must be on a special executable page on ppc64.  This is
> >* not explicitly required on ppc32 (right now), but it doesn't hurt 
> > */
> >   if (!ret) {
> > @@ -124,14 +137,18 @@ int arch_prepare_kprobe(struct kprobe *p)
> >   }
> >
> >   if (!ret) {
> > - memcpy(p->ainsn.insn, p->addr,
> > -

Re: [PATCH v2 09/13] powerpc/xmon: Dump prefixed instructions

[Jordan Niethe]

On Tue, Feb 11, 2020 at 5:39 PM Christophe Leroy
 wrote:
>
>
>
> Le 11/02/2020 à 06:33, Jordan Niethe a écrit :
> > Currently when xmon is dumping instructions it reads a word at a time
> > and then prints that instruction (either as a hex number or by
> > disassembling it). For prefixed instructions it would be nice to show
> > its prefix and suffix as together. Use read_instr() so that if a prefix
> > is encountered its suffix is loaded too. Then print these in the form:
> >  prefix:suffix
> > Xmon uses the disassembly routines from GNU binutils. These currently do
> > not support prefixed instructions so we will not disassemble the
> > prefixed instructions yet.
> >
> > Signed-off-by: Jordan Niethe 
> > ---
> > v2: Rename sufx to suffix
> > ---
> >   arch/powerpc/xmon/xmon.c | 50 +++-
> >   1 file changed, 39 insertions(+), 11 deletions(-)
> >
> > diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
> > index 0b085642bbe7..513901ee18b0 100644
> > --- a/arch/powerpc/xmon/xmon.c
> > +++ b/arch/powerpc/xmon/xmon.c
> > @@ -2903,6 +2903,21 @@ prdump(unsigned long adrs, long ndump)
> >   }
> >   }
> >
> > +static bool instrs_are_equal(unsigned long insta, unsigned long suffixa,
> > +  unsigned long instb, unsigned long suffixb)
> > +{
> > + if (insta != instb)
> > + return false;
> > +
> > + if (!IS_PREFIX(insta) && !IS_PREFIX(instb))
> > + return true;
> > +
> > + if (IS_PREFIX(insta) && IS_PREFIX(instb))
> > + return suffixa == suffixb;
> > +
> > + return false;
> > +}
> > +
> >   typedef int (*instruction_dump_func)(unsigned long inst, unsigned long 
> > addr);
> >
> >   static int
> > @@ -2911,12 +2926,11 @@ generic_inst_dump(unsigned long adr, long count, 
> > int praddr,
> >   {
> >   int nr, dotted;
> >   unsigned long first_adr;
> > - unsigned int inst, last_inst = 0;
> > - unsigned char val[4];
> > + unsigned int inst, suffix, last_inst = 0, last_suffix = 0;
> >
> >   dotted = 0;
> > - for (first_adr = adr; count > 0; --count, adr += 4) {
> > - nr = mread(adr, val, 4);
> > + for (first_adr = adr; count > 0; --count, adr += nr) {
> > + nr = read_instr(adr, , );
> >   if (nr == 0) {
> >   if (praddr) {
> >   const char *x = fault_chars[fault_type];
> > @@ -2924,8 +2938,9 @@ generic_inst_dump(unsigned long adr, long count, int 
> > praddr,
> >   }
> >   break;
> >   }
> > - inst = GETWORD(val);
> > - if (adr > first_adr && inst == last_inst) {
> > + if (adr > first_adr && instrs_are_equal(inst, suffix,
> > + last_inst,
> > + last_suffix)) {
> >   if (!dotted) {
> >   printf(" ...\n");
> >   dotted = 1;
> > @@ -2934,11 +2949,24 @@ generic_inst_dump(unsigned long adr, long count, 
> > int praddr,
> >   }
> >   dotted = 0;
> >   last_inst = inst;
> > - if (praddr)
> > - printf(REG"  %.8x", adr, inst);
> > - printf("\t");
> > - dump_func(inst, adr);
> > - printf("\n");
> > + last_suffix = suffix;
> > + if (IS_PREFIX(inst)) {
> > + if (praddr)
> > + printf(REG"  %.8x:%.8x", adr, inst, suffix);
> > + printf("\t");
> > + /*
> > +  * Just use this until binutils ppc disassembly
> > +  * prints prefixed instructions.
> > +  */
> > + printf("%.8x:%.8x", inst, suffix);
> > + printf("\n");
> > + } else {
> > + if (praddr)
> > + printf(REG"  %.8x", adr, inst);
> > + printf("\t");
> > + dump_func(inst, adr);
> > + printf("\n");
> > + }
>
> What about:
>
>
> if (pr_addr) {
> printf(REG"  %.8x", adr, inst);
> if (IS_PREFIX(inst))
> printf(":%.8x", suffix);
> }
> printf("\t");
> if (IS_PREFIX(inst))
> printf("%.8x:%.8x", inst, suffix);
> else
> dump_func(inst, adr);
> printf("\n");
>
Yeah that looks better.
> >   }
> >   return adr - first_adr;
> >   }
> >
>
> Christophe

Re: [PATCH v2 08/13] powerpc/xmon: Add initial support for prefixed instructions

[Jordan Niethe]

On Tue, Feb 11, 2020 at 5:32 PM Christophe Leroy
 wrote:
>
>
>
> Le 11/02/2020 à 06:33, Jordan Niethe a écrit :
> > A prefixed instruction is composed of a word prefix and a word suffix.
> > It does not make sense to be able to have a breakpoint on the suffix of
> > a prefixed instruction, so make this impossible.
> >
> > When leaving xmon_core() we check to see if we are currently at a
> > breakpoint. If this is the case, the breakpoint needs to be proceeded
> > from. Initially emulate_step() is tried, but if this fails then we need
> > to execute the saved instruction out of line. The NIP is set to the
> > address of bpt::instr[] for the current breakpoint.  bpt::instr[]
> > contains the instruction replaced by the breakpoint, followed by a trap
> > instruction.  After bpt::instr[0] is executed and we hit the trap we
> > enter back into xmon_bpt(). We know that if we got here and the offset
> > indicates we are at bpt::instr[1] then we have just executed out of line
> > so we can put the NIP back to the instruction after the breakpoint
> > location and continue on.
> >
> > Adding prefixed instructions complicates this as the bpt::instr[1] needs
> > to be used to hold the suffix. To deal with this make bpt::instr[] big
> > enough for three word instructions.  bpt::instr[2] contains the trap,
> > and in the case of word instructions pad bpt::instr[1] with a noop.
> >
> > No support for disassembling prefixed instructions.
> >
> > Signed-off-by: Jordan Niethe 
> > ---
> > v2: Rename sufx to suffix
> > ---
> >   arch/powerpc/xmon/xmon.c | 82 ++--
> >   1 file changed, 71 insertions(+), 11 deletions(-)
> >
> > diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
> > index 897e512c6379..0b085642bbe7 100644
> > --- a/arch/powerpc/xmon/xmon.c
> > +++ b/arch/powerpc/xmon/xmon.c
> > @@ -97,7 +97,8 @@ static long *xmon_fault_jmp[NR_CPUS];
> >   /* Breakpoint stuff */
> >   struct bpt {
> >   unsigned long   address;
> > - unsigned intinstr[2];
> > + /* Prefixed instructions can not cross 64-byte boundaries */
> > + unsigned intinstr[3] __aligned(64);
> >   atomic_tref_count;
> >   int enabled;
> >   unsigned long   pad;
> > @@ -113,6 +114,7 @@ static struct bpt bpts[NBPTS];
> >   static struct bpt dabr;
> >   static struct bpt *iabr;
> >   static unsigned bpinstr = 0x7fe8;   /* trap */
> > +static unsigned nopinstr = 0x6000;   /* nop */
>
> Use PPC_INST_NOP instead of 0x6000
>
> And this nopinstr variable will never change. Why not use directly
> PPC_INST_NOP  in the code ?
True, I will do that.
>
> >
> >   #define BP_NUM(bp)  ((bp) - bpts + 1)
> >
> > @@ -120,6 +122,7 @@ static unsigned bpinstr = 0x7fe8; /* trap */
> >   static int cmds(struct pt_regs *);
> >   static int mread(unsigned long, void *, int);
> >   static int mwrite(unsigned long, void *, int);
> > +static int read_instr(unsigned long, unsigned int *, unsigned int *);
> >   static int handle_fault(struct pt_regs *);
> >   static void byterev(unsigned char *, int);
> >   static void memex(void);
> > @@ -706,7 +709,7 @@ static int xmon_core(struct pt_regs *regs, int fromipi)
> >   bp = at_breakpoint(regs->nip);
> >   if (bp != NULL) {
> >   int stepped = emulate_step(regs, bp->instr[0],
> > -PPC_NO_SUFFIX);
> > +bp->instr[1]);
> >   if (stepped == 0) {
> >   regs->nip = (unsigned long) >instr[0];
> >   atomic_inc(>ref_count);
> > @@ -761,8 +764,8 @@ static int xmon_bpt(struct pt_regs *regs)
> >
> >   /* Are we at the trap at bp->instr[1] for some bp? */
> >   bp = in_breakpoint_table(regs->nip, );
> > - if (bp != NULL && offset == 4) {
> > - regs->nip = bp->address + 4;
> > + if (bp != NULL && (offset == 4 || offset == 8)) {
> > + regs->nip = bp->address + offset;
> >   atomic_dec(>ref_count);
> >   return 1;
> >   }
> > @@ -864,7 +867,8 @@ static struct bpt *in_breakpoint_table(unsigned long 
> > nip, unsigned long *offp)
> >   return NULL;
> >   off %= sizeof(struct bpt);
> >   if (off != offsetof(struct bpt, instr[0])
> >

Re: [PATCH v2 04/13] powerpc sstep: Add support for prefixed load/stores

[Jordan Niethe]

On Tue, Feb 11, 2020 at 5:05 PM Christophe Leroy
 wrote:
>
>
>
> Le 11/02/2020 à 06:33, Jordan Niethe a écrit :
> > This adds emulation support for the following prefixed integer
> > load/stores:
> >* Prefixed Load Byte and Zero (plbz)
> >* Prefixed Load Halfword and Zero (plhz)
> >* Prefixed Load Halfword Algebraic (plha)
> >* Prefixed Load Word and Zero (plwz)
> >* Prefixed Load Word Algebraic (plwa)
> >* Prefixed Load Doubleword (pld)
> >* Prefixed Store Byte (pstb)
> >* Prefixed Store Halfword (psth)
> >* Prefixed Store Word (pstw)
> >* Prefixed Store Doubleword (pstd)
> >* Prefixed Load Quadword (plq)
> >* Prefixed Store Quadword (pstq)
> >
> > the follow prefixed floating-point load/stores:
> >* Prefixed Load Floating-Point Single (plfs)
> >* Prefixed Load Floating-Point Double (plfd)
> >* Prefixed Store Floating-Point Single (pstfs)
> >* Prefixed Store Floating-Point Double (pstfd)
> >
> > and for the following prefixed VSX load/stores:
> >* Prefixed Load VSX Scalar Doubleword (plxsd)
> >* Prefixed Load VSX Scalar Single-Precision (plxssp)
> >* Prefixed Load VSX Vector [0|1]  (plxv, plxv0, plxv1)
> >* Prefixed Store VSX Scalar Doubleword (pstxsd)
> >* Prefixed Store VSX Scalar Single-Precision (pstxssp)
> >* Prefixed Store VSX Vector [0|1] (pstxv, pstxv0, pstxv1)
> >
> > Signed-off-by: Jordan Niethe 
> > ---
> > v2: - Combine all load/store patches
> >  - Fix the name of Type 01 instructions
> >  - Remove sign extension flag from pstd/pld
> >  - Rename sufx -> suffix
> > ---
> >   arch/powerpc/lib/sstep.c | 165 +++
> >   1 file changed, 165 insertions(+)
> >
> > diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
> > index 65143ab1bf64..0e21c21ff2be 100644
> > --- a/arch/powerpc/lib/sstep.c
> > +++ b/arch/powerpc/lib/sstep.c
> > @@ -187,6 +187,44 @@ static nokprobe_inline unsigned long xform_ea(unsigned 
> > int instr,
> >   return ea;
> >   }
> >
> > +/*
> > + * Calculate effective address for a MLS:D-form / 8LS:D-form
> > + * prefixed instruction
> > + */
> > +static nokprobe_inline unsigned long mlsd_8lsd_ea(unsigned int instr,
> > +   unsigned int suffix,
> > +   const struct pt_regs *regs)
> > +{
> > + int ra, prefix_r;
> > + unsigned int  dd;
> > + unsigned long ea, d0, d1, d;
> > +
> > + prefix_r = instr & (1ul << 20);
> > + ra = (suffix >> 16) & 0x1f;
> > +
> > + d0 = instr & 0x3;
> > + d1 = suffix & 0x;
> > + d = (d0 << 16) | d1;
> > +
> > + /*
> > +  * sign extend a 34 bit number
> > +  */
> > + dd = (unsigned int) (d >> 2);
> > + ea = (signed int) dd;
> > + ea = (ea << 2) | (d & 0x3);
> > +
> > + if (!prefix_r && ra)
> > + ea += regs->gpr[ra];
> > + else if (!prefix_r && !ra)
> > + ; /* Leave ea as is */
> > + else if (prefix_r && !ra)
> > + ea += regs->nip;
> > + else if (prefix_r && ra)
> > + ; /* Invalid form. Should already be checked for by caller! */
> > +
> > + return ea;
> > +}
> > +
> >   /*
> >* Return the largest power of 2, not greater than sizeof(unsigned long),
> >* such that x is a multiple of it.
> > @@ -1166,6 +1204,7 @@ int analyse_instr(struct instruction_op *op, const 
> > struct pt_regs *regs,
> > unsigned int instr, unsigned int suffix)
> >   {
> >   unsigned int opcode, ra, rb, rc, rd, spr, u;
> > + unsigned int suffixopcode, prefixtype, prefix_r;
> >   unsigned long int imm;
> >   unsigned long int val, val2;
> >   unsigned int mb, me, sh;
> > @@ -2652,6 +2691,132 @@ int analyse_instr(struct instruction_op *op, const 
> > struct pt_regs *regs,
> >
> >   }
> >
> > +/*
> > + * Prefixed instructions
> > + */
> > + switch (opcode) {
> > + case 1:
>
> Why not include it in the above switch () ?
I was wanting to keep all the prefixed instructions together, but you
are right, these are all load/stores so it would be clearer for them
to go in the Load and Stores switch.
>
> Should it be enclosed by #i

[PATCH v2 11/13] powerpc/uprobes: Add support for prefixed instructions

[Jordan Niethe]

Uprobes can execute instructions out of line. Increase the size of the
buffer used  for this so that this works for prefixed instructions. Take
into account the length of prefixed instructions when fixing up the nip.

Signed-off-by: Jordan Niethe 
---
v2: - Fix typo
- Use macro for instruction length
---
 arch/powerpc/include/asm/uprobes.h | 16 
 arch/powerpc/kernel/uprobes.c  |  4 ++--
 2 files changed, 14 insertions(+), 6 deletions(-)

diff --git a/arch/powerpc/include/asm/uprobes.h 
b/arch/powerpc/include/asm/uprobes.h
index 2bbdf27d09b5..5516ab27db47 100644
--- a/arch/powerpc/include/asm/uprobes.h
+++ b/arch/powerpc/include/asm/uprobes.h
@@ -14,18 +14,26 @@
 
 typedef ppc_opcode_t uprobe_opcode_t;
 
+/*
+ * Ensure we have enough space for prefixed instructions, which
+ * are double the size of a word instruction, i.e. 8 bytes.
+ */
 #define MAX_UINSN_BYTES4
-#define UPROBE_XOL_SLOT_BYTES  (MAX_UINSN_BYTES)
+#define UPROBE_XOL_SLOT_BYTES  (2 * MAX_UINSN_BYTES)
 
 /* The following alias is needed for reference from arch-agnostic code */
 #define UPROBE_SWBP_INSN   BREAKPOINT_INSTRUCTION
 #define UPROBE_SWBP_INSN_SIZE  4 /* swbp insn size in bytes */
 
 struct arch_uprobe {
+/*
+ * Ensure there is enough space for prefixed instructions. Prefixed
+ * instructions must not cross 64-byte boundaries.
+ */
union {
-   u32 insn;
-   u32 ixol;
-   };
+   uprobe_opcode_t insn[2];
+   uprobe_opcode_t ixol[2];
+   } __aligned(64);
 };
 
 struct arch_uprobe_task {
diff --git a/arch/powerpc/kernel/uprobes.c b/arch/powerpc/kernel/uprobes.c
index 4ab40c4b576f..7e0334ad5cfe 100644
--- a/arch/powerpc/kernel/uprobes.c
+++ b/arch/powerpc/kernel/uprobes.c
@@ -111,7 +111,7 @@ int arch_uprobe_post_xol(struct arch_uprobe *auprobe, 
struct pt_regs *regs)
 * support doesn't exist and have to fix-up the next instruction
 * to be executed.
 */
-   regs->nip = utask->vaddr + MAX_UINSN_BYTES;
+   regs->nip = utask->vaddr + PPC_INST_LENGTH(auprobe->insn[0]);
 
user_disable_single_step(current);
return 0;
@@ -173,7 +173,7 @@ bool arch_uprobe_skip_sstep(struct arch_uprobe *auprobe, 
struct pt_regs *regs)
 * emulate_step() returns 1 if the insn was successfully emulated.
 * For all other cases, we need to single-step in hardware.
 */
-   ret = emulate_step(regs, auprobe->insn, PPC_NO_SUFFIX);
+   ret = emulate_step(regs, auprobe->insn[0], auprobe->insn[1]);
if (ret > 0)
return true;
 
-- 
2.17.1

[PATCH v2 12/13] powerpc/hw_breakpoints: Initial support for prefixed instructions

[Jordan Niethe]

Currently when getting an instruction to emulate in
hw_breakpoint_handler() we do not load the suffix of a prefixed
instruction. Ensure we load the suffix if the instruction we need to
emulate is a prefixed instruction.

Signed-off-by: Jordan Niethe 
---
v2: Rename sufx to suffix
---
 arch/powerpc/kernel/hw_breakpoint.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/powerpc/kernel/hw_breakpoint.c 
b/arch/powerpc/kernel/hw_breakpoint.c
index 3a7ec6760dab..c69189641b05 100644
--- a/arch/powerpc/kernel/hw_breakpoint.c
+++ b/arch/powerpc/kernel/hw_breakpoint.c
@@ -243,15 +243,15 @@ dar_range_overlaps(unsigned long dar, int size, struct 
arch_hw_breakpoint *info)
 static bool stepping_handler(struct pt_regs *regs, struct perf_event *bp,
 struct arch_hw_breakpoint *info)
 {
-   unsigned int instr = 0;
+   unsigned int instr = 0, suffix = 0;
int ret, type, size;
struct instruction_op op;
unsigned long addr = info->address;
 
-   if (__get_user_inatomic(instr, (unsigned int *)regs->nip))
+   if (__get_user_instr_inatomic(instr, suffix, (unsigned int *)regs->nip))
goto fail;
 
-   ret = analyse_instr(, regs, instr, PPC_NO_SUFFIX);
+   ret = analyse_instr(, regs, instr, suffix);
type = GETTYPE(op.type);
size = GETSIZE(op.type);
 
@@ -275,7 +275,7 @@ static bool stepping_handler(struct pt_regs *regs, struct 
perf_event *bp,
return false;
}
 
-   if (!emulate_step(regs, instr, PPC_NO_SUFFIX))
+   if (!emulate_step(regs, instr, suffix))
goto fail;
 
return true;
-- 
2.17.1

[PATCH v2 03/13] powerpc sstep: Prepare to support prefixed instructions

[Jordan Niethe]

Currently all instructions are a single word long. A future ISA version
will include prefixed instructions which have a double word length. The
functions used for analysing and emulating instructions need to be
modified so that they can handle these new instruction types.

A prefixed instruction is a word prefix followed by a word suffix. All
prefixes uniquely have the primary op-code 1. Suffixes may be valid word
instructions or instructions that only exist as suffixes.

In handling prefixed instructions it will be convenient to treat the
suffix and prefix as separate words. To facilitate this modify
analyse_instr() and emulate_step() to take a suffix as a
parameter. For word instructions it does not matter what is passed in
here - it will be ignored.

We also define a new flag, PREFIXED, to be used in instruction_op:type.
This flag will indicate when emulating an analysed instruction if the
NIP should be advanced by word length or double word length.

The callers of analyse_instr() and emulate_step() will need their own
changes to be able to support prefixed instructions. For now modify them
to pass in 0 as a suffix.

Note that at this point no prefixed instructions are emulated or
analysed - this is just making it possible to do so.

Signed-off-by: Jordan Niethe 
---
v2: - Move definition of __get_user_instr() and
__get_user_instr_inatomic() to "powerpc: Support prefixed instructions
in alignment handler."
- Use a macro for returning the length of an op
- Rename sufx -> suffix
- Define and use PPC_NO_SUFFIX instead of 0
---
 arch/powerpc/include/asm/ppc-opcode.h |  5 +
 arch/powerpc/include/asm/sstep.h  |  9 ++--
 arch/powerpc/kernel/align.c   |  2 +-
 arch/powerpc/kernel/hw_breakpoint.c   |  4 ++--
 arch/powerpc/kernel/kprobes.c |  2 +-
 arch/powerpc/kernel/mce_power.c   |  2 +-
 arch/powerpc/kernel/optprobes.c   |  3 ++-
 arch/powerpc/kernel/uprobes.c |  2 +-
 arch/powerpc/kvm/emulate_loadstore.c  |  2 +-
 arch/powerpc/lib/sstep.c  | 12 ++-
 arch/powerpc/lib/test_emulate_step.c  | 30 +--
 arch/powerpc/xmon/xmon.c  |  5 +++--
 12 files changed, 46 insertions(+), 32 deletions(-)

diff --git a/arch/powerpc/include/asm/ppc-opcode.h 
b/arch/powerpc/include/asm/ppc-opcode.h
index c1df75edde44..72783bc92e50 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -377,6 +377,11 @@
 #define PPC_INST_VCMPEQUD  0x10c7
 #define PPC_INST_VCMPEQUB  0x1006
 
+/* macro to check if a word is a prefix */
+#define IS_PREFIX(x)   (((x) >> 26) == 1)
+#definePPC_NO_SUFFIX   0
+#definePPC_INST_LENGTH(x)  (IS_PREFIX(x) ? 8 : 4)
+
 /* macros to insert fields into opcodes */
 #define ___PPC_RA(a)   (((a) & 0x1f) << 16)
 #define ___PPC_RB(b)   (((b) & 0x1f) << 11)
diff --git a/arch/powerpc/include/asm/sstep.h b/arch/powerpc/include/asm/sstep.h
index 769f055509c9..9ea8904a1549 100644
--- a/arch/powerpc/include/asm/sstep.h
+++ b/arch/powerpc/include/asm/sstep.h
@@ -89,11 +89,15 @@ enum instruction_type {
 #define VSX_LDLEFT 4   /* load VSX register from left */
 #define VSX_CHECK_VEC  8   /* check MSR_VEC not MSR_VSX for reg >= 32 */
 
+/* Prefixed flag, ORed in with type */
+#define PREFIXED   0x800
+
 /* Size field in type word */
 #define SIZE(n)((n) << 12)
 #define GETSIZE(w) ((w) >> 12)
 
 #define GETTYPE(t) ((t) & INSTR_TYPE_MASK)
+#define OP_LENGTH(t)   (((t) & PREFIXED) ? 8 : 4)
 
 #define MKOP(t, f, s)  ((t) | (f) | SIZE(s))
 
@@ -132,7 +136,7 @@ union vsx_reg {
  * otherwise.
  */
 extern int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
-unsigned int instr);
+unsigned int instr, unsigned int suffix);
 
 /*
  * Emulate an instruction that can be executed just by updating
@@ -149,7 +153,8 @@ void emulate_update_regs(struct pt_regs *reg, struct 
instruction_op *op);
  * 0 if it could not be emulated, or -1 for an instruction that
  * should not be emulated (rfid, mtmsrd clearing MSR_RI, etc.).
  */
-extern int emulate_step(struct pt_regs *regs, unsigned int instr);
+extern int emulate_step(struct pt_regs *regs, unsigned int instr,
+   unsigned int suffix);
 
 /*
  * Emulate a load or store instruction by reading/writing the
diff --git a/arch/powerpc/kernel/align.c b/arch/powerpc/kernel/align.c
index 92045ed64976..ba3bf5c3ab62 100644
--- a/arch/powerpc/kernel/align.c
+++ b/arch/powerpc/kernel/align.c
@@ -334,7 +334,7 @@ int fix_alignment(struct pt_regs *regs)
if ((instr & 0xfc0006fe) == (PPC_INST_COPY & 0xfc0006fe))
return -EIO;
 
-   r = analyse_instr(, regs, instr);
+   r = analyse_instr(, regs, instr, PPC_NO_SUFFIX);
if (r < 0)
return -EINVAL;
 
diff --git a/a

[PATCH v2 04/13] powerpc sstep: Add support for prefixed load/stores

[Jordan Niethe]

This adds emulation support for the following prefixed integer
load/stores:
  * Prefixed Load Byte and Zero (plbz)
  * Prefixed Load Halfword and Zero (plhz)
  * Prefixed Load Halfword Algebraic (plha)
  * Prefixed Load Word and Zero (plwz)
  * Prefixed Load Word Algebraic (plwa)
  * Prefixed Load Doubleword (pld)
  * Prefixed Store Byte (pstb)
  * Prefixed Store Halfword (psth)
  * Prefixed Store Word (pstw)
  * Prefixed Store Doubleword (pstd)
  * Prefixed Load Quadword (plq)
  * Prefixed Store Quadword (pstq)

the follow prefixed floating-point load/stores:
  * Prefixed Load Floating-Point Single (plfs)
  * Prefixed Load Floating-Point Double (plfd)
  * Prefixed Store Floating-Point Single (pstfs)
  * Prefixed Store Floating-Point Double (pstfd)

and for the following prefixed VSX load/stores:
  * Prefixed Load VSX Scalar Doubleword (plxsd)
  * Prefixed Load VSX Scalar Single-Precision (plxssp)
  * Prefixed Load VSX Vector [0|1]  (plxv, plxv0, plxv1)
  * Prefixed Store VSX Scalar Doubleword (pstxsd)
  * Prefixed Store VSX Scalar Single-Precision (pstxssp)
  * Prefixed Store VSX Vector [0|1] (pstxv, pstxv0, pstxv1)

Signed-off-by: Jordan Niethe 
---
v2: - Combine all load/store patches
- Fix the name of Type 01 instructions
- Remove sign extension flag from pstd/pld
- Rename sufx -> suffix
---
 arch/powerpc/lib/sstep.c | 165 +++
 1 file changed, 165 insertions(+)

diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index 65143ab1bf64..0e21c21ff2be 100644
--- a/arch/powerpc/lib/sstep.c
+++ b/arch/powerpc/lib/sstep.c
@@ -187,6 +187,44 @@ static nokprobe_inline unsigned long xform_ea(unsigned int 
instr,
return ea;
 }
 
+/*
+ * Calculate effective address for a MLS:D-form / 8LS:D-form
+ * prefixed instruction
+ */
+static nokprobe_inline unsigned long mlsd_8lsd_ea(unsigned int instr,
+ unsigned int suffix,
+ const struct pt_regs *regs)
+{
+   int ra, prefix_r;
+   unsigned int  dd;
+   unsigned long ea, d0, d1, d;
+
+   prefix_r = instr & (1ul << 20);
+   ra = (suffix >> 16) & 0x1f;
+
+   d0 = instr & 0x3;
+   d1 = suffix & 0x;
+   d = (d0 << 16) | d1;
+
+   /*
+* sign extend a 34 bit number
+*/
+   dd = (unsigned int) (d >> 2);
+   ea = (signed int) dd;
+   ea = (ea << 2) | (d & 0x3);
+
+   if (!prefix_r && ra)
+   ea += regs->gpr[ra];
+   else if (!prefix_r && !ra)
+   ; /* Leave ea as is */
+   else if (prefix_r && !ra)
+   ea += regs->nip;
+   else if (prefix_r && ra)
+   ; /* Invalid form. Should already be checked for by caller! */
+
+   return ea;
+}
+
 /*
  * Return the largest power of 2, not greater than sizeof(unsigned long),
  * such that x is a multiple of it.
@@ -1166,6 +1204,7 @@ int analyse_instr(struct instruction_op *op, const struct 
pt_regs *regs,
  unsigned int instr, unsigned int suffix)
 {
unsigned int opcode, ra, rb, rc, rd, spr, u;
+   unsigned int suffixopcode, prefixtype, prefix_r;
unsigned long int imm;
unsigned long int val, val2;
unsigned int mb, me, sh;
@@ -2652,6 +2691,132 @@ int analyse_instr(struct instruction_op *op, const 
struct pt_regs *regs,
 
}
 
+/*
+ * Prefixed instructions
+ */
+   switch (opcode) {
+   case 1:
+   prefix_r = instr & (1ul << 20);
+   ra = (suffix >> 16) & 0x1f;
+   op->update_reg = ra;
+   rd = (suffix >> 21) & 0x1f;
+   op->reg = rd;
+   op->val = regs->gpr[rd];
+
+   suffixopcode = suffix >> 26;
+   prefixtype = (instr >> 24) & 0x3;
+   switch (prefixtype) {
+   case 0: /* Type 00  Eight-Byte Load/Store */
+   if (prefix_r && ra)
+   break;
+   op->ea = mlsd_8lsd_ea(instr, suffix, regs);
+   switch (suffixopcode) {
+   case 41:/* plwa */
+   op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 4);
+   break;
+   case 42:/* plxsd */
+   op->reg = rd + 32;
+   op->type = MKOP(LOAD_VSX, PREFIXED, 8);
+   op->element_size = 8;
+   op->vsx_flags = VSX_CHECK_VEC;
+   break;
+   case 43:/* plxssp */
+   op->reg = rd + 32;
+   op->type = MKOP(LOAD_VSX, PREFIXED, 4);
+  

[PATCH v2 08/13] powerpc/xmon: Add initial support for prefixed instructions

[Jordan Niethe]

A prefixed instruction is composed of a word prefix and a word suffix.
It does not make sense to be able to have a breakpoint on the suffix of
a prefixed instruction, so make this impossible.

When leaving xmon_core() we check to see if we are currently at a
breakpoint. If this is the case, the breakpoint needs to be proceeded
from. Initially emulate_step() is tried, but if this fails then we need
to execute the saved instruction out of line. The NIP is set to the
address of bpt::instr[] for the current breakpoint.  bpt::instr[]
contains the instruction replaced by the breakpoint, followed by a trap
instruction.  After bpt::instr[0] is executed and we hit the trap we
enter back into xmon_bpt(). We know that if we got here and the offset
indicates we are at bpt::instr[1] then we have just executed out of line
so we can put the NIP back to the instruction after the breakpoint
location and continue on.

Adding prefixed instructions complicates this as the bpt::instr[1] needs
to be used to hold the suffix. To deal with this make bpt::instr[] big
enough for three word instructions.  bpt::instr[2] contains the trap,
and in the case of word instructions pad bpt::instr[1] with a noop.

No support for disassembling prefixed instructions.

Signed-off-by: Jordan Niethe 
---
v2: Rename sufx to suffix
---
 arch/powerpc/xmon/xmon.c | 82 ++--
 1 file changed, 71 insertions(+), 11 deletions(-)

diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index 897e512c6379..0b085642bbe7 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -97,7 +97,8 @@ static long *xmon_fault_jmp[NR_CPUS];
 /* Breakpoint stuff */
 struct bpt {
unsigned long   address;
-   unsigned intinstr[2];
+   /* Prefixed instructions can not cross 64-byte boundaries */
+   unsigned intinstr[3] __aligned(64);
atomic_tref_count;
int enabled;
unsigned long   pad;
@@ -113,6 +114,7 @@ static struct bpt bpts[NBPTS];
 static struct bpt dabr;
 static struct bpt *iabr;
 static unsigned bpinstr = 0x7fe8;  /* trap */
+static unsigned nopinstr = 0x6000; /* nop */
 
 #define BP_NUM(bp) ((bp) - bpts + 1)
 
@@ -120,6 +122,7 @@ static unsigned bpinstr = 0x7fe8;   /* trap */
 static int cmds(struct pt_regs *);
 static int mread(unsigned long, void *, int);
 static int mwrite(unsigned long, void *, int);
+static int read_instr(unsigned long, unsigned int *, unsigned int *);
 static int handle_fault(struct pt_regs *);
 static void byterev(unsigned char *, int);
 static void memex(void);
@@ -706,7 +709,7 @@ static int xmon_core(struct pt_regs *regs, int fromipi)
bp = at_breakpoint(regs->nip);
if (bp != NULL) {
int stepped = emulate_step(regs, bp->instr[0],
-  PPC_NO_SUFFIX);
+  bp->instr[1]);
if (stepped == 0) {
regs->nip = (unsigned long) >instr[0];
atomic_inc(>ref_count);
@@ -761,8 +764,8 @@ static int xmon_bpt(struct pt_regs *regs)
 
/* Are we at the trap at bp->instr[1] for some bp? */
bp = in_breakpoint_table(regs->nip, );
-   if (bp != NULL && offset == 4) {
-   regs->nip = bp->address + 4;
+   if (bp != NULL && (offset == 4 || offset == 8)) {
+   regs->nip = bp->address + offset;
atomic_dec(>ref_count);
return 1;
}
@@ -864,7 +867,8 @@ static struct bpt *in_breakpoint_table(unsigned long nip, 
unsigned long *offp)
return NULL;
off %= sizeof(struct bpt);
if (off != offsetof(struct bpt, instr[0])
-   && off != offsetof(struct bpt, instr[1]))
+   && off != offsetof(struct bpt, instr[1])
+   && off != offsetof(struct bpt, instr[2]))
return NULL;
*offp = off - offsetof(struct bpt, instr[0]);
return (struct bpt *) (nip - off);
@@ -881,9 +885,18 @@ static struct bpt *new_breakpoint(unsigned long a)
 
for (bp = bpts; bp < [NBPTS]; ++bp) {
if (!bp->enabled && atomic_read(>ref_count) == 0) {
+   /*
+* Prefixed instructions are two words, but regular
+* instructions are only one. Use a nop to pad out the
+* regular instructions so that we can place the trap
+* at the same plac. For prefixed instructions the nop
+* will get overwritten during insert_bpts().
+*/
bp->address = a;
-   bp->instr[1] = bpinstr;
+   bp->instr[1] = nopinstr;
store_ins

[PATCH v2 13/13] powerpc: Add prefix support to mce_find_instr_ea_and_pfn()

[Jordan Niethe]

mce_find_instr_ea_and_pfn analyses an instruction to determine the
effective address that caused the machine check. Update this to load and
pass the suffix to analyse_instr for prefixed instructions.

Signed-off-by: Jordan Niethe 
---
v2: - Rename sufx to suffix
---
 arch/powerpc/kernel/mce_power.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/kernel/mce_power.c b/arch/powerpc/kernel/mce_power.c
index 824eda536f5d..091bab4a5464 100644
--- a/arch/powerpc/kernel/mce_power.c
+++ b/arch/powerpc/kernel/mce_power.c
@@ -365,7 +365,7 @@ static int mce_find_instr_ea_and_phys(struct pt_regs *regs, 
uint64_t *addr,
 * in real-mode is tricky and can lead to recursive
 * faults
 */
-   int instr;
+   int instr, suffix = 0;
unsigned long pfn, instr_addr;
struct instruction_op op;
struct pt_regs tmp = *regs;
@@ -374,7 +374,9 @@ static int mce_find_instr_ea_and_phys(struct pt_regs *regs, 
uint64_t *addr,
if (pfn != ULONG_MAX) {
instr_addr = (pfn << PAGE_SHIFT) + (regs->nip & ~PAGE_MASK);
instr = *(unsigned int *)(instr_addr);
-   if (!analyse_instr(, , instr, PPC_NO_SUFFIX)) {
+   if (IS_PREFIX(instr))
+   suffix = *(unsigned int *)(instr_addr + 4);
+   if (!analyse_instr(, , instr, suffix)) {
pfn = addr_to_pfn(regs, op.ea);
*addr = op.ea;
*phys_addr = (pfn << PAGE_SHIFT);
-- 
2.17.1

[PATCH v2 07/13] powerpc/traps: Check for prefixed instructions in facility_unavailable_exception()

[Jordan Niethe]

If prefixed instructions are made unavailable by the [H]FSCR, attempting
to use them will cause a facility unavailable exception. Add "PREFIX" to
the facility_strings[].

Currently there are no prefixed instructions that are actually emulated
by emulate_instruction() within facility_unavailable_exception().
However, when caused by a prefixed instructions the SRR1 PREFIXED bit is
set. Prepare for dealing with emulated prefixed instructions by checking
for this bit.

Signed-off-by: Jordan Niethe 
---
 arch/powerpc/kernel/traps.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index d80b82fc1ae3..cd8b3043c268 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -1739,6 +1739,7 @@ void facility_unavailable_exception(struct pt_regs *regs)
[FSCR_TAR_LG] = "TAR",
[FSCR_MSGP_LG] = "MSGP",
[FSCR_SCV_LG] = "SCV",
+   [FSCR_PREFIX_LG] = "PREFIX",
};
char *facility = "unknown";
u64 value;
-- 
2.17.1

[PATCH v2 05/13] powerpc sstep: Add support for prefixed fixed-point arithmetic

[Jordan Niethe]

This adds emulation support for the following prefixed Fixed-Point
Arithmetic instructions:
  * Prefixed Add Immediate (paddi)

Signed-off-by: Jordan Niethe 
---
 arch/powerpc/lib/sstep.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index 0e21c21ff2be..8ba74c10bc03 100644
--- a/arch/powerpc/lib/sstep.c
+++ b/arch/powerpc/lib/sstep.c
@@ -2777,6 +2777,10 @@ int analyse_instr(struct instruction_op *op, const 
struct pt_regs *regs,
break;
op->ea = mlsd_8lsd_ea(instr, suffix, regs);
switch (suffixopcode) {
+   case 14:/* paddi */
+   op->type = COMPUTE | PREFIXED;
+   op->val = op->ea;
+   goto compute_done;
case 32:/* plwz */
op->type = MKOP(LOAD, PREFIXED, 4);
break;
-- 
2.17.1

[PATCH v2 06/13] powerpc: Support prefixed instructions in alignment handler

[Jordan Niethe]

Alignment interrupts can be caused by prefixed instructions accessing
memory. In the alignment handler the instruction that caused the
exception is loaded and attempted emulate. If the instruction is a
prefixed instruction load the prefix and suffix to emulate. After
emulating increment the NIP by 8.

Prefixed instructions are not permitted to cross 64-byte boundaries. If
they do the alignment interrupt is invoked with SRR1 BOUNDARY bit set.
If this occurs send a SIGBUS to the offending process if in user mode.
If in kernel mode call bad_page_fault().

Signed-off-by: Jordan Niethe 
---
v2: - Move __get_user_instr() and __get_user_instr_inatomic() to this
commit (previously in "powerpc sstep: Prepare to support prefixed
instructions").
- Rename sufx to suffix
- Use a macro for calculating instruction length
---
 arch/powerpc/include/asm/uaccess.h | 30 ++
 arch/powerpc/kernel/align.c|  8 +---
 arch/powerpc/kernel/traps.c| 21 -
 3 files changed, 55 insertions(+), 4 deletions(-)

diff --git a/arch/powerpc/include/asm/uaccess.h 
b/arch/powerpc/include/asm/uaccess.h
index 2f500debae21..30f63a81c8d8 100644
--- a/arch/powerpc/include/asm/uaccess.h
+++ b/arch/powerpc/include/asm/uaccess.h
@@ -474,4 +474,34 @@ static __must_check inline bool user_access_begin(const 
void __user *ptr, size_t
 #define unsafe_copy_to_user(d, s, l, e) \
unsafe_op_wrap(raw_copy_to_user_allowed(d, s, l), e)
 
+/*
+ * When reading an instruction iff it is a prefix, the suffix needs to be also
+ * loaded.
+ */
+#define __get_user_instr(x, y, ptr)\
+({ \
+   long __gui_ret = 0; \
+   y = 0;  \
+   __gui_ret = __get_user(x, ptr); \
+   if (!__gui_ret) {   \
+   if (IS_PREFIX(x))   \
+   __gui_ret = __get_user(y, ptr + 1); \
+   }   \
+   \
+   __gui_ret;  \
+})
+
+#define __get_user_instr_inatomic(x, y, ptr)   \
+({ \
+   long __gui_ret = 0; \
+   y = 0;  \
+   __gui_ret = __get_user_inatomic(x, ptr);\
+   if (!__gui_ret) {   \
+   if (IS_PREFIX(x))   \
+   __gui_ret = __get_user_inatomic(y, ptr + 1);\
+   }   \
+   \
+   __gui_ret;  \
+})
+
 #endif /* _ARCH_POWERPC_UACCESS_H */
diff --git a/arch/powerpc/kernel/align.c b/arch/powerpc/kernel/align.c
index ba3bf5c3ab62..e42cfaa616d3 100644
--- a/arch/powerpc/kernel/align.c
+++ b/arch/powerpc/kernel/align.c
@@ -293,7 +293,7 @@ static int emulate_spe(struct pt_regs *regs, unsigned int 
reg,
 
 int fix_alignment(struct pt_regs *regs)
 {
-   unsigned int instr;
+   unsigned int instr, suffix;
struct instruction_op op;
int r, type;
 
@@ -303,13 +303,15 @@ int fix_alignment(struct pt_regs *regs)
 */
CHECK_FULL_REGS(regs);
 
-   if (unlikely(__get_user(instr, (unsigned int __user *)regs->nip)))
+   if (unlikely(__get_user_instr(instr, suffix,
+(unsigned int __user *)regs->nip)))
return -EFAULT;
if ((regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE)) {
/* We don't handle PPC little-endian any more... */
if (cpu_has_feature(CPU_FTR_PPC_LE))
return -EIO;
instr = swab32(instr);
+   suffix = swab32(suffix);
}
 
 #ifdef CONFIG_SPE
@@ -334,7 +336,7 @@ int fix_alignment(struct pt_regs *regs)
if ((instr & 0xfc0006fe) == (PPC_INST_COPY & 0xfc0006fe))
return -EIO;
 
-   r = analyse_instr(, regs, instr, PPC_NO_SUFFIX);
+   r = analyse_instr(, regs, instr, suffix);
if (r < 0)
return -EINVAL;
 
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 82a3438300fd..d80b82fc1ae3 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -583,6 +583,10 @@ static inline int check_io_access(struct pt_regs *regs)
 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
 #define REASON_PRIVILEGED  ESR_PPR
 #define REASON_TRAPESR_PTR
+#define REASON_PREFIXED0
+#define REASON_BOUNDARY0
+
+#define inst_length(reason)4
 
 /* single-step stuff */
 #define single_stepping(regs)  (current->thread.debug.dbcr0 & DBC

[PATCH v2 01/13] powerpc: Enable Prefixed Instructions

[Jordan Niethe]

From: Alistair Popple 

Prefix instructions have their own FSCR bit which needs to enabled via
a CPU feature. The kernel will save the FSCR for problem state but it
needs to be enabled initially.

Signed-off-by: Alistair Popple 
---
 arch/powerpc/include/asm/reg.h|  3 +++
 arch/powerpc/kernel/dt_cpu_ftrs.c | 23 +++
 2 files changed, 26 insertions(+)

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 1aa46dff0957..c7758c2ccc5f 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -397,6 +397,7 @@
 #define SPRN_RWMR  0x375   /* Region-Weighting Mode Register */
 
 /* HFSCR and FSCR bit numbers are the same */
+#define FSCR_PREFIX_LG 13  /* Enable Prefix Instructions */
 #define FSCR_SCV_LG12  /* Enable System Call Vectored */
 #define FSCR_MSGP_LG   10  /* Enable MSGP */
 #define FSCR_TAR_LG8   /* Enable Target Address Register */
@@ -408,11 +409,13 @@
 #define FSCR_VECVSX_LG 1   /* Enable VMX/VSX  */
 #define FSCR_FP_LG 0   /* Enable Floating Point */
 #define SPRN_FSCR  0x099   /* Facility Status & Control Register */
+#define   FSCR_PREFIX  __MASK(FSCR_PREFIX_LG)
 #define   FSCR_SCV __MASK(FSCR_SCV_LG)
 #define   FSCR_TAR __MASK(FSCR_TAR_LG)
 #define   FSCR_EBB __MASK(FSCR_EBB_LG)
 #define   FSCR_DSCR__MASK(FSCR_DSCR_LG)
 #define SPRN_HFSCR 0xbe/* HV=1 Facility Status & Control Register */
+#define   HFSCR_PREFIX __MASK(FSCR_PREFIX_LG)
 #define   HFSCR_MSGP   __MASK(FSCR_MSGP_LG)
 #define   HFSCR_TAR__MASK(FSCR_TAR_LG)
 #define   HFSCR_EBB__MASK(FSCR_EBB_LG)
diff --git a/arch/powerpc/kernel/dt_cpu_ftrs.c 
b/arch/powerpc/kernel/dt_cpu_ftrs.c
index 182b4047c1ef..396f2c6c588e 100644
--- a/arch/powerpc/kernel/dt_cpu_ftrs.c
+++ b/arch/powerpc/kernel/dt_cpu_ftrs.c
@@ -553,6 +553,28 @@ static int __init feat_enable_large_ci(struct 
dt_cpu_feature *f)
return 1;
 }
 
+static int __init feat_enable_prefix(struct dt_cpu_feature *f)
+{
+   u64 fscr, hfscr;
+
+   if (f->usable_privilege & USABLE_HV) {
+   hfscr = mfspr(SPRN_HFSCR);
+   hfscr |= HFSCR_PREFIX;
+   mtspr(SPRN_HFSCR, hfscr);
+   }
+
+   if (f->usable_privilege & USABLE_OS) {
+   fscr = mfspr(SPRN_FSCR);
+   fscr |= FSCR_PREFIX;
+   mtspr(SPRN_FSCR, fscr);
+
+   if (f->usable_privilege & USABLE_PR)
+   current->thread.fscr |= FSCR_PREFIX;
+   }
+
+   return 1;
+}
+
 struct dt_cpu_feature_match {
const char *name;
int (*enable)(struct dt_cpu_feature *f);
@@ -626,6 +648,7 @@ static struct dt_cpu_feature_match __initdata
{"vector-binary128", feat_enable, 0},
{"vector-binary16", feat_enable, 0},
{"wait-v3", feat_enable, 0},
+   {"prefix-instructions", feat_enable_prefix, 0},
 };
 
 static bool __initdata using_dt_cpu_ftrs;
-- 
2.17.1

[PATCH v2 00/13] Initial Prefixed Instruction support

[Jordan Niethe]

A future revision of the ISA will introduce prefixed instructions. A
prefixed instruction is composed of a 4-byte prefix followed by a
4-byte suffix.

All prefixes have the major opcode 1. A prefix will never be a valid
word instruction. A suffix may be an existing word instruction or a
new instruction.

This series enables prefixed instructions and extends the instruction
emulation to support them. Then the places where prefixed instructions
might need to be emulated are updated.

This v2 incorporates feedback from Daniel Axtens and and Balamuruhan
S. The major changes are:
- Squashing together all commits about SRR1 bits
- Squashing all commits for supporting prefixed load stores
- Changing abbreviated references to sufx/prfx -> suffix/prefix
- Introducing macros for returning the length of an instruction
- Removing sign extension flag from pstd/pld in sstep.c
- Dropping patch  "powerpc/fault: Use analyse_instr() to check for
  store with updates to sp" from the series, it did not really fit
  with prefixed enablement in the first place and as reported by Greg
  Kurz did not work correctly.


Alistair Popple (1):
  powerpc: Enable Prefixed Instructions

Jordan Niethe (12):
  powerpc: Define new SRR1 bits for a future ISA version
  powerpc sstep: Prepare to support prefixed instructions
  powerpc sstep: Add support for prefixed load/stores
  powerpc sstep: Add support for prefixed fixed-point arithmetic
  powerpc: Support prefixed instructions in alignment handler
  powerpc/traps: Check for prefixed instructions in
facility_unavailable_exception()
  powerpc/xmon: Add initial support for prefixed instructions
  powerpc/xmon: Dump prefixed instructions
  powerpc/kprobes: Support kprobes on prefixed instructions
  powerpc/uprobes: Add support for prefixed instructions
  powerpc/hw_breakpoints: Initial support for prefixed instructions
  powerpc: Add prefix support to mce_find_instr_ea_and_pfn()

 arch/powerpc/include/asm/kprobes.h|   5 +-
 arch/powerpc/include/asm/ppc-opcode.h |   5 +
 arch/powerpc/include/asm/reg.h|   7 +-
 arch/powerpc/include/asm/sstep.h  |   9 +-
 arch/powerpc/include/asm/uaccess.h|  30 +
 arch/powerpc/include/asm/uprobes.h|  16 ++-
 arch/powerpc/kernel/align.c   |   8 +-
 arch/powerpc/kernel/dt_cpu_ftrs.c |  23 
 arch/powerpc/kernel/hw_breakpoint.c   |   8 +-
 arch/powerpc/kernel/kprobes.c |  47 +--
 arch/powerpc/kernel/mce_power.c   |   6 +-
 arch/powerpc/kernel/optprobes.c   |  31 +++--
 arch/powerpc/kernel/optprobes_head.S  |   6 +
 arch/powerpc/kernel/traps.c   |  22 +++-
 arch/powerpc/kernel/uprobes.c |   4 +-
 arch/powerpc/kvm/book3s_hv_nested.c   |   2 +-
 arch/powerpc/kvm/book3s_hv_rm_mmu.c   |   2 +-
 arch/powerpc/kvm/emulate_loadstore.c  |   2 +-
 arch/powerpc/lib/sstep.c  | 181 +-
 arch/powerpc/lib/test_emulate_step.c  |  30 ++---
 arch/powerpc/xmon/xmon.c  | 133 +++
 21 files changed, 487 insertions(+), 90 deletions(-)

-- 
2.17.1

[PATCH v2 02/13] powerpc: Define new SRR1 bits for a future ISA version

[Jordan Niethe]

Add the BOUNDARY SRR1 bit definition for when the cause of an alignment
exception is a prefixed instruction that crosses a 64-byte boundary.
Add the PREFIXED SRR1 bit definition for exceptions caused by prefixed
instructions.

Bit 35 of SRR1 is called SRR1_ISI_N_OR_G. This name comes from it being
used to indicate that an ISI was due to the access being no-exec or
guarded. A future ISA version adds another purpose. It is also set if
there is an access in a cache-inhibited location for prefixed
instruction.  Rename from SRR1_ISI_N_OR_G to SRR1_ISI_N_G_OR_CIP.

Signed-off-by: Jordan Niethe 
---
v2: Combined all the commits concerning SRR1 bits.
---
 arch/powerpc/include/asm/reg.h  | 4 +++-
 arch/powerpc/kvm/book3s_hv_nested.c | 2 +-
 arch/powerpc/kvm/book3s_hv_rm_mmu.c | 2 +-
 3 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index c7758c2ccc5f..173f33df4fab 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -762,7 +762,7 @@
 #endif
 
 #define   SRR1_ISI_NOPT0x4000 /* ISI: Not found in hash */
-#define   SRR1_ISI_N_OR_G  0x1000 /* ISI: Access is no-exec or G */
+#define   SRR1_ISI_N_G_OR_CIP  0x1000 /* ISI: Access is no-exec or G or CI 
for a prefixed instruction */
 #define   SRR1_ISI_PROT0x0800 /* ISI: Other protection 
fault */
 #define   SRR1_WAKEMASK0x0038 /* reason for wakeup */
 #define   SRR1_WAKEMASK_P8 0x003c /* reason for wakeup on POWER8 and 9 
*/
@@ -789,6 +789,8 @@
 #define   SRR1_PROGADDR0x0001 /* SRR0 contains subsequent 
addr */
 
 #define   SRR1_MCE_MCP 0x0008 /* Machine check signal caused 
interrupt */
+#define   SRR1_BOUNDARY0x1000 /* Prefixed instruction 
crosses 64-byte boundary */
+#define   SRR1_PREFIXED0x2000 /* Exception caused by 
prefixed instruction */
 
 #define SPRN_HSRR0 0x13A   /* Save/Restore Register 0 */
 #define SPRN_HSRR1 0x13B   /* Save/Restore Register 1 */
diff --git a/arch/powerpc/kvm/book3s_hv_nested.c 
b/arch/powerpc/kvm/book3s_hv_nested.c
index dc97e5be76f6..6ab685227574 100644
--- a/arch/powerpc/kvm/book3s_hv_nested.c
+++ b/arch/powerpc/kvm/book3s_hv_nested.c
@@ -1169,7 +1169,7 @@ static int kvmhv_translate_addr_nested(struct kvm_vcpu 
*vcpu,
} else if (vcpu->arch.trap == BOOK3S_INTERRUPT_H_INST_STORAGE) {
/* Can we execute? */
if (!gpte_p->may_execute) {
-   flags |= SRR1_ISI_N_OR_G;
+   flags |= SRR1_ISI_N_G_OR_CIP;
goto forward_to_l1;
}
} else {
diff --git a/arch/powerpc/kvm/book3s_hv_rm_mmu.c 
b/arch/powerpc/kvm/book3s_hv_rm_mmu.c
index 220305454c23..b53a9f1c1a46 100644
--- a/arch/powerpc/kvm/book3s_hv_rm_mmu.c
+++ b/arch/powerpc/kvm/book3s_hv_rm_mmu.c
@@ -1260,7 +1260,7 @@ long kvmppc_hpte_hv_fault(struct kvm_vcpu *vcpu, unsigned 
long addr,
status &= ~DSISR_NOHPTE;/* DSISR_NOHPTE == SRR1_ISI_NOPT */
if (!data) {
if (gr & (HPTE_R_N | HPTE_R_G))
-   return status | SRR1_ISI_N_OR_G;
+   return status | SRR1_ISI_N_G_OR_CIP;
if (!hpte_read_permission(pp, slb_v & key))
return status | SRR1_ISI_PROT;
} else if (status & DSISR_ISSTORE) {
-- 
2.17.1

[PATCH v2 10/13] powerpc/kprobes: Support kprobes on prefixed instructions

[Jordan Niethe]

A prefixed instruction is composed of a word prefix followed by a word
suffix. It does not make sense to be able to have a kprobe on the suffix
of a prefixed instruction, so make this impossible.

Kprobes work by replacing an instruction with a trap and saving that
instruction to be single stepped out of place later. Currently there is
not enough space allocated to keep a prefixed instruction for single
stepping. Increase the amount of space allocated for holding the
instruction copy.

kprobe_post_handler() expects all instructions to be 4 bytes long which
means that it does not function correctly for prefixed instructions.
Add checks for prefixed instructions which will use a length of 8 bytes
instead.

For optprobes we normally patch in loading the instruction we put a
probe on into r4 before calling emulate_step(). We now make space and
patch in loading the suffix into r5 as well.

Signed-off-by: Jordan Niethe 
---
 arch/powerpc/include/asm/kprobes.h   |  5 +--
 arch/powerpc/kernel/kprobes.c| 47 +---
 arch/powerpc/kernel/optprobes.c  | 32 ++-
 arch/powerpc/kernel/optprobes_head.S |  6 
 4 files changed, 63 insertions(+), 27 deletions(-)

diff --git a/arch/powerpc/include/asm/kprobes.h 
b/arch/powerpc/include/asm/kprobes.h
index 66b3f2983b22..0d44ce8a3163 100644
--- a/arch/powerpc/include/asm/kprobes.h
+++ b/arch/powerpc/include/asm/kprobes.h
@@ -38,12 +38,13 @@ extern kprobe_opcode_t optprobe_template_entry[];
 extern kprobe_opcode_t optprobe_template_op_address[];
 extern kprobe_opcode_t optprobe_template_call_handler[];
 extern kprobe_opcode_t optprobe_template_insn[];
+extern kprobe_opcode_t optprobe_template_suffix[];
 extern kprobe_opcode_t optprobe_template_call_emulate[];
 extern kprobe_opcode_t optprobe_template_ret[];
 extern kprobe_opcode_t optprobe_template_end[];
 
-/* Fixed instruction size for powerpc */
-#define MAX_INSN_SIZE  1
+/* Prefixed instructions are two words */
+#define MAX_INSN_SIZE  2
 #define MAX_OPTIMIZED_LENGTH   sizeof(kprobe_opcode_t) /* 4 bytes */
 #define MAX_OPTINSN_SIZE   (optprobe_template_end - 
optprobe_template_entry)
 #define RELATIVEJUMP_SIZE  sizeof(kprobe_opcode_t) /* 4 bytes */
diff --git a/arch/powerpc/kernel/kprobes.c b/arch/powerpc/kernel/kprobes.c
index 24a56f062d9e..b061deba4fe7 100644
--- a/arch/powerpc/kernel/kprobes.c
+++ b/arch/powerpc/kernel/kprobes.c
@@ -104,17 +104,30 @@ kprobe_opcode_t *kprobe_lookup_name(const char *name, 
unsigned int offset)
 
 int arch_prepare_kprobe(struct kprobe *p)
 {
+   int len;
int ret = 0;
+   struct kprobe *prev;
kprobe_opcode_t insn = *p->addr;
+   kprobe_opcode_t prefix = *(p->addr - 1);
 
+   preempt_disable();
if ((unsigned long)p->addr & 0x03) {
printk("Attempt to register kprobe at an unaligned address\n");
ret = -EINVAL;
} else if (IS_MTMSRD(insn) || IS_RFID(insn) || IS_RFI(insn)) {
printk("Cannot register a kprobe on rfi/rfid or mtmsr[d]\n");
ret = -EINVAL;
+   } else if (IS_PREFIX(prefix)) {
+   printk("Cannot register a kprobe on the second word of prefixed 
instruction\n");
+   ret = -EINVAL;
+   }
+   prev = get_kprobe(p->addr - 1);
+   if (prev && IS_PREFIX(*prev->ainsn.insn)) {
+   printk("Cannot register a kprobe on the second word of prefixed 
instruction\n");
+   ret = -EINVAL;
}
 
+
/* insn must be on a special executable page on ppc64.  This is
 * not explicitly required on ppc32 (right now), but it doesn't hurt */
if (!ret) {
@@ -124,14 +137,18 @@ int arch_prepare_kprobe(struct kprobe *p)
}
 
if (!ret) {
-   memcpy(p->ainsn.insn, p->addr,
-   MAX_INSN_SIZE * sizeof(kprobe_opcode_t));
+   if (IS_PREFIX(insn))
+   len = MAX_INSN_SIZE * sizeof(kprobe_opcode_t);
+   else
+   len = sizeof(kprobe_opcode_t);
+   memcpy(p->ainsn.insn, p->addr, len);
p->opcode = *p->addr;
flush_icache_range((unsigned long)p->ainsn.insn,
(unsigned long)p->ainsn.insn + sizeof(kprobe_opcode_t));
}
 
p->ainsn.boostable = 0;
+   preempt_enable_no_resched();
return ret;
 }
 NOKPROBE_SYMBOL(arch_prepare_kprobe);
@@ -216,10 +233,11 @@ NOKPROBE_SYMBOL(arch_prepare_kretprobe);
 static int try_to_emulate(struct kprobe *p, struct pt_regs *regs)
 {
int ret;
-   unsigned int insn = *p->ainsn.insn;
+   unsigned int insn = p->ainsn.insn[0];
+   unsigned int suffix = p->ainsn.insn[1];
 
/* regs->nip is also adjusted if emulate_step returns 1 */
-   ret = emulate_step(regs, insn, PPC_NO_SUFFIX);
+  

[PATCH v2 09/13] powerpc/xmon: Dump prefixed instructions

[Jordan Niethe]

Currently when xmon is dumping instructions it reads a word at a time
and then prints that instruction (either as a hex number or by
disassembling it). For prefixed instructions it would be nice to show
its prefix and suffix as together. Use read_instr() so that if a prefix
is encountered its suffix is loaded too. Then print these in the form:
prefix:suffix
Xmon uses the disassembly routines from GNU binutils. These currently do
not support prefixed instructions so we will not disassemble the
prefixed instructions yet.

Signed-off-by: Jordan Niethe 
---
v2: Rename sufx to suffix
---
 arch/powerpc/xmon/xmon.c | 50 +++-
 1 file changed, 39 insertions(+), 11 deletions(-)

diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index 0b085642bbe7..513901ee18b0 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -2903,6 +2903,21 @@ prdump(unsigned long adrs, long ndump)
}
 }
 
+static bool instrs_are_equal(unsigned long insta, unsigned long suffixa,
+unsigned long instb, unsigned long suffixb)
+{
+   if (insta != instb)
+   return false;
+
+   if (!IS_PREFIX(insta) && !IS_PREFIX(instb))
+   return true;
+
+   if (IS_PREFIX(insta) && IS_PREFIX(instb))
+   return suffixa == suffixb;
+
+   return false;
+}
+
 typedef int (*instruction_dump_func)(unsigned long inst, unsigned long addr);
 
 static int
@@ -2911,12 +2926,11 @@ generic_inst_dump(unsigned long adr, long count, int 
praddr,
 {
int nr, dotted;
unsigned long first_adr;
-   unsigned int inst, last_inst = 0;
-   unsigned char val[4];
+   unsigned int inst, suffix, last_inst = 0, last_suffix = 0;
 
dotted = 0;
-   for (first_adr = adr; count > 0; --count, adr += 4) {
-   nr = mread(adr, val, 4);
+   for (first_adr = adr; count > 0; --count, adr += nr) {
+   nr = read_instr(adr, , );
if (nr == 0) {
if (praddr) {
const char *x = fault_chars[fault_type];
@@ -2924,8 +2938,9 @@ generic_inst_dump(unsigned long adr, long count, int 
praddr,
}
break;
}
-   inst = GETWORD(val);
-   if (adr > first_adr && inst == last_inst) {
+   if (adr > first_adr && instrs_are_equal(inst, suffix,
+   last_inst,
+   last_suffix)) {
if (!dotted) {
printf(" ...\n");
dotted = 1;
@@ -2934,11 +2949,24 @@ generic_inst_dump(unsigned long adr, long count, int 
praddr,
}
dotted = 0;
last_inst = inst;
-   if (praddr)
-   printf(REG"  %.8x", adr, inst);
-   printf("\t");
-   dump_func(inst, adr);
-   printf("\n");
+   last_suffix = suffix;
+   if (IS_PREFIX(inst)) {
+   if (praddr)
+   printf(REG"  %.8x:%.8x", adr, inst, suffix);
+   printf("\t");
+   /*
+* Just use this until binutils ppc disassembly
+* prints prefixed instructions.
+*/
+   printf("%.8x:%.8x", inst, suffix);
+   printf("\n");
+   } else {
+   if (praddr)
+   printf(REG"  %.8x", adr, inst);
+   printf("\t");
+   dump_func(inst, adr);
+   printf("\n");
+   }
}
return adr - first_adr;
 }
-- 
2.17.1

[PATCH v3 08/14] powerpc/xmon: Remove store_inst() for patch_instruction()

[Jordan Niethe]

For modifying instructions in xmon, patch_instruction() can serve the
same role that store_inst() is performing with the advantage of not
being specific to xmon. In some places patch_instruction() is already
being using followed by store_inst(). In these cases just remove the
store_inst(). Otherwise replace store_inst() with patch_instruction().

Signed-off-by: Jordan Niethe 
---
 arch/powerpc/xmon/xmon.c | 13 ++---
 1 file changed, 2 insertions(+), 11 deletions(-)

diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index 897e512c6379..a673cf55641c 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -325,11 +325,6 @@ static inline void sync(void)
asm volatile("sync; isync");
 }
 
-static inline void store_inst(void *p)
-{
-   asm volatile ("dcbst 0,%0; sync; icbi 0,%0; isync" : : "r" (p));
-}
-
 static inline void cflush(void *p)
 {
asm volatile ("dcbf 0,%0; icbi 0,%0" : : "r" (p));
@@ -882,8 +877,7 @@ static struct bpt *new_breakpoint(unsigned long a)
for (bp = bpts; bp < [NBPTS]; ++bp) {
if (!bp->enabled && atomic_read(>ref_count) == 0) {
bp->address = a;
-   bp->instr[1] = bpinstr;
-   store_inst(>instr[1]);
+   patch_instruction(>instr[1], bpinstr);
return bp;
}
}
@@ -913,7 +907,7 @@ static void insert_bpts(void)
bp->enabled = 0;
continue;
}
-   store_inst(>instr[0]);
+   patch_instruction(>instr[0], bp->instr[0]);
if (bp->enabled & BP_CIABR)
continue;
if (patch_instruction((unsigned int *)bp->address,
@@ -923,7 +917,6 @@ static void insert_bpts(void)
bp->enabled &= ~BP_TRAP;
continue;
}
-   store_inst((void *)bp->address);
}
 }
 
@@ -958,8 +951,6 @@ static void remove_bpts(void)
(unsigned int *)bp->address, bp->instr[0]) != 0)
printf("Couldn't remove breakpoint at %lx\n",
   bp->address);
-   else
-   store_inst((void *)bp->address);
}
 }
 
-- 
2.17.1

[PATCH v3 09/14] powerpc/xmon: Add initial support for prefixed instructions

[Jordan Niethe]

A prefixed instruction is composed of a word prefix and a word suffix.
It does not make sense to be able to have a breakpoint on the suffix of
a prefixed instruction, so make this impossible.

When leaving xmon_core() we check to see if we are currently at a
breakpoint. If this is the case, the breakpoint needs to be proceeded
from. Initially emulate_step() is tried, but if this fails then we need
to execute the saved instruction out of line. The NIP is set to the
address of bpt::instr[] for the current breakpoint.  bpt::instr[]
contains the instruction replaced by the breakpoint, followed by a trap
instruction.  After bpt::instr[0] is executed and we hit the trap we
enter back into xmon_bpt(). We know that if we got here and the offset
indicates we are at bpt::instr[1] then we have just executed out of line
so we can put the NIP back to the instruction after the breakpoint
location and continue on.

Adding prefixed instructions complicates this as the bpt::instr[1] needs
to be used to hold the suffix. To deal with this make bpt::instr[] big
enough for three word instructions.  bpt::instr[2] contains the trap,
and in the case of word instructions pad bpt::instr[1] with a noop.

No support for disassembling prefixed instructions.

Signed-off-by: Jordan Niethe 
---
v2: Rename sufx to suffix
v3: - Just directly use PPC_INST_NOP
- Typo: plac -> place
- Rename read_inst() to mread_inst(). Do not have it call mread().
---
 arch/powerpc/xmon/xmon.c | 90 ++--
 1 file changed, 78 insertions(+), 12 deletions(-)

diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index a673cf55641c..a73a35aa4a75 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -97,7 +97,8 @@ static long *xmon_fault_jmp[NR_CPUS];
 /* Breakpoint stuff */
 struct bpt {
unsigned long   address;
-   unsigned intinstr[2];
+   /* Prefixed instructions can not cross 64-byte boundaries */
+   unsigned intinstr[3] __aligned(64);
atomic_tref_count;
int enabled;
unsigned long   pad;
@@ -120,6 +121,7 @@ static unsigned bpinstr = 0x7fe8;   /* trap */
 static int cmds(struct pt_regs *);
 static int mread(unsigned long, void *, int);
 static int mwrite(unsigned long, void *, int);
+static int mread_instr(unsigned long, unsigned int *, unsigned int *);
 static int handle_fault(struct pt_regs *);
 static void byterev(unsigned char *, int);
 static void memex(void);
@@ -701,7 +703,7 @@ static int xmon_core(struct pt_regs *regs, int fromipi)
bp = at_breakpoint(regs->nip);
if (bp != NULL) {
int stepped = emulate_step(regs, bp->instr[0],
-  PPC_NO_SUFFIX);
+  bp->instr[1]);
if (stepped == 0) {
regs->nip = (unsigned long) >instr[0];
atomic_inc(>ref_count);
@@ -756,8 +758,8 @@ static int xmon_bpt(struct pt_regs *regs)
 
/* Are we at the trap at bp->instr[1] for some bp? */
bp = in_breakpoint_table(regs->nip, );
-   if (bp != NULL && offset == 4) {
-   regs->nip = bp->address + 4;
+   if (bp != NULL && (offset == 4 || offset == 8)) {
+   regs->nip = bp->address + offset;
atomic_dec(>ref_count);
return 1;
}
@@ -858,8 +860,9 @@ static struct bpt *in_breakpoint_table(unsigned long nip, 
unsigned long *offp)
if (off >= sizeof(bpts))
return NULL;
off %= sizeof(struct bpt);
-   if (off != offsetof(struct bpt, instr[0])
-   && off != offsetof(struct bpt, instr[1]))
+   if (off != offsetof(struct bpt, instr[0]) &&
+   off != offsetof(struct bpt, instr[1]) &&
+   off != offsetof(struct bpt, instr[2]))
return NULL;
*offp = off - offsetof(struct bpt, instr[0]);
return (struct bpt *) (nip - off);
@@ -876,8 +879,16 @@ static struct bpt *new_breakpoint(unsigned long a)
 
for (bp = bpts; bp < [NBPTS]; ++bp) {
if (!bp->enabled && atomic_read(>ref_count) == 0) {
+   /*
+* Prefixed instructions are two words, but regular
+* instructions are only one. Use a nop to pad out the
+* regular instructions so that we can place the trap
+* at the same place. For prefixed instructions the nop
+* will get overwritten during insert_bpts().
+*/
bp->address = a;
-   patch_instruction(>instr[1], bpinstr);
+   patch_instruction(>instr[1], 

[PATCH v3 11/14] powerpc/kprobes: Support kprobes on prefixed instructions

[Jordan Niethe]

A prefixed instruction is composed of a word prefix followed by a word
suffix. It does not make sense to be able to have a kprobe on the suffix
of a prefixed instruction, so make this impossible.

Kprobes work by replacing an instruction with a trap and saving that
instruction to be single stepped out of place later. Currently there is
not enough space allocated to keep a prefixed instruction for single
stepping. Increase the amount of space allocated for holding the
instruction copy.

kprobe_post_handler() expects all instructions to be 4 bytes long which
means that it does not function correctly for prefixed instructions.
Add checks for prefixed instructions which will use a length of 8 bytes
instead.

For optprobes we normally patch in loading the instruction we put a
probe on into r4 before calling emulate_step(). We now make space and
patch in loading the suffix into r5 as well.

Signed-off-by: Jordan Niethe 
---
v3: - Base on top of  https://patchwork.ozlabs.org/patch/1232619/
- Change printing format to %x:%x
---
 arch/powerpc/include/asm/kprobes.h   |  5 ++--
 arch/powerpc/kernel/kprobes.c| 43 +---
 arch/powerpc/kernel/optprobes.c  | 32 -
 arch/powerpc/kernel/optprobes_head.S |  6 
 4 files changed, 60 insertions(+), 26 deletions(-)

diff --git a/arch/powerpc/include/asm/kprobes.h 
b/arch/powerpc/include/asm/kprobes.h
index 66b3f2983b22..0d44ce8a3163 100644
--- a/arch/powerpc/include/asm/kprobes.h
+++ b/arch/powerpc/include/asm/kprobes.h
@@ -38,12 +38,13 @@ extern kprobe_opcode_t optprobe_template_entry[];
 extern kprobe_opcode_t optprobe_template_op_address[];
 extern kprobe_opcode_t optprobe_template_call_handler[];
 extern kprobe_opcode_t optprobe_template_insn[];
+extern kprobe_opcode_t optprobe_template_suffix[];
 extern kprobe_opcode_t optprobe_template_call_emulate[];
 extern kprobe_opcode_t optprobe_template_ret[];
 extern kprobe_opcode_t optprobe_template_end[];
 
-/* Fixed instruction size for powerpc */
-#define MAX_INSN_SIZE  1
+/* Prefixed instructions are two words */
+#define MAX_INSN_SIZE  2
 #define MAX_OPTIMIZED_LENGTH   sizeof(kprobe_opcode_t) /* 4 bytes */
 #define MAX_OPTINSN_SIZE   (optprobe_template_end - 
optprobe_template_entry)
 #define RELATIVEJUMP_SIZE  sizeof(kprobe_opcode_t) /* 4 bytes */
diff --git a/arch/powerpc/kernel/kprobes.c b/arch/powerpc/kernel/kprobes.c
index 6b2e9e37f12b..9ccf1b9a1275 100644
--- a/arch/powerpc/kernel/kprobes.c
+++ b/arch/powerpc/kernel/kprobes.c
@@ -117,16 +117,28 @@ void *alloc_insn_page(void)
 int arch_prepare_kprobe(struct kprobe *p)
 {
int ret = 0;
+   struct kprobe *prev;
kprobe_opcode_t insn = *p->addr;
+   kprobe_opcode_t prefix = *(p->addr - 1);
 
+   preempt_disable();
if ((unsigned long)p->addr & 0x03) {
printk("Attempt to register kprobe at an unaligned address\n");
ret = -EINVAL;
} else if (IS_MTMSRD(insn) || IS_RFID(insn) || IS_RFI(insn)) {
printk("Cannot register a kprobe on rfi/rfid or mtmsr[d]\n");
ret = -EINVAL;
+   } else if (IS_PREFIX(prefix)) {
+   printk("Cannot register a kprobe on the second word of prefixed 
instruction\n");
+   ret = -EINVAL;
+   }
+   prev = get_kprobe(p->addr - 1);
+   if (prev && IS_PREFIX(*prev->ainsn.insn)) {
+   printk("Cannot register a kprobe on the second word of prefixed 
instruction\n");
+   ret = -EINVAL;
}
 
+
/* insn must be on a special executable page on ppc64.  This is
 * not explicitly required on ppc32 (right now), but it doesn't hurt */
if (!ret) {
@@ -136,11 +148,14 @@ int arch_prepare_kprobe(struct kprobe *p)
}
 
if (!ret) {
-   patch_instruction(p->ainsn.insn, *p->addr);
+   patch_instruction(>ainsn.insn[0], p->addr[0]);
+   if (IS_PREFIX(insn))
+   patch_instruction(>ainsn.insn[1], p->addr[1]);
p->opcode = *p->addr;
}
 
p->ainsn.boostable = 0;
+   preempt_enable_no_resched();
return ret;
 }
 NOKPROBE_SYMBOL(arch_prepare_kprobe);
@@ -225,10 +240,11 @@ NOKPROBE_SYMBOL(arch_prepare_kretprobe);
 static int try_to_emulate(struct kprobe *p, struct pt_regs *regs)
 {
int ret;
-   unsigned int insn = *p->ainsn.insn;
+   unsigned int insn = p->ainsn.insn[0];
+   unsigned int suffix = p->ainsn.insn[1];
 
/* regs->nip is also adjusted if emulate_step returns 1 */
-   ret = emulate_step(regs, insn, PPC_NO_SUFFIX);
+   ret = emulate_step(regs, insn, suffix);
if (ret > 0) {
/*
 * Once this instruction has been boosted
@@ -242,7 +258,11 @@ static int try_to_emulate(struct kprobe *p, struct pt_regs 
*regs)

[PATCH v3 10/14] powerpc/xmon: Dump prefixed instructions

[Jordan Niethe]

Currently when xmon is dumping instructions it reads a word at a time
and then prints that instruction (either as a hex number or by
disassembling it). For prefixed instructions it would be nice to show
its prefix and suffix as together. Use read_instr() so that if a prefix
is encountered its suffix is loaded too. Then print these in the form:
prefix:suffix
Xmon uses the disassembly routines from GNU binutils. These currently do
not support prefixed instructions so we will not disassemble the
prefixed instructions yet.

Signed-off-by: Jordan Niethe 
---
v2: Rename sufx to suffix
v3: Simplify generic_inst_dump()
---
 arch/powerpc/xmon/xmon.c | 38 ++
 1 file changed, 30 insertions(+), 8 deletions(-)

diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index a73a35aa4a75..bf304189e33a 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -2900,6 +2900,21 @@ prdump(unsigned long adrs, long ndump)
}
 }
 
+static bool instrs_are_equal(unsigned long insta, unsigned long suffixa,
+unsigned long instb, unsigned long suffixb)
+{
+   if (insta != instb)
+   return false;
+
+   if (!IS_PREFIX(insta) && !IS_PREFIX(instb))
+   return true;
+
+   if (IS_PREFIX(insta) && IS_PREFIX(instb))
+   return suffixa == suffixb;
+
+   return false;
+}
+
 typedef int (*instruction_dump_func)(unsigned long inst, unsigned long addr);
 
 static int
@@ -2908,12 +2923,11 @@ generic_inst_dump(unsigned long adr, long count, int 
praddr,
 {
int nr, dotted;
unsigned long first_adr;
-   unsigned int inst, last_inst = 0;
-   unsigned char val[4];
+   unsigned int inst, suffix, last_inst = 0, last_suffix = 0;
 
dotted = 0;
-   for (first_adr = adr; count > 0; --count, adr += 4) {
-   nr = mread(adr, val, 4);
+   for (first_adr = adr; count > 0; --count, adr += nr) {
+   nr = mread_instr(adr, , );
if (nr == 0) {
if (praddr) {
const char *x = fault_chars[fault_type];
@@ -2921,8 +2935,9 @@ generic_inst_dump(unsigned long adr, long count, int 
praddr,
}
break;
}
-   inst = GETWORD(val);
-   if (adr > first_adr && inst == last_inst) {
+   if (adr > first_adr && instrs_are_equal(inst, suffix,
+   last_inst,
+   last_suffix)) {
if (!dotted) {
printf(" ...\n");
dotted = 1;
@@ -2931,10 +2946,17 @@ generic_inst_dump(unsigned long adr, long count, int 
praddr,
}
dotted = 0;
last_inst = inst;
-   if (praddr)
+   last_suffix = suffix;
+   if (praddr) {
printf(REG"  %.8x", adr, inst);
+   if (IS_PREFIX(inst))
+   printf(":%.8x", suffix);
+   }
printf("\t");
-   dump_func(inst, adr);
+   if (IS_PREFIX(inst))
+   printf("%.8x:%.8x", inst, suffix);
+   else
+   dump_func(inst, adr);
printf("\n");
}
return adr - first_adr;
-- 
2.17.1

[PATCH v3 02/14] powerpc: Define new SRR1 bits for a future ISA version

[Jordan Niethe]

Add the BOUNDARY SRR1 bit definition for when the cause of an alignment
exception is a prefixed instruction that crosses a 64-byte boundary.
Add the PREFIXED SRR1 bit definition for exceptions caused by prefixed
instructions.

Bit 35 of SRR1 is called SRR1_ISI_N_OR_G. This name comes from it being
used to indicate that an ISI was due to the access being no-exec or
guarded. A future ISA version adds another purpose. It is also set if
there is an access in a cache-inhibited location for prefixed
instruction.  Rename from SRR1_ISI_N_OR_G to SRR1_ISI_N_G_OR_CIP.

Signed-off-by: Jordan Niethe 
---
v2: Combined all the commits concerning SRR1 bits.
---
 arch/powerpc/include/asm/reg.h  | 4 +++-
 arch/powerpc/kvm/book3s_hv_nested.c | 2 +-
 arch/powerpc/kvm/book3s_hv_rm_mmu.c | 2 +-
 3 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index c7758c2ccc5f..173f33df4fab 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -762,7 +762,7 @@
 #endif
 
 #define   SRR1_ISI_NOPT0x4000 /* ISI: Not found in hash */
-#define   SRR1_ISI_N_OR_G  0x1000 /* ISI: Access is no-exec or G */
+#define   SRR1_ISI_N_G_OR_CIP  0x1000 /* ISI: Access is no-exec or G or CI 
for a prefixed instruction */
 #define   SRR1_ISI_PROT0x0800 /* ISI: Other protection 
fault */
 #define   SRR1_WAKEMASK0x0038 /* reason for wakeup */
 #define   SRR1_WAKEMASK_P8 0x003c /* reason for wakeup on POWER8 and 9 
*/
@@ -789,6 +789,8 @@
 #define   SRR1_PROGADDR0x0001 /* SRR0 contains subsequent 
addr */
 
 #define   SRR1_MCE_MCP 0x0008 /* Machine check signal caused 
interrupt */
+#define   SRR1_BOUNDARY0x1000 /* Prefixed instruction 
crosses 64-byte boundary */
+#define   SRR1_PREFIXED0x2000 /* Exception caused by 
prefixed instruction */
 
 #define SPRN_HSRR0 0x13A   /* Save/Restore Register 0 */
 #define SPRN_HSRR1 0x13B   /* Save/Restore Register 1 */
diff --git a/arch/powerpc/kvm/book3s_hv_nested.c 
b/arch/powerpc/kvm/book3s_hv_nested.c
index dc97e5be76f6..6ab685227574 100644
--- a/arch/powerpc/kvm/book3s_hv_nested.c
+++ b/arch/powerpc/kvm/book3s_hv_nested.c
@@ -1169,7 +1169,7 @@ static int kvmhv_translate_addr_nested(struct kvm_vcpu 
*vcpu,
} else if (vcpu->arch.trap == BOOK3S_INTERRUPT_H_INST_STORAGE) {
/* Can we execute? */
if (!gpte_p->may_execute) {
-   flags |= SRR1_ISI_N_OR_G;
+   flags |= SRR1_ISI_N_G_OR_CIP;
goto forward_to_l1;
}
} else {
diff --git a/arch/powerpc/kvm/book3s_hv_rm_mmu.c 
b/arch/powerpc/kvm/book3s_hv_rm_mmu.c
index 220305454c23..b53a9f1c1a46 100644
--- a/arch/powerpc/kvm/book3s_hv_rm_mmu.c
+++ b/arch/powerpc/kvm/book3s_hv_rm_mmu.c
@@ -1260,7 +1260,7 @@ long kvmppc_hpte_hv_fault(struct kvm_vcpu *vcpu, unsigned 
long addr,
status &= ~DSISR_NOHPTE;/* DSISR_NOHPTE == SRR1_ISI_NOPT */
if (!data) {
if (gr & (HPTE_R_N | HPTE_R_G))
-   return status | SRR1_ISI_N_OR_G;
+   return status | SRR1_ISI_N_G_OR_CIP;
if (!hpte_read_permission(pp, slb_v & key))
return status | SRR1_ISI_PROT;
} else if (status & DSISR_ISSTORE) {
-- 
2.17.1

[PATCH v3 01/14] powerpc: Enable Prefixed Instructions

[Jordan Niethe]

From: Alistair Popple 

Prefix instructions have their own FSCR bit which needs to enabled via
a CPU feature. The kernel will save the FSCR for problem state but it
needs to be enabled initially.

Signed-off-by: Alistair Popple 
---
 arch/powerpc/include/asm/reg.h|  3 +++
 arch/powerpc/kernel/dt_cpu_ftrs.c | 23 +++
 2 files changed, 26 insertions(+)

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 1aa46dff0957..c7758c2ccc5f 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -397,6 +397,7 @@
 #define SPRN_RWMR  0x375   /* Region-Weighting Mode Register */
 
 /* HFSCR and FSCR bit numbers are the same */
+#define FSCR_PREFIX_LG 13  /* Enable Prefix Instructions */
 #define FSCR_SCV_LG12  /* Enable System Call Vectored */
 #define FSCR_MSGP_LG   10  /* Enable MSGP */
 #define FSCR_TAR_LG8   /* Enable Target Address Register */
@@ -408,11 +409,13 @@
 #define FSCR_VECVSX_LG 1   /* Enable VMX/VSX  */
 #define FSCR_FP_LG 0   /* Enable Floating Point */
 #define SPRN_FSCR  0x099   /* Facility Status & Control Register */
+#define   FSCR_PREFIX  __MASK(FSCR_PREFIX_LG)
 #define   FSCR_SCV __MASK(FSCR_SCV_LG)
 #define   FSCR_TAR __MASK(FSCR_TAR_LG)
 #define   FSCR_EBB __MASK(FSCR_EBB_LG)
 #define   FSCR_DSCR__MASK(FSCR_DSCR_LG)
 #define SPRN_HFSCR 0xbe/* HV=1 Facility Status & Control Register */
+#define   HFSCR_PREFIX __MASK(FSCR_PREFIX_LG)
 #define   HFSCR_MSGP   __MASK(FSCR_MSGP_LG)
 #define   HFSCR_TAR__MASK(FSCR_TAR_LG)
 #define   HFSCR_EBB__MASK(FSCR_EBB_LG)
diff --git a/arch/powerpc/kernel/dt_cpu_ftrs.c 
b/arch/powerpc/kernel/dt_cpu_ftrs.c
index 182b4047c1ef..396f2c6c588e 100644
--- a/arch/powerpc/kernel/dt_cpu_ftrs.c
+++ b/arch/powerpc/kernel/dt_cpu_ftrs.c
@@ -553,6 +553,28 @@ static int __init feat_enable_large_ci(struct 
dt_cpu_feature *f)
return 1;
 }
 
+static int __init feat_enable_prefix(struct dt_cpu_feature *f)
+{
+   u64 fscr, hfscr;
+
+   if (f->usable_privilege & USABLE_HV) {
+   hfscr = mfspr(SPRN_HFSCR);
+   hfscr |= HFSCR_PREFIX;
+   mtspr(SPRN_HFSCR, hfscr);
+   }
+
+   if (f->usable_privilege & USABLE_OS) {
+   fscr = mfspr(SPRN_FSCR);
+   fscr |= FSCR_PREFIX;
+   mtspr(SPRN_FSCR, fscr);
+
+   if (f->usable_privilege & USABLE_PR)
+   current->thread.fscr |= FSCR_PREFIX;
+   }
+
+   return 1;
+}
+
 struct dt_cpu_feature_match {
const char *name;
int (*enable)(struct dt_cpu_feature *f);
@@ -626,6 +648,7 @@ static struct dt_cpu_feature_match __initdata
{"vector-binary128", feat_enable, 0},
{"vector-binary16", feat_enable, 0},
{"wait-v3", feat_enable, 0},
+   {"prefix-instructions", feat_enable_prefix, 0},
 };
 
 static bool __initdata using_dt_cpu_ftrs;
-- 
2.17.1

[PATCH v3 13/14] powerpc/hw_breakpoints: Initial support for prefixed instructions

[Jordan Niethe]

Currently when getting an instruction to emulate in
hw_breakpoint_handler() we do not load the suffix of a prefixed
instruction. Ensure we load the suffix if the instruction we need to
emulate is a prefixed instruction.

Signed-off-by: Jordan Niethe 
---
v2: Rename sufx to suffix
v3: Add __user to type cast to remove sparse warning
---
 arch/powerpc/kernel/hw_breakpoint.c | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/arch/powerpc/kernel/hw_breakpoint.c 
b/arch/powerpc/kernel/hw_breakpoint.c
index 3a7ec6760dab..edf46356dfb2 100644
--- a/arch/powerpc/kernel/hw_breakpoint.c
+++ b/arch/powerpc/kernel/hw_breakpoint.c
@@ -243,15 +243,16 @@ dar_range_overlaps(unsigned long dar, int size, struct 
arch_hw_breakpoint *info)
 static bool stepping_handler(struct pt_regs *regs, struct perf_event *bp,
 struct arch_hw_breakpoint *info)
 {
-   unsigned int instr = 0;
+   unsigned int instr = 0, suffix = 0;
int ret, type, size;
struct instruction_op op;
unsigned long addr = info->address;
 
-   if (__get_user_inatomic(instr, (unsigned int *)regs->nip))
+   if (__get_user_instr_inatomic(instr, suffix,
+ (unsigned int __user *)regs->nip))
goto fail;
 
-   ret = analyse_instr(, regs, instr, PPC_NO_SUFFIX);
+   ret = analyse_instr(, regs, instr, suffix);
type = GETTYPE(op.type);
size = GETSIZE(op.type);
 
@@ -275,7 +276,7 @@ static bool stepping_handler(struct pt_regs *regs, struct 
perf_event *bp,
return false;
}
 
-   if (!emulate_step(regs, instr, PPC_NO_SUFFIX))
+   if (!emulate_step(regs, instr, suffix))
goto fail;
 
return true;
-- 
2.17.1

[PATCH v3 00/14] Initial Prefixed Instruction support

[Jordan Niethe]

A future revision of the ISA will introduce prefixed instructions. A
prefixed instruction is composed of a 4-byte prefix followed by a
4-byte suffix.

All prefixes have the major opcode 1. A prefix will never be a valid
word instruction. A suffix may be an existing word instruction or a
new instruction.

This series enables prefixed instructions and extends the instruction
emulation to support them. Then the places where prefixed instructions
might need to be emulated are updated.

v3 is based on feedback from Christophe Leroy. The major changes:
- Completely replacing store_inst() with patch_instruction() in
  xmon
- Improve implementation of mread_instr() to not use mread().
- Base the series on top of
  https://patchwork.ozlabs.org/patch/1232619/ as this will effect
  kprobes.
- Some renaming and simplification of conditionals.

v2 incorporates feedback from Daniel Axtens and and Balamuruhan
S. The major changes are:
- Squashing together all commits about SRR1 bits
- Squashing all commits for supporting prefixed load stores
- Changing abbreviated references to sufx/prfx -> suffix/prefix
- Introducing macros for returning the length of an instruction
- Removing sign extension flag from pstd/pld in sstep.c
- Dropping patch  "powerpc/fault: Use analyse_instr() to check for
  store with updates to sp" from the series, it did not really fit
  with prefixed enablement in the first place and as reported by Greg
  Kurz did not work correctly.

Alistair Popple (1):
  powerpc: Enable Prefixed Instructions

Jordan Niethe (13):
  powerpc: Define new SRR1 bits for a future ISA version
  powerpc sstep: Prepare to support prefixed instructions
  powerpc sstep: Add support for prefixed load/stores
  powerpc sstep: Add support for prefixed fixed-point arithmetic
  powerpc: Support prefixed instructions in alignment handler
  powerpc/traps: Check for prefixed instructions in
facility_unavailable_exception()
  powerpc/xmon: Remove store_inst() for patch_instruction()
  powerpc/xmon: Add initial support for prefixed instructions
  powerpc/xmon: Dump prefixed instructions
  powerpc/kprobes: Support kprobes on prefixed instructions
  powerpc/uprobes: Add support for prefixed instructions
  powerpc/hw_breakpoints: Initial support for prefixed instructions
  powerpc: Add prefix support to mce_find_instr_ea_and_pfn()

 arch/powerpc/include/asm/kprobes.h|   5 +-
 arch/powerpc/include/asm/ppc-opcode.h |  13 ++
 arch/powerpc/include/asm/reg.h|   7 +-
 arch/powerpc/include/asm/sstep.h  |   9 +-
 arch/powerpc/include/asm/uaccess.h|  25 
 arch/powerpc/include/asm/uprobes.h|  16 ++-
 arch/powerpc/kernel/align.c   |   8 +-
 arch/powerpc/kernel/dt_cpu_ftrs.c |  23 
 arch/powerpc/kernel/hw_breakpoint.c   |   9 +-
 arch/powerpc/kernel/kprobes.c |  43 --
 arch/powerpc/kernel/mce_power.c   |   6 +-
 arch/powerpc/kernel/optprobes.c   |  31 +++--
 arch/powerpc/kernel/optprobes_head.S  |   6 +
 arch/powerpc/kernel/traps.c   |  22 ++-
 arch/powerpc/kernel/uprobes.c |   4 +-
 arch/powerpc/kvm/book3s_hv_nested.c   |   2 +-
 arch/powerpc/kvm/book3s_hv_rm_mmu.c   |   2 +-
 arch/powerpc/kvm/emulate_loadstore.c  |   2 +-
 arch/powerpc/lib/sstep.c  | 191 +-
 arch/powerpc/lib/test_emulate_step.c  |  30 ++--
 arch/powerpc/xmon/xmon.c  | 140 +++
 21 files changed, 497 insertions(+), 97 deletions(-)

-- 
2.17.1

[PATCH v3 05/14] powerpc sstep: Add support for prefixed fixed-point arithmetic

[Jordan Niethe]

This adds emulation support for the following prefixed Fixed-Point
Arithmetic instructions:
  * Prefixed Add Immediate (paddi)

Signed-off-by: Jordan Niethe 
---
v3: Since we moved the prefixed loads/stores into the load/store switch
statement it no longer makes sense to have paddi in there, so move it
out.
---
 arch/powerpc/lib/sstep.c | 20 
 1 file changed, 20 insertions(+)

diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index 8e4ec953e279..f2010a3e1e06 100644
--- a/arch/powerpc/lib/sstep.c
+++ b/arch/powerpc/lib/sstep.c
@@ -1331,6 +1331,26 @@ int analyse_instr(struct instruction_op *op, const 
struct pt_regs *regs,
 
switch (opcode) {
 #ifdef __powerpc64__
+   case 1:
+   prefix_r = instr & (1ul << 20);
+   ra = (suffix >> 16) & 0x1f;
+   rd = (suffix >> 21) & 0x1f;
+   op->reg = rd;
+   op->val = regs->gpr[rd];
+   suffixopcode = suffix >> 26;
+   prefixtype = (instr >> 24) & 0x3;
+   switch (prefixtype) {
+   case 2:
+   if (prefix_r && ra)
+   return 0;
+   switch (suffixopcode) {
+   case 14:/* paddi */
+   op->type = COMPUTE | PREFIXED;
+   op->val = mlsd_8lsd_ea(instr, suffix, regs);
+   goto compute_done;
+   }
+   }
+   break;
case 2: /* tdi */
if (rd & trap_compare(regs->gpr[ra], (short) instr))
goto trap;
-- 
2.17.1

[PATCH v3 12/14] powerpc/uprobes: Add support for prefixed instructions

[Jordan Niethe]

Uprobes can execute instructions out of line. Increase the size of the
buffer used  for this so that this works for prefixed instructions. Take
into account the length of prefixed instructions when fixing up the nip.

Signed-off-by: Jordan Niethe 
---
v2: - Fix typo
- Use macro for instruction length
---
 arch/powerpc/include/asm/uprobes.h | 16 
 arch/powerpc/kernel/uprobes.c  |  4 ++--
 2 files changed, 14 insertions(+), 6 deletions(-)

diff --git a/arch/powerpc/include/asm/uprobes.h 
b/arch/powerpc/include/asm/uprobes.h
index 2bbdf27d09b5..5516ab27db47 100644
--- a/arch/powerpc/include/asm/uprobes.h
+++ b/arch/powerpc/include/asm/uprobes.h
@@ -14,18 +14,26 @@
 
 typedef ppc_opcode_t uprobe_opcode_t;
 
+/*
+ * Ensure we have enough space for prefixed instructions, which
+ * are double the size of a word instruction, i.e. 8 bytes.
+ */
 #define MAX_UINSN_BYTES4
-#define UPROBE_XOL_SLOT_BYTES  (MAX_UINSN_BYTES)
+#define UPROBE_XOL_SLOT_BYTES  (2 * MAX_UINSN_BYTES)
 
 /* The following alias is needed for reference from arch-agnostic code */
 #define UPROBE_SWBP_INSN   BREAKPOINT_INSTRUCTION
 #define UPROBE_SWBP_INSN_SIZE  4 /* swbp insn size in bytes */
 
 struct arch_uprobe {
+/*
+ * Ensure there is enough space for prefixed instructions. Prefixed
+ * instructions must not cross 64-byte boundaries.
+ */
union {
-   u32 insn;
-   u32 ixol;
-   };
+   uprobe_opcode_t insn[2];
+   uprobe_opcode_t ixol[2];
+   } __aligned(64);
 };
 
 struct arch_uprobe_task {
diff --git a/arch/powerpc/kernel/uprobes.c b/arch/powerpc/kernel/uprobes.c
index 4ab40c4b576f..7e0334ad5cfe 100644
--- a/arch/powerpc/kernel/uprobes.c
+++ b/arch/powerpc/kernel/uprobes.c
@@ -111,7 +111,7 @@ int arch_uprobe_post_xol(struct arch_uprobe *auprobe, 
struct pt_regs *regs)
 * support doesn't exist and have to fix-up the next instruction
 * to be executed.
 */
-   regs->nip = utask->vaddr + MAX_UINSN_BYTES;
+   regs->nip = utask->vaddr + PPC_INST_LENGTH(auprobe->insn[0]);
 
user_disable_single_step(current);
return 0;
@@ -173,7 +173,7 @@ bool arch_uprobe_skip_sstep(struct arch_uprobe *auprobe, 
struct pt_regs *regs)
 * emulate_step() returns 1 if the insn was successfully emulated.
 * For all other cases, we need to single-step in hardware.
 */
-   ret = emulate_step(regs, auprobe->insn, PPC_NO_SUFFIX);
+   ret = emulate_step(regs, auprobe->insn[0], auprobe->insn[1]);
if (ret > 0)
return true;
 
-- 
2.17.1

[PATCH v3 07/14] powerpc/traps: Check for prefixed instructions in facility_unavailable_exception()

[Jordan Niethe]

If prefixed instructions are made unavailable by the [H]FSCR, attempting
to use them will cause a facility unavailable exception. Add "PREFIX" to
the facility_strings[].

Currently there are no prefixed instructions that are actually emulated
by emulate_instruction() within facility_unavailable_exception().
However, when caused by a prefixed instructions the SRR1 PREFIXED bit is
set. Prepare for dealing with emulated prefixed instructions by checking
for this bit.

Signed-off-by: Jordan Niethe 
---
 arch/powerpc/kernel/traps.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index d80b82fc1ae3..cd8b3043c268 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -1739,6 +1739,7 @@ void facility_unavailable_exception(struct pt_regs *regs)
[FSCR_TAR_LG] = "TAR",
[FSCR_MSGP_LG] = "MSGP",
[FSCR_SCV_LG] = "SCV",
+   [FSCR_PREFIX_LG] = "PREFIX",
};
char *facility = "unknown";
u64 value;
-- 
2.17.1

[PATCH v3 06/14] powerpc: Support prefixed instructions in alignment handler

[Jordan Niethe]

Alignment interrupts can be caused by prefixed instructions accessing
memory. In the alignment handler the instruction that caused the
exception is loaded and attempted emulate. If the instruction is a
prefixed instruction load the prefix and suffix to emulate. After
emulating increment the NIP by 8.

Prefixed instructions are not permitted to cross 64-byte boundaries. If
they do the alignment interrupt is invoked with SRR1 BOUNDARY bit set.
If this occurs send a SIGBUS to the offending process if in user mode.
If in kernel mode call bad_page_fault().

Signed-off-by: Jordan Niethe 
---
v2: - Move __get_user_instr() and __get_user_instr_inatomic() to this
commit (previously in "powerpc sstep: Prepare to support prefixed
instructions").
- Rename sufx to suffix
- Use a macro for calculating instruction length
v3: Move __get_user_{instr(), instr_inatomic()} up with the other
get_user definitions and remove nested if.
---
 arch/powerpc/include/asm/uaccess.h | 25 +
 arch/powerpc/kernel/align.c|  8 +---
 arch/powerpc/kernel/traps.c| 21 -
 3 files changed, 50 insertions(+), 4 deletions(-)

diff --git a/arch/powerpc/include/asm/uaccess.h 
b/arch/powerpc/include/asm/uaccess.h
index 2f500debae21..8903a96cbb4b 100644
--- a/arch/powerpc/include/asm/uaccess.h
+++ b/arch/powerpc/include/asm/uaccess.h
@@ -105,6 +105,31 @@ static inline int __access_ok(unsigned long addr, unsigned 
long size,
 #define __put_user_inatomic(x, ptr) \
__put_user_nosleep((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)))
 
+/*
+ * When reading an instruction iff it is a prefix, the suffix needs to be also
+ * loaded.
+ */
+#define __get_user_instr(x, y, ptr)\
+({ \
+   long __gui_ret = 0; \
+   y = 0;  \
+   __gui_ret = __get_user(x, ptr); \
+   if (!__gui_ret && IS_PREFIX(x)) \
+   __gui_ret = __get_user(y, ptr + 1); \
+   __gui_ret;  \
+})
+
+#define __get_user_instr_inatomic(x, y, ptr)   \
+({ \
+   long __gui_ret = 0; \
+   y = 0;  \
+   __gui_ret = __get_user_inatomic(x, ptr);\
+   if (!__gui_ret && IS_PREFIX(x)) \
+   __gui_ret = __get_user_inatomic(y, ptr + 1);\
+   __gui_ret;  \
+})
+
+
 extern long __put_user_bad(void);
 
 /*
diff --git a/arch/powerpc/kernel/align.c b/arch/powerpc/kernel/align.c
index ba3bf5c3ab62..4984cf681215 100644
--- a/arch/powerpc/kernel/align.c
+++ b/arch/powerpc/kernel/align.c
@@ -293,7 +293,7 @@ static int emulate_spe(struct pt_regs *regs, unsigned int 
reg,
 
 int fix_alignment(struct pt_regs *regs)
 {
-   unsigned int instr;
+   unsigned int instr, suffix;
struct instruction_op op;
int r, type;
 
@@ -303,13 +303,15 @@ int fix_alignment(struct pt_regs *regs)
 */
CHECK_FULL_REGS(regs);
 
-   if (unlikely(__get_user(instr, (unsigned int __user *)regs->nip)))
+   if (unlikely(__get_user_instr(instr, suffix,
+ (unsigned int __user *)regs->nip)))
return -EFAULT;
if ((regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE)) {
/* We don't handle PPC little-endian any more... */
if (cpu_has_feature(CPU_FTR_PPC_LE))
return -EIO;
instr = swab32(instr);
+   suffix = swab32(suffix);
}
 
 #ifdef CONFIG_SPE
@@ -334,7 +336,7 @@ int fix_alignment(struct pt_regs *regs)
if ((instr & 0xfc0006fe) == (PPC_INST_COPY & 0xfc0006fe))
return -EIO;
 
-   r = analyse_instr(, regs, instr, PPC_NO_SUFFIX);
+   r = analyse_instr(, regs, instr, suffix);
if (r < 0)
return -EINVAL;
 
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 82a3438300fd..d80b82fc1ae3 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -583,6 +583,10 @@ static inline int check_io_access(struct pt_regs *regs)
 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
 #define REASON_PRIVILEGED  ESR_PPR
 #define REASON_TRAPESR_PTR
+#define REASON_PREFIXED0
+#define REASON_BOUNDARY0
+
+#define inst_length(reason)4
 
 /* single-step stuff */
 #define single_stepping(regs)  (current->thread.debug.dbcr0 & DBCR0_IC)
@@ -597,6 +601,10 @@ static inline int check_io_access(struct pt_regs *regs)
 #define REASON_ILLEGAL SRR1_PROGILL
 #define REASON_PRIVILEGED  SRR1_PROGPRIV
 #define REASON_TRAPSRR1_PROGTRAP
+#define REASON_P

[PATCH v3 04/14] powerpc sstep: Add support for prefixed load/stores

[Jordan Niethe]

This adds emulation support for the following prefixed integer
load/stores:
  * Prefixed Load Byte and Zero (plbz)
  * Prefixed Load Halfword and Zero (plhz)
  * Prefixed Load Halfword Algebraic (plha)
  * Prefixed Load Word and Zero (plwz)
  * Prefixed Load Word Algebraic (plwa)
  * Prefixed Load Doubleword (pld)
  * Prefixed Store Byte (pstb)
  * Prefixed Store Halfword (psth)
  * Prefixed Store Word (pstw)
  * Prefixed Store Doubleword (pstd)
  * Prefixed Load Quadword (plq)
  * Prefixed Store Quadword (pstq)

the follow prefixed floating-point load/stores:
  * Prefixed Load Floating-Point Single (plfs)
  * Prefixed Load Floating-Point Double (plfd)
  * Prefixed Store Floating-Point Single (pstfs)
  * Prefixed Store Floating-Point Double (pstfd)

and for the following prefixed VSX load/stores:
  * Prefixed Load VSX Scalar Doubleword (plxsd)
  * Prefixed Load VSX Scalar Single-Precision (plxssp)
  * Prefixed Load VSX Vector [0|1]  (plxv, plxv0, plxv1)
  * Prefixed Store VSX Scalar Doubleword (pstxsd)
  * Prefixed Store VSX Scalar Single-Precision (pstxssp)
  * Prefixed Store VSX Vector [0|1] (pstxv, pstxv0, pstxv1)

Signed-off-by: Jordan Niethe 
---
v2: - Combine all load/store patches
- Fix the name of Type 01 instructions
- Remove sign extension flag from pstd/pld
- Rename sufx -> suffix
v3: - Move prefixed loads and stores into the switch statement
---
 arch/powerpc/lib/sstep.c | 159 +++
 1 file changed, 159 insertions(+)

diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index efbe72370670..8e4ec953e279 100644
--- a/arch/powerpc/lib/sstep.c
+++ b/arch/powerpc/lib/sstep.c
@@ -187,6 +187,44 @@ static nokprobe_inline unsigned long xform_ea(unsigned int 
instr,
return ea;
 }
 
+/*
+ * Calculate effective address for a MLS:D-form / 8LS:D-form
+ * prefixed instruction
+ */
+static nokprobe_inline unsigned long mlsd_8lsd_ea(unsigned int instr,
+ unsigned int suffix,
+ const struct pt_regs *regs)
+{
+   int ra, prefix_r;
+   unsigned int  dd;
+   unsigned long ea, d0, d1, d;
+
+   prefix_r = instr & (1ul << 20);
+   ra = (suffix >> 16) & 0x1f;
+
+   d0 = instr & 0x3;
+   d1 = suffix & 0x;
+   d = (d0 << 16) | d1;
+
+   /*
+* sign extend a 34 bit number
+*/
+   dd = (unsigned int)(d >> 2);
+   ea = (signed int)dd;
+   ea = (ea << 2) | (d & 0x3);
+
+   if (!prefix_r && ra)
+   ea += regs->gpr[ra];
+   else if (!prefix_r && !ra)
+   ; /* Leave ea as is */
+   else if (prefix_r && !ra)
+   ea += regs->nip;
+   else if (prefix_r && ra)
+   ; /* Invalid form. Should already be checked for by caller! */
+
+   return ea;
+}
+
 /*
  * Return the largest power of 2, not greater than sizeof(unsigned long),
  * such that x is a multiple of it.
@@ -1166,6 +1204,7 @@ int analyse_instr(struct instruction_op *op, const struct 
pt_regs *regs,
  unsigned int instr, unsigned int suffix)
 {
unsigned int opcode, ra, rb, rc, rd, spr, u;
+   unsigned int suffixopcode, prefixtype, prefix_r;
unsigned long int imm;
unsigned long int val, val2;
unsigned int mb, me, sh;
@@ -2648,6 +2687,126 @@ int analyse_instr(struct instruction_op *op, const 
struct pt_regs *regs,
break;
}
break;
+   case 1: /* Prefixed instructions */
+   prefix_r = instr & (1ul << 20);
+   ra = (suffix >> 16) & 0x1f;
+   op->update_reg = ra;
+   rd = (suffix >> 21) & 0x1f;
+   op->reg = rd;
+   op->val = regs->gpr[rd];
+
+   suffixopcode = suffix >> 26;
+   prefixtype = (instr >> 24) & 0x3;
+   switch (prefixtype) {
+   case 0: /* Type 00  Eight-Byte Load/Store */
+   if (prefix_r && ra)
+   break;
+   op->ea = mlsd_8lsd_ea(instr, suffix, regs);
+   switch (suffixopcode) {
+   case 41:/* plwa */
+   op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 4);
+   break;
+   case 42:/* plxsd */
+   op->reg = rd + 32;
+   op->type = MKOP(LOAD_VSX, PREFIXED, 8);
+   op->element_size = 8;
+   op->vsx_flags = VSX_CHECK_VEC;
+   break;
+   case 43:/* plxssp */
+   op->reg = rd + 32;
+ 

[PATCH v3 03/14] powerpc sstep: Prepare to support prefixed instructions

[Jordan Niethe]

Currently all instructions are a single word long. A future ISA version
will include prefixed instructions which have a double word length. The
functions used for analysing and emulating instructions need to be
modified so that they can handle these new instruction types.

A prefixed instruction is a word prefix followed by a word suffix. All
prefixes uniquely have the primary op-code 1. Suffixes may be valid word
instructions or instructions that only exist as suffixes.

In handling prefixed instructions it will be convenient to treat the
suffix and prefix as separate words. To facilitate this modify
analyse_instr() and emulate_step() to take a suffix as a
parameter. For word instructions it does not matter what is passed in
here - it will be ignored.

We also define a new flag, PREFIXED, to be used in instruction_op:type.
This flag will indicate when emulating an analysed instruction if the
NIP should be advanced by word length or double word length.

The callers of analyse_instr() and emulate_step() will need their own
changes to be able to support prefixed instructions. For now modify them
to pass in 0 as a suffix.

Note that at this point no prefixed instructions are emulated or
analysed - this is just making it possible to do so.

Signed-off-by: Jordan Niethe 
---
v2: - Move definition of __get_user_instr() and
__get_user_instr_inatomic() to "powerpc: Support prefixed instructions
in alignment handler."
- Use a macro for returning the length of an op
- Rename sufx -> suffix
- Define and use PPC_NO_SUFFIX instead of 0
v3: - Define and use OP_PREFIX
- Rename OP_LENGTH() to GETLENGTH()
- Define IS_PREFIX() as 0 for non 64 bit ppc
---
 arch/powerpc/include/asm/ppc-opcode.h | 13 
 arch/powerpc/include/asm/sstep.h  |  9 ++--
 arch/powerpc/kernel/align.c   |  2 +-
 arch/powerpc/kernel/hw_breakpoint.c   |  4 ++--
 arch/powerpc/kernel/kprobes.c |  2 +-
 arch/powerpc/kernel/mce_power.c   |  2 +-
 arch/powerpc/kernel/optprobes.c   |  3 ++-
 arch/powerpc/kernel/uprobes.c |  2 +-
 arch/powerpc/kvm/emulate_loadstore.c  |  2 +-
 arch/powerpc/lib/sstep.c  | 12 ++-
 arch/powerpc/lib/test_emulate_step.c  | 30 +--
 arch/powerpc/xmon/xmon.c  |  5 +++--
 12 files changed, 54 insertions(+), 32 deletions(-)

diff --git a/arch/powerpc/include/asm/ppc-opcode.h 
b/arch/powerpc/include/asm/ppc-opcode.h
index c1df75edde44..24dc193cd3ef 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -158,6 +158,9 @@
 /* VMX Vector Store Instructions */
 #define OP_31_XOP_STVX  231
 
+/* Prefixed Instructions */
+#define OP_PREFIX  1
+
 #define OP_31   31
 #define OP_LWZ  32
 #define OP_STFS 52
@@ -377,6 +380,16 @@
 #define PPC_INST_VCMPEQUD  0x10c7
 #define PPC_INST_VCMPEQUB  0x1006
 
+/* macros for prefixed instructions */
+#ifdef __powerpc64__
+#define IS_PREFIX(x)   (((x) >> 26) == OP_PREFIX)
+#else
+#define IS_PREFIX(x)   (0)
+#endif
+
+#definePPC_NO_SUFFIX   0
+#definePPC_INST_LENGTH(x)  (IS_PREFIX(x) ? 8 : 4)
+
 /* macros to insert fields into opcodes */
 #define ___PPC_RA(a)   (((a) & 0x1f) << 16)
 #define ___PPC_RB(b)   (((b) & 0x1f) << 11)
diff --git a/arch/powerpc/include/asm/sstep.h b/arch/powerpc/include/asm/sstep.h
index 769f055509c9..5539df5c50a4 100644
--- a/arch/powerpc/include/asm/sstep.h
+++ b/arch/powerpc/include/asm/sstep.h
@@ -89,11 +89,15 @@ enum instruction_type {
 #define VSX_LDLEFT 4   /* load VSX register from left */
 #define VSX_CHECK_VEC  8   /* check MSR_VEC not MSR_VSX for reg >= 32 */
 
+/* Prefixed flag, ORed in with type */
+#define PREFIXED   0x800
+
 /* Size field in type word */
 #define SIZE(n)((n) << 12)
 #define GETSIZE(w) ((w) >> 12)
 
 #define GETTYPE(t) ((t) & INSTR_TYPE_MASK)
+#define GETLENGTH(t)   (((t) & PREFIXED) ? 8 : 4)
 
 #define MKOP(t, f, s)  ((t) | (f) | SIZE(s))
 
@@ -132,7 +136,7 @@ union vsx_reg {
  * otherwise.
  */
 extern int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
-unsigned int instr);
+unsigned int instr, unsigned int suffix);
 
 /*
  * Emulate an instruction that can be executed just by updating
@@ -149,7 +153,8 @@ void emulate_update_regs(struct pt_regs *reg, struct 
instruction_op *op);
  * 0 if it could not be emulated, or -1 for an instruction that
  * should not be emulated (rfid, mtmsrd clearing MSR_RI, etc.).
  */
-extern int emulate_step(struct pt_regs *regs, unsigned int instr);
+extern int emulate_step(struct pt_regs *regs, unsigned int instr,
+   unsigned int suffix);
 
 /*
  * Emulate a load or store instruction by reading/writing the
diff --git a/arch/powerpc/kernel/align.c b/arch/powerpc/kernel/align.c
index 92045ed64976..ba

[PATCH v3 14/14] powerpc: Add prefix support to mce_find_instr_ea_and_pfn()

[Jordan Niethe]

mce_find_instr_ea_and_pfn analyses an instruction to determine the
effective address that caused the machine check. Update this to load and
pass the suffix to analyse_instr for prefixed instructions.

Signed-off-by: Jordan Niethe 
---
v2: - Rename sufx to suffix
---
 arch/powerpc/kernel/mce_power.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/kernel/mce_power.c b/arch/powerpc/kernel/mce_power.c
index 824eda536f5d..091bab4a5464 100644
--- a/arch/powerpc/kernel/mce_power.c
+++ b/arch/powerpc/kernel/mce_power.c
@@ -365,7 +365,7 @@ static int mce_find_instr_ea_and_phys(struct pt_regs *regs, 
uint64_t *addr,
 * in real-mode is tricky and can lead to recursive
 * faults
 */
-   int instr;
+   int instr, suffix = 0;
unsigned long pfn, instr_addr;
struct instruction_op op;
struct pt_regs tmp = *regs;
@@ -374,7 +374,9 @@ static int mce_find_instr_ea_and_phys(struct pt_regs *regs, 
uint64_t *addr,
if (pfn != ULONG_MAX) {
instr_addr = (pfn << PAGE_SHIFT) + (regs->nip & ~PAGE_MASK);
instr = *(unsigned int *)(instr_addr);
-   if (!analyse_instr(, , instr, PPC_NO_SUFFIX)) {
+   if (IS_PREFIX(instr))
+   suffix = *(unsigned int *)(instr_addr + 4);
+   if (!analyse_instr(, , instr, suffix)) {
pfn = addr_to_pfn(regs, op.ea);
*addr = op.ea;
*phys_addr = (pfn << PAGE_SHIFT);
-- 
2.17.1

Re: [PATCH v3 07/14] powerpc/traps: Check for prefixed instructions in facility_unavailable_exception()

[Jordan Niethe]

On Wed, Feb 26, 2020 at 5:53 PM Nicholas Piggin  wrote:
>
> Jordan Niethe's on February 26, 2020 2:07 pm:
> > If prefixed instructions are made unavailable by the [H]FSCR, attempting
> > to use them will cause a facility unavailable exception. Add "PREFIX" to
> > the facility_strings[].
> >
> > Currently there are no prefixed instructions that are actually emulated
> > by emulate_instruction() within facility_unavailable_exception().
> > However, when caused by a prefixed instructions the SRR1 PREFIXED bit is
> > set. Prepare for dealing with emulated prefixed instructions by checking
> > for this bit.
> >
> > Signed-off-by: Jordan Niethe 
>
> Oh you've got it here, I would just squash this together with the first
> patch.
Sure, I'll put them together. When you mentioned a couple more things
to do in traps.c, was it just this? Or is there still more to be done
adding an FSCR?
>
> Thanks,
> Nick

Re: [PATCH v3 11/14] powerpc/kprobes: Support kprobes on prefixed instructions

[Jordan Niethe]

On Fri, Feb 28, 2020 at 12:48 PM Nicholas Piggin  wrote:
>
> Jordan Niethe's on February 27, 2020 10:58 am:
> > On Wed, Feb 26, 2020 at 6:18 PM Nicholas Piggin  wrote:
> >>
> >> Jordan Niethe's on February 26, 2020 2:07 pm:
> >> > @@ -136,11 +148,14 @@ int arch_prepare_kprobe(struct kprobe *p)
> >> >   }
> >> >
> >> >   if (!ret) {
> >> > - patch_instruction(p->ainsn.insn, *p->addr);
> >> > + patch_instruction(>ainsn.insn[0], p->addr[0]);
> >> > + if (IS_PREFIX(insn))
> >> > + patch_instruction(>ainsn.insn[1], p->addr[1]);
> >> >   p->opcode = *p->addr;
> >>
> >> Not to single out this hunk or this patch even, but what do you reckon
> >> about adding an instruction data type, and then use that in all these
> >> call sites rather than adding the extra arg or doing the extra copy
> >> manually in each place depending on prefix?
> >>
> >> instrs_are_equal, get_user_instr, analyse_instr, patch_instruction,
> >> etc., would all take this new instr. Places that open code a memory
> >> access like your MCE change need some accessor
> >>
> >>instr = *(unsigned int *)(instr_addr);
> >> -   if (!analyse_instr(, , instr, PPC_NO_SUFFIX)) {
> >> +   if (IS_PREFIX(instr))
> >> +   suffix = *(unsigned int *)(instr_addr + 4);
> >>
> >> Becomes
> >>read_instr(instr_addr, );
> >>if (!analyse_instr(, , instr)) ...
> >>
> >> etc.
> > Daniel Axtens also talked about this and my reasons not to do so were
> > pretty unconvincing, so I started trying something like this. One
>
> Okay.
>
> > thing I have been wondering is how pervasive should the new type be.
>
> I wouldn't mind it being quite pervasive. We have to be careful not
> to copy it directly to/from memory now, but if we have accessors to
> do all that with, I think it should be okay.
>
> > Below is data type I have started using, which I think works
> > reasonably for replacing unsigned ints everywhere (like within
> > code-patching.c). In a few architecture independent places such as
> > uprobes which want to do ==, etc the union type does not work so well.
>
> There will be some places you have to make the boundary. I would start
> by just making it a powerpc thing, but possibly there is or could be
> some generic helpers. How does something like x86 cope with this?

One of the places I was thinking of was is_swbp_insn() in
kernel/events/uprobes.c. The problem was I wanted to typedef
uprobe_opcode_t as ppc_insn type which was probably the wrong thing to
do. x86 typedef's it as u8 (size of the trap they use). So we probably
can do the same thing and just keep it as a u32.

>
> > I will have the next revision of the series start using a type.
>
> Thanks for doing that.
>
> >
> > diff --git a/arch/powerpc/include/asm/inst.h 
> > b/arch/powerpc/include/asm/inst.h
> > new file mode 100644
> > index ..50adb3dbdeb4
> > --- /dev/null
> > +++ b/arch/powerpc/include/asm/inst.h
> > @@ -0,0 +1,87 @@
> > +
> > +#ifndef _ASM_INST_H
> > +#define _ASM_INST_H
> > +
> > +#ifdef __powerpc64__
> > +
> > +/* 64  bit Instruction */
> > +
> > +typedef struct {
> > +unsigned int prefix;
> > +unsigned int suffix;
>
> u32?
Sure.
>
> > +} __packed ppc_prefixed_inst;
> > +
> > +typedef union ppc_inst {
> > +unsigned int w;
> > +ppc_prefixed_inst p;
> > +} ppc_inst;
>
> I'd make it a struct and use nameless structs/unions inside it (with
> appropriate packed annotation):
Yeah that will be nicer.
>
> struct ppc_inst {
> union {
> struct {
> u32 word;
> u32 pad;
> };
> struct {
> u32 prefix;
> u32 suffix;
> };
> };
> };
>
> > +
> > +#define PPC_INST_IS_PREFIXED(inst) (((inst).w >> 26) == 1)
> > +#define PPC_INST_LEN(inst) (PPC_INST_IS_PREFIXED((inst)) ?
> > sizeof((inst).p) : sizeof((inst).w))
>
> Good accessors, I'd make them all C inline functions and lower case.
Will change.
>
> > +
> > +#define PPC_INST_NEW_WORD(x) ((ppc_inst) { .w = (x) })
> > +#define PPC_INST_NEW_WORD_PAD(x) ((ppc_inst) { .p.prefix = (x),
> > .p.suffix = (0x6000) })
> > +#define PPC_INST_NEW_PREFIXED(x, y) ((ppc_inst) { .p.prefix = (x),
> > .p.suffix = (y) })
>
> If these are widely used, I'd make them a bit shorter
>
> #define PPC_INST(x)
> #define PPC_INST_PREFIXED(x)
Good idea, they do end up used quite widely.
>
> I'd also set padding to something invalid 0 or 0x for the first
> case, and have your accessors check that rather than carrying around
> another type of ppc_inst (prefixed, padded, non-padded).
>
> > +
> > +#define PPC_INST_WORD(x) ((x).w)
> > +#define PPC_INST_PREFIX(x) (x.p.prefix)
> > +#define PPC_INST_SUFFIX(x) (x.p.suffix)
> > +#define PPC_INST_EMPTY(x) (PPC_INST_WORD(x) == 0)
>
> I'd avoid simple accessors like this completely. If they have any use
> it would be to ensure you don't try to use prefix/suffix on a
> 

Re: [PATCH v3 01/14] powerpc: Enable Prefixed Instructions

[Jordan Niethe]

On Wed, Feb 26, 2020 at 5:50 PM Nicholas Piggin  wrote:
>
> Jordan Niethe's on February 26, 2020 2:07 pm:
> > From: Alistair Popple 
> >
> > Prefix instructions have their own FSCR bit which needs to enabled via
> > a CPU feature. The kernel will save the FSCR for problem state but it
> > needs to be enabled initially.
> >
> > Signed-off-by: Alistair Popple 
> > ---
> >  arch/powerpc/include/asm/reg.h|  3 +++
> >  arch/powerpc/kernel/dt_cpu_ftrs.c | 23 +++
> >  2 files changed, 26 insertions(+)
> >
> > diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
> > index 1aa46dff0957..c7758c2ccc5f 100644
> > --- a/arch/powerpc/include/asm/reg.h
> > +++ b/arch/powerpc/include/asm/reg.h
> > @@ -397,6 +397,7 @@
> >  #define SPRN_RWMR0x375   /* Region-Weighting Mode Register */
> >
> >  /* HFSCR and FSCR bit numbers are the same */
> > +#define FSCR_PREFIX_LG   13  /* Enable Prefix Instructions */
> >  #define FSCR_SCV_LG  12  /* Enable System Call Vectored */
> >  #define FSCR_MSGP_LG 10  /* Enable MSGP */
> >  #define FSCR_TAR_LG  8   /* Enable Target Address Register */
> > @@ -408,11 +409,13 @@
> >  #define FSCR_VECVSX_LG   1   /* Enable VMX/VSX  */
> >  #define FSCR_FP_LG   0   /* Enable Floating Point */
> >  #define SPRN_FSCR0x099   /* Facility Status & Control Register */
> > +#define   FSCR_PREFIX__MASK(FSCR_PREFIX_LG)
>
> When you add a new FSCR, there's a couple more things to do, check
> out traps.c.
>
> >  #define   FSCR_SCV   __MASK(FSCR_SCV_LG)
> >  #define   FSCR_TAR   __MASK(FSCR_TAR_LG)
> >  #define   FSCR_EBB   __MASK(FSCR_EBB_LG)
> >  #define   FSCR_DSCR  __MASK(FSCR_DSCR_LG)
> >  #define SPRN_HFSCR   0xbe/* HV=1 Facility Status & Control Register */
> > +#define   HFSCR_PREFIX   __MASK(FSCR_PREFIX_LG)
> >  #define   HFSCR_MSGP __MASK(FSCR_MSGP_LG)
> >  #define   HFSCR_TAR  __MASK(FSCR_TAR_LG)
> >  #define   HFSCR_EBB  __MASK(FSCR_EBB_LG)
> > diff --git a/arch/powerpc/kernel/dt_cpu_ftrs.c 
> > b/arch/powerpc/kernel/dt_cpu_ftrs.c
> > index 182b4047c1ef..396f2c6c588e 100644
> > --- a/arch/powerpc/kernel/dt_cpu_ftrs.c
> > +++ b/arch/powerpc/kernel/dt_cpu_ftrs.c
> > @@ -553,6 +553,28 @@ static int __init feat_enable_large_ci(struct 
> > dt_cpu_feature *f)
> >   return 1;
> >  }
> >
> > +static int __init feat_enable_prefix(struct dt_cpu_feature *f)
> > +{
> > + u64 fscr, hfscr;
> > +
> > + if (f->usable_privilege & USABLE_HV) {
> > + hfscr = mfspr(SPRN_HFSCR);
> > + hfscr |= HFSCR_PREFIX;
> > + mtspr(SPRN_HFSCR, hfscr);
> > + }
> > +
> > + if (f->usable_privilege & USABLE_OS) {
> > + fscr = mfspr(SPRN_FSCR);
> > + fscr |= FSCR_PREFIX;
> > + mtspr(SPRN_FSCR, fscr);
> > +
> > + if (f->usable_privilege & USABLE_PR)
> > + current->thread.fscr |= FSCR_PREFIX;
> > + }
> > +
> > + return 1;
> > +}
>
> It would be good to be able to just use the default feature matching
> for this, if possible? Do we not do the right thing with
> init_thread.fscr?
The default feature matching do you mean feat_enable()?
I just tested using that again, within feat_enable() I can print and
see that the [h]fscr gets the bits set for enabling prefixed
instructions. However once I get to the shell and start xmon, the fscr
bit for prefixed instructions can be seen to be unset. What we are
doing in feat_enable_prefix() avoids that problem. So it seems maybe
something is not quite right with the init_thread.fscr. I will look
into further.
>
>
> > +
> >  struct dt_cpu_feature_match {
> >   const char *name;
> >   int (*enable)(struct dt_cpu_feature *f);
> > @@ -626,6 +648,7 @@ static struct dt_cpu_feature_match __initdata
> >   {"vector-binary128", feat_enable, 0},
> >   {"vector-binary16", feat_enable, 0},
> >   {"wait-v3", feat_enable, 0},
> > + {"prefix-instructions", feat_enable_prefix, 0},
>
> That's reasonable to make that a feature, will it specify a minimum
> base set of prefix instructions or just that prefix instructions
> with the prefix/suffix arrangement exist?
This was just going to be that they exist.
>
> You may not need "-instructions" on the end, none of the other
> instructions do.
Good point.
>
> I would maybe just hold off upstreaming the dt_cpu_ftrs changes for
> a bit. We have to do a pass over new CPU feature device tree, and
> some compatibility questions have come up recently.
>
> If you wouldn't mind just adding the new [H]FSCR bits and faults
> upstream for now, that would be good.
No problem.
>
> Thanks,
> Nick

Re: [PATCH v3 09/14] powerpc/xmon: Add initial support for prefixed instructions

[Jordan Niethe]

On Wed, Feb 26, 2020 at 6:10 PM Nicholas Piggin  wrote:
>
> Jordan Niethe's on February 26, 2020 2:07 pm:
> > A prefixed instruction is composed of a word prefix and a word suffix.
> > It does not make sense to be able to have a breakpoint on the suffix of
> > a prefixed instruction, so make this impossible.
> >
> > When leaving xmon_core() we check to see if we are currently at a
> > breakpoint. If this is the case, the breakpoint needs to be proceeded
> > from. Initially emulate_step() is tried, but if this fails then we need
> > to execute the saved instruction out of line. The NIP is set to the
> > address of bpt::instr[] for the current breakpoint.  bpt::instr[]
> > contains the instruction replaced by the breakpoint, followed by a trap
> > instruction.  After bpt::instr[0] is executed and we hit the trap we
> > enter back into xmon_bpt(). We know that if we got here and the offset
> > indicates we are at bpt::instr[1] then we have just executed out of line
> > so we can put the NIP back to the instruction after the breakpoint
> > location and continue on.
> >
> > Adding prefixed instructions complicates this as the bpt::instr[1] needs
> > to be used to hold the suffix. To deal with this make bpt::instr[] big
> > enough for three word instructions.  bpt::instr[2] contains the trap,
> > and in the case of word instructions pad bpt::instr[1] with a noop.
> >
> > No support for disassembling prefixed instructions.
> >
> > Signed-off-by: Jordan Niethe 
> > ---
> > v2: Rename sufx to suffix
> > v3: - Just directly use PPC_INST_NOP
> > - Typo: plac -> place
> > - Rename read_inst() to mread_inst(). Do not have it call mread().
> > ---
> >  arch/powerpc/xmon/xmon.c | 90 ++--
> >  1 file changed, 78 insertions(+), 12 deletions(-)
> >
> > diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
> > index a673cf55641c..a73a35aa4a75 100644
> > --- a/arch/powerpc/xmon/xmon.c
> > +++ b/arch/powerpc/xmon/xmon.c
> > @@ -97,7 +97,8 @@ static long *xmon_fault_jmp[NR_CPUS];
> >  /* Breakpoint stuff */
> >  struct bpt {
> >   unsigned long   address;
> > - unsigned intinstr[2];
> > + /* Prefixed instructions can not cross 64-byte boundaries */
> > + unsigned intinstr[3] __aligned(64);
>
> This is pretty wild, I didn't realize xmon executes breakpoints out
> of line like this.
>
> IMO the break point entries here should correspond with a range of
> reserved bytes in .text so we patch instructions into normal executable
> pages rather than .data.
Would it make sense to use vmalloc_exec() and use that like we are
going to do in kprobes()?
>
> Anyway that's for patch.
>
> Thanks,
> Nick

Re: [PATCH v3 08/14] powerpc/xmon: Remove store_inst() for patch_instruction()

[Jordan Niethe]

On Wed, Feb 26, 2020 at 6:04 PM Nicholas Piggin  wrote:
>
> Jordan Niethe's on February 26, 2020 2:07 pm:
> > For modifying instructions in xmon, patch_instruction() can serve the
> > same role that store_inst() is performing with the advantage of not
> > being specific to xmon. In some places patch_instruction() is already
> > being using followed by store_inst(). In these cases just remove the
> > store_inst(). Otherwise replace store_inst() with patch_instruction().
> >
> > Signed-off-by: Jordan Niethe 
> > ---
> >  arch/powerpc/xmon/xmon.c | 13 ++---
> >  1 file changed, 2 insertions(+), 11 deletions(-)
> >
> > diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
> > index 897e512c6379..a673cf55641c 100644
> > --- a/arch/powerpc/xmon/xmon.c
> > +++ b/arch/powerpc/xmon/xmon.c
> > @@ -325,11 +325,6 @@ static inline void sync(void)
> >   asm volatile("sync; isync");
> >  }
> >
> > -static inline void store_inst(void *p)
> > -{
> > - asm volatile ("dcbst 0,%0; sync; icbi 0,%0; isync" : : "r" (p));
> > -}
> > -
> >  static inline void cflush(void *p)
> >  {
> >   asm volatile ("dcbf 0,%0; icbi 0,%0" : : "r" (p));
> > @@ -882,8 +877,7 @@ static struct bpt *new_breakpoint(unsigned long a)
> >   for (bp = bpts; bp < [NBPTS]; ++bp) {
> >   if (!bp->enabled && atomic_read(>ref_count) == 0) {
> >   bp->address = a;
> > - bp->instr[1] = bpinstr;
> > - store_inst(>instr[1]);
> > + patch_instruction(>instr[1], bpinstr);
> >   return bp;
> >   }
> >   }
> > @@ -913,7 +907,7 @@ static void insert_bpts(void)
> >   bp->enabled = 0;
> >   continue;
> >   }
> > - store_inst(>instr[0]);
> > + patch_instruction(>instr[0], bp->instr[0]);
>
> Hmm that's a bit weird. Can you read instructions into a local variable
> first, do the checks on them, then patch them into their execution
> location?
I agree it is weird, local variables would be better.
>
> Otherwise, good cleanup.
>
> Thanks,
> Nick

Re: [PATCH v3 11/14] powerpc/kprobes: Support kprobes on prefixed instructions

[Jordan Niethe]

On Wed, Feb 26, 2020 at 6:18 PM Nicholas Piggin  wrote:
>
> Jordan Niethe's on February 26, 2020 2:07 pm:
> > @@ -136,11 +148,14 @@ int arch_prepare_kprobe(struct kprobe *p)
> >   }
> >
> >   if (!ret) {
> > - patch_instruction(p->ainsn.insn, *p->addr);
> > + patch_instruction(>ainsn.insn[0], p->addr[0]);
> > + if (IS_PREFIX(insn))
> > + patch_instruction(>ainsn.insn[1], p->addr[1]);
> >   p->opcode = *p->addr;
>
> Not to single out this hunk or this patch even, but what do you reckon
> about adding an instruction data type, and then use that in all these
> call sites rather than adding the extra arg or doing the extra copy
> manually in each place depending on prefix?
>
> instrs_are_equal, get_user_instr, analyse_instr, patch_instruction,
> etc., would all take this new instr. Places that open code a memory
> access like your MCE change need some accessor
>
>instr = *(unsigned int *)(instr_addr);
> -   if (!analyse_instr(, , instr, PPC_NO_SUFFIX)) {
> +   if (IS_PREFIX(instr))
> +   suffix = *(unsigned int *)(instr_addr + 4);
>
> Becomes
>read_instr(instr_addr, );
>if (!analyse_instr(, , instr)) ...
>
> etc.
Daniel Axtens also talked about this and my reasons not to do so were
pretty unconvincing, so I started trying something like this. One
thing I have been wondering is how pervasive should the new type be.
Below is data type I have started using, which I think works
reasonably for replacing unsigned ints everywhere (like within
code-patching.c). In a few architecture independent places such as
uprobes which want to do ==, etc the union type does not work so well.
I will have the next revision of the series start using a type.

diff --git a/arch/powerpc/include/asm/inst.h b/arch/powerpc/include/asm/inst.h
new file mode 100644
index ..50adb3dbdeb4
--- /dev/null
+++ b/arch/powerpc/include/asm/inst.h
@@ -0,0 +1,87 @@
+
+#ifndef _ASM_INST_H
+#define _ASM_INST_H
+
+#ifdef __powerpc64__
+
+/* 64  bit Instruction */
+
+typedef struct {
+unsigned int prefix;
+unsigned int suffix;
+} __packed ppc_prefixed_inst;
+
+typedef union ppc_inst {
+unsigned int w;
+ppc_prefixed_inst p;
+} ppc_inst;
+
+#define PPC_INST_IS_PREFIXED(inst) (((inst).w >> 26) == 1)
+#define PPC_INST_LEN(inst) (PPC_INST_IS_PREFIXED((inst)) ?
sizeof((inst).p) : sizeof((inst).w))
+
+#define PPC_INST_NEW_WORD(x) ((ppc_inst) { .w = (x) })
+#define PPC_INST_NEW_WORD_PAD(x) ((ppc_inst) { .p.prefix = (x),
.p.suffix = (0x6000) })
+#define PPC_INST_NEW_PREFIXED(x, y) ((ppc_inst) { .p.prefix = (x),
.p.suffix = (y) })
+
+#define PPC_INST_WORD(x) ((x).w)
+#define PPC_INST_PREFIX(x) (x.p.prefix)
+#define PPC_INST_SUFFIX(x) (x.p.suffix)
+#define PPC_INST_EMPTY(x) (PPC_INST_WORD(x) == 0)
+
+#define DEREF_PPC_INST_PTR(ptr)\
+({\
+ppc_inst __inst;\
+__inst.w = *(unsigned int *)(ptr);\
+if (PPC_INST_IS_PREFIXED(__inst))\
+__inst.p = *(ppc_prefixed_inst *)(ptr);\
+__inst;\
+})
+
+#define PPC_INST_NEXT(ptr) ((ptr) += PPC_INST_LEN(DEREF_PPC_INST_PTR((ptr
+#define PPC_INST_PREV(ptr) ((ptr) -= PPC_INST_LEN(DEREF_PPC_INST_PTR((ptr
+
+#define PPC_INST_EQ(x, y)\
+({\
+long pic_ret = 0;\
+pic_ret = (PPC_INST_PREFIX(x) == PPC_INST_PREFIX(y));\
+if (pic_ret) {\
+if (PPC_INST_IS_PREFIXED(x) && PPC_INST_IS_PREFIXED(y)) {\
+pic_ret = (PPC_INST_SUFFIX(x) == PPC_INST_SUFFIX(y));\
+} else {\
+pic_ret = 0;\
+}\
+}\
+pic_ret;\
+})
+
+#else /* !__powerpc64__ */
+
+/* 32 bit Instruction */
+
+typedef unsigned int ppc_inst;
+
+#define PPC_INST_IS_PREFIXED(inst) (0)
+#define PPC_INST_LEN(inst) (4)
+
+#define PPC_INST_NEW_WORD(x) (x)
+#define PPC_INST_NEW_WORD_PAD(x) (x)
+#define PPC_INST_NEW_PREFIXED(x, y) (x)
+
+#define PPC_INST_WORD(x) (x)
+#define PPC_INST_PREFIX(x) (x)
+#define PPC_INST_SUFFIX(x) (0)
+#define PPC_INST_EMPTY(x) (PPC_INST_WORD(x) == 0)
+
+#define DEREF_PPC_INST_PTR(ptr)(*ptr)
+
+#define PPC_INST_NEXT(ptr) ((ptr) += 4)
+#define PPC_INST_PREV(ptr) ((ptr) -= 4)
+
+#define PPC_INST_EQ(x, y) ((x) == (y))
+
+#endif /* __powerpc64__ */
+
+
+#endif /* _ASM_INST_H */

>
> Thanks,
> Nick

Re: [PATCH v3 09/14] powerpc/xmon: Add initial support for prefixed instructions

[Jordan Niethe]

On Thu, Feb 27, 2020 at 6:14 PM Christophe Leroy
 wrote:
>
>
>
> Le 27/02/2020 à 01:11, Jordan Niethe a écrit :
> > On Wed, Feb 26, 2020 at 6:10 PM Nicholas Piggin  wrote:
> >>
> >> Jordan Niethe's on February 26, 2020 2:07 pm:
> >>> A prefixed instruction is composed of a word prefix and a word suffix.
> >>> It does not make sense to be able to have a breakpoint on the suffix of
> >>> a prefixed instruction, so make this impossible.
> >>>
> >>> When leaving xmon_core() we check to see if we are currently at a
> >>> breakpoint. If this is the case, the breakpoint needs to be proceeded
> >>> from. Initially emulate_step() is tried, but if this fails then we need
> >>> to execute the saved instruction out of line. The NIP is set to the
> >>> address of bpt::instr[] for the current breakpoint.  bpt::instr[]
> >>> contains the instruction replaced by the breakpoint, followed by a trap
> >>> instruction.  After bpt::instr[0] is executed and we hit the trap we
> >>> enter back into xmon_bpt(). We know that if we got here and the offset
> >>> indicates we are at bpt::instr[1] then we have just executed out of line
> >>> so we can put the NIP back to the instruction after the breakpoint
> >>> location and continue on.
> >>>
> >>> Adding prefixed instructions complicates this as the bpt::instr[1] needs
> >>> to be used to hold the suffix. To deal with this make bpt::instr[] big
> >>> enough for three word instructions.  bpt::instr[2] contains the trap,
> >>> and in the case of word instructions pad bpt::instr[1] with a noop.
> >>>
> >>> No support for disassembling prefixed instructions.
> >>>
> >>> Signed-off-by: Jordan Niethe 
> >>> ---
> >>> v2: Rename sufx to suffix
> >>> v3: - Just directly use PPC_INST_NOP
> >>>  - Typo: plac -> place
> >>>  - Rename read_inst() to mread_inst(). Do not have it call mread().
> >>> ---
> >>>   arch/powerpc/xmon/xmon.c | 90 ++--
> >>>   1 file changed, 78 insertions(+), 12 deletions(-)
> >>>
> >>> diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
> >>> index a673cf55641c..a73a35aa4a75 100644
> >>> --- a/arch/powerpc/xmon/xmon.c
> >>> +++ b/arch/powerpc/xmon/xmon.c
> >>> @@ -97,7 +97,8 @@ static long *xmon_fault_jmp[NR_CPUS];
> >>>   /* Breakpoint stuff */
> >>>   struct bpt {
> >>>unsigned long   address;
> >>> - unsigned intinstr[2];
> >>> + /* Prefixed instructions can not cross 64-byte boundaries */
> >>> + unsigned intinstr[3] __aligned(64);
> >>
> >> This is pretty wild, I didn't realize xmon executes breakpoints out
> >> of line like this.
>
> Neither did I. That's problematic. Kernel data is mapped NX on some
> platforms.
>
> >>
> >> IMO the break point entries here should correspond with a range of
> >> reserved bytes in .text so we patch instructions into normal executable
> >> pages rather than .data.
> > Would it make sense to use vmalloc_exec() and use that like we are
> > going to do in kprobes()?
>
> As we are (already) doing in kprobes() you mean ?
Sorry for the confusion, I was mainly thinking of the patch that you
pointed out before:
https://patchwork.ozlabs.org/patch/1232619/
>
> In fact kprobes uses module_alloc(), and it works because kprobe depends
> on module. On some platforms (i.e. book3s/32) vmalloc space is marked NX
> in segment registers when CONFIG_MODULES is not set, see
> mmu_mark_initmem_nx().  On other ones the Instruction TLB miss exception
> does not manage misses at kernel addresses when CONFIG_MODULES is not
> selected.
>
> So if we want XMON to work at all time, we need to use some (linear)
> text address and use patch_instruction() to change it.
Thank you for the detailed clarification, I will do it like that.
>
> Christophe
>
> >>
> >> Anyway that's for patch.
> >>
> >> Thanks,
> >> Nick

Re: [PATCH 06/18] powerpc sstep: Add support for prefixed integer load/stores

[Jordan Niethe]

On Fri, Jan 10, 2020 at 9:38 PM Balamuruhan S  wrote:
>
> On Tue, Nov 26, 2019 at 04:21:29PM +1100, Jordan Niethe wrote:
> > This adds emulation support for the following prefixed integer
> > load/stores:
> >   * Prefixed Load Byte and Zero (plbz)
> >   * Prefixed Load Halfword and Zero (plhz)
> >   * Prefixed Load Halfword Algebraic (plha)
> >   * Prefixed Load Word and Zero (plwz)
> >   * Prefixed Load Word Algebraic (plwa)
> >   * Prefixed Load Doubleword (pld)
> >   * Prefixed Store Byte (pstb)
> >   * Prefixed Store Halfword (psth)
> >   * Prefixed Store Word (pstw)
> >   * Prefixed Store Doubleword (pstd)
> >   * Prefixed Load Quadword (plq)
> >   * Prefixed Store Quadword (pstq)
> >
> > Signed-off-by: Jordan Niethe 
> > ---
> >  arch/powerpc/lib/sstep.c | 110 +++
> >  1 file changed, 110 insertions(+)
> >
> > diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
> > index ade3f5eba2e5..4f5ad1f602d8 100644
> > --- a/arch/powerpc/lib/sstep.c
> > +++ b/arch/powerpc/lib/sstep.c
> > @@ -187,6 +187,43 @@ static nokprobe_inline unsigned long xform_ea(unsigned 
> > int instr,
> >   return ea;
> >  }
> >
> > +/*
> > + * Calculate effective address for a MLS:D-form / 8LS:D-form prefixed 
> > instruction
> > + */
> > +static nokprobe_inline unsigned long mlsd_8lsd_ea(unsigned int instr,
> > +   unsigned int sufx,
> > +   const struct pt_regs *regs)
> > +{
> > + int ra, prefix_r;
> > + unsigned int  dd;
> > + unsigned long ea, d0, d1, d;
> > +
> > + prefix_r = instr & (1ul << 20);
> > + ra = (sufx >> 16) & 0x1f;
> > +
> > + d0 = instr & 0x3;
> > + d1 = sufx & 0x;
> > + d = (d0 << 16) | d1;
> > +
> > + /*
> > +  * sign extend a 34 bit number
> > +  */
> > + dd = (unsigned int) (d >> 2);
> > + ea = (signed int) dd;
> > + ea = (ea << 2) | (d & 0x3);
> > +
> > + if (!prefix_r && ra)
> > + ea += regs->gpr[ra];
> > + else if (!prefix_r && !ra)
> > + ; /* Leave ea as is */
> > + else if (prefix_r && !ra)
> > + ea += regs->nip;
> > + else if (prefix_r && ra)
> > + ; /* Invalid form. Should already be checked for by caller! */
> > +
> > + return ea;
> > +}
> > +
> >  /*
> >   * Return the largest power of 2, not greater than sizeof(unsigned long),
> >   * such that x is a multiple of it.
> > @@ -1166,6 +1203,7 @@ int analyse_instr(struct instruction_op *op, const 
> > struct pt_regs *regs,
> > unsigned int instr, unsigned int sufx)
> >  {
> >   unsigned int opcode, ra, rb, rc, rd, spr, u;
> > + unsigned int sufxopcode, prefixtype, prefix_r;
> >   unsigned long int imm;
> >   unsigned long int val, val2;
> >   unsigned int mb, me, sh;
> > @@ -2652,6 +2690,78 @@ int analyse_instr(struct instruction_op *op, const 
> > struct pt_regs *regs,
> >
> >   }
> >
> > +/*
> > + * Prefixed instructions
> > + */
> > + switch (opcode) {
> > + case 1:
> > + prefix_r = instr & (1ul << 20);
> > + ra = (sufx >> 16) & 0x1f;
> > + op->update_reg = ra;
> > + rd = (sufx >> 21) & 0x1f;
> > + op->reg = rd;
> > + op->val = regs->gpr[rd];
> > +
> > + sufxopcode = sufx >> 26;
> > + prefixtype = (instr >> 24) & 0x3;
> > + switch (prefixtype) {
> > + case 0: /* Type 00  Eight-Byte Load/Store */
> > + if (prefix_r && ra)
> > + break;
> > + op->ea = mlsd_8lsd_ea(instr, sufx, regs);
> > + switch (sufxopcode) {
> > + case 41:/* plwa */
> > + op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 4);
> > + break;
> > + case 56:/* plq */
> > + op->type = MKOP(LOAD, PREFIXED, 16);
> > + break;
> > +   

Re: [PATCH 06/18] powerpc sstep: Add support for prefixed integer load/stores

[Jordan Niethe]

On Sat, Jan 11, 2020 at 2:13 AM Balamuruhan S  wrote:
>
> On Tue, Nov 26, 2019 at 04:21:29PM +1100, Jordan Niethe wrote:
> > This adds emulation support for the following prefixed integer
> > load/stores:
> >   * Prefixed Load Byte and Zero (plbz)
> >   * Prefixed Load Halfword and Zero (plhz)
> >   * Prefixed Load Halfword Algebraic (plha)
> >   * Prefixed Load Word and Zero (plwz)
> >   * Prefixed Load Word Algebraic (plwa)
> >   * Prefixed Load Doubleword (pld)
> >   * Prefixed Store Byte (pstb)
> >   * Prefixed Store Halfword (psth)
> >   * Prefixed Store Word (pstw)
> >   * Prefixed Store Doubleword (pstd)
> >   * Prefixed Load Quadword (plq)
> >   * Prefixed Store Quadword (pstq)
> >
> > Signed-off-by: Jordan Niethe 
> > ---
> >  arch/powerpc/lib/sstep.c | 110 +++
> >  1 file changed, 110 insertions(+)
> >
> > diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
> > index ade3f5eba2e5..4f5ad1f602d8 100644
> > --- a/arch/powerpc/lib/sstep.c
> > +++ b/arch/powerpc/lib/sstep.c
> > @@ -187,6 +187,43 @@ static nokprobe_inline unsigned long xform_ea(unsigned 
> > int instr,
> >   return ea;
> >  }
> >
> > +/*
> > + * Calculate effective address for a MLS:D-form / 8LS:D-form prefixed 
> > instruction
> > + */
> > +static nokprobe_inline unsigned long mlsd_8lsd_ea(unsigned int instr,
> > +   unsigned int sufx,
> > +   const struct pt_regs *regs)
> > +{
> > + int ra, prefix_r;
> > + unsigned int  dd;
> > + unsigned long ea, d0, d1, d;
> > +
> > + prefix_r = instr & (1ul << 20);
> > + ra = (sufx >> 16) & 0x1f;
> > +
> > + d0 = instr & 0x3;
> > + d1 = sufx & 0x;
> > + d = (d0 << 16) | d1;
> > +
> > + /*
> > +  * sign extend a 34 bit number
> > +  */
> > + dd = (unsigned int) (d >> 2);
> > + ea = (signed int) dd;
> > + ea = (ea << 2) | (d & 0x3);
> > +
> > + if (!prefix_r && ra)
> > + ea += regs->gpr[ra];
> > + else if (!prefix_r && !ra)
> > + ; /* Leave ea as is */
> > + else if (prefix_r && !ra)
> > + ea += regs->nip;
> > + else if (prefix_r && ra)
> > + ; /* Invalid form. Should already be checked for by caller! */
> > +
> > + return ea;
> > +}
> > +
> >  /*
> >   * Return the largest power of 2, not greater than sizeof(unsigned long),
> >   * such that x is a multiple of it.
> > @@ -1166,6 +1203,7 @@ int analyse_instr(struct instruction_op *op, const 
> > struct pt_regs *regs,
> > unsigned int instr, unsigned int sufx)
> >  {
> >   unsigned int opcode, ra, rb, rc, rd, spr, u;
> > + unsigned int sufxopcode, prefixtype, prefix_r;
> >   unsigned long int imm;
> >   unsigned long int val, val2;
> >   unsigned int mb, me, sh;
> > @@ -2652,6 +2690,78 @@ int analyse_instr(struct instruction_op *op, const 
> > struct pt_regs *regs,
> >
> >   }
> >
> > +/*
> > + * Prefixed instructions
> > + */
> > + switch (opcode) {
> > + case 1:
> > + prefix_r = instr & (1ul << 20);
> > + ra = (sufx >> 16) & 0x1f;
> > + op->update_reg = ra;
> > + rd = (sufx >> 21) & 0x1f;
> > + op->reg = rd;
> > + op->val = regs->gpr[rd];
> > +
> > + sufxopcode = sufx >> 26;
> > + prefixtype = (instr >> 24) & 0x3;
> > + switch (prefixtype) {
> > + case 0: /* Type 00  Eight-Byte Load/Store */
> > + if (prefix_r && ra)
> > + break;
> > + op->ea = mlsd_8lsd_ea(instr, sufx, regs);
> > + switch (sufxopcode) {
> > + case 41:/* plwa */
> > + op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 4);
> > + break;
> > + case 56:/* plq */
> > + op->type = MKOP(LOAD, PREFIXED, 16);
> > + break;
> > + case 57:/* pld */
> > +  

Re: [PATCH 15/18] powerpc/uprobes: Add support for prefixed instructions

[Jordan Niethe]

On Mon, Jan 13, 2020 at 10:30 PM Balamuruhan S  wrote:
>
> On Tue, Nov 26, 2019 at 04:21:38PM +1100, Jordan Niethe wrote:
> > Uprobes can execute instructions out of line. Increase the size of the
> > buffer used  for this so that this works for prefixed instructions. Take
> > into account the length of prefixed instructions when fixing up the nip.
> >
> > Signed-off-by: Jordan Niethe 
> > ---
> >  arch/powerpc/include/asm/uprobes.h | 18 ++
> >  arch/powerpc/kernel/uprobes.c  |  4 ++--
> >  2 files changed, 16 insertions(+), 6 deletions(-)
> >
> > diff --git a/arch/powerpc/include/asm/uprobes.h 
> > b/arch/powerpc/include/asm/uprobes.h
> > index 2bbdf27d09b5..5b5e8a3d2f55 100644
> > --- a/arch/powerpc/include/asm/uprobes.h
> > +++ b/arch/powerpc/include/asm/uprobes.h
> > @@ -14,18 +14,28 @@
> >
> >  typedef ppc_opcode_t uprobe_opcode_t;
> >
> > +/*
> > + * We have to ensure we have enought space for prefixed instructions, which
>
> minor typo of `enought` and we can have something like below,
Thanks for catching that.
>
> s/We have to ensure we have enought/Ensure we have enough
Will do.
>
> -- Bala
>
> > + * are double the size of a word instruction, i.e. 8 bytes. However,
> > + * sometimes it is simpler to treat a prefixed instruction like 2 word
> > + * instructions.
> > + */
> >  #define MAX_UINSN_BYTES  4
> > -#define UPROBE_XOL_SLOT_BYTES(MAX_UINSN_BYTES)
> > +#define UPROBE_XOL_SLOT_BYTES(2 * MAX_UINSN_BYTES)
> >
> >  /* The following alias is needed for reference from arch-agnostic code */
> >  #define UPROBE_SWBP_INSN BREAKPOINT_INSTRUCTION
> >  #define UPROBE_SWBP_INSN_SIZE4 /* swbp insn size in bytes */
> >
> >  struct arch_uprobe {
> > +  /*
> > +   * Ensure there is enough space for prefixed instructions. Prefixed
> > +   * instructions must not cross 64-byte boundaries.
> > +   */
> >   union {
> > - u32 insn;
> > - u32 ixol;
> > - };
> > + uprobe_opcode_t insn[2];
> > + uprobe_opcode_t ixol[2];
> > + } __aligned(64);
> >  };
> >
> >  struct arch_uprobe_task {
> > diff --git a/arch/powerpc/kernel/uprobes.c b/arch/powerpc/kernel/uprobes.c
> > index ab1077dc6148..cfcea6946f8b 100644
> > --- a/arch/powerpc/kernel/uprobes.c
> > +++ b/arch/powerpc/kernel/uprobes.c
> > @@ -111,7 +111,7 @@ int arch_uprobe_post_xol(struct arch_uprobe *auprobe, 
> > struct pt_regs *regs)
> >* support doesn't exist and have to fix-up the next instruction
> >* to be executed.
> >*/
> > - regs->nip = utask->vaddr + MAX_UINSN_BYTES;
> > + regs->nip = utask->vaddr + ((IS_PREFIX(auprobe->insn[0])) ? 8 : 4);
> >
> >   user_disable_single_step(current);
> >   return 0;
> > @@ -173,7 +173,7 @@ bool arch_uprobe_skip_sstep(struct arch_uprobe 
> > *auprobe, struct pt_regs *regs)
> >* emulate_step() returns 1 if the insn was successfully emulated.
> >* For all other cases, we need to single-step in hardware.
> >*/
> > - ret = emulate_step(regs, auprobe->insn, 0);
> > + ret = emulate_step(regs, auprobe->insn[0], auprobe->insn[1]);
> >   if (ret > 0)
> >   return true;
> >
> > --
> > 2.20.1
> >
>

Re: [PATCH 05/18] powerpc sstep: Prepare to support prefixed instructions

[Jordan Niethe]

On Mon, Jan 13, 2020 at 5:18 PM Balamuruhan S  wrote:
>
> On Tue, Nov 26, 2019 at 04:21:28PM +1100, Jordan Niethe wrote:
> > Currently all instructions are a single word long. A future ISA version
> > will include prefixed instructions which have a double word length. The
> > functions used for analysing and emulating instructions need to be
> > modified so that they can handle these new instruction types.
> >
> > A prefixed instruction is a word prefix followed by a word suffix. All
> > prefixes uniquely have the primary op-code 1. Suffixes may be valid word
> > instructions or instructions that only exist as suffixes.
> >
> > In handling prefixed instructions it will be convenient to treat the
> > suffix and prefix as separate words. To facilitate this modify
> > analyse_instr() and emulate_step() to take a take a suffix as a
>
> typo - s/take a take a/take a
Thanks for catching this.
>
> > parameter. For word instructions it does not matter what is passed in
> > here - it will be ignored.
> >
> > We also define a new flag, PREFIXED, to be used in instruction_op:type.
> > This flag will indicate when emulating an analysed instruction if the
> > NIP should be advanced by word length or double word length.
> >
> > The callers of analyse_instr() and emulate_step() will need their own
> > changes to be able to support prefixed instructions. For now modify them
> > to pass in 0 as a suffix.
> >
> > Note that at this point no prefixed instructions are emulated or
> > analysed - this is just making it possible to do so.
> >
> > Signed-off-by: Jordan Niethe 
> > ---
> >  arch/powerpc/include/asm/ppc-opcode.h |  3 +++
> >  arch/powerpc/include/asm/sstep.h  |  8 +--
> >  arch/powerpc/include/asm/uaccess.h| 30 +++
> >  arch/powerpc/kernel/align.c   |  2 +-
> >  arch/powerpc/kernel/hw_breakpoint.c   |  4 ++--
> >  arch/powerpc/kernel/kprobes.c |  2 +-
> >  arch/powerpc/kernel/mce_power.c   |  2 +-
> >  arch/powerpc/kernel/optprobes.c   |  2 +-
> >  arch/powerpc/kernel/uprobes.c |  2 +-
> >  arch/powerpc/kvm/emulate_loadstore.c  |  2 +-
> >  arch/powerpc/lib/sstep.c  | 12 ++-
> >  arch/powerpc/lib/test_emulate_step.c  | 30 +--
> >  arch/powerpc/xmon/xmon.c  |  4 ++--
> >  13 files changed, 71 insertions(+), 32 deletions(-)
> >
> > diff --git a/arch/powerpc/include/asm/ppc-opcode.h 
> > b/arch/powerpc/include/asm/ppc-opcode.h
> > index c1df75edde44..a1dfa4bdd22f 100644
> > --- a/arch/powerpc/include/asm/ppc-opcode.h
> > +++ b/arch/powerpc/include/asm/ppc-opcode.h
> > @@ -377,6 +377,9 @@
> >  #define PPC_INST_VCMPEQUD0x10c7
> >  #define PPC_INST_VCMPEQUB0x1006
> >
> > +/* macro to check if a word is a prefix */
> > +#define IS_PREFIX(x) (((x) >> 26) == 1)
> > +
> >  /* macros to insert fields into opcodes */
> >  #define ___PPC_RA(a) (((a) & 0x1f) << 16)
> >  #define ___PPC_RB(b) (((b) & 0x1f) << 11)
> > diff --git a/arch/powerpc/include/asm/sstep.h 
> > b/arch/powerpc/include/asm/sstep.h
> > index 769f055509c9..6d4cb602e231 100644
> > --- a/arch/powerpc/include/asm/sstep.h
> > +++ b/arch/powerpc/include/asm/sstep.h
> > @@ -89,6 +89,9 @@ enum instruction_type {
> >  #define VSX_LDLEFT   4   /* load VSX register from left */
> >  #define VSX_CHECK_VEC8   /* check MSR_VEC not MSR_VSX for reg 
> > >= 32 */
> >
> > +/* Prefixed flag, ORed in with type */
> > +#define PREFIXED 0x800
> > +
> >  /* Size field in type word */
> >  #define SIZE(n)  ((n) << 12)
> >  #define GETSIZE(w)   ((w) >> 12)
> > @@ -132,7 +135,7 @@ union vsx_reg {
> >   * otherwise.
> >   */
> >  extern int analyse_instr(struct instruction_op *op, const struct pt_regs 
> > *regs,
> > -  unsigned int instr);
> > +  unsigned int instr, unsigned int sufx);
> >
> >  /*
> >   * Emulate an instruction that can be executed just by updating
> > @@ -149,7 +152,8 @@ void emulate_update_regs(struct pt_regs *reg, struct 
> > instruction_op *op);
> >   * 0 if it could not be emulated, or -1 for an instruction that
> >   * should not be emulated (rfid, mtmsrd clearing MSR_RI, etc.).
> >   */
> > -extern int emulate_step(struct pt_regs *regs, unsigned int instr);
> > +extern int emulate_step(struct pt_regs *regs, unsigned int instr,
> > +

Re: [PATCH 18/18] powerpc/fault: Use analyse_instr() to check for store with updates to sp

[Jordan Niethe]

On Fri, Feb 7, 2020 at 7:16 PM Greg Kurz  wrote:
>
> On Thu, 19 Dec 2019 01:11:33 +1100
> Daniel Axtens  wrote:
>
> > Jordan Niethe  writes:
> >
> > > A user-mode access to an address a long way below the stack pointer is
> > > only valid if the instruction is one that would update the stack pointer
> > > to the address accessed. This is checked by directly looking at the
> > > instructions op-code. As a result is does not take into account prefixed
> > > instructions. Instead of looking at the instruction our self, use
> > > analyse_instr() determine if this a store instruction that will update
> > > the stack pointer.
> > >
> > > Something to note is that there currently are not any store with update
> > > prefixed instructions. Actually there is no plan for prefixed
> > > update-form loads and stores. So this patch is probably not needed but
> > > it might be preferable to use analyse_instr() rather than open coding
> > > the test anyway.
> >
> > Yes please. I was looking through this code recently and was
> > horrified. This improves things a lot and I think is justification
> > enough as-is.
> >
>
> Except it doesn't work... I'm now experiencing a systematic crash of
> systemd at boot in my fedora31 guest:
>
> [3.322912] systemd[1]: segfault (11) at 73eaf550 nip 7ce4d42f8d78 lr 
> 9d82c098fc0 code 1 in libsystemd-shared-243.so[7ce4d415+2e]
> [3.323112] systemd[1]: code: 0480 6042 3c4c001e 3842edb0 7c0802a6 
> 3d81fff0 fb81ffe0 fba1ffe8
> [3.323244] systemd[1]: code: fbc1fff0 fbe1fff8 f8010010 7c200b78 
>  7c216000 4082fff8 f801ff71
>
> f801f001 is
>
> 0x1a8d78 : stdur0,-4096(r1)
>
> which analyse_instr() is supposed to decode as a STORE that
> updates r1 so we should be good... Unfortunately analyse_instr()
> forbids partial register sets, since it might return op->val
> based on some register content depending on the instruction:
>
> /* Following cases refer to regs->gpr[], so we need all regs */
> if (!FULL_REGS(regs))
> return -1;
>
> analyse_instr() was introduced with instruction emulation in mind, which
> goes far beyond the need we have in store_updates_sp(). Especially the
> fault path doesn't care for the register content at all...
>
> Not sure how to cope with that correctly (refactor analyse_instr() ? ) but
> until someone comes up with a solution, please don't merge this patch.
>
> Cheers,
>
> --
> Greg
Thank you this information. I agree analyse_instr() is overkill for
the situation
especially as there are no prefixed store-with-updates. I am going to drop this
patch from the series.
>
> > Regards,
> > Daniel
> > >
> > > Signed-off-by: Jordan Niethe 
> > > ---
> > >  arch/powerpc/mm/fault.c | 39 +++
> > >  1 file changed, 11 insertions(+), 28 deletions(-)
> > >
> > > diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
> > > index b5047f9b5dec..cb78b3ca1800 100644
> > > --- a/arch/powerpc/mm/fault.c
> > > +++ b/arch/powerpc/mm/fault.c
> > > @@ -41,37 +41,17 @@
> > >  #include 
> > >  #include 
> > >  #include 
> > > +#include 
> > >
> > >  /*
> > >   * Check whether the instruction inst is a store using
> > >   * an update addressing form which will update r1.
> > >   */
> > > -static bool store_updates_sp(unsigned int inst)
> > > +static bool store_updates_sp(struct instruction_op *op)
> > >  {
> > > -   /* check for 1 in the rA field */
> > > -   if (((inst >> 16) & 0x1f) != 1)
> > > -   return false;
> > > -   /* check major opcode */
> > > -   switch (inst >> 26) {
> > > -   case OP_STWU:
> > > -   case OP_STBU:
> > > -   case OP_STHU:
> > > -   case OP_STFSU:
> > > -   case OP_STFDU:
> > > -   return true;
> > > -   case OP_STD:/* std or stdu */
> > > -   return (inst & 3) == 1;
> > > -   case OP_31:
> > > -   /* check minor opcode */
> > > -   switch ((inst >> 1) & 0x3ff) {
> > > -   case OP_31_XOP_STDUX:
> > > -   case OP_31_XOP_STWUX:
> > > -   case OP_31_XOP_STBUX:
> > > -   case OP_31_XOP_STHUX:
> > > -   case OP_31_XOP_STFSUX:
> > > -   case OP_31_XOP_STFDUX:
> > > +   if (GETTYPE(op->type) == STORE) {
> > > +   if ((op->type

Re: [PATCH v2 03/13] powerpc sstep: Prepare to support prefixed instructions

[Jordan Niethe]

On Tue, Feb 11, 2020 at 4:57 PM Christophe Leroy
 wrote:
>
>
>
> Le 11/02/2020 à 06:33, Jordan Niethe a écrit :
> > Currently all instructions are a single word long. A future ISA version
> > will include prefixed instructions which have a double word length. The
> > functions used for analysing and emulating instructions need to be
> > modified so that they can handle these new instruction types.
> >
> > A prefixed instruction is a word prefix followed by a word suffix. All
> > prefixes uniquely have the primary op-code 1. Suffixes may be valid word
> > instructions or instructions that only exist as suffixes.
> >
> > In handling prefixed instructions it will be convenient to treat the
> > suffix and prefix as separate words. To facilitate this modify
> > analyse_instr() and emulate_step() to take a suffix as a
> > parameter. For word instructions it does not matter what is passed in
> > here - it will be ignored.
> >
> > We also define a new flag, PREFIXED, to be used in instruction_op:type.
> > This flag will indicate when emulating an analysed instruction if the
> > NIP should be advanced by word length or double word length.
> >
> > The callers of analyse_instr() and emulate_step() will need their own
> > changes to be able to support prefixed instructions. For now modify them
> > to pass in 0 as a suffix.
> >
> > Note that at this point no prefixed instructions are emulated or
> > analysed - this is just making it possible to do so.
> >
> > Signed-off-by: Jordan Niethe 
> > ---
> > v2: - Move definition of __get_user_instr() and
> > __get_user_instr_inatomic() to "powerpc: Support prefixed instructions
> > in alignment handler."
> >  - Use a macro for returning the length of an op
> >  - Rename sufx -> suffix
> >  - Define and use PPC_NO_SUFFIX instead of 0
> > ---
> >   arch/powerpc/include/asm/ppc-opcode.h |  5 +
> >   arch/powerpc/include/asm/sstep.h  |  9 ++--
> >   arch/powerpc/kernel/align.c   |  2 +-
> >   arch/powerpc/kernel/hw_breakpoint.c   |  4 ++--
> >   arch/powerpc/kernel/kprobes.c |  2 +-
> >   arch/powerpc/kernel/mce_power.c   |  2 +-
> >   arch/powerpc/kernel/optprobes.c   |  3 ++-
> >   arch/powerpc/kernel/uprobes.c |  2 +-
> >   arch/powerpc/kvm/emulate_loadstore.c  |  2 +-
> >   arch/powerpc/lib/sstep.c  | 12 ++-
> >   arch/powerpc/lib/test_emulate_step.c  | 30 +--
> >   arch/powerpc/xmon/xmon.c  |  5 +++--
> >   12 files changed, 46 insertions(+), 32 deletions(-)
> >
> > diff --git a/arch/powerpc/include/asm/ppc-opcode.h 
> > b/arch/powerpc/include/asm/ppc-opcode.h
> > index c1df75edde44..72783bc92e50 100644
> > --- a/arch/powerpc/include/asm/ppc-opcode.h
> > +++ b/arch/powerpc/include/asm/ppc-opcode.h
> > @@ -377,6 +377,11 @@
> >   #define PPC_INST_VCMPEQUD   0x10c7
> >   #define PPC_INST_VCMPEQUB   0x1006
> >
> > +/* macro to check if a word is a prefix */
> > +#define IS_PREFIX(x) (((x) >> 26) == 1)
>
> Can you add an OP_PREFIX in the OP list and use it instead of '1' ?
Will do.
>
> > +#define  PPC_NO_SUFFIX   0
> > +#define  PPC_INST_LENGTH(x)  (IS_PREFIX(x) ? 8 : 4)
> > +
> >   /* macros to insert fields into opcodes */
> >   #define ___PPC_RA(a)(((a) & 0x1f) << 16)
> >   #define ___PPC_RB(b)(((b) & 0x1f) << 11)
> > diff --git a/arch/powerpc/include/asm/sstep.h 
> > b/arch/powerpc/include/asm/sstep.h
> > index 769f055509c9..9ea8904a1549 100644
> > --- a/arch/powerpc/include/asm/sstep.h
> > +++ b/arch/powerpc/include/asm/sstep.h
> > @@ -89,11 +89,15 @@ enum instruction_type {
> >   #define VSX_LDLEFT  4   /* load VSX register from left */
> >   #define VSX_CHECK_VEC   8   /* check MSR_VEC not MSR_VSX for reg 
> > >= 32 */
> >
> > +/* Prefixed flag, ORed in with type */
> > +#define PREFIXED 0x800
> > +
> >   /* Size field in type word */
> >   #define SIZE(n) ((n) << 12)
> >   #define GETSIZE(w)  ((w) >> 12)
> >
> >   #define GETTYPE(t)  ((t) & INSTR_TYPE_MASK)
> > +#define OP_LENGTH(t) (((t) & PREFIXED) ? 8 : 4)
>
> Is it worth naming it OP_LENGTH ? Can't it be mistaken as one of the
> OP_xxx from the list in asm/opcode.h ?
>
> What about GETLENGTH() instead to be consistant with the above lines ?
Good point, will do.
>
> Christophe

Re: [PATCH 05/18] powerpc sstep: Prepare to support prefixed instructions

[Jordan Niethe]

On Fri, Dec 20, 2019 at 4:17 PM Jordan Niethe  wrote:
>
> On Thu, Dec 19, 2019 at 1:15 AM Daniel Axtens  wrote:
> >
> > Jordan Niethe  writes:
> >
> > > Currently all instructions are a single word long. A future ISA version
> > > will include prefixed instructions which have a double word length. The
> > > functions used for analysing and emulating instructions need to be
> > > modified so that they can handle these new instruction types.
> > >
> > > A prefixed instruction is a word prefix followed by a word suffix. All
> > > prefixes uniquely have the primary op-code 1. Suffixes may be valid word
> > > instructions or instructions that only exist as suffixes.
> > >
> > > In handling prefixed instructions it will be convenient to treat the
> > > suffix and prefix as separate words. To facilitate this modify
> > > analyse_instr() and emulate_step() to take a take a suffix as a
> > > parameter. For word instructions it does not matter what is passed in
> > > here - it will be ignored.
> > >
> > > We also define a new flag, PREFIXED, to be used in instruction_op:type.
> > > This flag will indicate when emulating an analysed instruction if the
> > > NIP should be advanced by word length or double word length.
> > >
> > > The callers of analyse_instr() and emulate_step() will need their own
> > > changes to be able to support prefixed instructions. For now modify them
> > > to pass in 0 as a suffix.
> > >
> > > Note that at this point no prefixed instructions are emulated or
> > > analysed - this is just making it possible to do so.
> > >
> > > Signed-off-by: Jordan Niethe 
> > > ---
> > >  arch/powerpc/include/asm/ppc-opcode.h |  3 +++
> > >  arch/powerpc/include/asm/sstep.h  |  8 +--
> > >  arch/powerpc/include/asm/uaccess.h| 30 +++
> > >  arch/powerpc/kernel/align.c   |  2 +-
> > >  arch/powerpc/kernel/hw_breakpoint.c   |  4 ++--
> > >  arch/powerpc/kernel/kprobes.c |  2 +-
> > >  arch/powerpc/kernel/mce_power.c   |  2 +-
> > >  arch/powerpc/kernel/optprobes.c   |  2 +-
> > >  arch/powerpc/kernel/uprobes.c |  2 +-
> > >  arch/powerpc/kvm/emulate_loadstore.c  |  2 +-
> > >  arch/powerpc/lib/sstep.c  | 12 ++-
> > >  arch/powerpc/lib/test_emulate_step.c  | 30 +--
> > >  arch/powerpc/xmon/xmon.c  |  4 ++--
> > >  13 files changed, 71 insertions(+), 32 deletions(-)
> > >
> > > diff --git a/arch/powerpc/include/asm/ppc-opcode.h 
> > > b/arch/powerpc/include/asm/ppc-opcode.h
> > > index c1df75edde44..a1dfa4bdd22f 100644
> > > --- a/arch/powerpc/include/asm/ppc-opcode.h
> > > +++ b/arch/powerpc/include/asm/ppc-opcode.h
> > > @@ -377,6 +377,9 @@
> > >  #define PPC_INST_VCMPEQUD0x10c7
> > >  #define PPC_INST_VCMPEQUB0x1006
> > >
> > > +/* macro to check if a word is a prefix */
> > > +#define IS_PREFIX(x) (((x) >> 26) == 1)
> > > +
> > >  /* macros to insert fields into opcodes */
> > >  #define ___PPC_RA(a) (((a) & 0x1f) << 16)
> > >  #define ___PPC_RB(b) (((b) & 0x1f) << 11)
> > > diff --git a/arch/powerpc/include/asm/sstep.h 
> > > b/arch/powerpc/include/asm/sstep.h
> > > index 769f055509c9..6d4cb602e231 100644
> > > --- a/arch/powerpc/include/asm/sstep.h
> > > +++ b/arch/powerpc/include/asm/sstep.h
> > > @@ -89,6 +89,9 @@ enum instruction_type {
> > >  #define VSX_LDLEFT   4   /* load VSX register from left */
> > >  #define VSX_CHECK_VEC8   /* check MSR_VEC not MSR_VSX for 
> > > reg >= 32 */
> > >
> > > +/* Prefixed flag, ORed in with type */
> > > +#define PREFIXED 0x800
> > > +
> > >  /* Size field in type word */
> > >  #define SIZE(n)  ((n) << 12)
> > >  #define GETSIZE(w)   ((w) >> 12)
> > > @@ -132,7 +135,7 @@ union vsx_reg {
> > >   * otherwise.
> > >   */
> > >  extern int analyse_instr(struct instruction_op *op, const struct pt_regs 
> > > *regs,
> > > -  unsigned int instr);
> > > +  unsigned int instr, unsigned int sufx);
> > >
> >
> > I'm not saying this is necessarily better, but did you consider:
> >
> >  - making instr 64 bits and using masking and shifting

Re: [PATCH v5 05/21] powerpc: Use a function for getting the instruction op code

[Jordan Niethe]

On Thu, Apr 9, 2020 at 4:21 AM Segher Boessenkool
 wrote:
>
> Hi!
>
> On Mon, Apr 06, 2020 at 06:09:20PM +1000, Jordan Niethe wrote:
> > +static inline int ppc_inst_opcode(u32 x)
> > +{
> > + return x >> 26;
> > +}
>
> Maybe you should have "primary opcode" in this function name?
Thanks, that is a good idea.
>
>
> Segher

Re: [PATCH v5 13/21] powerpc/xmon: Use a function for reading instructions

[Jordan Niethe]

On Thu, Apr 9, 2020 at 3:04 PM Balamuruhan S  wrote:
>
> On Wed, 2020-04-08 at 12:18 +1000, Jordan Niethe wrote:
> > On Tue, Apr 7, 2020 at 9:31 PM Balamuruhan S  wrote:
> > > On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> > > > Currently in xmon, mread() is used for reading instructions. In
> > > > preparation for prefixed instructions, create and use a new function,
> > > > mread_instr(), especially for reading instructions.
> > > >
> > > > Signed-off-by: Jordan Niethe 
> > > > ---
> > > > v5: New to series, seperated from "Add prefixed instructions to
> > > > instruction data type"
> > > > ---
> > > >  arch/powerpc/xmon/xmon.c | 24 
> > > >  1 file changed, 20 insertions(+), 4 deletions(-)
> > > >
> > > > diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
> > > > index 5e3949322a6c..6f4cf01a58c1 100644
> > > > --- a/arch/powerpc/xmon/xmon.c
> > > > +++ b/arch/powerpc/xmon/xmon.c
> > > > @@ -125,6 +125,7 @@ extern unsigned int bpt_table[NBPTS * BPT_WORDS];
> > > >  static int cmds(struct pt_regs *);
> > > >  static int mread(unsigned long, void *, int);
> > > >  static int mwrite(unsigned long, void *, int);
> > > > +static int mread_instr(unsigned long, struct ppc_inst *);
> > > >  static int handle_fault(struct pt_regs *);
> > > >  static void byterev(unsigned char *, int);
> > > >  static void memex(void);
> > > > @@ -899,7 +900,7 @@ static void insert_bpts(void)
> > > >   for (i = 0; i < NBPTS; ++i, ++bp) {
> > > >   if ((bp->enabled & (BP_TRAP|BP_CIABR)) == 0)
> > > >   continue;
> > > > - if (mread(bp->address, , 4) != 4) {
> > > > + if (!mread_instr(bp->address, )) {
> > >
> > > Are these checks made based on whether `ppc_inst_len()` returns bool from
> > > mread_instr() ?
> > No, it was meant to be the length itself returned with a length of 0
> > indicating an error. I will need to fix that.
>
>
> I doubt it would return 0, whether we read instruction or not ppc_inst_len()
> would always return sizeof(struct ppc_inst).
Yes, sorry I meant I would have to change the function so that it
would return 0.
>
> can we do something like,
>
> static int
> mread_instr(unsigned long adrs, struct ppc_inst *instr)
> {
> int size = 0;
> if (setjmp(bus_error_jmp) == 0) {
> catch_memory_errors = 1;
> sync();
> *instr = ppc_inst_read((struct ppc_inst *)adrs);
> sync();
> /* wait a little while to see if we get a machine check */
> __delay(200);
> size = ppc_inst_len(instr);
> }
> catch_memory_errors = 0;
> return size;
> }
Yeah that looks right.
>
> -- Bala
> > > -- Bala
> > >
> > >
> > > >   printf("Couldn't read instruction at %lx, "
> > > >  "disabling breakpoint there\n", bp-
> > > > >address);
> > > >   bp->enabled = 0;
> > > > @@ -949,7 +950,7 @@ static void remove_bpts(void)
> > > >   for (i = 0; i < NBPTS; ++i, ++bp) {
> > > >   if ((bp->enabled & (BP_TRAP|BP_CIABR)) != BP_TRAP)
> > > >   continue;
> > > > - if (mread(bp->address, , 4) == 4
> > > > + if (mread_instr(bp->address, )
> > > >   && ppc_inst_equal(instr, ppc_inst(bpinstr))
> > > >   && patch_instruction(
> > > >   (struct ppc_inst *)bp->address, ppc_inst_read(bp-
> > > > > instr)) != 0)
> > > > @@ -1165,7 +1166,7 @@ static int do_step(struct pt_regs *regs)
> > > >   force_enable_xmon();
> > > >   /* check we are in 64-bit kernel mode, translation enabled */
> > > >   if ((regs->msr & (MSR_64BIT|MSR_PR|MSR_IR)) == (MSR_64BIT|MSR_IR))
> > > > {
> > > > - if (mread(regs->nip, , 4) == 4) {
> > > > + if (mread_instr(regs->nip, )) {
> > > >   stepped = emulate_step(regs, instr);
> > > >   if (stepped < 0) {
> > > >   

Re: [PATCH v5 02/21] powerpc/xmon: Move out-of-line instructions to text section

[Jordan Niethe]

On Thu, Apr 9, 2020 at 4:11 PM Christophe Leroy  wrote:
>
>
>
> Le 06/04/2020 à 10:09, Jordan Niethe a écrit :
> > To execute an instruction out of line after a breakpoint, the NIP is set
> > to the address of struct bpt::instr. Here a copy of the instruction that
> > was replaced with a breakpoint is kept, along with a trap so normal flow
> > can be resumed after XOLing. The struct bpt's are located within the
> > data section. This is problematic as the data section may be marked as
> > no execute.
> >
> > Instead of each struct bpt holding the instructions to be XOL'd, make a
> > new array, bpt_table[], with enough space to hold instructions for the
> > number of supported breakpoints. Place this array in the text section.
> > Make struct bpt::instr a pointer to the instructions in bpt_table[]
> > associated with that breakpoint. This association is a simple mapping:
> > bpts[n] -> bpt_table[n * words per breakpoint]. Currently we only need
> > the copied instruction followed by a trap, so 2 words per breakpoint.
> >
> > Signed-off-by: Jordan Niethe 
> > ---
> > v4: New to series
> > v5: - Do not use __section(), use a .space directive in .S file
>
> I was going to comment to use __section() instead of creating a
> dedicated .S file.
>
> Why did you change that in v5 ?
I noticed with some toolchains I was getting this message:
Warning: setting incorrect section attributes for .text.xmon_bpts
I was talking with mpe about it and he said that the usual way for
doing things like this was with .space in a .S file so I changed to
that way.
>
> >  - Simplify in_breakpoint_table() calculation
> >  - Define BPT_SIZE
> > ---
> >   arch/powerpc/xmon/Makefile|  2 +-
> >   arch/powerpc/xmon/xmon.c  | 23 +--
> >   arch/powerpc/xmon/xmon_bpts.S |  8 
> >   arch/powerpc/xmon/xmon_bpts.h |  8 
> >   4 files changed, 30 insertions(+), 11 deletions(-)
> >   create mode 100644 arch/powerpc/xmon/xmon_bpts.S
> >   create mode 100644 arch/powerpc/xmon/xmon_bpts.h
> >
> > diff --git a/arch/powerpc/xmon/Makefile b/arch/powerpc/xmon/Makefile
> > index c3842dbeb1b7..515a13ea6f28 100644
> > --- a/arch/powerpc/xmon/Makefile
> > +++ b/arch/powerpc/xmon/Makefile
> > @@ -21,7 +21,7 @@ endif
> >
> >   ccflags-$(CONFIG_PPC64) := $(NO_MINIMAL_TOC)
> >
> > -obj-y+= xmon.o nonstdio.o spr_access.o
> > +obj-y+= xmon.o nonstdio.o spr_access.o xmon_bpts.o
> >
> >   ifdef CONFIG_XMON_DISASSEMBLY
> >   obj-y   += ppc-dis.o ppc-opc.o
> > diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
> > index 02e3bd62cab4..049375206510 100644
> > --- a/arch/powerpc/xmon/xmon.c
> > +++ b/arch/powerpc/xmon/xmon.c
> > @@ -62,6 +62,7 @@
> >
> >   #include "nonstdio.h"
> >   #include "dis-asm.h"
> > +#include "xmon_bpts.h"
> >
> >   #ifdef CONFIG_SMP
> >   static cpumask_t cpus_in_xmon = CPU_MASK_NONE;
> > @@ -97,7 +98,7 @@ static long *xmon_fault_jmp[NR_CPUS];
> >   /* Breakpoint stuff */
> >   struct bpt {
> >   unsigned long   address;
> > - unsigned intinstr[2];
> > + unsigned int*instr;
> >   atomic_tref_count;
> >   int enabled;
> >   unsigned long   pad;
> > @@ -108,7 +109,6 @@ struct bpt {
> >   #define BP_TRAP 2
> >   #define BP_DABR 4
> >
> > -#define NBPTS256
> >   static struct bpt bpts[NBPTS];
> >   static struct bpt dabr;
> >   static struct bpt *iabr;
> > @@ -116,6 +116,10 @@ static unsigned bpinstr = 0x7fe8;/* trap */
> >
> >   #define BP_NUM(bp)  ((bp) - bpts + 1)
> >
> > +#define BPT_SIZE (sizeof(unsigned int) * 2)
> > +#define BPT_WORDS(BPT_SIZE / sizeof(unsigned int))
>
> Wouldn't it make more sense to do the following ? :
>
> #define BPT_WORDS   2
> #define BPT_SIZE(BPT_WORDS * sizeof(unsigned int))
I defined it like that so when we changed unsigned int -> struct
ppc_inst it would be the correct size whether or not the struct
included a suffix.
Otherwise it would be more straightforward to do it like that.
>
> > +extern unsigned int bpt_table[NBPTS * BPT_WORDS];
>
> Should go in xmon_bpts.h if we keep the definition in xmon_bpts.S
Right.
>
> > +
> >   /* Prototypes */
> >   static int cmds(struct pt_regs *);
> >   static int mread(unsigned long, void *, int);
> > @@ -853,15 +857,13 @@ static struct bpt *in_breakp

Re: [PATCH v5 00/21] Initial Prefixed Instruction support

[Jordan Niethe]

On Thu, Apr 9, 2020 at 4:39 PM Christophe Leroy  wrote:
>
>
>
> On 04/06/2020 08:09 AM, Jordan Niethe wrote:
> > A future revision of the ISA will introduce prefixed instructions. A
> > prefixed instruction is composed of a 4-byte prefix followed by a
> > 4-byte suffix.
> >
> > All prefixes have the major opcode 1. A prefix will never be a valid
> > word instruction. A suffix may be an existing word instruction or a
> > new instruction.
> >
> > This series enables prefixed instructions and extends the instruction
> > emulation to support them. Then the places where prefixed instructions
> > might need to be emulated are updated.
> >
> > v5 is based on feedback from Nick Piggins, Michael Ellerman, Balamuruhan
> > Suriyakumar and Alistair Popple.
> > The major changes:
> >  - The ppc instruction type is now a struct
> >  - Series now just based on next
> >  - ppc_inst_masked() dropped
> >  - Space for xmon breakpoints allocated in an assembly file
> >  - "Add prefixed instructions to instruction data type" patch seperated 
> > in
> >to smaller patches
> >  - Calling convention for create_branch() is changed
> >  - Some places which had not been updated to use the data type are now 
> > updated
>
> Build fails. I have not investigated why:
Thanks, I will check it out.
>
>CC  arch/powerpc/kernel/process.o
> In file included from ./arch/powerpc/include/asm/code-patching.h:14:0,
>   from arch/powerpc/kernel/process.c:60:
> ./arch/powerpc/include/asm/inst.h:69:38: error: unknown type name ‘ppc_inst’
>   static inline bool ppc_inst_prefixed(ppc_inst x)
>^
> ./arch/powerpc/include/asm/inst.h:79:19: error: redefinition of
> ‘ppc_inst_val’
>   static inline u32 ppc_inst_val(struct ppc_inst x)
> ^
> ./arch/powerpc/include/asm/inst.h:21:19: note: previous definition of
> ‘ppc_inst_val’ was here
>   static inline u32 ppc_inst_val(struct ppc_inst x)
> ^
> ./arch/powerpc/include/asm/inst.h: In function ‘ppc_inst_len’:
> ./arch/powerpc/include/asm/inst.h:103:10: error: implicit declaration of
> function ‘ppc_inst_prefixed’ [-Werror=implicit-function-declaration]
>return (ppc_inst_prefixed(x)) ? 8  : 4;
>^
>
> Christophe
>
> >
> > v4 is based on feedback from Nick Piggins, Christophe Leroy and Daniel 
> > Axtens.
> > The major changes:
> >  - Move xmon breakpoints from data section to text section
> >  - Introduce a data type for instructions on powerpc
> >
> > v3 is based on feedback from Christophe Leroy. The major changes:
> >  - Completely replacing store_inst() with patch_instruction() in
> >xmon
> >  - Improve implementation of mread_instr() to not use mread().
> >  - Base the series on top of
> >https://patchwork.ozlabs.org/patch/1232619/ as this will effect
> >kprobes.
> >  - Some renaming and simplification of conditionals.
> >
> > v2 incorporates feedback from Daniel Axtens and and Balamuruhan
> > S. The major changes are:
> >  - Squashing together all commits about SRR1 bits
> >  - Squashing all commits for supporting prefixed load stores
> >  - Changing abbreviated references to sufx/prfx -> suffix/prefix
> >  - Introducing macros for returning the length of an instruction
> >  - Removing sign extension flag from pstd/pld in sstep.c
> >  - Dropping patch  "powerpc/fault: Use analyse_instr() to check for
> >store with updates to sp" from the series, it did not really fit
> >with prefixed enablement in the first place and as reported by Greg
> >Kurz did not work correctly.
> >
> >
> > Alistair Popple (1):
> >powerpc: Enable Prefixed Instructions
> >
> > Jordan Niethe (20):
> >powerpc/xmon: Remove store_inst() for patch_instruction()
> >powerpc/xmon: Move out-of-line instructions to text section
> >powerpc: Change calling convention for create_branch() et. al.
> >powerpc: Use a macro for creating instructions from u32s
> >powerpc: Use a function for getting the instruction op code
> >powerpc: Use an accessor for instructions
> >powerpc: Use a function for byte swapping instructions
> >powerpc: Introduce functions for instruction equality
> >powerpc: Use a datatype for instructions
> >powerpc: Use a function for reading instructions
> >powerpc: Define and use __get_user_instr{,inatomic}()
> >

Re: [PATCH v5 18/21] powerpc64: Add prefixed instructions to instruction data type

[Jordan Niethe]

On Mon, Apr 13, 2020 at 10:04 PM Balamuruhan S  wrote:
>
> On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> > For powerpc64, redefine the ppc_inst type so both word and prefixed
> > instructions can be represented. On powerpc32 the type will remain the
> > same.  Update places which had assumed instructions to be 4 bytes long.
> >
> > Signed-off-by: Jordan Niethe 
> > ---
> > v4: New to series
> > v5:  - Distinguish normal instructions from prefixed instructions with a
> >0xff marker for the suffix.
> >  - __patch_instruction() using std for prefixed instructions
> > ---
> >  arch/powerpc/include/asm/inst.h  | 71 ++--
> >  arch/powerpc/include/asm/kprobes.h   |  2 +-
> >  arch/powerpc/include/asm/uaccess.h   | 31 ++--
> >  arch/powerpc/include/asm/uprobes.h   |  2 +-
> >  arch/powerpc/kernel/optprobes.c  | 42 
> >  arch/powerpc/kernel/optprobes_head.S |  3 ++
> >  arch/powerpc/kernel/trace/ftrace.c   | 26 +-
> >  arch/powerpc/lib/code-patching.c | 19 +---
> >  arch/powerpc/lib/feature-fixups.c|  5 +-
> >  arch/powerpc/lib/sstep.c |  4 +-
> >  arch/powerpc/xmon/xmon.c |  6 +--
> >  arch/powerpc/xmon/xmon_bpts.S|  4 +-
> >  12 files changed, 171 insertions(+), 44 deletions(-)
> >
> > diff --git a/arch/powerpc/include/asm/inst.h
> > b/arch/powerpc/include/asm/inst.h
> > index 70b37a35a91a..7e23e7146c66 100644
> > --- a/arch/powerpc/include/asm/inst.h
> > +++ b/arch/powerpc/include/asm/inst.h
> > @@ -8,23 +8,67 @@
> >
> >  struct ppc_inst {
> >  u32 val;
> > +#ifdef __powerpc64__
> > +u32 suffix;
> > +#endif /* __powerpc64__ */
> >  } __packed;
> >
> > -#define ppc_inst(x) ((struct ppc_inst){ .val = x })
> > +static inline int ppc_inst_opcode(struct ppc_inst x)
> > +{
> > + return x.val >> 26;
>
>
> why don't we wrap here and in `ppc_inst_opcode()` in patch 9 using
> `ppc_inst_val()` ?
Will do.
>
>
> > +}
> >
> >  static inline u32 ppc_inst_val(struct ppc_inst x)
>
>
> There is another same definition below for the same function in
> #else part of __powerpc64__ ifdef.
Thanks
>
>
> >  {
> >   return x.val;
> >  }
> >
> > -static inline bool ppc_inst_len(struct ppc_inst x)
> > +#ifdef __powerpc64__
> > +#define ppc_inst(x) ((struct ppc_inst){ .val = (x), .suffix = 0xff })
> > +
> > +#define ppc_inst_prefix(x, y) ((struct ppc_inst){ .val = (x), .suffix = (y)
> > })
> > +
> > +static inline u32 ppc_inst_suffix(struct ppc_inst x)
> >  {
> > - return sizeof(struct ppc_inst);
> > + return x.suffix;
> >  }
> >
> > -static inline int ppc_inst_opcode(struct ppc_inst x)
> > +static inline bool ppc_inst_prefixed(struct ppc_inst x) {
> > + return ((ppc_inst_val(x) >> 26) == 1) && ppc_inst_suffix(x) != 0xff;
> > +}
> > +
> > +static inline struct ppc_inst ppc_inst_swab(struct ppc_inst x)
> >  {
> > - return x.val >> 26;
> > + return ppc_inst_prefix(swab32(ppc_inst_val(x)),
> > +swab32(ppc_inst_suffix(x)));
> > +}
> > +
> > +static inline struct ppc_inst ppc_inst_read(const struct ppc_inst *ptr)
> > +{
> > + u32 val, suffix = 0xff;
> > + val = *(u32 *)ptr;
> > + if ((val >> 26) == 1)
> > + suffix = *((u32 *)ptr + 1);
> > + return ppc_inst_prefix(val, suffix);
> > +}
> > +
> > +static inline void ppc_inst_write(struct ppc_inst *ptr, struct ppc_inst x)
> > +{
> > + if (ppc_inst_prefixed(x)) {
> > + *(u32 *)ptr = x.val;
> > + *((u32 *)ptr + 1) = x.suffix;
> > + } else {
> > + *(u32 *)ptr = x.val;
>
>
> can we wrap here as well with `ppc_inst_val()` and `ppc_inst_suffix()` ?
Yeah no reason not too.
>
>
> > + }
> > +}
> > +
> > +#else
> > +
> > +#define ppc_inst(x) ((struct ppc_inst){ .val = x })
> > +
> > +static inline bool ppc_inst_prefixed(ppc_inst x)
> > +{
> > + return 0;
>
>
> Is it return !!0 or return false ?
False probably will make more sense.
>
>
> >  }
> >
> >  static inline struct ppc_inst ppc_inst_swab(struct ppc_inst x)
> > @@ -32,14 +76,31 @@ static inline struct ppc_inst ppc_inst_swab(struct
> > ppc_inst x)
> >   return ppc_inst(swab32(ppc_inst_val(x)));
> >  }
> >
> > +static 

Re: [PATCH v5 09/21] powerpc: Use a datatype for instructions

[Jordan Niethe]

On Tue, Apr 7, 2020 at 8:30 PM Balamuruhan S  wrote:
>
> On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> > Currently unsigned ints are used to represent instructions on powerpc.
> > This has worked well as instructions have always been 4 byte words.
> > However, a future ISA version will introduce some changes to
> > instructions that mean this scheme will no longer work as well. This
> > change is Prefixed Instructions. A prefixed instruction is made up of a
> > word prefix followed by a word suffix to make an 8 byte double word
> > instruction. No matter the endianess of the system the prefix always
> > comes first. Prefixed instructions are only planned for powerpc64.
> >
> > Introduce a ppc_inst type to represent both prefixed and word
> > instructions on powerpc64 while keeping it possible to exclusively have
> > word instructions on powerpc32, A latter patch will expand the type to
> > include prefixed instructions but for now just typedef it to a u32.
> >
> > Later patches will introduce helper functions and macros for
> > manipulating the instructions so that powerpc64 and powerpc32 might
> > maintain separate type definitions.
> >
> > Signed-off-by: Jordan Niethe 
> > ---
> > v4: New to series
> > v5: Add to epapr_paravirt.c, kgdb.c
> > ---
> >  arch/powerpc/include/asm/code-patching.h | 32 -
> >  arch/powerpc/include/asm/inst.h  | 20 +++---
> >  arch/powerpc/include/asm/sstep.h |  5 +-
> >  arch/powerpc/include/asm/uprobes.h   |  5 +-
> >  arch/powerpc/kernel/align.c  |  4 +-
> >  arch/powerpc/kernel/epapr_paravirt.c |  4 +-
> >  arch/powerpc/kernel/hw_breakpoint.c  |  4 +-
> >  arch/powerpc/kernel/jump_label.c |  2 +-
> >  arch/powerpc/kernel/kgdb.c   |  4 +-
> >  arch/powerpc/kernel/kprobes.c|  8 +--
> >  arch/powerpc/kernel/mce_power.c  |  5 +-
> >  arch/powerpc/kernel/optprobes.c  | 40 ++--
> >  arch/powerpc/kernel/setup_32.c   |  2 +-
> >  arch/powerpc/kernel/trace/ftrace.c   | 83 
> >  arch/powerpc/kernel/vecemu.c |  5 +-
> >  arch/powerpc/lib/code-patching.c | 69 ++--
> >  arch/powerpc/lib/feature-fixups.c| 48 +++---
> >  arch/powerpc/lib/sstep.c |  4 +-
> >  arch/powerpc/lib/test_emulate_step.c |  9 +--
> >  arch/powerpc/perf/core-book3s.c  |  4 +-
> >  arch/powerpc/xmon/xmon.c | 24 +++
> >  21 files changed, 196 insertions(+), 185 deletions(-)
> >
> > diff --git a/arch/powerpc/include/asm/code-patching.h
> > b/arch/powerpc/include/asm/code-patching.h
> > index 48e021957ee5..eacc9102c251 100644
> > --- a/arch/powerpc/include/asm/code-patching.h
> > +++ b/arch/powerpc/include/asm/code-patching.h
> > @@ -23,33 +23,33 @@
> >  #define BRANCH_ABSOLUTE  0x2
> >
> >  bool is_offset_in_branch_range(long offset);
> > -int create_branch(unsigned int *instr, const unsigned int *addr,
> > +int create_branch(struct ppc_inst *instr, const struct ppc_inst *addr,
> > unsigned long target, int flags);
> > -int create_cond_branch(unsigned int *instr, const unsigned int *addr,
> > +int create_cond_branch(struct ppc_inst *instr, const struct ppc_inst *addr,
> >  unsigned long target, int flags);
> > -int patch_branch(unsigned int *addr, unsigned long target, int flags);
> > -int patch_instruction(unsigned int *addr, unsigned int instr);
> > -int raw_patch_instruction(unsigned int *addr, unsigned int instr);
> > +int patch_branch(struct ppc_inst *addr, unsigned long target, int flags);
> > +int patch_instruction(struct ppc_inst *addr, struct ppc_inst instr);
> > +int raw_patch_instruction(struct ppc_inst *addr, struct ppc_inst instr);
> >
> >  static inline unsigned long patch_site_addr(s32 *site)
> >  {
> >   return (unsigned long)site + *site;
> >  }
> >
> > -static inline int patch_instruction_site(s32 *site, unsigned int instr)
> > +static inline int patch_instruction_site(s32 *site, struct ppc_inst instr)
> >  {
> > - return patch_instruction((unsigned int *)patch_site_addr(site), 
> > instr);
> > + return patch_instruction((struct ppc_inst *)patch_site_addr(site),
> > instr);
> >  }
> >
> >  static inline int patch_branch_site(s32 *site, unsigned long target, int
> > flags)
> >  {
> > - return patch_branch((unsigned int *)patch_site_addr(site), target,
> > flags);
> > + ret

Re: [PATCH v5 13/21] powerpc/xmon: Use a function for reading instructions

[Jordan Niethe]

On Tue, Apr 7, 2020 at 9:31 PM Balamuruhan S  wrote:
>
> On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> > Currently in xmon, mread() is used for reading instructions. In
> > preparation for prefixed instructions, create and use a new function,
> > mread_instr(), especially for reading instructions.
> >
> > Signed-off-by: Jordan Niethe 
> > ---
> > v5: New to series, seperated from "Add prefixed instructions to
> > instruction data type"
> > ---
> >  arch/powerpc/xmon/xmon.c | 24 
> >  1 file changed, 20 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
> > index 5e3949322a6c..6f4cf01a58c1 100644
> > --- a/arch/powerpc/xmon/xmon.c
> > +++ b/arch/powerpc/xmon/xmon.c
> > @@ -125,6 +125,7 @@ extern unsigned int bpt_table[NBPTS * BPT_WORDS];
> >  static int cmds(struct pt_regs *);
> >  static int mread(unsigned long, void *, int);
> >  static int mwrite(unsigned long, void *, int);
> > +static int mread_instr(unsigned long, struct ppc_inst *);
> >  static int handle_fault(struct pt_regs *);
> >  static void byterev(unsigned char *, int);
> >  static void memex(void);
> > @@ -899,7 +900,7 @@ static void insert_bpts(void)
> >   for (i = 0; i < NBPTS; ++i, ++bp) {
> >   if ((bp->enabled & (BP_TRAP|BP_CIABR)) == 0)
> >   continue;
> > - if (mread(bp->address, , 4) != 4) {
> > + if (!mread_instr(bp->address, )) {
>
>
> Are these checks made based on whether `ppc_inst_len()` returns bool from
> mread_instr() ?
No, it was meant to be the length itself returned with a length of 0
indicating an error. I will need to fix that.
>
> -- Bala
>
>
> >   printf("Couldn't read instruction at %lx, "
> >  "disabling breakpoint there\n", bp->address);
> >   bp->enabled = 0;
> > @@ -949,7 +950,7 @@ static void remove_bpts(void)
> >   for (i = 0; i < NBPTS; ++i, ++bp) {
> >   if ((bp->enabled & (BP_TRAP|BP_CIABR)) != BP_TRAP)
> >   continue;
> > - if (mread(bp->address, , 4) == 4
> > + if (mread_instr(bp->address, )
> >   && ppc_inst_equal(instr, ppc_inst(bpinstr))
> >   && patch_instruction(
> >   (struct ppc_inst *)bp->address, ppc_inst_read(bp-
> > >instr)) != 0)
> > @@ -1165,7 +1166,7 @@ static int do_step(struct pt_regs *regs)
> >   force_enable_xmon();
> >   /* check we are in 64-bit kernel mode, translation enabled */
> >   if ((regs->msr & (MSR_64BIT|MSR_PR|MSR_IR)) == (MSR_64BIT|MSR_IR)) {
> > - if (mread(regs->nip, , 4) == 4) {
> > + if (mread_instr(regs->nip, )) {
> >   stepped = emulate_step(regs, instr);
> >   if (stepped < 0) {
> >   printf("Couldn't single-step %s 
> > instruction\n",
> > @@ -1332,7 +1333,7 @@ static long check_bp_loc(unsigned long addr)
> >   printf("Breakpoints may only be placed at kernel 
> > addresses\n");
> >   return 0;
> >   }
> > - if (!mread(addr, , sizeof(instr))) {
> > + if (!mread_instr(addr, )) {
> >   printf("Can't read instruction at address %lx\n", addr);
> >   return 0;
> >   }
> > @@ -2125,6 +2126,21 @@ mwrite(unsigned long adrs, void *buf, int size)
> >   return n;
> >  }
> >
> > +static int
> > +mread_instr(unsigned long adrs, struct ppc_inst *instr)
> > +{
> > + if (setjmp(bus_error_jmp) == 0) {
> > + catch_memory_errors = 1;
> > + sync();
> > + *instr = ppc_inst_read((struct ppc_inst *)adrs);
> > + sync();
> > + /* wait a little while to see if we get a machine check */
> > + __delay(200);
> > + }
> > + catch_memory_errors = 0;
> > + return ppc_inst_len(*instr);
> > +}
> > +
> >  static int fault_type;
> >  static int fault_except;
> >  static char *fault_chars[] = { "--", "**", "##" };
>

Re: [PATCH v5 12/21] powerpc: Introduce a function for reporting instruction length

[Jordan Niethe]

On Tue, Apr 7, 2020 at 9:15 PM Balamuruhan S  wrote:
>
> On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> > Currently all instructions have the same length, but in preparation for
> > prefixed instructions introduce a function for returning instruction
> > length.
> >
> > Signed-off-by: Jordan Niethe 
> > ---
> >  arch/powerpc/include/asm/inst.h | 5 +
> >  arch/powerpc/kernel/kprobes.c   | 6 --
> >  arch/powerpc/kernel/uprobes.c   | 2 +-
> >  3 files changed, 10 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/powerpc/include/asm/inst.h
> > b/arch/powerpc/include/asm/inst.h
> > index 369b35ce964c..70b37a35a91a 100644
> > --- a/arch/powerpc/include/asm/inst.h
> > +++ b/arch/powerpc/include/asm/inst.h
> > @@ -17,6 +17,11 @@ static inline u32 ppc_inst_val(struct ppc_inst x)
> >   return x.val;
> >  }
> >
> > +static inline bool ppc_inst_len(struct ppc_inst x)
>
>
> return type shouldn't be a bool, `size_t` instead.
Thank you.
>
> -- Bala
>
> > +{
> > + return sizeof(struct ppc_inst);
> > +}
> > +
> >  static inline int ppc_inst_opcode(struct ppc_inst x)
> >  {
> >   return x.val >> 26;
> > diff --git a/arch/powerpc/kernel/kprobes.c b/arch/powerpc/kernel/kprobes.c
> > index ff53e5ef7e40..8d17cfdcdc54 100644
> > --- a/arch/powerpc/kernel/kprobes.c
> > +++ b/arch/powerpc/kernel/kprobes.c
> > @@ -474,14 +474,16 @@ NOKPROBE_SYMBOL(trampoline_probe_handler);
> >   */
> >  int kprobe_post_handler(struct pt_regs *regs)
> >  {
> > + int len;
> >   struct kprobe *cur = kprobe_running();
> >   struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
> >
> >   if (!cur || user_mode(regs))
> >   return 0;
> >
> > + len = ppc_inst_len(ppc_inst_read((struct ppc_inst *)cur->ainsn.insn));
> >   /* make sure we got here for instruction we have a kprobe on */
> > - if (((unsigned long)cur->ainsn.insn + 4) != regs->nip)
> > + if (((unsigned long)cur->ainsn.insn + len) != regs->nip)
> >   return 0;
> >
> >   if ((kcb->kprobe_status != KPROBE_REENTER) && cur->post_handler) {
> > @@ -490,7 +492,7 @@ int kprobe_post_handler(struct pt_regs *regs)
> >   }
> >
> >   /* Adjust nip to after the single-stepped instruction */
> > - regs->nip = (unsigned long)cur->addr + 4;
> > + regs->nip = (unsigned long)cur->addr + len;
> >   regs->msr |= kcb->kprobe_saved_msr;
> >
> >   /*Restore back the original saved kprobes variables and continue. */
> > diff --git a/arch/powerpc/kernel/uprobes.c b/arch/powerpc/kernel/uprobes.c
> > index 31c870287f2b..8e63afa012ba 100644
> > --- a/arch/powerpc/kernel/uprobes.c
> > +++ b/arch/powerpc/kernel/uprobes.c
> > @@ -112,7 +112,7 @@ int arch_uprobe_post_xol(struct arch_uprobe *auprobe,
> > struct pt_regs *regs)
> >* support doesn't exist and have to fix-up the next instruction
> >* to be executed.
> >*/
> > - regs->nip = utask->vaddr + MAX_UINSN_BYTES;
> > + regs->nip = utask->vaddr + ppc_inst_len(auprobe->insn);
> >
> >   user_disable_single_step(current);
> >   return 0;
>

Re: [PATCH v5 11/21] powerpc: Define and use __get_user_instr{, inatomic}()

[Jordan Niethe]

On Tue, Apr 7, 2020 at 8:48 PM Balamuruhan S  wrote:
>
> On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> > Define specific __get_user_instr() and __get_user_instr_inatomic()
> > macros for reading instructions from user space.
> >
> > Signed-off-by: Jordan Niethe 
> > ---
> >  arch/powerpc/include/asm/uaccess.h  | 5 +
> >  arch/powerpc/kernel/align.c | 2 +-
> >  arch/powerpc/kernel/hw_breakpoint.c | 2 +-
> >  arch/powerpc/kernel/vecemu.c| 2 +-
> >  4 files changed, 8 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/powerpc/include/asm/uaccess.h
> > b/arch/powerpc/include/asm/uaccess.h
> > index 2f500debae21..c0a35e4586a5 100644
> > --- a/arch/powerpc/include/asm/uaccess.h
> > +++ b/arch/powerpc/include/asm/uaccess.h
> > @@ -105,6 +105,11 @@ static inline int __access_ok(unsigned long addr,
> > unsigned long size,
> >  #define __put_user_inatomic(x, ptr) \
> >   __put_user_nosleep((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)))
> >
> > +#define __get_user_instr(x, ptr) \
> > + __get_user_nocheck((x).val, (u32 *)(ptr), sizeof(u32), true)
> > +
> > +#define __get_user_instr_inatomic(x, ptr) \
> > + __get_user_nosleep((x).val, (u32 *)(ptr), sizeof(u32))
>
>
> should we use ppc_inst_val() ?
The __get_user() macros load a value into the given variable, so we
can not use ppc_inst_val().
>
> -- Bala
>
>
> >  extern long __put_user_bad(void);
> >
> >  /*
> > diff --git a/arch/powerpc/kernel/align.c b/arch/powerpc/kernel/align.c
> > index 66a6d1de7799..65cdfd41e3a1 100644
> > --- a/arch/powerpc/kernel/align.c
> > +++ b/arch/powerpc/kernel/align.c
> > @@ -304,7 +304,7 @@ int fix_alignment(struct pt_regs *regs)
> >*/
> >   CHECK_FULL_REGS(regs);
> >
> > - if (unlikely(__get_user(instr.val, (unsigned int __user *)regs->nip)))
> > + if (unlikely(__get_user_instr(instr, (void __user *)regs->nip)))
> >   return -EFAULT;
> >   if ((regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE)) {
> >   /* We don't handle PPC little-endian any more... */
> > diff --git a/arch/powerpc/kernel/hw_breakpoint.c
> > b/arch/powerpc/kernel/hw_breakpoint.c
> > index 542f65ccf68b..cebab14e2788 100644
> > --- a/arch/powerpc/kernel/hw_breakpoint.c
> > +++ b/arch/powerpc/kernel/hw_breakpoint.c
> > @@ -249,7 +249,7 @@ static bool stepping_handler(struct pt_regs *regs, 
> > struct
> > perf_event *bp,
> >   struct instruction_op op;
> >   unsigned long addr = info->address;
> >
> > - if (__get_user_inatomic(instr.val, (unsigned int *)regs->nip))
> > + if (__get_user_instr_inatomic(instr, (void __user *)regs->nip))
> >   goto fail;
> >
> >   ret = analyse_instr(, regs, instr);
> > diff --git a/arch/powerpc/kernel/vecemu.c b/arch/powerpc/kernel/vecemu.c
> > index bbf536e10902..c82ede46d71b 100644
> > --- a/arch/powerpc/kernel/vecemu.c
> > +++ b/arch/powerpc/kernel/vecemu.c
> > @@ -266,7 +266,7 @@ int emulate_altivec(struct pt_regs *regs)
> >   unsigned int va, vb, vc, vd;
> >   vector128 *vrs;
> >
> > - if (get_user(instr.val, (unsigned int __user *) regs->nip))
> > + if (__get_user_instr(instr, (void __user *) regs->nip))
> >   return -EFAULT;
> >
> >   word = ppc_inst_val(instr);
>

Re: [PATCH v5 03/21] powerpc: Change calling convention for create_branch() et. al.

[Jordan Niethe]

On Tue, Apr 7, 2020 at 4:10 PM Balamuruhan S  wrote:
>
> On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> > create_branch(), create_cond_branch() and translate_branch() return the
> > instruction that they create, or return 0 to signal an error. Seperate
>
> s/seperate/separate
thanks.
>
> > these concerns in preparation for an instruction type that is not just
> > an unsigned int.  Fill the created instruction to a pointer passed as
> > the first parameter to the function and use a non-zero return value to
> > signify an error.
> >
> > Signed-off-by: Jordan Niethe 
> > ---
> > v5: New to series
> > ---
> >  arch/powerpc/include/asm/code-patching.h |  12 +-
> >  arch/powerpc/kernel/optprobes.c  |  24 ++--
> >  arch/powerpc/kernel/setup_32.c   |   2 +-
> >  arch/powerpc/kernel/trace/ftrace.c   |  24 ++--
> >  arch/powerpc/lib/code-patching.c | 133 +--
> >  arch/powerpc/lib/feature-fixups.c|   5 +-
> >  6 files changed, 117 insertions(+), 83 deletions(-)
> >
> > diff --git a/arch/powerpc/include/asm/code-patching.h
> > b/arch/powerpc/include/asm/code-patching.h
> > index 898b54262881..351dda7215b6 100644
> > --- a/arch/powerpc/include/asm/code-patching.h
> > +++ b/arch/powerpc/include/asm/code-patching.h
> > @@ -22,10 +22,10 @@
> >  #define BRANCH_ABSOLUTE  0x2
> >
> >  bool is_offset_in_branch_range(long offset);
> > -unsigned int create_branch(const unsigned int *addr,
> > -unsigned long target, int flags);
> > -unsigned int create_cond_branch(const unsigned int *addr,
> > - unsigned long target, int flags);
> > +int create_branch(unsigned int *instr, const unsigned int *addr,
> > +   unsigned long target, int flags);
> > +int create_cond_branch(unsigned int *instr, const unsigned int *addr,
> > +unsigned long target, int flags);
> >  int patch_branch(unsigned int *addr, unsigned long target, int flags);
> >  int patch_instruction(unsigned int *addr, unsigned int instr);
> >  int raw_patch_instruction(unsigned int *addr, unsigned int instr);
> > @@ -60,8 +60,8 @@ int instr_is_relative_branch(unsigned int instr);
> >  int instr_is_relative_link_branch(unsigned int instr);
> >  int instr_is_branch_to_addr(const unsigned int *instr, unsigned long addr);
> >  unsigned long branch_target(const unsigned int *instr);
> > -unsigned int translate_branch(const unsigned int *dest,
> > -   const unsigned int *src);
> > +int translate_branch(unsigned int *instr, const unsigned int *dest,
> > +  const unsigned int *src);
> >  extern bool is_conditional_branch(unsigned int instr);
> >  #ifdef CONFIG_PPC_BOOK3E_64
> >  void __patch_exception(int exc, unsigned long addr);
> > diff --git a/arch/powerpc/kernel/optprobes.c
> > b/arch/powerpc/kernel/optprobes.c
> > index 024f7aad1952..445b3dad82dc 100644
> > --- a/arch/powerpc/kernel/optprobes.c
> > +++ b/arch/powerpc/kernel/optprobes.c
> > @@ -251,15 +251,17 @@ int arch_prepare_optimized_kprobe(struct
> > optimized_kprobe *op, struct kprobe *p)
> >   goto error;
> >   }
> >
> > - branch_op_callback = create_branch((unsigned int *)buff +
> > TMPL_CALL_HDLR_IDX,
> > - (unsigned long)op_callback_addr,
> > - BRANCH_SET_LINK);
> > + rc = create_branch(_op_callback,
> > +(unsigned int *)buff + TMPL_CALL_HDLR_IDX,
> > +(unsigned long)op_callback_addr,
> > +BRANCH_SET_LINK);
> >
> > - branch_emulate_step = create_branch((unsigned int *)buff +
> > TMPL_EMULATE_IDX,
> > - (unsigned long)emulate_step_addr,
> > - BRANCH_SET_LINK);
> > + rc |= create_branch(_emulate_step,
> > + (unsigned int *)buff + TMPL_EMULATE_IDX,
> > + (unsigned long)emulate_step_addr,
> > + BRANCH_SET_LINK);
> >
> > - if (!branch_op_callback || !branch_emulate_step)
> > + if (rc)
> >   goto error;
> >
> >   patch_instruction(buff + TMPL_CALL_HDLR_IDX, branch_op_callback);
> > @@ -305,6 +307,7 @@ int arch_check_optimized_kprobe(struct optimized_kprobe
> > *op)
> >
> >  void arch_optimize_kprobes(struct list_head *oplist)
> >  {
> > + unsigned int 

Re: [PATCH v5 05/21] powerpc: Use a function for getting the instruction op code

[Jordan Niethe]

On Mon, Apr 6, 2020 at 6:22 PM Christophe Leroy  wrote:
>
>
>
> Le 06/04/2020 à 10:09, Jordan Niethe a écrit :
> > In preparation for using a data type for instructions that can not be
> > directly used with the '>>' operator use a function for getting the op
> > code of an instruction.
> >
> > Signed-off-by: Jordan Niethe 
> > ---
> > v4: New to series
> > ---
> >   arch/powerpc/include/asm/inst.h  | 5 +
> >   arch/powerpc/kernel/align.c  | 2 +-
> >   arch/powerpc/lib/code-patching.c | 4 ++--
>
> What about store_updates_sp() in mm/fault.c ?
True. An early revision of this series used analyse_instr() there,
which ended up causing issues. But it still can use the instruction
data type. I will change that.
>
> Christophe
>
> >   3 files changed, 8 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/powerpc/include/asm/inst.h 
> > b/arch/powerpc/include/asm/inst.h
> > index 5298ba33b6e5..93959016fe4b 100644
> > --- a/arch/powerpc/include/asm/inst.h
> > +++ b/arch/powerpc/include/asm/inst.h
> > @@ -8,4 +8,9 @@
> >
> >   #define ppc_inst(x) (x)
> >
> > +static inline int ppc_inst_opcode(u32 x)
> > +{
> > + return x >> 26;
> > +}
> > +
> >   #endif /* _ASM_INST_H */
> > diff --git a/arch/powerpc/kernel/align.c b/arch/powerpc/kernel/align.c
> > index 86e9bf62f18c..691013aa9f3c 100644
> > --- a/arch/powerpc/kernel/align.c
> > +++ b/arch/powerpc/kernel/align.c
> > @@ -314,7 +314,7 @@ int fix_alignment(struct pt_regs *regs)
> >   }
> >
> >   #ifdef CONFIG_SPE
> > - if ((instr >> 26) == 0x4) {
> > + if (ppc_inst_opcode(instr) == 0x4) {
> >   int reg = (instr >> 21) & 0x1f;
> >   PPC_WARN_ALIGNMENT(spe, regs);
> >   return emulate_spe(regs, reg, instr);
> > diff --git a/arch/powerpc/lib/code-patching.c 
> > b/arch/powerpc/lib/code-patching.c
> > index fdf0d6ea3575..099a515202aa 100644
> > --- a/arch/powerpc/lib/code-patching.c
> > +++ b/arch/powerpc/lib/code-patching.c
> > @@ -231,7 +231,7 @@ bool is_offset_in_branch_range(long offset)
> >*/
> >   bool is_conditional_branch(unsigned int instr)
> >   {
> > - unsigned int opcode = instr >> 26;
> > + unsigned int opcode = ppc_inst_opcode(instr);
> >
> >   if (opcode == 16)   /* bc, bca, bcl, bcla */
> >   return true;
> > @@ -289,7 +289,7 @@ int create_cond_branch(unsigned int *instr, const 
> > unsigned int *addr,
> >
> >   static unsigned int branch_opcode(unsigned int instr)
> >   {
> > - return (instr >> 26) & 0x3F;
> > + return ppc_inst_opcode(instr) & 0x3F;
> >   }
> >
> >   static int instr_is_branch_iform(unsigned int instr)
> >

Re: [PATCH v5 04/21] powerpc: Use a macro for creating instructions from u32s

[Jordan Niethe]

On Tue, Apr 7, 2020 at 4:40 PM Balamuruhan S  wrote:
>
> On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> > In preparation for instructions having a more complex data type start
> > using a macro, ppc_inst(), for making an instruction out of a u32.  A
> > macro is used so that instructions can be used as initializer elements.
> > Currently this does nothing, but it will allow for creating a data type
> > that can represent prefixed instructions.
> >
> > Signed-off-by: Jordan Niethe 
> > ---
> > v4: New to series
> > v5: - Rename PPC_INST() -> ppc_inst().
> > - Use on epapr_paravirt.c, kgdb.c
> > ---
> >  arch/powerpc/include/asm/code-patching.h |  3 +-
> >  arch/powerpc/include/asm/inst.h  | 11 +
> >  arch/powerpc/kernel/align.c  |  1 +
> >  arch/powerpc/kernel/epapr_paravirt.c |  5 ++-
> >  arch/powerpc/kernel/hw_breakpoint.c  |  3 +-
> >  arch/powerpc/kernel/jump_label.c |  3 +-
> >  arch/powerpc/kernel/kgdb.c   |  5 ++-
> >  arch/powerpc/kernel/kprobes.c|  5 ++-
> >  arch/powerpc/kernel/module_64.c  |  3 +-
> >  arch/powerpc/kernel/optprobes.c  | 31 ++---
> >  arch/powerpc/kernel/security.c   |  9 ++--
> >  arch/powerpc/kernel/trace/ftrace.c   | 25 ++-
> >  arch/powerpc/kernel/uprobes.c|  1 +
> >  arch/powerpc/kvm/emulate_loadstore.c |  2 +-
> >  arch/powerpc/lib/code-patching.c | 57 
> >  arch/powerpc/lib/feature-fixups.c| 39 
> >  arch/powerpc/lib/test_emulate_step.c | 39 
> >  arch/powerpc/xmon/xmon.c |  7 +--
> >  18 files changed, 138 insertions(+), 111 deletions(-)
> >  create mode 100644 arch/powerpc/include/asm/inst.h
> >
> > diff --git a/arch/powerpc/include/asm/code-patching.h
> > b/arch/powerpc/include/asm/code-patching.h
> > index 351dda7215b6..48e021957ee5 100644
> > --- a/arch/powerpc/include/asm/code-patching.h
> > +++ b/arch/powerpc/include/asm/code-patching.h
> > @@ -11,6 +11,7 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >
> >  /* Flags for create_branch:
> >   * "b"   == create_branch(addr, target, 0);
> > @@ -48,7 +49,7 @@ static inline int patch_branch_site(s32 *site, unsigned
> > long target, int flags)
> >  static inline int modify_instruction(unsigned int *addr, unsigned int clr,
> >unsigned int set)
> >  {
> > - return patch_instruction(addr, (*addr & ~clr) | set);
> > + return patch_instruction(addr, ppc_inst((*addr & ~clr) | set));
> >  }
> >
> >  static inline int modify_instruction_site(s32 *site, unsigned int clr,
> > unsigned int set)
> > diff --git a/arch/powerpc/include/asm/inst.h
> > b/arch/powerpc/include/asm/inst.h
> > new file mode 100644
> > index ..5298ba33b6e5
> > --- /dev/null
> > +++ b/arch/powerpc/include/asm/inst.h
> > @@ -0,0 +1,11 @@
> > +/* SPDX-License-Identifier: GPL-2.0-or-later */
> > +#ifndef _ASM_INST_H
> > +#define _ASM_INST_H
> > +
> > +/*
> > + * Instruction data type for POWER
> > + */
> > +
> > +#define ppc_inst(x) (x)
> > +
> > +#endif /* _ASM_INST_H */
> > diff --git a/arch/powerpc/kernel/align.c b/arch/powerpc/kernel/align.c
> > index 92045ed64976..86e9bf62f18c 100644
> > --- a/arch/powerpc/kernel/align.c
> > +++ b/arch/powerpc/kernel/align.c
> > @@ -24,6 +24,7 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >
> >  struct aligninfo {
> >   unsigned char len;
> > diff --git a/arch/powerpc/kernel/epapr_paravirt.c
> > b/arch/powerpc/kernel/epapr_paravirt.c
> > index 9d32158ce36f..c53e863fb484 100644
> > --- a/arch/powerpc/kernel/epapr_paravirt.c
> > +++ b/arch/powerpc/kernel/epapr_paravirt.c
> > @@ -11,6 +11,7 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >
> >  #if !defined(CONFIG_64BIT) || defined(CONFIG_PPC_BOOK3E_64)
> >  extern void epapr_ev_idle(void);
> > @@ -37,9 +38,9 @@ static int __init early_init_dt_scan_epapr(unsigned long
> > node,
> >
> >   for (i = 0; i < (len / 4); i++) {
> >   u32 inst = be32_to_cpu(insts[i]);
> > - patch_instruction(epapr_hypercall_start + i, inst);
> > + patch_instruction(epapr_hypercall_start + i, ppc_inst(inst));
> >  #if !defined(CONFIG_64BIT) || defined(CONFIG_