-off-by: Jordan Niethe
---
arch/powerpc/include/asm/reg.h | 3 +++
arch/powerpc/kernel/cpu_setup_power.S | 6 ++
arch/powerpc/kernel/dt_cpu_ftrs.c | 3 ++-
arch/powerpc/kvm/book3s_hv.c| 11 +++
arch/powerpc/kvm/book3s_hv_nested.c | 6 +++---
arch
ive-regs.h
Signed-off-by: Jordan Niethe
---
arch/powerpc/sysdev/xive/common.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/sysdev/xive/common.c
b/arch/powerpc/sysdev/xive/common.c
index 1cdb39575eae..083f657091d7 100644
--- a/arch/powerpc/sysdev/xive/common.c
On Wed, 2019-08-07 at 13:44 +1000, Sam Bobroff wrote:
> From: Oliver O'Halloran
>
> Preparation for removing pci_dn from the powernv EEH code. The only
> thing we really use pci_dn for is to get the bdfn of the device for
> config space accesses, so adding that information to eeh_dev reduces
> th
Commit 2874c5fd2842 ("treewide: Replace GPLv2 boilerplate/reference with
SPDX - rule 152") left an empty comment in machdep.h, as the boilerplate
was the only text in the comment. Remove the empty comment.
Signed-off-by: Jordan Niethe
---
arch/powerpc/include/asm/machdep.h | 3 -
On Tue, 2019-08-13 at 20:03 +1000, Paul Mackerras wrote:
> Escalation interrupts are interrupts sent to the host by the XIVE
> hardware when it has an interrupt to deliver to a guest VCPU but that
> VCPU is not running anywhere in the system. Hence we disable the
> escalation interrupt for the VCP
On Wed, 2019-08-14 at 17:47 +0200, Cédric Le Goater wrote:
> Currently, the xmon 'dx' command calls OPAL to dump the XIVE state in
> the OPAL logs and also outputs some of the fields of the internal
> XIVE
> structures in Linux. The OPAL calls can only be done on baremetal
> (PowerNV) and they cras
"KVM: PPC: Book3S PR: Don't include SPAPR TCE code on
non-pseries platforms")
Signed-off-by: Jordan Niethe
---
arch/powerpc/kvm/book3s_hv.c| 2 ++
arch/powerpc/kvm/book3s_hv_rmhandlers.S | 10 ++
2 files changed, 12 insertions(+)
diff --git a/arch/powerpc
In entry_64.S there are places that open code saving and restoring the
non-volatile registers. There are already macros for doing this so use
them.
Signed-off-by: Jordan Niethe
---
arch/powerpc/kernel/entry_64.S | 18 ++
1 file changed, 6 insertions(+), 12 deletions(-)
diff
The hsrr and n parameters are never used by the KVMTEST macro so remove
them.
Signed-off-by: Jordan Niethe
---
arch/powerpc/kernel/exceptions-64s.S | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S
b/arch/powerpc/kernel
The INT_KVM_HANDLER macro for system_reset is missing a comma so add it
to be consistent.
Signed-off-by: Jordan Niethe
---
arch/powerpc/kernel/exceptions-64s.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S
b/arch/powerpc/kernel
On Fri, Dec 13, 2019 at 2:19 AM Daniel Axtens wrote:
>
> KASAN support on Book3S is a bit tricky to get right:
>
> - It would be good to support inline instrumentation so as to be able to
>catch stack issues that cannot be caught with outline mode.
>
> - Inline instrumentation requires a fix
On Wed, Dec 18, 2019 at 7:23 PM Daniel Axtens wrote:
>
> Jordan Niethe writes:
>
> > Add the bit definition for exceptions caused by prefixed instructions.
> >
> > Signed-off-by: Jordan Niethe
> > ---
> > arch/powerpc/include/asm/reg.h | 1 +
> >
On Wed, Dec 18, 2019 at 7:35 PM Daniel Axtens wrote:
>
> Jordan Niethe writes:
>
> > Currently all instructions are a single word long. A future ISA version
> > will include prefixed instructions which have a double word length. The
> > functions used for analysing
On Thu, Dec 19, 2019 at 1:15 AM Daniel Axtens wrote:
>
> Jordan Niethe writes:
>
> > Currently all instructions are a single word long. A future ISA version
> > will include prefixed instructions which have a double word length. The
> > functions used for analysing
On Fri, Dec 20, 2019 at 4:17 PM Jordan Niethe wrote:
>
> On Thu, Dec 19, 2019 at 1:15 AM Daniel Axtens wrote:
> >
> > Jordan Niethe writes:
> >
> > > Currently all instructions are a single word long. A future ISA version
> > > will include prefixed in
On Mon, Jan 13, 2020 at 10:30 PM Balamuruhan S wrote:
>
> On Tue, Nov 26, 2019 at 04:21:38PM +1100, Jordan Niethe wrote:
> > Uprobes can execute instructions out of line. Increase the size of the
> > buffer used for this so that this works for prefixed instructions. Take
&g
On Mon, Jan 13, 2020 at 5:18 PM Balamuruhan S wrote:
>
> On Tue, Nov 26, 2019 at 04:21:28PM +1100, Jordan Niethe wrote:
> > Currently all instructions are a single word long. A future ISA version
> > will include prefixed instructions which have a double word length. The
>
On Fri, Jan 10, 2020 at 9:38 PM Balamuruhan S wrote:
>
> On Tue, Nov 26, 2019 at 04:21:29PM +1100, Jordan Niethe wrote:
> > This adds emulation support for the following prefixed integer
> > load/stores:
> > * Prefixed Load Byte and Zero (plbz)
> > * Prefixe
On Sat, Jan 11, 2020 at 2:13 AM Balamuruhan S wrote:
>
> On Tue, Nov 26, 2019 at 04:21:29PM +1100, Jordan Niethe wrote:
> > This adds emulation support for the following prefixed integer
> > load/stores:
> > * Prefixed Load Byte and Zero (plbz)
> > * Prefixe
On Fri, Feb 7, 2020 at 7:16 PM Greg Kurz wrote:
>
> On Thu, 19 Dec 2019 01:11:33 +1100
> Daniel Axtens wrote:
>
> > Jordan Niethe writes:
> >
> > > A user-mode access to an address a long way below the stack pointer is
> > > only valid if the inst
werpc: Enable Prefixed Instructions
Jordan Niethe (12):
powerpc: Define new SRR1 bits for a future ISA version
powerpc sstep: Prepare to support prefixed instructions
powerpc sstep: Add support for prefixed load/stores
powerpc sstep: Add support for prefixed fixed-point arithmetic
pow
From: Alistair Popple
Prefix instructions have their own FSCR bit which needs to enabled via
a CPU feature. The kernel will save the FSCR for problem state but it
needs to be enabled initially.
Signed-off-by: Alistair Popple
---
arch/powerpc/include/asm/reg.h| 3 +++
arch/powerpc/kernel/d
used to indicate that an ISI was due to the access being no-exec or
guarded. A future ISA version adds another purpose. It is also set if
there is an access in a cache-inhibited location for prefixed
instruction. Rename from SRR1_ISI_N_OR_G to SRR1_ISI_N_G_OR_CIP.
Signed-off-by: Jordan Niethe
emulated or
analysed - this is just making it possible to do so.
Signed-off-by: Jordan Niethe
---
v2: - Move definition of __get_user_instr() and
__get_user_instr_inatomic() to "powerpc: Support prefixed instructions
in alignment handler."
- Use a macro for returning the length of an op
-Precision (plxssp)
* Prefixed Load VSX Vector [0|1] (plxv, plxv0, plxv1)
* Prefixed Store VSX Scalar Doubleword (pstxsd)
* Prefixed Store VSX Scalar Single-Precision (pstxssp)
* Prefixed Store VSX Vector [0|1] (pstxv, pstxv0, pstxv1)
Signed-off-by: Jordan Niethe
---
v2: - Combine all load/store
This adds emulation support for the following prefixed Fixed-Point
Arithmetic instructions:
* Prefixed Add Immediate (paddi)
Signed-off-by: Jordan Niethe
---
arch/powerpc/lib/sstep.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
8.
Prefixed instructions are not permitted to cross 64-byte boundaries. If
they do the alignment interrupt is invoked with SRR1 BOUNDARY bit set.
If this occurs send a SIGBUS to the offending process if in user mode.
If in kernel mode call bad_page_fault().
Signed-off-by: Jordan Niethe
---
v2
n() within facility_unavailable_exception().
However, when caused by a prefixed instructions the SRR1 PREFIXED bit is
set. Prepare for dealing with emulated prefixed instructions by checking
for this bit.
Signed-off-by: Jordan Niethe
---
arch/powerpc/kernel/traps.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/ar
.
No support for disassembling prefixed instructions.
Signed-off-by: Jordan Niethe
---
v2: Rename sufx to suffix
---
arch/powerpc/xmon/xmon.c | 82 ++--
1 file changed, 71 insertions(+), 11 deletions(-)
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon
suffix is loaded too. Then print these in the form:
prefix:suffix
Xmon uses the disassembly routines from GNU binutils. These currently do
not support prefixed instructions so we will not disassemble the
prefixed instructions yet.
Signed-off-by: Jordan Niethe
---
v2: Rename sufx to suffix
.
Signed-off-by: Jordan Niethe
---
arch/powerpc/include/asm/kprobes.h | 5 +--
arch/powerpc/kernel/kprobes.c| 47 +---
arch/powerpc/kernel/optprobes.c | 32 ++-
arch/powerpc/kernel/optprobes_head.S | 6
4 files changed, 63 insertions
Uprobes can execute instructions out of line. Increase the size of the
buffer used for this so that this works for prefixed instructions. Take
into account the length of prefixed instructions when fixing up the nip.
Signed-off-by: Jordan Niethe
---
v2: - Fix typo
- Use macro for instruction
Currently when getting an instruction to emulate in
hw_breakpoint_handler() we do not load the suffix of a prefixed
instruction. Ensure we load the suffix if the instruction we need to
emulate is a prefixed instruction.
Signed-off-by: Jordan Niethe
---
v2: Rename sufx to suffix
---
arch/powerpc
mce_find_instr_ea_and_pfn analyses an instruction to determine the
effective address that caused the machine check. Update this to load and
pass the suffix to analyse_instr for prefixed instructions.
Signed-off-by: Jordan Niethe
---
v2: - Rename sufx to suffix
---
arch/powerpc/kernel
On Tue, Feb 11, 2020 at 4:57 PM Christophe Leroy
wrote:
>
>
>
> Le 11/02/2020 à 06:33, Jordan Niethe a écrit :
> > Currently all instructions are a single word long. A future ISA version
> > will include prefixed instructions which have a double word length. The
> >
On Tue, Feb 11, 2020 at 5:32 PM Christophe Leroy
wrote:
>
>
>
> Le 11/02/2020 à 06:33, Jordan Niethe a écrit :
> > A prefixed instruction is composed of a word prefix and a word suffix.
> > It does not make sense to be able to have a breakpoint on the suffix of
> > a
On Tue, Feb 11, 2020 at 5:39 PM Christophe Leroy
wrote:
>
>
>
> Le 11/02/2020 à 06:33, Jordan Niethe a écrit :
> > Currently when xmon is dumping instructions it reads a word at a time
> > and then prints that instruction (either as a hex number or by
> > d
On Tue, Feb 11, 2020 at 5:46 PM Christophe Leroy
wrote:
>
>
>
> Le 11/02/2020 à 06:33, Jordan Niethe a écrit :
> > A prefixed instruction is composed of a word prefix followed by a word
> > suffix. It does not make sense to be able to have a kprobe on the suffix
> >
On Tue, Feb 11, 2020 at 5:14 PM Christophe Leroy
wrote:
>
>
>
> Le 11/02/2020 à 06:33, Jordan Niethe a écrit :
> > Alignment interrupts can be caused by prefixed instructions accessing
> > memory. In the alignment handler the instruction that caused the
> > exc
On Tue, Feb 11, 2020 at 5:05 PM Christophe Leroy
wrote:
>
>
>
> Le 11/02/2020 à 06:33, Jordan Niethe a écrit :
> > This adds emulation support for the following prefixed integer
> > load/stores:
> >* Prefixed Load Byte and Zero (plbz)
> >* P
orted by Greg
Kurz did not work correctly.
Alistair Popple (1):
powerpc: Enable Prefixed Instructions
Jordan Niethe (13):
powerpc: Define new SRR1 bits for a future ISA version
powerpc sstep: Prepare to support prefixed instructions
powerpc sstep: Add support for prefixed load/stores
power
From: Alistair Popple
Prefix instructions have their own FSCR bit which needs to enabled via
a CPU feature. The kernel will save the FSCR for problem state but it
needs to be enabled initially.
Signed-off-by: Alistair Popple
---
arch/powerpc/include/asm/reg.h| 3 +++
arch/powerpc/kernel/d
used to indicate that an ISI was due to the access being no-exec or
guarded. A future ISA version adds another purpose. It is also set if
there is an access in a cache-inhibited location for prefixed
instruction. Rename from SRR1_ISI_N_OR_G to SRR1_ISI_N_G_OR_CIP.
Signed-off-by: Jordan Niethe
emulated or
analysed - this is just making it possible to do so.
Signed-off-by: Jordan Niethe
---
v2: - Move definition of __get_user_instr() and
__get_user_instr_inatomic() to "powerpc: Support prefixed instructions
in alignment handler."
- Use a macro for returning the length of an op
-Precision (plxssp)
* Prefixed Load VSX Vector [0|1] (plxv, plxv0, plxv1)
* Prefixed Store VSX Scalar Doubleword (pstxsd)
* Prefixed Store VSX Scalar Single-Precision (pstxssp)
* Prefixed Store VSX Vector [0|1] (pstxv, pstxv0, pstxv1)
Signed-off-by: Jordan Niethe
---
v2: - Combine all load/store
This adds emulation support for the following prefixed Fixed-Point
Arithmetic instructions:
* Prefixed Add Immediate (paddi)
Signed-off-by: Jordan Niethe
---
v3: Since we moved the prefixed loads/stores into the load/store switch
statement it no longer makes sense to have paddi in there, so
8.
Prefixed instructions are not permitted to cross 64-byte boundaries. If
they do the alignment interrupt is invoked with SRR1 BOUNDARY bit set.
If this occurs send a SIGBUS to the offending process if in user mode.
If in kernel mode call bad_page_fault().
Signed-off-by: Jordan Niethe
---
v2
n() within facility_unavailable_exception().
However, when caused by a prefixed instructions the SRR1 PREFIXED bit is
set. Prepare for dealing with emulated prefixed instructions by checking
for this bit.
Signed-off-by: Jordan Niethe
---
arch/powerpc/kernel/traps.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/ar
(). Otherwise replace store_inst() with patch_instruction().
Signed-off-by: Jordan Niethe
---
arch/powerpc/xmon/xmon.c | 13 ++---
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index 897e512c6379..a673cf55641c 100644
--- a/arch
.
No support for disassembling prefixed instructions.
Signed-off-by: Jordan Niethe
---
v2: Rename sufx to suffix
v3: - Just directly use PPC_INST_NOP
- Typo: plac -> place
- Rename read_inst() to mread_inst(). Do not have it call mread().
---
arch/powerpc/xmon/xmon.c |
suffix is loaded too. Then print these in the form:
prefix:suffix
Xmon uses the disassembly routines from GNU binutils. These currently do
not support prefixed instructions so we will not disassemble the
prefixed instructions yet.
Signed-off-by: Jordan Niethe
---
v2: Rename sufx to suffix
v3
.
Signed-off-by: Jordan Niethe
---
v3: - Base on top of https://patchwork.ozlabs.org/patch/1232619/
- Change printing format to %x:%x
---
arch/powerpc/include/asm/kprobes.h | 5 ++--
arch/powerpc/kernel/kprobes.c| 43 +---
arch/powerpc/kernel/optprobes.c
Uprobes can execute instructions out of line. Increase the size of the
buffer used for this so that this works for prefixed instructions. Take
into account the length of prefixed instructions when fixing up the nip.
Signed-off-by: Jordan Niethe
---
v2: - Fix typo
- Use macro for instruction
Currently when getting an instruction to emulate in
hw_breakpoint_handler() we do not load the suffix of a prefixed
instruction. Ensure we load the suffix if the instruction we need to
emulate is a prefixed instruction.
Signed-off-by: Jordan Niethe
---
v2: Rename sufx to suffix
v3: Add __user to
mce_find_instr_ea_and_pfn analyses an instruction to determine the
effective address that caused the machine check. Update this to load and
pass the suffix to analyse_instr for prefixed instructions.
Signed-off-by: Jordan Niethe
---
v2: - Rename sufx to suffix
---
arch/powerpc/kernel
. Prepare for dealing with emulated prefixed instructions by checking
> > for this bit.
> >
> > Signed-off-by: Jordan Niethe
>
> Oh you've got it here, I would just squash this together with the first
> patch.
Sure, I'll put them together. When you mentioned
cific to xmon. In some places patch_instruction() is already
> > being using followed by store_inst(). In these cases just remove the
> > store_inst(). Otherwise replace store_inst() with patch_instruction().
> >
> > Signed-off-by: Jordan Niethe
> > ---
> > a
t; Adding prefixed instructions complicates this as the bpt::instr[1] needs
> > to be used to hold the suffix. To deal with this make bpt::instr[] big
> > enough for three word instructions. bpt::instr[2] contains the trap,
> > and in the case of word instructions pad bpt::ins
On Wed, Feb 26, 2020 at 6:18 PM Nicholas Piggin wrote:
>
> Jordan Niethe's on February 26, 2020 2:07 pm:
> > @@ -136,11 +148,14 @@ int arch_prepare_kprobe(struct kprobe *p)
> > }
> >
> > if (!ret) {
> > - patch_instruction(p->ainsn.insn, *p->addr);
> > + patch_i
Fix by making sure r0 is 0 before storing it to kvmppc_vcore->in_guest.
Fixes: 13c7bb3c57dc ("powerpc/64s: Set reserved PCR bits")
Reported-by: Alexey Kardashevskiy
Signed-off-by: Jordan Niethe
---
arch/powerpc/kvm/book3s_hv_rmhandlers.S | 1 +
1 file changed, 1 insertion(+
v/20230905034658.82835-1-jniet...@gmail.com/
Jordan Niethe (10):
KVM: PPC: Always use the GPR accessors
KVM: PPC: Introduce FPR/VR accessor functions
KVM: PPC: Rename accessor generator macros
KVM: PPC: Use accessors for VCPU registers
KVM: PPC: Use accessors for VCORE registers
KVM: PPC: Boo
Always use the GPR accessor functions. This will be important later for
Nested APIv2 support which requires additional functionality for
accessing and modifying VCPU state.
Signed-off-by: Jordan Niethe
---
v4:
- Split into unique patch
---
arch/powerpc/kvm/book3s_64_vio.c | 4 ++--
arch
state.
Signed-off-by: Gautam Menghani
Signed-off-by: Jordan Niethe
---
v3:
- Guatam: Pass vector elements by reference
v4:
- Split into unique patch
---
arch/powerpc/include/asm/kvm_book3s.h | 55
arch/powerpc/include/asm/kvm_booke.h | 10
arch/powerpc/kvm/book3s.c
More "wrapper" style accessor generating macros will be introduced for
the nestedv2 guest support. Rename the existing macros with more
descriptive names now so there is a consistent naming convention.
Reviewed-by: Nicholas Piggin
Signed-off-by: Jordan Niethe
---
v3:
- New to
Introduce accessor generator macros for VCPU registers. Use the accessor
functions to replace direct accesses to this registers.
This will be important later for Nested APIv2 support which requires
additional functionality for accessing and modifying VCPU state.
Signed-off-by: Jordan Niethe
Introduce accessor generator macros for VCORE registers. Use the accessor
functions to replace direct accesses to this registers.
This will be important later for Nested APIv2 support which requires
additional functionality for accessing and modifying VCPU state.
Signed-off-by: Jordan Niethe
Introduce accessor generator macros for Book3S HV VCPU registers. Use
the accessor functions to replace direct accesses to this registers.
This will be important later for Nested APIv2 support which requires
additional functionality for accessing and modifying VCPU state.
Signed-off-by: Jordan
not currently present.
kvmppc_set_msr_hv() already exists, it is used for the
kvmppc_ops::set_msr callback.
Introduce a low level accessor __kvmppc_{s,g}et_msr_hv() that simply
gets and sets shregs::msr. This will be extend for Nested APIv2 support.
Signed-off-by: Jordan Niethe
---
v4:
- New
the value of elements and parsing buffers. This will be used
later by the nestedv2 guest support.
Signed-off-by: Jordan Niethe
---
v2:
- Add missing #ifdef CONFIG_VSXs
- Move files from lib/ to kvm/
- Guard compilation on CONFIG_KVM_BOOK3S_HV_POSSIBLE
- Use kunit for guest state buffer test
eries_rpt_invalidate() to
match that. Update the callers of pseries_rpt_invalidate() to also take
an unsigned long if they take an lpid value.
Signed-off-by: Jordan Niethe
---
v3:
- New to series
v4:
- Use u64
- Change format strings instead of casting
---
arch/powerpc/include/asm/k
d to be loaded again.
Tested-by: Sachin Sant
Signed-off-by: Vaibhav Jain
Signed-off-by: Gautam Menghani
Signed-off-by: Kautuk Consul
Signed-off-by: Amit Machhiwal
Signed-off-by: Jordan Niethe
---
v2:
- Declare op structs as static
- Guatam: Use expressions in switch case with local variables
From: Michael Neuling
Document support for nested KVM on POWER using the existing API as well
as the new PAPR API. This includes the new HCALL interface and how it
used by KVM.
Signed-off-by: Michael Neuling
Signed-off-by: Jordan Niethe
---
v2:
- Separated into individual patch
v3:
- Fix
On 26/6/23 5:04 pm, Mahesh Salgaonkar wrote:
opal_prd_msg_notifier extracts the opal prd message size from the message
header and uses it for allocating opal_prd_msg_queue_item that includes
the correct message size to be copied. However, while running under
CONFIG_FORTIFY_SOURCE=y, it trigger
On 8/6/23 10:34 pm, Kautuk Consul wrote:
Need at least a little context in the commit message itself:
"Enable ring-based dirty memory tracking on ppc64:"
- Enable CONFIG_HAVE_KVM_DIRTY_RING_ACQ_REL as ppc64 is weakly
ordered.
- Enable CONFIG_NEED_KVM_DIRTY_RING_WITH_BITMAP because the
powernv: Fix endian issues in OPAL ICS
backend") used a new variable 'oserver' as the parameter to
opal_get_xive() instead of 'server' for endian correctness. It also
removed 'server' from the error message for the call to opal_get_xive().
It was commit bf8e0
nuxppc-dev/20230508072332.2937883-1-...@linux.vnet.ibm.com/
- v2:
https://lore.kernel.org/linuxppc-dev/20230605064848.12319-1-...@linux.vnet.ibm.com/
Jordan Niethe (5):
KVM: PPC: Use getters and setters for vcpu register state
KVM: PPC: Rename accessor generator macros
KVM: PPC: Add helper library
ers. These wrappers will
be augmented for supporting Nestedv2 guests later.
Signed-off-by: Gautam Menghani
Signed-off-by: Jordan Niethe
---
v3:
- Do not add a helper for pvr
- Use an expression when declaring variable in case
- Squash in all getters and setters
- Guatam: Pass vector re
More "wrapper" style accessor generating macros will be introduced for
the nestedv2 guest support. Rename the existing macros with more
descriptive names now so there is a consistent naming convention.
Signed-off-by: Jordan Niethe
---
v3:
- New to series
---
arch/powerpc/include/asm
the value of elements and parsing buffers. This will be used
later by the nestedv2 guest support.
Signed-off-by: Jordan Niethe
---
v2:
- Add missing #ifdef CONFIG_VSXs
- Move files from lib/ to kvm/
- Guard compilation on CONFIG_KVM_BOOK3S_HV_POSSIBLE
- Use kunit for guest state buffer test
eries_rpt_invalidate() to
match that. Update the callers of pseries_rpt_invalidate() to also take
an unsigned long if they take an lpid value.
Signed-off-by: Jordan Niethe
---
v3:
- New to series
---
arch/powerpc/include/asm/kvm_book3s.h | 10 +-
arch/powerpc/include/asm/kvm_book3s
d to be loaded again.
Signed-off-by: Vaibhav Jain
Signed-off-by: Gautam Menghani
Signed-off-by: Kautuk Consul
Signed-off-by: Amit Machhiwal
Signed-off-by: Jordan Niethe
---
v2:
- Declare op structs as static
- Guatam: Use expressions in switch case with local variables
- Do not use the PVR fo
From: Michael Neuling
Document support for nested KVM on POWER using the existing API as well
as the new PAPR API. This includes the new HCALL interface and how it
used by KVM.
Signed-off-by: Michael Neuling
Signed-off-by: Jordan Niethe
---
v2:
- Separated into individual patch
v3:
- Fix
On 14/8/23 6:08 pm, Nicholas Piggin wrote:
On Mon Aug 7, 2023 at 11:45 AM AEST, Jordan Niethe wrote:
There are already some getter and setter functions used for accessing
vcpu register state, e.g. kvmppc_get_pc(). There are also more
complicated examples that are generated by macros like
On 14/8/23 6:12 pm, Nicholas Piggin wrote:
On Mon Aug 7, 2023 at 11:45 AM AEST, Jordan Niethe wrote:
The LPID register is 32 bits long. The host keeps the lpids for each
guest in an unsigned word struct kvm_arch. Currently, LPIDs are already
limited by mmu_lpid_bits and
On 14/8/23 6:15 pm, David Laight wrote:
From: Jordan Niethe
Sent: 07 August 2023 02:46
The LPID register is 32 bits long. The host keeps the lpids for each
guest in an unsigned word struct kvm_arch. Currently, LPIDs are already
limited by mmu_lpid_bits and KVM_MAX_NESTED_GUESTS_SHIFT.
The
On 14/8/23 6:27 pm, Nicholas Piggin wrote:
On Mon Aug 7, 2023 at 11:45 AM AEST, Jordan Niethe wrote:
More "wrapper" style accessor generating macros will be introduced for
the nestedv2 guest support. Rename the existing macros with more
descriptive names now so there is a consist
On 15/8/23 8:45 pm, Michael Ellerman wrote:
"Nicholas Piggin" writes:
On Mon Aug 7, 2023 at 11:45 AM AEST, Jordan Niethe wrote:
The LPID register is 32 bits long. The host keeps the lpids for each
guest in an unsigned word struct kvm_arch. Currently, LPIDs are already
tps://lore.kernel.org/linuxppc-dev/20230807014553.1168699-1-jniet...@gmail.com/
Jordan Niethe (10):
KVM: PPC: Always use the GPR accessors
KVM: PPC: Introduce FPR/VR accessor functions
KVM: PPC: Rename accessor generator macros
KVM: PPC: Use accessors for VCPU registers
KVM: PPC: Use a
Always use the GPR accessor functions. This will be important later for
Nested APIv2 support which requires additional functionality for
accessing and modifying VCPU state.
Signed-off-by: Jordan Niethe
---
v4:
- Split into unique patch
---
arch/powerpc/kvm/book3s_64_vio.c | 4 ++--
arch
state.
Signed-off-by: Jordan Niethe
---
v4:
- Split into unique patch
---
arch/powerpc/include/asm/kvm_book3s.h | 55
arch/powerpc/include/asm/kvm_booke.h | 10
arch/powerpc/kvm/book3s.c | 16 +++---
arch/powerpc/kvm/emulate_loadstore.c | 2 +-
arch/powerpc
More "wrapper" style accessor generating macros will be introduced for
the nestedv2 guest support. Rename the existing macros with more
descriptive names now so there is a consistent naming convention.
Reviewed-by: Nicholas Piggin
Signed-off-by: Jordan Niethe
---
v3:
- New to
Introduce accessor generator macros for VCPU registers. Use the accessor
functions to replace direct accesses to this registers.
This will be important later for Nested APIv2 support which requires
additional functionality for accessing and modifying VCPU state.
Signed-off-by: Jordan Niethe
Introduce accessor generator macros for VCORE registers. Use the accessor
functions to replace direct accesses to this registers.
This will be important later for Nested APIv2 support which requires
additional functionality for accessing and modifying VCPU state.
Signed-off-by: Jordan Niethe
Introduce accessor generator macros for Book3S HV VCPU registers. Use
the accessor functions to replace direct accesses to this registers.
This will be important later for Nested APIv2 support which requires
additional functionality for accessing and modifying VCPU state.
Signed-off-by: Jordan
not currently present.
kvmppc_set_msr_hv() already exists, it is used for the
kvmppc_ops::set_msr callback.
Introduce a low level accessor __kvmppc_{s,g}et_msr_hv() that simply
gets and sets shregs::msr. This will be extend for Nested APIv2 support.
Signed-off-by: Jordan Niethe
---
v4:
- New
the value of elements and parsing buffers. This will be used
later by the nestedv2 guest support.
Signed-off-by: Jordan Niethe
---
v2:
- Add missing #ifdef CONFIG_VSXs
- Move files from lib/ to kvm/
- Guard compilation on CONFIG_KVM_BOOK3S_HV_POSSIBLE
- Use kunit for guest state buffer test
eries_rpt_invalidate() to
match that. Update the callers of pseries_rpt_invalidate() to also take
an unsigned long if they take an lpid value.
Signed-off-by: Jordan Niethe
---
v3:
- New to series
v4:
- Use u64
- Change format strings instead of casting
---
arch/powerpc/include/asm/k
d to be loaded again.
Signed-off-by: Vaibhav Jain
Signed-off-by: Gautam Menghani
Signed-off-by: Kautuk Consul
Signed-off-by: Amit Machhiwal
Signed-off-by: Jordan Niethe
---
v2:
- Declare op structs as static
- Guatam: Use expressions in switch case with local variables
- Do not use the PVR fo
From: Michael Neuling
Document support for nested KVM on POWER using the existing API as well
as the new PAPR API. This includes the new HCALL interface and how it
used by KVM.
Signed-off-by: Michael Neuling
Signed-off-by: Jordan Niethe
---
v2:
- Separated into individual patch
v3:
- Fix
, Shivaprasad
Bhat, Harsh Prateek Bora, Paul Mackerras and Nicholas Piggin.
Jordan Niethe (5):
KVM: PPC: Use getters and setters for vcpu register state
KVM: PPC: Add fpr getters and setters
KVM: PPC: Add vr getters and setters
powerpc: Add helper library for Guest State Buffers
KVM: PPC: Add
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