[PATCH v2 21/33] KVM: PPC: Book3S HV: Handle hypercalls correctly when nested

, then the virtual-mode handlers assume that they are being called only to finish up the operation. Therefore we turn off the real-mode flag in the XICS code when running as a nested hypervisor. Reviewed-by: David Gibson Signed-off-by: Paul Mackerras --- arch/powerpc/include/asm/asm-prototypes.h

[PATCH v2 20/33] KVM: PPC: Book3S HV: Use XICS hypercalls when running as a nested hypervisor

This adds code to call the H_IPI and H_EOI hypercalls when we are running as a nested hypervisor (i.e. without the CPU_FTR_HVMODE cpu feature) and we would otherwise access the XICS interrupt controller directly or via an OPAL call. Signed-off-by: Paul Mackerras --- arch/powerpc/kvm/book3s_hv.c

[PATCH v2 19/33] KVM: PPC: Book3S HV: Nested guest entry via hypercall

. If they are of different endianness, the version number check will fail and the hcall will be rejected. Nested hypervisors do not support indep_threads_mode=N, so this adds code to print a warning message if the administrator has set indep_threads_mode=N, and treat it as Y. Signed-off-by: Paul Mackerras --- arch

[PATCH v2 18/33] KVM: PPC: Book3S HV: Framework and hcall stubs for nested virtualization

(or later) processor. Signed-off-by: Paul Mackerras --- arch/powerpc/include/asm/hvcall.h | 5 + arch/powerpc/include/asm/kvm_book3s.h | 10 +- arch/powerpc/include/asm/kvm_book3s_64.h | 33 arch/powerpc/include/asm/kvm_book3s_asm.h | 3 + arch/powerpc/include/asm/kvm_host.h

[PATCH v2 17/33] KVM: PPC: Book3S HV: Use kvmppc_unmap_pte() in kvm_unmap_radix()

kvmppc_unmap_pte() does a sequence of operations that are open-coded in kvm_unmap_radix(). This extends kvmppc_unmap_pte() a little so that it can be used by kvm_unmap_radix(), and makes kvm_unmap_radix() call it. Reviewed-by: David Gibson Signed-off-by: Paul Mackerras --- arch/powerpc/kvm

[PATCH v2 16/33] KVM: PPC: Book3S HV: Refactor radix page fault handler

for any pgtable, not specific to the one for this guest. [pau...@ozlabs.org - reduced diffs from previous code] Reviewed-by: David Gibson Signed-off-by: Suraj Jitindar Singh Signed-off-by: Paul Mackerras --- arch/powerpc/kvm/book3s_64_mmu_radix.c | 210 +++-- 1 file

[PATCH v2 14/33] KVM: PPC: Book3S HV: Clear partition table entry on vm teardown

as a nested hypervisor the real hypervisor could use this to determine when it can free resources. Reviewed-by: David Gibson Signed-off-by: Suraj Jitindar Singh Signed-off-by: Paul Mackerras --- arch/powerpc/kvm/book3s_hv.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git

[PATCH v2 15/33] KVM: PPC: Book3S HV: Make kvmppc_mmu_radix_xlate process/partition table agnostic

through the process tables or a guest real address through the partition tables. [pau...@ozlabs.org - reduced diffs from previous code] Reviewed-by: David Gibson Signed-off-by: Suraj Jitindar Singh Signed-off-by: Paul Mackerras --- arch/powerpc/include/asm/kvm_book3s.h | 3 + arch/powerpc/kvm

[PATCH v2 13/33] KVM: PPC: Use ccr field in pt_regs struct embedded in vcpu struct

. This changes the code to use the regs.ccr field instead of cr, and changes the assembly code on 64-bit platforms to use 64-bit loads and stores instead of 32-bit ones. Reviewed-by: David Gibson Signed-off-by: Paul Mackerras --- arch/powerpc/include/asm/kvm_book3s.h| 4 ++-- arch/powerpc/include/asm

[PATCH v2 12/33] powerpc: Turn off CPU_FTR_P9_TM_HV_ASSIST in non-hypervisor mode

are not in hypervisor mode, along with the CPU_FTR_HVMODE bit. Doing this will not change anything at this stage because the only code that tests CPU_FTR_P9_TM_HV_ASSIST is in HV KVM, which currently can only be used when when CPU_FTR_HVMODE is set. Reviewed-by: David Gibson Signed-off-by: Paul

[PATCH v2 11/33] powerpc: Add LPCR_EVIRT define

From: Suraj Jitindar Singh Add definition of the LPCR EVIRT (enhanced virtualisation) bit. Reviewed-by: David Gibson Signed-off-by: Suraj Jitindar Singh Signed-off-by: Paul Mackerras --- arch/powerpc/include/asm/reg.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/powerpc/include

[PATCH v2 10/33] KVM: PPC: Book3S HV: Add a debugfs file to dump radix mappings

. Reviewed-by: David Gibson Signed-off-by: Paul Mackerras --- arch/powerpc/include/asm/kvm_book3s_64.h | 1 + arch/powerpc/include/asm/kvm_host.h | 1 + arch/powerpc/kvm/book3s_64_mmu_radix.c | 179 +++ arch/powerpc/kvm/book3s_hv.c | 2 + 4 files

[PATCH v2 09/33] KVM: PPC: Book3S HV: Handle hypervisor instruction faults better

Reviewed-by: David Gibson Signed-off-by: Paul Mackerras --- arch/powerpc/include/asm/reg.h | 1 + arch/powerpc/kvm/book3s_hv.c | 5 - 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index e5b314e..6fda746 100644

[PATCH v2 08/33] KVM: PPC: Book3S HV: Streamlined guest entry/exit path on P9 for radix guests

Signed-off-by: Paul Mackerras --- arch/powerpc/include/asm/asm-prototypes.h | 2 + arch/powerpc/include/asm/kvm_ppc.h| 2 + arch/powerpc/kvm/book3s_hv.c | 425 +- arch/powerpc/kvm/book3s_hv_ras.c | 2 + arch/powerpc/kvm

[PATCH v2 07/33] KVM: PPC: Book3S HV: Call kvmppc_handle_exit_hv() with vcore unlocked

ngs for following patches, let's drop the vcore lock in the for_each_runnable_thread loop, so kvmppc_handle_exit_hv() gets called without the vcore lock held. Reviewed-by: David Gibson Signed-off-by: Paul Mackerras --- arch/powerpc/kvm/book3s_hv.c | 19 ++- 1 file changed, 10 inserti

[PATCH v2 06/33] KVM: PPC: Book3S: Rework TM save/restore code and make it C-callable

the code to be simplified quite a bit. _kvmppc_save_tm_pr and _kvmppc_restore_tm_pr become much simpler with this change, since they now only need to save and restore TAR and pass 1 for the 3rd argument to __kvmppc_{save,restore}_tm. Signed-off-by: Paul Mackerras --- arch/powerpc/include/asm/asm

[PATCH v2 05/33] KVM: PPC: Book3S HV: Simplify real-mode interrupt handling

he machine check and HMI real-mode handling is moved before that label. Also, the code to handle external interrupts is moved out of line, as is the code that calls kvmppc_realmode_hmi_handler(). Signed-off-by: Paul Mackerras --- arch/powerpc/kvm/book3s_hv_ras.c| 8 ++ arch/p

[PATCH v2 04/33] KVM: PPC: Book3S HV: Extract PMU save/restore operations as C-callable functions

This pulls out the assembler code that is responsible for saving and restoring the PMU state for the host and guest into separate functions so they can be used from an alternate entry path. The calling convention is made compatible with C. Reviewed-by: David Gibson Signed-off-by: Paul Mackerras

[PATCH v2 01/33] KVM: PPC: Book3S: Simplify external interrupt handling

wed-by: David Gibson Signed-off-by: Paul Mackerras --- arch/powerpc/include/asm/kvm_asm.h | 4 +-- arch/powerpc/include/asm/kvm_host.h| 1 + arch/powerpc/kvm/book3s.c | 43 -- arch/powerpc/kvm/book3s_hv_rm_xics.c |

[PATCH v2 02/33] KVM: PPC: Book3S HV: Remove left-over code in XICS-on-XIVE emulation

ing flag instead for this purpose. Therefore there is no need to do anything with the pending_exceptions bitmap. Signed-off-by: Paul Mackerras --- arch/powerpc/kvm/book3s_xive_template.c | 8 1 file changed, 8 deletions(-) diff --git a/arch/powerpc/kvm/book3s_xive_template.c b/arch/powe

[PATCH v2 00/33] KVM: PPC: Book3S HV: Nested HV virtualization

This patch series implements nested virtualization in the KVM-HV module for radix guests on POWER9 systems. Unlike PR KVM, nested guests are able to run in supervisor mode, meaning that performance is much better than with PR KVM, and is very close to the performance of a non-nested guests for

[PATCH v2 03/33] KVM: PPC: Book3S HV: Move interrupt delivery on guest entry to C code

. The algorithm expressed in the C code is almost identical to the previous algorithm. Reviewed-by: David Gibson Signed-off-by: Paul Mackerras --- arch/powerpc/include/asm/kvm_ppc.h | 1 + arch/powerpc/kvm/book3s_hv.c| 3 +- arch/powerpc/kvm/book3s_hv_builtin.c| 48

Re: [PATCH] KVM: PPC: Book3S HV: Don't use compound_order to determine host mapping size

On Tue, Sep 04, 2018 at 06:16:01PM +1000, Nicholas Piggin wrote: > THP paths can defer splitting compound pages until after the actual > remap and TLB flushes to split a huge PMD/PUD. This causes radix > partition scope page table mappings to get out of synch with the host > qemu page table

Re: [PATCH] powerpc: Avoid code patching freed init sections

On Mon, Sep 10, 2018 at 08:05:38PM +1000, Michael Neuling wrote: > > > > + /* Make sure we aren't patching a freed init section */ > > > + if (in_init_section(patch_addr) && init_freed()) > > > + return 0; > > > + > > > > Do we even need the init_freed() check? > > Maybe not. If

Re: [PATCH 3/6] powerpc sstep: Add cnttzw, cnttzd instruction emulation

On Tue, Sep 04, 2018 at 04:12:07PM -0500, Segher Boessenkool wrote: > On Mon, Sep 03, 2018 at 08:49:35PM +0530, Sandipan Das wrote: > > + case 538: /* cnttzw */ > > + if (!cpu_has_feature(CPU_FTR_ARCH_300)) > > + return -1; > > +

Re: [PATCH kernel] KVM: PPC: Avoid mapping compound pages to TCEs in real mode

On Mon, Sep 03, 2018 at 01:28:44PM +1000, David Gibson wrote: > On Fri, Aug 31, 2018 at 04:08:50PM +1000, Alexey Kardashevskiy wrote: > > At the moment the real mode handler of H_PUT_TCE calls iommu_tce_xchg_rm() > > which in turn reads the old TCE and if it was a valid entry - marks > > the

[PATCH] KVM: PPC: Book3S: Fix guest DMA when guest partially backed by THP pages

n dereferenced because that seems safer, and adds a check to avoid doing the find_linux_pte() call once mem->pageshift has been reduced to PAGE_SHIFT, as an optimization. Cc: sta...@vger.kernel.org # v4.12+ Fixes: 76fa4975f3ed ("KVM: PPC: Check if IOMMU page is contained in the pinned physical page&q

[PATCH v3 0/4] powerpc/64: copy_tofrom_user exception handling improvements

This is a repost of a series that I posted back in 2016 but which was never applied. It aims to make the exception handling code in __copy_tofrom_user_base clearer and easier to verify, and strengthens the selftests for the user copy code to test all the paths and to test the exception handling.

[PATCH v3 4/4] powerpc/64: Copy as much as possible in __copy_tofrom_user

, the code has been written to be compact rather than as fast as possible. Signed-off-by: Paul Mackerras --- arch/powerpc/lib/copyuser_64.S | 29 +++-- 1 file changed, 23 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/lib/copyuser_64.S b/arch/powerpc/lib/copyuser_64.S

[PATCH v3 1/4] powerpc/64: Make exception table clearer in __copy_tofrom_user_base

o per load or store. These loads and stores all use exactly the same exception handler, which simply resets the argument registers r3, r4 and r5 to there original values and re-does the whole copy using the slower loop. Signed-off-by: Paul Mackerras --- arch/powerpc/lib/copyuser_

[PATCH v3 3/4] selftests/powerpc/64: Test exception cases in copy_tofrom_user

, and that is reflected in failures in these tests. Based on a test program from Anton Blanchard. [pau...@ozlabs.org - test all three paths, wrote commit description, made EX_TABLE create an exception table.] Signed-off-by: Paul Mackerras --- .../testing/selftests/powerpc/copyloops/.gitignore

[PATCH v3 2/4] selftests/powerpc/64: Test all paths through copy routines

, and makes 2 or 3 versions of each test, each using a different code path, so as to cover all the possible paths. Signed-off-by: Paul Mackerras --- arch/powerpc/lib/copyuser_64.S | 7 + arch/powerpc/lib/copyuser_power7.S | 21 ++--- arch/powerpc/lib

[PATCH 1/2] KVM: PPC: Book3S HV: Allow creating max number of VCPUs on POWER9

configured in, so that a full complement of KVM_MAX_VCPUS VCPUs can be created on POWER9 in all guest SMT modes and emulated hardware SMT modes. Signed-off-by: Paul Mackerras --- This and the next patch apply on my kvm-ppc-next branch, which includes Sam Bobroff's patch "KVM: PPC: Book3S HV:

[PATCH 2/2] KVM: PPC: Book3S HV: Read kvm->arch.emul_smt_mode under kvm->lock

s created. Hence it is (theoretically) possible for the check in kvmppc_core_vcpu_create_hv() to race with another userspace thread changing kvm->arch.emul_smt_mode. This fixes it by moving the test that uses kvm->arch.emul_smt_mode into the block where kvm->lock is held. Signed-off-by: Paul Mackerr

Re: [PATCH v4 1/1] KVM: PPC: Book3S HV: pack VCORE IDs to access full VCPU ID space

On Wed, Jul 25, 2018 at 04:12:02PM +1000, Sam Bobroff wrote: > From: Sam Bobroff > > It is not currently possible to create the full number of possible > VCPUs (KVM_MAX_VCPUS) on Power9 with KVM-HV when the guest uses less > threads per core than it's core stride (or "VSMT mode"). This is >

Re: [PATCH v4 1/1] KVM: PPC: Book3S HV: pack VCORE IDs to access full VCPU ID space

On Wed, Jul 25, 2018 at 04:12:02PM +1000, Sam Bobroff wrote: > From: Sam Bobroff > > It is not currently possible to create the full number of possible > VCPUs (KVM_MAX_VCPUS) on Power9 with KVM-HV when the guest uses less > threads per core than it's core stride (or "VSMT mode"). This is >

Re: [PATCH v3 1/1] KVM: PPC: Book3S HV: pack VCORE IDs to access full VCPU ID space

On Thu, Jul 19, 2018 at 12:25:10PM +1000, Sam Bobroff wrote: > From: Sam Bobroff > > It is not currently possible to create the full number of possible > VCPUs (KVM_MAX_VCPUS) on Power9 with KVM-HV when the guest uses less > threads per core than it's core stride (or "VSMT mode"). This is >

Re: [kernel,v7,1/2] vfio/spapr: Use IOMMU pageshift rather than pagesize

On Thu, Jul 19, 2018 at 04:06:10PM +1000, Michael Ellerman wrote: > On Tue, 2018-07-17 at 07:19:12 UTC, Alexey Kardashevskiy wrote: > > The size is always equal to 1 page so let's use this. Later on this will > > be used for other checks which use page shifts to check the granularity > > of

Re: [PATCH] KVM: PPC: Book3S HV: fix constant size warning

On Sat, Jul 07, 2018 at 11:07:25AM +0200, Nicholas Mc Guire wrote: > The constants are 64bit but not explicitly declared UL resulting > in sparse warnings. Fixed by declaring the constants UL. > > Signed-off-by: Nicholas Mc Guire Thanks, patch applied to my kvm-ppc-next branch. Paul.

Re: [PATCH] KVM: PPC: Book3S HV: add of_node_put() in success path

On Sat, Jul 07, 2018 at 08:53:07AM +0200, Nicholas Mc Guire wrote: > The call to of_find_compatible_node() is returning a pointer with > incremented refcount so it must be explicitly decremented after the > last use. As here it is only being used for checking of node presence > but the result is

Re: [PATCH v2] KVM: PPC: remove mmio_vsx_tx_sx_enabled in KVM MMIO emulation

On Mon, May 28, 2018 at 09:48:26AM +0800, wei.guo.si...@gmail.com wrote: > From: Simon Guo > > Originally PPC KVM MMIO emulation uses only 0~31#(5 bits) for VSR > reg number, and use mmio_vsx_tx_sx_enabled field together for > 0~63# VSR regs. > > Currently PPC KVM MMIO emulation is

Re: [PATCH kernel] KVM: PPC: Fix hardware and emulated TCE tables matching

On Wed, Jun 20, 2018 at 06:42:58PM +1000, Alexey Kardashevskiy wrote: > When attaching a hardware table to LIOBN in KVM, we match table parameters > such as page size, table offset and table size. However the tables are > created via very different paths - VFIO and KVM - and the VFIO path goes >

Re: [PATCH kernel v7 0/2] KVM: PPC: Check if IOMMU page is contained in the pinned physical page

On Tue, Jul 17, 2018 at 05:19:11PM +1000, Alexey Kardashevskiy wrote: > This is to improve page boundaries checking and should probably > be cc:stable. I came accross this while debugging nvlink2 passthrough > but the lack of checking might be exploited by the existing userspace. > > The

Re: [PATCH kernel] KVM: PPC: Expose userspace mm context id via debugfs

On Thu, Jul 12, 2018 at 05:30:26PM +1000, Alexey Kardashevskiy wrote: > This adds a debugfs entry with mm context id of a process which is using > KVM. This id is an index in the process table so the userspace can dump > that tree provided it is granted access to /dev/mem. Is the main intention

Re: [PATCH kernel v3 3/6] KVM: PPC: Make iommu_table::it_userspace big endian

exey Kardashevskiy Acked-by: Paul Mackerras

Re: [PATCH v4 04/29] KVM: PPC: Book3S PR: Move kvmppc_save_tm/kvmppc_restore_tm to separate file

On Wed, May 23, 2018 at 03:01:47PM +0800, wei.guo.si...@gmail.com wrote: > From: Simon Guo > > It is a simple patch just for moving kvmppc_save_tm/kvmppc_restore_tm() > functionalities to tm.S. There is no logic change. The reconstruct of > those APIs will be done in later patches to improve

Re: [PATCH v3 24/29] KVM: PPC: Book3S PR: Support TAR handling for PR KVM HTM.

On Mon, May 21, 2018 at 12:09:41PM +0800, wei.guo.si...@gmail.com wrote: > From: Simon Guo > > Currently guest kernel doesn't handle TAR fac unavailable and it always > runs with TAR bit on. PR KVM will lazily enable TAR. TAR is not a > frequent-use reg and it is not

Re: [PATCH v3 5/7] KVM: PPC: reimplements LOAD_VSX/STORE_VSX instruction mmio emulation with analyse_intr() input

On Mon, May 21, 2018 at 01:24:24PM +0800, wei.guo.si...@gmail.com wrote: > From: Simon Guo > > This patch reimplements LOAD_VSX/STORE_VSX instruction MMIO emulation with > analyse_intr() input. It utilizes VSX_FPCONV/VSX_SPLAT/SIGNEXT exported > by analyse_instr() and

Re: [PATCH v2 00/10] KVM: PPC: reimplement mmio emulation with analyse_instr()

On Mon, May 07, 2018 at 02:20:06PM +0800, wei.guo.si...@gmail.com wrote: > From: Simon Guo > > We already have analyse_instr() which analyzes instructions for the > instruction > type, size, addtional flags, etc. What kvmppc_emulate_loadstore() did is > somehow >

Re: [PATCH 2/2] KVM: PPC: Book3S HV: lockless tlbie for HPT hcalls

On Mon, May 14, 2018 at 02:04:10PM +1000, Michael Ellerman wrote: [snip] > OK good, in commit: > > c17b98cf6028 ("KVM: PPC: Book3S HV: Remove code for PPC970 processors") (Dec > 2014) > > So we should be able to do the patch below. > > cheers > > > diff --git

Re: [PATCH v2 00/10] KVM: PPC: reimplement mmio emulation with analyse_instr()

On Mon, May 07, 2018 at 02:20:06PM +0800, wei.guo.si...@gmail.com wrote: > From: Simon Guo > > We already have analyse_instr() which analyzes instructions for the > instruction > type, size, addtional flags, etc. What kvmppc_emulate_loadstore() did is > somehow >

Re: [PATCH v2 07/10] KVM: PPC: reimplement LOAD_FP/STORE_FP instruction mmio emulation with analyse_intr() input

by > analyse_instr() and invokes kvmppc_handle_load(s)/kvmppc_handle_store() > accordingly. > > For FP store MMIO emulation, the FP regs need to be flushed firstly so > that the right FP reg vals can be read from vcpu->arch.fpr, which will > be stored into MMIO data. > > Su

Re: [PATCH v2 05/10] KVM: PPC: reimplement non-SIMD LOAD/STORE instruction mmio emulation with analyse_intr() input

; properties exported by analyse_instr() and invokes > kvmppc_handle_load(s)/kvmppc_handle_store() accordingly. > > It also move CACHEOP type handling into the skeleton. > > instruction_type within kvm_ppc.h is renamed to avoid conflict with > sstep.h. > > Suggested-by: Paul Mackerras &

Re: [PATCH] Revert "powerpc/64: Fix checksum folding in csum_add()"

c 80 22 14 add r4,r0,r4 > 24c: 78 83 00 20 clrldi r3,r4,32 > 250: 4e 80 00 20 blr > > Fixes: 6ad966d7303b7 ("powerpc/64: Fix checksum folding in csum_add()") > Signed-off-by: Christophe Leroy <christophe.le...@c-s.fr> Seems I was right first time... :) Acked-by: Paul Mackerras <pau...@ozlabs.org>

Re: [PATCH v2] powerpc: kvm: Change return type to vm_fault_t

On Wed, May 16, 2018 at 10:11:11AM +0530, Souptick Joarder wrote: > On Thu, May 10, 2018 at 11:57 PM, Souptick Joarder > wrote: > > Use new return type vm_fault_t for fault handler > > in struct vm_operations_struct. For now, this is > > just documenting that the function

Re: [PATCH v2 07/30] KVM: PPC: Book3S PR: add C function wrapper for _kvmppc_save/restore_tm()

On Wed, Feb 28, 2018 at 01:37:14AM +0800, wei.guo.si...@gmail.com wrote: > From: Simon Guo > > Currently _kvmppc_save/restore_tm() APIs can only be invoked from > assembly function. This patch adds C function wrappers for them so > that they can be safely called from C

Re: [PATCH v2 29/30] KVM: PPC: add KVM_SET_ONE_REG/KVM_GET_ONE_REG to async ioctl

On Wed, Feb 28, 2018 at 01:52:37AM +0800, wei.guo.si...@gmail.com wrote: > From: Simon Guo > > In both HV/PR KVM, the KVM_SET_ONE_REG/KVM_GET_ONE_REG ioctl should > be able to perform without load vcpu. This patch adds > KVM_SET_ONE_REG/KVM_GET_ONE_REG implementation to

Re: [PATCH v2 00/30] KVM: PPC: Book3S PR: Transaction memory support on PR KVM

On Wed, Feb 28, 2018 at 01:37:07AM +0800, wei.guo.si...@gmail.com wrote: > From: Simon Guo > > In current days, many OS distributions have utilized transaction > memory functionality. In PowerPC, HV KVM supports TM. But PR KVM > does not. > > The drive for the

Re: [PATCH v2 18/30] KVM: PPC: Book3S PR: always fail transaction in guest privilege state

On Wed, Feb 28, 2018 at 01:52:26AM +0800, wei.guo.si...@gmail.com wrote: > From: Simon Guo > > Currently kernel doesn't use transaction memory. > And there is an issue for privilege guest that: > tbegin/tsuspend/tresume/tabort TM instructions can impact MSR TM bits >

Re: [PATCH v2 17/30] KVM: PPC: Book3S PR: make mtspr/mfspr emulation behavior based on active TM SPRs

On Wed, Feb 28, 2018 at 01:52:25AM +0800, wei.guo.si...@gmail.com wrote: > From: Simon Guo > > The mfspr/mtspr on TM SPRs(TEXASR/TFIAR/TFHAR) are non-privileged > instructions and can be executed at PR KVM guest without trapping > into host in problem state. We only

Re: [PATCH 2/2] KVM: PPC: Book3S HV: lockless tlbie for HPT hcalls

On Fri, Apr 06, 2018 at 04:12:32PM +1000, Michael Ellerman wrote: > Nicholas Piggin writes: > > diff --git a/arch/powerpc/kvm/book3s_hv_rm_mmu.c > > b/arch/powerpc/kvm/book3s_hv_rm_mmu.c > > index 78e6a392330f..0221a0f74f07 100644 > > --- a/arch/powerpc/kvm/book3s_hv_rm_mmu.c

Re: [PATCH 06/10] powerpc/mm/radix: implement LPID based TLB flushes to be used by KVM

On Sun, May 06, 2018 at 05:37:27PM +1000, Nicholas Piggin wrote: > Implement a local TLB flush for invalidating an LPID with variants for > process or partition scope. And a global TLB flush for invalidating > a partition scoped page of an LPID. > > These will be used by KVM in subsequent

Re: [PATCH 00/11] KVM: PPC: reconstruct mmio emulation with analyse_instr()

On Wed, Apr 25, 2018 at 07:54:33PM +0800, wei.guo.si...@gmail.com wrote: > From: Simon Guo > > We already have analyse_instr() which analyzes instructions for the > instruction > type, size, addtional flags, etc. What kvmppc_emulate_loadstore() did is > somehow >

Re: [PATCH 08/11] KVM: PPC: add giveup_ext() hook for PPC KVM ops

On Wed, Apr 25, 2018 at 07:54:41PM +0800, wei.guo.si...@gmail.com wrote: > From: Simon Guo > > Currently HV will save math regs(FP/VEC/VSX) when trap into host. But > PR KVM will only save math regs when qemu task switch out of CPU. > > To emulate FP/VEC/VSX load, PR

Re: [PATCH 04/11] KVM: PPC: fix incorrect element_size for stxsiwx in analyse_instr

On Wed, Apr 25, 2018 at 07:54:37PM +0800, wei.guo.si...@gmail.com wrote: > From: Simon Guo > > stwsiwx will place contents of word element 1 of VSR into word > storage of EA. So the element size of stwsiwx should be 4. > > This patch correct the size from 8 to 4. > >

Re: [PATCH 06/11] KVM: PPC: add KVMPPC_VSX_COPY_WORD_LOAD_DUMP type support for mmio emulation

Signed-off-by: Simon Guo <wei.guo.si...@gmail.com> Reviewed-by: Paul Mackerras <pau...@ozlabs.org>

Re: [PATCH 07/11] KVM: PPC: reconstruct non-SIMD LOAD/STORE instruction mmio emulation with analyse_intr() input

_ppc.h, especially since that one isn't exactly about the type of instruction, but more about the type of interrupt led to us trying to fetch the instruction. > Suggested-by: Paul Mackerras <pau...@ozlabs.org> > Signed-off-by: Simon Guo <wei.guo.si...@gmail.com> > --- > ar

Re: [PATCH 03/11] KVM: PPC: Fix a mmio_host_swabbed uninitialized usage issue when VMX store

On Wed, Apr 25, 2018 at 07:54:36PM +0800, wei.guo.si...@gmail.com wrote: > From: Simon Guo > > When KVM emulates VMX store, it will invoke kvmppc_get_vmx_data() to > retrieve VMX reg val. kvmppc_get_vmx_data() will check mmio_host_swabbed > to decide which double word of

Re: [PATCH 01/11] KVM: PPC: add pt_regs into kvm_vcpu_arch and move vcpu->arch.gpr[] into it

On Wed, Apr 25, 2018 at 07:54:34PM +0800, wei.guo.si...@gmail.com wrote: > From: Simon Guo > > Current regs are scattered at kvm_vcpu_arch structure and it will > be more neat to organize them into pt_regs structure. > > Also it will enable reconstruct MMIO emulation

Re: [PATCH 02/11] KVM: PPC: mov nip/ctr/lr/xer registers to pt_regs in kvm_vcpu_arch

On Wed, Apr 25, 2018 at 07:54:35PM +0800, wei.guo.si...@gmail.com wrote: > From: Simon Guo > > This patch moves nip/ctr/lr/xer registers from scattered places in > kvm_vcpu_arch to pt_regs structure. > > cr register is "unsigned long" in pt_regs and u32 in vcpu->arch. >

Re: [PATCH 09/11] KVM: PPC: reconstruct LOAD_FP/STORE_FP instruction mmio emulation with analyse_intr() input

by > analyse_instr() and invokes kvmppc_handle_load(s)/kvmppc_handle_store() > accordingly. > > The FP regs need to be flushed so that the right FP reg vals can be read > from vcpu->arch.fpr. This only applies for store instructions; it would be clearer if you said that explicitly. &g

Re: [PATCH 11/11] KVM: PPC: reconstruct LOAD_VSX/STORE_VSX instruction mmio emulation with analyse_intr() input

> by analyse_instr() and handle accordingly. > > When emulating VSX store, the VSX reg will need to be flushed so that > the right reg val can be retrieved before writing to IO MEM. > > Suggested-by: Paul Mackerras <pau...@ozlabs.org> > Signed-off-by: Simon Guo <wei.g

Re: [PATCH 10/11] KVM: PPC: reconstruct LOAD_VMX/STORE_VMX instruction mmio emulation with analyse_intr() input

to > be flushed so that the right reg val can be retrieved before writing to > IO MEM. > > Suggested-by: Paul Mackerras <pau...@ozlabs.org> > Signed-off-by: Simon Guo <wei.guo.si...@gmail.com> This looks fine for lvx and stvx, but now we are also doing something for the vector e

Re: [PATCH 05/11] KVM: PPC: add GPR RA update skeleton for MMIO emulation

On Wed, Apr 25, 2018 at 07:54:38PM +0800, wei.guo.si...@gmail.com wrote: > From: Simon Guo > > To optimize kvm emulation code with analyse_instr, adds new > mmio_update_ra flag to aid with GPR RA update. > > This patch arms RA update at load/store emulation path for

Re: [PATCH] powerpc/misc: get rid of add_reloc_offset()

On Tue, Apr 17, 2018 at 09:56:24AM +0200, Christophe Leroy wrote: > add_reloc_offset() is almost redundant with reloc_offset() > > Signed-off-by: Christophe Leroy > --- > arch/powerpc/include/asm/setup.h | 3 +-- > arch/powerpc/kernel/misc.S | 16

Re: [PATCH] powerpc/64: Fix checksum folding in csum_add

On Tue, Mar 27, 2018 at 05:22:32PM +0200, LEROY Christophe wrote: > Shile Zhang a écrit : > > >fix the missed point in Paul's patch: > >"powerpc/64: Fix checksum folding in csum_tcpudp_nofold and > >ip_fast_csum_nofold" > > > >Signed-off-by: Shile Zhang

[PATCH] powerpc/powernv: Fix sparse data type warnings in pci-ioda.c

oda.c:2647:45: \ warning: cast to restricted __be64 Signed-off-by: Gavin Shan <gws...@linux.vnet.ibm.com> Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c index a6c92c7..71de0

[PATCH v2 5/5] KVM: PPC: Book3S HV: Work around TEXASR bug in fake suspend state

recording, which will have already been done before we get into fake suspend state). Therefore these changes are not made subject to a CPU feature bit. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/kvm/book3s_hv_rmhandlers.S | 17 ++--- 1 file changed, 10

[PATCH v2 4/5] KVM: PPC: Book3S HV: Work around XER[SO] bug in fake suspend mode

ode before doing the treclaim. This patch adds the code to do that, conditional on the CPU_FTR_P9_TM_XER_SO_BUG feature bit. Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/kvm/book3s_hv_rmhandlers.S | 24

[PATCH v2 3/5] KVM: PPC: Book3S HV: Work around transactional memory bugs in POWER9

treclaim instruction that had done failure recording, not the treclaim done in hypervisor state in the guest exit path. With this, the KVM_CAP_PPC_HTM capability returns true (1) even if transactional memory is not available to host userspace. Signed-off-by: Paul Mackerras <pau...@ozlabs.org>

[PATCH v2 2/5] powerpc/powernv: Provide a way to force a core into SMT4 mode

er9_force_smt4_catch() function returns, until the pnv_power9_force_smt4_release() function is called. It undoes the effect of step 1 above and allows the other threads to go into a stop state. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/asm-prototypes.h | 3 ++

[PATCH v2 1/5] powerpc: Add CPU feature bits for TM bug workarounds on POWER9 v2.2

bled using a "tm-suspend-hypervisor-assist" node in the device tree, and a "tm-suspend-xer-so-bug" node enables the workarounds for the XER[SO] bug. In the absence of such nodes, a quirk enables both for POWER9 "Nimbus" DD2.2 processors. Signed-off-by: Paul Mackerr

[PATCH v2 0/5] KVM & powerpc: Work around POWER9 TM hardware bugs

This patch series applies on top of my patch series "powerpc: Free up CPU feature bits". POWER9 has some shortcomings in its implementation of transactional memory. Starting with v2.2 of the "Nimbus" chip, some changes have been made to the hardware which make it able to generate hypervisor

Re: [PATCH 0/5] KVM & powerpc: Work around POWER9 TM hardware bugs

On Wed, Mar 21, 2018 at 09:24:56PM +1100, Paul Mackerras wrote: > This patch series applies on top of my patch series "powerpc: Free up > CPU feature bits". > > POWER9 has some shortcomings in its implementation of transactional > memory. Starting with v2.2 of the &q

Re: [PATCH V5 2/4] powerpc/mm: Add support for handling > 512TB address in SLB miss

On Sun, Mar 18, 2018 at 04:35:56PM +0530, Aneesh Kumar K.V wrote: [snip] > +static inline int get_ea_context(mm_context_t *ctx, unsigned long ea) > +{ > + int index = ea >> MAX_EA_BITS_PER_CONTEXT; > + > + if (likely(index < ARRAY_SIZE(ctx->extended_id))) > + return

[PATCH 5/5] KVM: PPC: Book3S HV: Work around TEXASR bug in fake suspend state

recording, which will have already been done before we get into fake suspend state). Therefore these changes are not made subject to a CPU feature bit. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/kernel/idle_book3s.S | 4 ++-- arch/powerpc/kvm/book3s_hv_r

[PATCH 4/5] KVM: PPC: Book3S HV: Work around XER[SO] bug in fake suspend mode

ode before doing the treclaim. This patch adds the code to do that, conditional on the CPU_FTR_P9_TM_XER_SO_BUG feature bit. Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/kvm/book3s_hv_rmhandlers.S | 24

[PATCH 3/5] KVM: PPC: Book3S HV: Work around transactional memory bugs in POWER9

treclaim instruction that had done failure recording, not the treclaim done in hypervisor state in the guest exit path. With this, the KVM_CAP_PPC_HTM capability returns true (1) even if transactional memory is not available to host userspace. Signed-off-by: Paul Mackerras <pau...@ozlabs.org>

[PATCH 2/5] powerpc/powernv: Provide a way to force a core into SMT4 mode

er9_force_smt4_catch() function returns, until the pnv_power9_force_smt4_release() function is called. It undoes the effect of step 1 above and allows the other threads to go into a stop state. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/asm-prototypes.h | 3 ++

[PATCH 1/5] powerpc: Add CPU feature bits for TM bug workarounds on POWER9 v2.2

bled using a "tm-suspend-hypervisor-assist" node in the device tree, and a "tm-suspend-xer-so-bug" node enables the workarounds for the XER[SO] bug. In the absence of such nodes, a quirk enables both for POWER9 "Nimbus" DD2.2 processors. Signed-off-by: Paul Mackerr

[PATCH 0/5] KVM & powerpc: Work around POWER9 TM hardware bugs

This patch series applies on top of my patch series "powerpc: Free up CPU feature bits". POWER9 has some shortcomings in its implementation of transactional memory. Starting with v2.2 of the "Nimbus" chip, some changes have been made to the hardware which make it able to generate hypervisor

[PATCH 3/3] powerpc: Free up CPU feature bits on 64-bit machines

feature bits on 64-bit machines. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/cputable.h | 133 -- arch/powerpc/kernel/cpu_setup_6xx.S | 2 +- arch/powerpc/kernel/cpu_setup_fsl_booke.S | 2 +- 3 files chang

[PATCH 1/3] powerpc: Use feature bit for RTC presence rather than timebase presence

nse to use a bit to indicate the unusual situation rather than the common situation. This therefore defines a CPU_FTR_USE_RTC bit in place of the CPU_FTR_USE_TB bit, and arranges for it to be set on PPC601 systems. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm

[PATCH 2/3] powerpc: Book E: Remove unused CPU_FTR_L2CSR bit

The CPU_FTR_L2CSR bit is never tested anywhere, so let's reclaim the bit. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/cputable.h | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/include/asm/cputable.h b/arch/p

[PATCH 0/3] powerpc: Free up CPU feature bits

This patch series is against the powerpc next branch. It takes advantage of the fact that there are only a few CPU feature bits that are meaningful on both 32-bit and 64-bit platforms. At the moment, many of the 64 bits of the CPU feature mask on 64-bit platforms are taken up with bits which are

[PATCH RFC 5/5] KVM: PPC: Book3S HV: Work around TEXASR bug in fake suspend mode

lue in non-transactional state (e.g. after a treclaim), and treclaim will work correctly. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/kvm/book3s_hv_rmhandlers.S | 17 ++--- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/arch/powerpc/kvm/book3s

[PATCH RFC 0/5] powerpc & KVM: Work around POWER9 TM hardware bugs

POWER9 has some shortcomings in its implementation of transactional memory. Starting with v2.2 of the "Nimbus" chip, some changes have been made to the hardware which make it able to generate hypervisor interrupts in the situations where hardware needs the hypervisor to provide some assistance

[PATCH RFC 3/5] KVM: PPC: Book3S HV: Work around transactional memory bugs in POWER9

treclaim instruction that had done failure recording, not the treclaim done in hypervisor state in the guest exit path. With this, the KVM_CAP_PPC_HTM capability returns true (1) even if transactional memory is not available to host userspace. Signed-off-by: Paul Mackerras <pau...@ozlabs.org>

[PATCH RFC 1/5] powerpc: Add a CPU feature bit for TM bug workarounds on POWER9 v2.2

subsystem is in use, the software assistance can be enabled using a "tm-suspend-hypervisor-assist" node in the device tree. In the absence of such a node, a quirk enables the assistance for POWER9 "Nimbus" DD2.2 processors. Signed-off-by: Paul Mackerras <pau...@ozlabs.o

[PATCH RFC 2/5] powerpc/powernv: Provide a way to force a core into SMT4 mode

ction returns, until the pnv_power9_force_smt4_release() function is called. It undoes the effect of step 1 above and allows the other threads to go into a stop state. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/asm-prototypes.h | 3 ++ arch/powerpc/include/asm/paca.h |

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