RE: [PATCH v3 1/2] fsl: Add binding for RCPM
> +++ b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt > @@ -0,0 +1,63 @@ > +* Run Control and Power Management > +--- > +The RCPM performs all device-level tasks associated with device run control > +and power management. > + > +Required properites: > + - reg : Offset and length of the register set of RCPM block. s/RCPM block/the RCPM block/ > + - fsl,#rcpm-wakeup-cells : The number of cells in rcpm-wakeup property. s/rcpm-wakeup-property/the rcpm-wakeup-property/ > + - compatible : Sould contain a chip-specific RCPM block compatible string s/Sould/Should "Should" means it is recommended, but does not mean "must". Is it really optional? > + and (if applicable) may contain a chassis-version RCPM compatible > + string. Chip-specific strings are of the form "fsl,-rcpm", > + such as: > + * "fsl,p2041-rcpm" > + * "fsl,p3041-rcpm" > + * "fsl,p4080-rcpm" > + * "fsl,p5020-rcpm" > + * "fsl,p5040-rcpm" > + * "fsl,t4240-rcpm" > + * "fsl,b4420-rcpm" > + * "fsl,b4860-rcpm" 2 or 3 examples is enough. > + Chassis-version strings are of the form "fsl,qoriq-rcpm-", > + such as: > + * "fsl,qoriq-rcpm-1.0": for chassis 1.0 rcpm > + * "fsl,qoriq-rcpm-2.0": for chassis 2.0 rcpm > + * "fsl,qoriq-rcpm-2.1": for chassis 2.1 rcpm > + > +All references to "1.0" and "2.0" refer to the QorIQ chassis version to > +which the chip complies. > +Chassis VersionExample Chips > +------ > +1.0p4080, p5020, p5040, p2041, p3041 > +2.0t4240, b4860, b4420 > +2.1t1040, ls1021 Not sure this binding is the place to maintain a table of chassis versions to SoCs. Thanks, Stuart ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH] powerpc: move epapr paravirt init of power_save to an initcall
-Original Message-
From: Alexander Graf [mailto:ag...@suse.de]
Sent: Wednesday, April 30, 2014 2:56 PM
To: Yoder Stuart-B08248; b...@kernel.crashing.org; Wood Scott-B07421
Cc: linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH] powerpc: move epapr paravirt init of power_save to
an initcall
On 30.04.14 21:54, Stuart Yoder wrote:
From: Stuart Yoder stuart.yo...@freescale.com
some restructuring of epapr paravirt init resulted in
ppc_md.power_save being set, and then overwritten to
NULL during machine_init. This patch splits the
initialization of ppc_md.power_save out into a postcore
init call.
Signed-off-by: Stuart Yoder stuart.yo...@freescale.com
---
arch/powerpc/kernel/epapr_paravirt.c | 25 -
1 file changed, 20 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/kernel/epapr_paravirt.c
b/arch/powerpc/kernel/epapr_paravirt.c
index 6300c13..c49b69c 100644
--- a/arch/powerpc/kernel/epapr_paravirt.c
+++ b/arch/powerpc/kernel/epapr_paravirt.c
@@ -52,11 +52,6 @@ static int __init early_init_dt_scan_epapr(unsigned
long node,
#endif
}
-#if !defined(CONFIG_64BIT) || defined(CONFIG_PPC_BOOK3E_64)
- if (of_get_flat_dt_prop(node, has-idle, NULL))
- ppc_md.power_save = epapr_ev_idle;
-#endif
-
epapr_paravirt_enabled = true;
return 1;
@@ -69,3 +64,23 @@ int __init epapr_paravirt_early_init(void)
return 0;
}
+static int __init epapr_idle_init_dt_scan(unsigned long node,
+ const char *uname,
+ int depth, void *data)
+{
+#if !defined(CONFIG_64BIT) || defined(CONFIG_PPC_BOOK3E_64)
+ if (of_get_flat_dt_prop(node, has-idle, NULL))
+ ppc_md.power_save = epapr_ev_idle;
+#endif
+ return 0;
+}
+
+static int __init epapr_idle_init(void)
+{
+ if (epapr_paravirt_enabled)
+ of_scan_flat_dt(epapr_idle_init_dt_scan, NULL);
Doesn't this scan all nodes? We only want to match on
/hypervisor/has-idle, no?
I cut/pasted from the approach the existing code in that file
took, but yes you're right we just need the one property.
Let me respin that to look at the hypervisor node only.
Stuart
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[PATCH] powerpc: move epapr paravirt init of power_save to an initcall
From: Stuart Yoder stuart.yo...@freescale.com
some restructuring of epapr paravirt init resulted in
ppc_md.power_save being set, and then overwritten to
NULL during machine_init. This patch splits the
initialization of ppc_md.power_save out into a postcore
init call.
Signed-off-by: Stuart Yoder stuart.yo...@freescale.com
---
arch/powerpc/kernel/epapr_paravirt.c | 25 -
1 file changed, 20 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/kernel/epapr_paravirt.c
b/arch/powerpc/kernel/epapr_paravirt.c
index 6300c13..c49b69c 100644
--- a/arch/powerpc/kernel/epapr_paravirt.c
+++ b/arch/powerpc/kernel/epapr_paravirt.c
@@ -52,11 +52,6 @@ static int __init early_init_dt_scan_epapr(unsigned long
node,
#endif
}
-#if !defined(CONFIG_64BIT) || defined(CONFIG_PPC_BOOK3E_64)
- if (of_get_flat_dt_prop(node, has-idle, NULL))
- ppc_md.power_save = epapr_ev_idle;
-#endif
-
epapr_paravirt_enabled = true;
return 1;
@@ -69,3 +64,23 @@ int __init epapr_paravirt_early_init(void)
return 0;
}
+static int __init epapr_idle_init_dt_scan(unsigned long node,
+ const char *uname,
+ int depth, void *data)
+{
+#if !defined(CONFIG_64BIT) || defined(CONFIG_PPC_BOOK3E_64)
+ if (of_get_flat_dt_prop(node, has-idle, NULL))
+ ppc_md.power_save = epapr_ev_idle;
+#endif
+ return 0;
+}
+
+static int __init epapr_idle_init(void)
+{
+ if (epapr_paravirt_enabled)
+ of_scan_flat_dt(epapr_idle_init_dt_scan, NULL);
+
+ return 0;
+}
+
+postcore_initcall(epapr_idle_init);
--
1.7.9.7
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[PATCH][v2] powerpc: move epapr paravirt init of power_save to an initcall
From: Stuart Yoder stuart.yo...@freescale.com
some restructuring of epapr paravirt init resulted in
ppc_md.power_save being set, and then overwritten to
NULL during machine_init. This patch splits the
initialization of ppc_md.power_save out into a postcore
init call.
Signed-off-by: Stuart Yoder stuart.yo...@freescale.com
---
-v2: don't iterate over the entire DT, just look at
the hypervisor node
arch/powerpc/kernel/epapr_paravirt.c | 25 -
1 file changed, 20 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/kernel/epapr_paravirt.c
b/arch/powerpc/kernel/epapr_paravirt.c
index 7898be9..a01df5e 100644
--- a/arch/powerpc/kernel/epapr_paravirt.c
+++ b/arch/powerpc/kernel/epapr_paravirt.c
@@ -53,11 +53,6 @@ static int __init early_init_dt_scan_epapr(unsigned long
node,
#endif
}
-#if !defined(CONFIG_64BIT) || defined(CONFIG_PPC_BOOK3E_64)
- if (of_get_flat_dt_prop(node, has-idle, NULL))
- ppc_md.power_save = epapr_ev_idle;
-#endif
-
epapr_paravirt_enabled = true;
return 1;
@@ -70,3 +65,23 @@ int __init epapr_paravirt_early_init(void)
return 0;
}
+static int __init epapr_idle_init(void)
+{
+ struct device_node *node;
+
+ if (!epapr_paravirt_enabled)
+ return 0;
+
+ node = of_find_node_by_path(/hypervisor);
+ if (!node)
+ return -ENODEV;
+
+#if !defined(CONFIG_64BIT) || defined(CONFIG_PPC_BOOK3E_64)
+ if (of_get_property(node, has-idle, NULL))
+ ppc_md.power_save = epapr_ev_idle;
+#endif
+
+ return 0;
+}
+
+postcore_initcall(epapr_idle_init);
--
1.7.9.7
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RE: [PATCH][v2] powerpc: move epapr paravirt init of power_save to an initcall
-Original Message-
From: Wood Scott-B07421
Sent: Wednesday, April 30, 2014 5:49 PM
To: Yoder Stuart-B08248
Cc: b...@kernel.crashing.org; linuxppc-dev@lists.ozlabs.org;
ag...@suse.de
Subject: Re: [PATCH][v2] powerpc: move epapr paravirt init of power_save
to an initcall
On Wed, 2014-04-30 at 15:20 -0500, Stuart Yoder wrote:
From: Stuart Yoder stuart.yo...@freescale.com
some restructuring of epapr paravirt init resulted in
ppc_md.power_save being set, and then overwritten to
NULL during machine_init. This patch splits the
initialization of ppc_md.power_save out into a postcore
init call.
Signed-off-by: Stuart Yoder stuart.yo...@freescale.com
---
-v2: don't iterate over the entire DT, just look at
the hypervisor node
arch/powerpc/kernel/epapr_paravirt.c | 25 -
1 file changed, 20 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/kernel/epapr_paravirt.c
b/arch/powerpc/kernel/epapr_paravirt.c
index 7898be9..a01df5e 100644
--- a/arch/powerpc/kernel/epapr_paravirt.c
+++ b/arch/powerpc/kernel/epapr_paravirt.c
@@ -53,11 +53,6 @@ static int __init early_init_dt_scan_epapr(unsigned
long node,
#endif
}
-#if !defined(CONFIG_64BIT) || defined(CONFIG_PPC_BOOK3E_64)
- if (of_get_flat_dt_prop(node, has-idle, NULL))
- ppc_md.power_save = epapr_ev_idle;
-#endif
-
epapr_paravirt_enabled = true;
return 1;
@@ -70,3 +65,23 @@ int __init epapr_paravirt_early_init(void)
return 0;
}
+static int __init epapr_idle_init(void)
+{
+ struct device_node *node;
+
+ if (!epapr_paravirt_enabled)
+ return 0;
+
+ node = of_find_node_by_path(/hypervisor);
+ if (!node)
+ return -ENODEV;
+
+#if !defined(CONFIG_64BIT) || defined(CONFIG_PPC_BOOK3E_64)
+ if (of_get_property(node, has-idle, NULL))
+ ppc_md.power_save = epapr_ev_idle;
+#endif
+
+ return 0;
+}
Why duplicate the search-for-hv-node code? Just have the early init
func set a flag indicating whether has-idle was found, and have
epapr_idle_init act on that flag.
That's a good idea, and the patch would be quite a bit smaller.
I'll do that and leave the stuff in early_init_dt_scan_epapr() alone
mostly. Then as a separate step we could put back the code that
looks at only /hypervisor (based on feedback from Laurentiu).
Stuart
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[PATCH][v3] powerpc: move epapr paravirt init of power_save to an initcall
From: Stuart Yoder stuart.yo...@freescale.com
some restructuring of epapr paravirt init resulted in
ppc_md.power_save being set, and then overwritten to
NULL during machine_init. This patch splits the
initialization of ppc_md.power_save out into a postcore
init call.
Signed-off-by: Stuart Yoder stuart.yo...@freescale.com
---
-v3
-changed approach slightly, set flag in the dt scanning
code and just look at that flag in the initcall
arch/powerpc/kernel/epapr_paravirt.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/epapr_paravirt.c
b/arch/powerpc/kernel/epapr_paravirt.c
index 7898be9..6596cd7 100644
--- a/arch/powerpc/kernel/epapr_paravirt.c
+++ b/arch/powerpc/kernel/epapr_paravirt.c
@@ -30,6 +30,7 @@ extern u32 epapr_ev_idle_start[];
#endif
bool epapr_paravirt_enabled;
+bool epapr_has_idle;
static int __init early_init_dt_scan_epapr(unsigned long node,
const char *uname,
@@ -55,7 +56,7 @@ static int __init early_init_dt_scan_epapr(unsigned long node,
#if !defined(CONFIG_64BIT) || defined(CONFIG_PPC_BOOK3E_64)
if (of_get_flat_dt_prop(node, has-idle, NULL))
- ppc_md.power_save = epapr_ev_idle;
+ epapr_has_idle = true;
#endif
epapr_paravirt_enabled = true;
@@ -70,3 +71,12 @@ int __init epapr_paravirt_early_init(void)
return 0;
}
+static int __init epapr_idle_init(void)
+{
+ if (epapr_has_idle)
+ ppc_md.power_save = epapr_ev_idle;
+
+ return 0;
+}
+
+postcore_initcall(epapr_idle_init);
--
1.7.9.7
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[PATCH][v4] powerpc: move epapr paravirt init of power_save to an initcall
From: Stuart Yoder stuart.yo...@freescale.com
some restructuring of epapr paravirt init resulted in
ppc_md.power_save being set, and then overwritten to
NULL during machine_init. This patch splits the
initialization of ppc_md.power_save out into a postcore
init call.
Signed-off-by: Stuart Yoder stuart.yo...@freescale.com
---
-v3
-changed approach slightly, set flag in the dt scanning
code and just look at that flag in the initcall
-v4
-made idle flag static
arch/powerpc/kernel/epapr_paravirt.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/epapr_paravirt.c
b/arch/powerpc/kernel/epapr_paravirt.c
index 7898be9..8a7a62c 100644
--- a/arch/powerpc/kernel/epapr_paravirt.c
+++ b/arch/powerpc/kernel/epapr_paravirt.c
@@ -30,6 +30,7 @@ extern u32 epapr_ev_idle_start[];
#endif
bool epapr_paravirt_enabled;
+static bool epapr_has_idle;
static int __init early_init_dt_scan_epapr(unsigned long node,
const char *uname,
@@ -55,7 +56,7 @@ static int __init early_init_dt_scan_epapr(unsigned long node,
#if !defined(CONFIG_64BIT) || defined(CONFIG_PPC_BOOK3E_64)
if (of_get_flat_dt_prop(node, has-idle, NULL))
- ppc_md.power_save = epapr_ev_idle;
+ epapr_has_idle = true;
#endif
epapr_paravirt_enabled = true;
@@ -70,3 +71,12 @@ int __init epapr_paravirt_early_init(void)
return 0;
}
+static int __init epapr_idle_init(void)
+{
+ if (epapr_has_idle)
+ ppc_md.power_save = epapr_ev_idle;
+
+ return 0;
+}
+
+postcore_initcall(epapr_idle_init);
--
1.7.9.7
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Re: [PATCH] bookehv: Handle debug exception on guest exit
On Thu, Apr 11, 2013 at 1:33 PM, Kumar Gala ga...@kernel.crashing.org wrote: On Apr 5, 2013, at 2:53 AM, Bhushan Bharat-R65777 wrote: Hi Kumar/Benh, After further looking into the code I think that if we correct the vector range below in DebugDebug handler then we do not need the change I provided in this patch. Here is the snapshot for 32 bit (head_booke.h, same will be true for 64 bit): #define DEBUG_DEBUG_EXCEPTION \ START_EXCEPTION(DebugDebug); \ DEBUG_EXCEPTION_PROLOG; \ \ /* \ * If there is a single step or branch-taken exception in an \ * exception entry sequence, it was probably meant to apply to \ * the code where the exception occurred (since exception entry \ * doesn't turn off DE automatically). We simulate the effect \ * of turning off DE on entry to an exception handler by turning \ * off DE in the DSRR1 value and clearing the debug status. \ */ \ mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \ andis. r10,r10,(DBSR_IC|DBSR_BT)@h; \ beq+2f; \ \ lis r10,KERNELBASE@h; /* check if exception in vectors */ \ ori r10,r10,KERNELBASE@l; \ cmplw r12,r10; \ blt+2f; /* addr below exception vectors */ \ \ lis r10,DebugDebug@h;\ ori r10,r10,DebugDebug@l; \ Here we assume all exception vector ends at DebugDebug, which is not correct. We probably should get proper end by using some start_vector and end_vector lebels or at least use end at Ehvpriv (which is last defined in head_fsl_booke.S for PowerPC. Is that correct? cmplw r12,r10; \ bgt+2f; /* addr above exception vectors */ \ Thanks -Bharat I talked to Stuart and this general approach is good. Just make sure to update both head_44x.S and head_fsl_booke.S. Plus do this for both DEBUG_CRIT_EXCEPTION DEBUG_DEBUG_EXCEPTION Also, it looks like 64-bit already handles this properly with symbols identifying the start/end of the vectors (exceptions-64e.S). Stuart ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] bookehv: Handle debug exception on guest exit
So the patch should look something like this (on a 3.8 kernel): diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h index 5f051ee..92b675a 100644 --- a/arch/powerpc/kernel/head_booke.h +++ b/arch/powerpc/kernel/head_booke.h @@ -286,13 +286,13 @@ label: andis. r10,r10,(DBSR_IC|DBSR_BT)@h; \ beq+2f; \ \ - lis r10,KERNELBASE@h; /* check if exception in vectors */ \ - ori r10,r10,KERNELBASE@l; \ + lis r10,interrupt_base@h; /* check if exception in vectors */ \ + ori r10,r10,interrupt_base@l; cmplw r12,r10; \ blt+2f; /* addr below exception vectors */\ \ - lis r10,DebugDebug@h; \ - ori r10,r10,DebugDebug@l; \ + lis r10,interrupt_end@h; \ + ori r10,r10,interrupt_end@l; cmplw r12,r10; \ bgt+2f; /* addr above exception vectors */\ \ @@ -339,13 +339,13 @@ label: andis. r10,r10,(DBSR_IC|DBSR_BT)@h; \ beq+2f; \ \ - lis r10,KERNELBASE@h; /* check if exception in vectors */ \ - ori r10,r10,KERNELBASE@l; \ + lis r10,interrupt_base@h; /* check if exception in vectors */ \ + ori r10,r10,interrupt_base@l; cmplw r12,r10; \ blt+2f; /* addr below exception vectors */\ \ - lis r10,DebugCrit@h; \ - ori r10,r10,DebugCrit@l; \ + lis r10,interrupt_end@h; \ + ori r10,r10,interrupt_end@l; cmplw r12,r10; \ bgt+2f; /* addr above exception vectors */\ \ diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S index 7a2e5e4..97e2671 100644 --- a/arch/powerpc/kernel/head_44x.S +++ b/arch/powerpc/kernel/head_44x.S @@ -769,6 +769,8 @@ finish_tlb_load_47x: */ DEBUG_CRIT_EXCEPTION +interrupt_end: + /* * Global functions */ diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl index 58925b6..2c3e31d 100644 --- a/arch/powerpc/kernel/head_fsl_booke.S +++ b/arch/powerpc/kernel/head_fsl_booke.S @@ -605,6 +605,8 @@ END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) /* Embedded Hypervisor Privilege */ EXCEPTION(0, HV_PRIV, Ehvpriv, unknown_exception, EXC_XFER_EE) +interrupt_end: + /* * Local functions */ ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] PPC: define the conditions where the ePAPR idle hcall can be supported
From: Stuart Yoder stuart.yo...@freescale.com
For 32-bit, CONFIG_EPAPR_PARAVIRT pulls in both epapr_paravirt.c
and epapr_hcalls.c which contains the 32-bit paravirt idle loop.
For 64-bit, the paravirt idle loop is in idle_book3e.S and that
source file is included only if CONFIG_PPC_BOOK3E_64 defined.
This patch makes that dependency for 64-bit explicit.
Signed-off-by: Stuart Yoder stuart.yo...@freescale.com
---
arch/powerpc/kernel/epapr_paravirt.c |6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/powerpc/kernel/epapr_paravirt.c
b/arch/powerpc/kernel/epapr_paravirt.c
index f3eab85..d44a571 100644
--- a/arch/powerpc/kernel/epapr_paravirt.c
+++ b/arch/powerpc/kernel/epapr_paravirt.c
@@ -23,8 +23,10 @@
#include asm/code-patching.h
#include asm/machdep.h
+#if !defined(CONFIG_64BIT) || defined(CONFIG_PPC_BOOK3E_64)
extern void epapr_ev_idle(void);
extern u32 epapr_ev_idle_start[];
+#endif
bool epapr_paravirt_enabled;
@@ -47,11 +49,15 @@ static int __init epapr_paravirt_init(void)
for (i = 0; i (len / 4); i++) {
patch_instruction(epapr_hypercall_start + i, insts[i]);
+#if !defined(CONFIG_64BIT) || defined(CONFIG_PPC_BOOK3E_64)
patch_instruction(epapr_ev_idle_start + i, insts[i]);
+#endif
}
+#if !defined(CONFIG_64BIT) || defined(CONFIG_PPC_BOOK3E_64)
if (of_get_property(hyper_node, has-idle, NULL))
ppc_md.power_save = epapr_ev_idle;
+#endif
epapr_paravirt_enabled = true;
--
1.7.9.7
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[PATCH] powerpc/e6500: Add Power ISA properties for e6500 cores
From: Stuart Yoder stuart.yo...@freescale.com
Signed-off-by: Stuart Yoder stuart.yo...@freescale.com
---
arch/powerpc/boot/dts/fsl/e6500_power_isa.dtsi | 66
1 file changed, 66 insertions(+)
create mode 100644 arch/powerpc/boot/dts/fsl/e6500_power_isa.dtsi
diff --git a/arch/powerpc/boot/dts/fsl/e6500_power_isa.dtsi
b/arch/powerpc/boot/dts/fsl/e6500_power_isa.dtsi
new file mode 100644
index 000..b763252
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/e6500_power_isa.dtsi
@@ -0,0 +1,66 @@
+/*
+ * e6500 Power ISA Device Tree Source (include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/ {
+ cpus {
+ power-isa-version = 2.06;
+ power-isa-b;// Base
+ power-isa-e;// Embedded
+ power-isa-atb; // Alternate Time Base
+ power-isa-cs; // Cache Specification
+ power-isa-ds; // Decorated Storage
+ power-isa-e.ed; // Embedded.Enhanced Debug
+ power-isa-e.pd; // Embedded.External PID
+ power-isa-e.hv; // Embedded.Hypervisor
+ power-isa-e.le; // Embedded.Little-Endian
+ power-isa-e.pm; // Embedded.Performance Monitor
+ power-isa-e.pc; // Embedded.Processor Control
+ power-isa-ecl; // Embedded Cache Locking
+ power-isa-exp; // External Proxy
+ power-isa-fp; // Floating Point
+ power-isa-fp.r; // Floating Point.Record
+ power-isa-mmc; // Memory Coherence
+ power-isa-scpm; // Store Conditional Page Mobility
+ power-isa-wt; // Wait
+ power-isa-64; // 64-bit
+ power-isa-e.pt; // Embedded.Page Table
+ power-isa-e.hv.lrat // Embedded.Hypervisor.LRAT
+ power-isa-e.em // Embedded Multi-Threading
+ power-isa-v // Vector (AltiVec)
+ power-isa-er// Enhanced Reservations (Load and
Reserve and Store Cond.)
+ power-isa-deo // Data Cache Extended Operations
+ power-isa-cs// Cache Stashing
+ mmu-type = power-embedded;
+ };
+};
--
1.7.9.7
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[PATCH][v2] powerpc/e6500: Add Power ISA properties for e6500 cores
From: Stuart Yoder stuart.yo...@freescale.com
Signed-off-by: Stuart Yoder stuart.yo...@freescale.com
---
-v2
-fix some typos
arch/powerpc/boot/dts/fsl/e6500_power_isa.dtsi | 65
1 file changed, 65 insertions(+)
create mode 100644 arch/powerpc/boot/dts/fsl/e6500_power_isa.dtsi
diff --git a/arch/powerpc/boot/dts/fsl/e6500_power_isa.dtsi
b/arch/powerpc/boot/dts/fsl/e6500_power_isa.dtsi
new file mode 100644
index 000..6b4d16a
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/e6500_power_isa.dtsi
@@ -0,0 +1,65 @@
+/*
+ * e6500 Power ISA Device Tree Source (include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/ {
+ cpus {
+ power-isa-version = 2.06;
+ power-isa-b;// Base
+ power-isa-e;// Embedded
+ power-isa-atb; // Alternate Time Base
+ power-isa-cs; // Cache Specification
+ power-isa-ds; // Decorated Storage
+ power-isa-e.ed; // Embedded.Enhanced Debug
+ power-isa-e.pd; // Embedded.External PID
+ power-isa-e.hv; // Embedded.Hypervisor
+ power-isa-e.le; // Embedded.Little-Endian
+ power-isa-e.pm; // Embedded.Performance Monitor
+ power-isa-e.pc; // Embedded.Processor Control
+ power-isa-ecl; // Embedded Cache Locking
+ power-isa-exp; // External Proxy
+ power-isa-fp; // Floating Point
+ power-isa-fp.r; // Floating Point.Record
+ power-isa-mmc; // Memory Coherence
+ power-isa-scpm; // Store Conditional Page Mobility
+ power-isa-wt; // Wait
+ power-isa-64; // 64-bit
+ power-isa-e.pt; // Embedded.Page Table
+ power-isa-e.hv.lrat;// Embedded.Hypervisor.LRAT
+ power-isa-e.em; // Embedded Multi-Threading
+ power-isa-v;// Vector (AltiVec)
+ power-isa-er; // Enhanced Reservations (Load and
Reserve and Store Cond.)
+ power-isa-deo; // Data Cache Extended Operations
+ mmu-type = power-embedded;
+ };
+};
--
1.7.9.7
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[PATCH] powerpc: add missing deo ISA category to e500mc/e5500 dts
From: Stuart Yoder stuart.yo...@freescale.com Signed-off-by: Stuart Yoder stuart.yo...@freescale.com --- arch/powerpc/boot/dts/fsl/e500mc_power_isa.dtsi |1 + arch/powerpc/boot/dts/fsl/e5500_power_isa.dtsi |1 + 2 files changed, 2 insertions(+) diff --git a/arch/powerpc/boot/dts/fsl/e500mc_power_isa.dtsi b/arch/powerpc/boot/dts/fsl/e500mc_power_isa.dtsi index 870c653..0e7bb68 100644 --- a/arch/powerpc/boot/dts/fsl/e500mc_power_isa.dtsi +++ b/arch/powerpc/boot/dts/fsl/e500mc_power_isa.dtsi @@ -53,6 +53,7 @@ power-isa-mmc; // Memory Coherence power-isa-scpm; // Store Conditional Page Mobility power-isa-wt; // Wait + power-isa-deo; // Data Cache Extended Operations mmu-type = power-embedded; }; }; diff --git a/arch/powerpc/boot/dts/fsl/e5500_power_isa.dtsi b/arch/powerpc/boot/dts/fsl/e5500_power_isa.dtsi index 3230212..39eba29 100644 --- a/arch/powerpc/boot/dts/fsl/e5500_power_isa.dtsi +++ b/arch/powerpc/boot/dts/fsl/e5500_power_isa.dtsi @@ -54,6 +54,7 @@ power-isa-scpm; // Store Conditional Page Mobility power-isa-wt; // Wait power-isa-64; // 64-bit + power-isa-deo; // Data Cache Extended Operations mmu-type = power-embedded; }; }; -- 1.7.9.7 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH][v3] powerpc/e6500: Add architecture categories for e6500 cores
From: Stuart Yoder stuart.yo...@freescale.com
-also define a binding for fsl,eref-* properties
Signed-off-by: Stuart Yoder stuart.yo...@freescale.com
---
-v3
-converted EREF specific properties to fsl,eref-*
.../devicetree/bindings/powerpc/fsl/cpus.txt | 21 +++
arch/powerpc/boot/dts/fsl/e6500_power_isa.dtsi | 65
2 files changed, 86 insertions(+)
create mode 100644 Documentation/devicetree/bindings/powerpc/fsl/cpus.txt
create mode 100644 arch/powerpc/boot/dts/fsl/e6500_power_isa.dtsi
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpus.txt
b/Documentation/devicetree/bindings/powerpc/fsl/cpus.txt
new file mode 100644
index 000..79dadf1
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/cpus.txt
@@ -0,0 +1,21 @@
+===
+Power Architecture CPU Binding
+Copyright 2013 Freescale Semiconductor Inc.
+
+Power Architecture CPUs in Freescale SOCs are represented in device trees as
per the
+definition in ePAPR.
+
+In addition to the ePAPR definitions, the properties defined below may be
present
+on CPU nodes.
+
+PROPERTIES
+
+ - fsl,eref-*
+Usage: optional
+Value type: empty
+Definition: The EREF (EREF: A Programmer.s Reference Manual for
Freescale Power Architecture)
+defines the architecture for Freescale Power CPUs. The EREF defines
some architecture categories
+not defined by the Power ISA. For these EREF-specific categories, the
existence of a property
+named fsl,eref-[CAT], where [CAT] is the abbreviated category name
with all uppercase letters
+converted to lowercase, indicates that the category is supported by
the implementation.
+
diff --git a/arch/powerpc/boot/dts/fsl/e6500_power_isa.dtsi
b/arch/powerpc/boot/dts/fsl/e6500_power_isa.dtsi
new file mode 100644
index 000..a912dbe
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/e6500_power_isa.dtsi
@@ -0,0 +1,65 @@
+/*
+ * e6500 Power ISA Device Tree Source (include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/ {
+ cpus {
+ power-isa-version = 2.06;
+ power-isa-b;// Base
+ power-isa-e;// Embedded
+ power-isa-atb; // Alternate Time Base
+ power-isa-cs; // Cache Specification
+ power-isa-ds; // Decorated Storage
+ power-isa-e.ed; // Embedded.Enhanced Debug
+ power-isa-e.pd; // Embedded.External PID
+ power-isa-e.hv; // Embedded.Hypervisor
+ power-isa-e.le; // Embedded.Little-Endian
+ power-isa-e.pm; // Embedded.Performance Monitor
+ power-isa-e.pc; // Embedded.Processor Control
+ power-isa-ecl; // Embedded Cache Locking
+ power-isa-exp; // External Proxy
+ power-isa-fp; // Floating Point
+ power-isa-fp.r; // Floating Point.Record
+ power-isa-mmc; // Memory Coherence
+ power-isa-scpm; // Store
[PATCH][v2] powerpc: add missing deo arch category to e500mc/e5500 dts
From: Stuart Yoder stuart.yo...@freescale.com Signed-off-by: Stuart Yoder stuart.yo...@freescale.com --- -v2 -deo is EREF specific, changed name of property arch/powerpc/boot/dts/fsl/e500mc_power_isa.dtsi |1 + arch/powerpc/boot/dts/fsl/e5500_power_isa.dtsi |1 + 2 files changed, 2 insertions(+) diff --git a/arch/powerpc/boot/dts/fsl/e500mc_power_isa.dtsi b/arch/powerpc/boot/dts/fsl/e500mc_power_isa.dtsi index 870c653..ea145c9 100644 --- a/arch/powerpc/boot/dts/fsl/e500mc_power_isa.dtsi +++ b/arch/powerpc/boot/dts/fsl/e500mc_power_isa.dtsi @@ -53,6 +53,7 @@ power-isa-mmc; // Memory Coherence power-isa-scpm; // Store Conditional Page Mobility power-isa-wt; // Wait + fsl,eref-deo; // Data Cache Extended Operations mmu-type = power-embedded; }; }; diff --git a/arch/powerpc/boot/dts/fsl/e5500_power_isa.dtsi b/arch/powerpc/boot/dts/fsl/e5500_power_isa.dtsi index 3230212..c254c98 100644 --- a/arch/powerpc/boot/dts/fsl/e5500_power_isa.dtsi +++ b/arch/powerpc/boot/dts/fsl/e5500_power_isa.dtsi @@ -54,6 +54,7 @@ power-isa-scpm; // Store Conditional Page Mobility power-isa-wt; // Wait power-isa-64; // 64-bit + fsl,eref-deo; // Data Cache Extended Operations mmu-type = power-embedded; }; }; -- 1.7.9.7 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH V4] powerpc/85xx: Add machine check handler to fix PCIe erratum on mpc85xx
On Mon, Mar 4, 2013 at 2:40 AM, Jia Hongtao b38...@freescale.com wrote: A PCIe erratum of mpc85xx may causes a core hang when a link of PCIe goes down. when the link goes down, Non-posted transactions issued via the ATMU requiring completion result in an instruction stall. At the same time a machine-check exception is generated to the core to allow further processing by the handler. We implements the handler which skips the instruction caused the stall. Can you explain at a high level how just skipping an instruction solves anything? If you just skip a load/store and continue like nothing is wrong, isn't your system possibly in a really bad state. And if the core is already hung, due to the PCI link going down, isn't it too late? How does skipping help? Stuart ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 6/6 v8] iommu/fsl: Freescale PAMU driver and IOMMU API implementation.
On Mon, Feb 18, 2013 at 6:52 AM, Varun Sethi varun.se...@freescale.com wrote:
[cut]
+static phys_addr_t get_phys_addr(struct fsl_dma_domain *dma_domain, unsigned
long iova)
+{
+ u32 win_cnt = dma_domain-win_cnt;
+ struct dma_window *win_ptr =
+ dma_domain-win_arr[0];
+ struct iommu_domain_geometry *geom;
+
+ geom = dma_domain-iommu_domain-geometry;
+
+ if (!win_cnt || !dma_domain-geom_size) {
+ pr_err(Number of windows/geometry not configured for the
domain\n);
+ return 0;
+ }
+
+ if (win_cnt 1) {
+ u64 subwin_size;
+ unsigned long subwin_iova;
+ u32 wnd;
+
+ subwin_size = dma_domain-geom_size ilog2(win_cnt);
Could it be just geom_size / win_cnt ??
+ subwin_iova = iova ~(subwin_size - 1);
+ wnd = (subwin_iova - geom-aperture_start)
ilog2(subwin_size);
+ win_ptr = dma_domain-win_arr[wnd];
+ }
+
+ if (win_ptr-valid)
+ return (win_ptr-paddr + (iova (win_ptr-size - 1)));
+
+ return 0;
+}
+
+static int map_liodn_subwins(int liodn, struct fsl_dma_domain *dma_domain)
Just call it map_subwins(). They are just sub windows, not liodn sub windows.
[cut]
+static int map_liodn_win(int liodn, struct fsl_dma_domain *dma_domain)
Call it map_win().
[cut]
+static struct fsl_dma_domain *iommu_alloc_dma_domain(void)
+{
+ struct fsl_dma_domain *domain;
+
+ domain = kmem_cache_zalloc(fsl_pamu_domain_cache, GFP_KERNEL);
+ if (!domain)
+ return NULL;
+
+ domain-stash_id = ~(u32)0;
+ domain-snoop_id = ~(u32)0;
+ domain-win_cnt = max_subwindow_count;
To align with my previous comments on fsl_pamu.c, I think instead of referencing
a global variable (in fsl_pamu.c) you should be making an accessor API
call here to get
the max subwindow _count.
+ domain-geom_size = 0;
+
+ INIT_LIST_HEAD(domain-devices);
+
+ spin_lock_init(domain-domain_lock);
+
+ return domain;
+}
+
+static inline struct device_domain_info *find_domain(struct device *dev)
+{
+ return dev-archdata.iommu_domain;
+}
+
+static void remove_domain_ref(struct device_domain_info *info, u32 win_cnt)
+{
+ list_del(info-link);
+ spin_lock(iommu_lock);
+ if (win_cnt)
+ pamu_free_subwins(info-liodn);
+ pamu_disable_liodn(info-liodn);
+ spin_unlock(iommu_lock);
+ spin_lock(device_domain_lock);
+ info-dev-archdata.iommu_domain = NULL;
+ kmem_cache_free(iommu_devinfo_cache, info);
+ spin_unlock(device_domain_lock);
+}
The above function is literally removing the _device_ reference from the domain.
The name implies that it is removing a domain reference. Suggestion is
to call it remove_device_ref.
Also, the whitespace is messed up there. You have 2 tabs instead of 1.
+static void destroy_domain(struct fsl_dma_domain *dma_domain)
+{
+ struct device_domain_info *info;
+
+ /* Dissociate all the devices from this domain */
+ while (!list_empty(dma_domain-devices)) {
+ info = list_entry(dma_domain-devices.next,
+ struct device_domain_info, link);
+ remove_domain_ref(info, dma_domain-win_cnt);
+ }
+}
This function is removing all devices from a domain...maybe to be
consistent with my
suggestion below on detach_domain(), call this detach_all_devices().
We have 2 functions
doing almost the same thingone detaches a single device, one
detaches all devices.
The current names destroy_domain and detach_domain are not as clear to me.
+static void detach_domain(struct device *dev, struct fsl_dma_domain
*dma_domain)
+{
+ struct device_domain_info *info;
+ struct list_head *entry, *tmp;
+ unsigned long flags;
+
+ spin_lock_irqsave(dma_domain-domain_lock, flags);
+ /* Remove the device from the domain device list */
+ if (!list_empty(dma_domain-devices)) {
+ list_for_each_safe(entry, tmp, dma_domain-devices) {
+ info = list_entry(entry, struct device_domain_info,
link);
+ if (info-dev == dev)
+ remove_domain_ref(info, dma_domain-win_cnt);
+ }
+ }
+ spin_unlock_irqrestore(dma_domain-domain_lock, flags);
+}
This function is not detaching a domain, but is detaching a device.
Call it detach_device().
+static void attach_domain(struct fsl_dma_domain *dma_domain, int liodn,
struct device *dev)
+{
Same thing here. This is not attaching a domain, but attaching a
device. Call it attach_device.
+ struct device_domain_info *info, *old_domain_info;
+
+ spin_lock(device_domain_lock);
Re: [PATCH 6/6 v8] iommu/fsl: Freescale PAMU driver and IOMMU API implementation.
Some more comments...
On Mon, Feb 18, 2013 at 6:52 AM, Varun Sethi varun.se...@freescale.com wrote:
+/* Handling access violations */
+#define make64(high, low) (((u64)(high) 32) | (low))
+
+struct pamu_isr_data {
+ void __iomem *pamu_reg_base;/* Base address of PAMU regs*/
+ unsigned int count; /* The number of PAMUs */
+};
+
+static struct paace *ppaact;
+static struct paace *spaact;
+static struct ome *omt;
+
+/* maximum subwindows permitted per liodn */
+unsigned int max_subwindow_count;
+/* Number of SPAACT entries */
+unsigned long max_subwins;
I don't like that these variables are not static... and they are
referenced directly
from code in fsl_pamu_domain.c. It would be better if fsl_pamu_domain.c
called an accessor function-- like pamu_get_max_subwins.
+/* Pool for fspi allocation */
+struct gen_pool *spaace_pool;
spaace_pool should be static?
I'm wondering if you should change pamu_isr_data into a more
general struct analagous to struct intel_iommu. You could
put in there the max # of subwins, etc. You could then
provide an accessor to get at that data.
[cut]
+/**
+ * pamu_get_fspi_and_allocate() - Allocates fspi index and reserves
subwindows
+ *required for primary PAACE in the secondary
+ *PAACE table.
+ * @subwin_cnt: Number of subwindows to be reserved.
+ *
+ * A PPAACE entry may have a number of associated subwindows. A subwindow
+ * corresponds to a SPAACE entry in the SPAACT table. Each PAACE entry stores
+ * the index (fspi) of the first SPAACE entry in the SPAACT table. This
+ * function returns the index of the first SPAACE entry. The remaining
+ * SPAACE entries are reserved contiguously from that index.
+ *
+ * Returns a valid fspi index in the range of 0 - max_subwins on success.
+ * If no SPAACE entry is available or the allocator can not reserve the
required
+ * number of contiguous entries function returns ULONG_MAX indicating a
failure.
+ *
+*/
+static unsigned long pamu_get_fspi_and_allocate(u32 subwin_cnt)
+{
+ unsigned long spaace_addr;
+
+ spaace_addr = gen_pool_alloc(spaace_pool, subwin_cnt * sizeof(struct
paace));
+ if (!spaace_addr)
+ return ULONG_MAX;
+
+ return (spaace_addr - (unsigned long)spaact) / (sizeof(struct paace));
+}
In order to keep things symmetric (with the free function) can we just
call the above
function:
pamu_alloc_subwins()
+/* Release the subwindows reserved for a particular LIODN */
+void pamu_free_subwins(int liodn)
+{
+ struct paace *ppaace;
+ u32 subwin_cnt, size;
+
+ ppaace = pamu_get_ppaace(liodn);
+ if (!ppaace) {
+ pr_err(Invalid liodn entry\n);
+ return;
+ }
+
+ if (get_bf(ppaace-addr_bitfields, PPAACE_AF_MW)) {
+ subwin_cnt = 1UL (get_bf(ppaace-impl_attr, PAACE_IA_WCE)
+ 1);
+ size = (subwin_cnt - 1) * sizeof(struct paace);
+ gen_pool_free(spaace_pool, (unsigned
long)spaact[ppaace-fspi], size);
+ set_bf(ppaace-addr_bitfields, PPAACE_AF_MW, 0);
+ }
+}
[cut]
+/**
+ * get_stash_id - Returns stash destination id corresponding to a
+ *cache type and vcpu.
+ * @stash_dest_hint: L1, L2 or L3
+ * @vcpu: vpcu target for a particular cache type.
+ *
+ * Returs stash on success or ~(u32)0 on failure.
+ *
+ */
+u32 get_stash_id(u32 stash_dest_hint, u32 vcpu)
+{
The stash dest is really not a hint, right? It's the requested stash
destination. So maybe just drop 'hint' from the name.
The CPU here is really a physical CPU number and has nothing to do
with vcpus I think. vcpu implies the index is inside a virtual machine...but
this API is generic and may or may not be used with KVM.
+
+/*
+ * Get the maximum number of PAACT table entries
+ * and subwindows supported by PAMU
+ */
+static void get_pamu_cap_values(unsigned long pamu_reg_base)
+{
+ u32 pc_val;
+
+ pc_val = in_be32((u32 *)(pamu_reg_base + PAMU_PC3));
+ /* Maximum number of subwindows per liodn */
+ max_subwindow_count = 1 (1 + PAMU_PC3_MWCE(pc_val));
+ /* Total number of SPACCT entries */
+ max_subwins = PAACE_NUMBER_ENTRIES * max_subwindow_count;
+}
If you follow the suggestion at the top of this file, this function
would become something like-- init_pamu_capabilities(). And then
create an accessor function to access max subwins, etc.
Also, BTW, I don't see any support for the DOMAIN_ATTR_WINDOWS
attribute in your patch. Was that coming in a later patch?
[cut
+static int __init fsl_pamu_probe(struct platform_device *pdev)
+{
+ void __iomem *pamu_regs = NULL;
+ struct ccsr_guts __iomem *guts_regs = NULL;
+ u32 pamubypenr, pamu_counter;
+ unsigned long pamu_reg_off;
+ unsigned long pamu_reg_base;
+ struct
Re: [PATCH 6/6 v8] iommu/fsl: Freescale PAMU driver and IOMMU API implementation.
Have not got through the entire file, but have a few comments...
+/*
+ * Set the PAACE type as primary and set the coherency required domain
+ * attribute
+ */
+static void pamu_setup_default_xfer_to_host_ppaace(struct paace *ppaace)
+{
+ set_bf(ppaace-addr_bitfields, PAACE_AF_PT, PAACE_PT_PRIMARY);
+
+ set_bf(ppaace-domain_attr.to_host.coherency_required, PAACE_DA_HOST_CR,
+ PAACE_M_COHERENCE_REQ);
+}
+
+/*
+ * Set the PAACE type as secondary and set the coherency required domain
+ * attribute.
+ */
+static void pamu_setup_default_xfer_to_host_spaace(struct paace *spaace)
+{
+ set_bf(spaace-addr_bitfields, PAACE_AF_PT, PAACE_PT_SECONDARY);
+ set_bf(spaace-domain_attr.to_host.coherency_required, PAACE_DA_HOST_CR,
+ PAACE_M_COHERENCE_REQ);
+}
Can we change the names of the above functions... I know there is some history
with the name, but xfer_to_host is confusing.
Maybe just call them:
pamu_init_paace()
pamu_init_spaace()
+/**
+ * pamu_config_spaace() - Sets up SPAACE entry for specified subwindow
+ *
+ * @liodn: Logical IO device number
+ * @subwin_cnt: number of sub-windows associated with dma-window
+ * @subwin_addr: starting address of subwindow
+ * @subwin_size: size of subwindow
+ * @omi: Operation mapping index
+ * @rpn: real (true physical) page number
+ * @snoopid: snoop id for hardware coherency -- if ~snoopid == 0 then
+ * snoopid not defined
+ * @stashid: cache stash id for associated cpu
+ * @enable: enable/disable subwindow after reconfiguration
+ * @prot: sub window permissions
+ *
+ * Returns 0 upon success else error code 0 returned
+ */
+int pamu_config_spaace(int liodn, u32 subwin_cnt, u32 subwin_addr,
+ phys_addr_t subwin_size, u32 omi, unsigned long rpn,
+ u32 snoopid, u32 stashid, int enable, int prot)
+{
+ struct paace *paace;
+
+ /* setup sub-windows */
+ if (!subwin_cnt) {
+ pr_err(Invalid subwindow count\n);
+ return -EINVAL;
+ }
+
+ paace = pamu_get_ppaace(liodn);
+ if (subwin_addr 0 subwin_addr subwin_cnt paace) {
Why is the comparison subwin_addr subwin_cnt? Seems wrong...
+ paace = pamu_get_spaace(paace, subwin_addr - 1);
+
+ if (paace !(paace-addr_bitfields PAACE_V_VALID)) {
+ pamu_setup_default_xfer_to_host_spaace(paace);
+ set_bf(paace-addr_bitfields, SPAACE_AF_LIODN, liodn);
+ }
+ }
+
+ if (!paace) {
+ pr_err(Invalid liodn entry\n);
+ return -ENOENT;
+ }
+
+ if (!enable prot == PAACE_AP_PERMS_DENIED) {
+ if (subwin_addr 0)
+ set_bf(paace-addr_bitfields, PAACE_AF_V,
+PAACE_V_INVALID);
+ else
+ set_bf(paace-addr_bitfields, PAACE_AF_AP,
+prot);
+ mb();
+ return 0;
+ }
Can you add a comment to the above if statement...when is this function called
with PAACE_AP_PERMS_DENIED?
+ if (subwin_size (subwin_size - 1) || subwin_size PAMU_PAGE_SIZE) {
+ pr_err(subwindow size out of range, or not a power of 2\n);
+ return -EINVAL;
+ }
+
+ if (rpn == ULONG_MAX) {
+ pr_err(real page number out of range\n);
+ return -EINVAL;
+ }
+
+ /* window size is 2^(WSE+1) bytes */
+ set_bf(paace-win_bitfields, PAACE_WIN_SWSE,
+ map_addrspace_size_to_wse(subwin_size));
+
+ set_bf(paace-impl_attr, PAACE_IA_ATM, PAACE_ATM_WINDOW_XLATE);
+ paace-twbah = rpn 20;
+ set_bf(paace-win_bitfields, PAACE_WIN_TWBAL, rpn);
+ set_bf(paace-addr_bitfields, PAACE_AF_AP, prot);
+
+ /* configure snoop id */
+ if (~snoopid != 0)
+ paace-domain_attr.to_host.snpid = snoopid;
+
+ /* set up operation mapping if it's configured */
+ if (omi OME_NUMBER_ENTRIES) {
+ set_bf(paace-impl_attr, PAACE_IA_OTM, PAACE_OTM_INDEXED);
+ paace-op_encode.index_ot.omi = omi;
+ } else if (~omi != 0) {
+ pr_err(bad operation mapping index: %d\n, omi);
+ return -EINVAL;
+ }
+
+ if (~stashid != 0)
+ set_bf(paace-impl_attr, PAACE_IA_CID, stashid);
+
+ smp_wmb();
+
+ if (enable)
+ paace-addr_bitfields |= PAACE_V_VALID;
+
+ mb();
+
+ return 0;
+}
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Re: [PATCH 2/6] powerpc/fsl_pci: Store the platform device information corresponding to the pci controller.
This patch was submitted separately to linuxppc-dev (and was already
applied). You don't need it in this patch set, right?
Stuart
On Mon, Feb 18, 2013 at 6:52 AM, Varun Sethi varun.se...@freescale.com wrote:
The pci controller structure has a provision to store the device strcuture
pointer of the corresponding platform device. Currently this information is
not stored during fsl pci controller initialization. This information is
required while dealing with iommu groups for pci devices connected to the fsl
pci controller. For the case where the pci devices can't be paritioned, they
would fall under the same device group as the pci controller.
This patch stores the platform device information in the pci controller
structure during initialization.
Signed-off-by: Varun Sethi varun.se...@freescale.com
---
arch/powerpc/sysdev/fsl_pci.c |9 +++--
arch/powerpc/sysdev/fsl_pci.h |2 +-
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 92a5915..b393ae7 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -421,13 +421,16 @@ void fsl_pcibios_fixup_bus(struct pci_bus *bus)
}
}
-int __init fsl_add_bridge(struct device_node *dev, int is_primary)
+int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
{
int len;
struct pci_controller *hose;
struct resource rsrc;
const int *bus_range;
u8 hdr_type, progif;
+ struct device_node *dev;
+
+ dev = pdev-dev.of_node;
if (!of_device_is_available(dev)) {
pr_warning(%s: disabled\n, dev-full_name);
@@ -453,6 +456,8 @@ int __init fsl_add_bridge(struct device_node *dev, int
is_primary)
if (!hose)
return -ENOMEM;
+ /* set platform device as the parent */
+ hose-parent = pdev-dev;
hose-first_busno = bus_range ? bus_range[0] : 0x0;
hose-last_busno = bus_range ? bus_range[1] : 0xff;
@@ -880,7 +885,7 @@ static int fsl_pci_probe(struct platform_device *pdev)
#endif
node = pdev-dev.of_node;
- ret = fsl_add_bridge(node, fsl_pci_primary == node);
+ ret = fsl_add_bridge(pdev, fsl_pci_primary == node);
#ifdef CONFIG_SWIOTLB
if (ret == 0) {
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
index d078537..c495c00 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -91,7 +91,7 @@ struct ccsr_pci {
__be32 pex_err_cap_r3; /* 0x.e34 - PCIE error capture
register 0 */
};
-extern int fsl_add_bridge(struct device_node *dev, int is_primary);
+extern int fsl_add_bridge(struct platform_device *pdev, int is_primary);
extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
extern int mpc83xx_add_bridge(struct device_node *dev);
u64 fsl_pci_immrbar_base(struct pci_controller *hose);
--
1.7.4.1
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Re: [PATCH][RFC] Replaced tlbilx with tlbwe in the initialization code
On Tue, Feb 19, 2013 at 1:47 PM, Scott Wood scottw...@freescale.com wrote: This patch addresses boot-time invalidations only. How will you handle hugetlb invalidations (or indirect entry invalidations, once that becomes supported)? We do envision that direct guest TLB management is an opt-in option that a guest can enable. If LRAT is on, with TLB management directly handled by guests, the only mechanism we have to do TLB1 invalidates is tlbwe. That is our only option as far as I know. So, hugetlb and indirect entries will each need to be addressed separately.The kernel code that handles these either needs to be A) modified to unconditionally do all invalidates by tlbwe or B) conditionally use tlbwe depending on whether this is a guest that has enabled direct TLB management. Stuart ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH][v4] PPC: add paravirt idle loop for 64-bit book E
From: Stuart Yoder stuart.yo...@freescale.com Signed-off-by: Stuart Yoder stuart.yo...@freescale.com --- -removed KVM prefix to patch subject, patch is not KVM specific arch/powerpc/kernel/epapr_hcalls.S |2 ++ arch/powerpc/kernel/idle_book3e.S | 32 ++-- 2 files changed, 32 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/kernel/epapr_hcalls.S b/arch/powerpc/kernel/epapr_hcalls.S index 62c0dc2..9f1ebf7 100644 --- a/arch/powerpc/kernel/epapr_hcalls.S +++ b/arch/powerpc/kernel/epapr_hcalls.S @@ -17,6 +17,7 @@ #include asm/asm-compat.h #include asm/asm-offsets.h +#ifndef CONFIG_PPC64 /* epapr_ev_idle() was derived from e500_idle() */ _GLOBAL(epapr_ev_idle) CURRENT_THREAD_INFO(r3, r1) @@ -42,6 +43,7 @@ epapr_ev_idle_start: * _TLF_NAPPING. */ b idle_loop +#endif /* Hypercall entry point. Will be patched with device tree instructions. */ .global epapr_hypercall_start diff --git a/arch/powerpc/kernel/idle_book3e.S b/arch/powerpc/kernel/idle_book3e.S index 4c7cb400..bfb73cc 100644 --- a/arch/powerpc/kernel/idle_book3e.S +++ b/arch/powerpc/kernel/idle_book3e.S @@ -16,11 +16,13 @@ #include asm/ppc-opcode.h #include asm/processor.h #include asm/thread_info.h +#include asm/epapr_hcalls.h /* 64-bit version only for now */ #ifdef CONFIG_PPC64 -_GLOBAL(book3e_idle) +.macro BOOK3E_IDLE name loop +_GLOBAL(\name) /* Save LR for later */ mflrr0 std r0,16(r1) @@ -67,7 +69,33 @@ _GLOBAL(book3e_idle) /* We can now re-enable hard interrupts and go to sleep */ wrteei 1 -1: PPC_WAIT(0) + \loop + +.endm + +.macro BOOK3E_IDLE_LOOP +1: + PPC_WAIT(0) b 1b +.endm + +/* epapr_ev_idle_start below is patched with the proper hcall + opcodes during kernel initialization */ +.macro EPAPR_EV_IDLE_LOOP +idle_loop: + LOAD_REG_IMMEDIATE(r11, EV_HCALL_TOKEN(EV_IDLE)) + +.global epapr_ev_idle_start +epapr_ev_idle_start: + li r3, -1 + nop + nop + nop + b idle_loop +.endm + +BOOK3E_IDLE epapr_ev_idle EPAPR_EV_IDLE_LOOP + +BOOK3E_IDLE book3e_idle BOOK3E_IDLE_LOOP #endif /* CONFIG_PPC64 */ -- 1.7.9.7 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH][v3] KVM: PPC: add paravirt idle loop for 64-bit book E
From: Stuart Yoder stuart.yo...@freescale.com Signed-off-by: Stuart Yoder stuart.yo...@freescale.com --- -v3 -whitespace cleanup, deleted stray comma, added comment arch/powerpc/kernel/epapr_hcalls.S |2 ++ arch/powerpc/kernel/idle_book3e.S | 32 ++-- 2 files changed, 32 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/kernel/epapr_hcalls.S b/arch/powerpc/kernel/epapr_hcalls.S index 62c0dc2..9f1ebf7 100644 --- a/arch/powerpc/kernel/epapr_hcalls.S +++ b/arch/powerpc/kernel/epapr_hcalls.S @@ -17,6 +17,7 @@ #include asm/asm-compat.h #include asm/asm-offsets.h +#ifndef CONFIG_PPC64 /* epapr_ev_idle() was derived from e500_idle() */ _GLOBAL(epapr_ev_idle) CURRENT_THREAD_INFO(r3, r1) @@ -42,6 +43,7 @@ epapr_ev_idle_start: * _TLF_NAPPING. */ b idle_loop +#endif /* Hypercall entry point. Will be patched with device tree instructions. */ .global epapr_hypercall_start diff --git a/arch/powerpc/kernel/idle_book3e.S b/arch/powerpc/kernel/idle_book3e.S index 4c7cb400..bfb73cc 100644 --- a/arch/powerpc/kernel/idle_book3e.S +++ b/arch/powerpc/kernel/idle_book3e.S @@ -16,11 +16,13 @@ #include asm/ppc-opcode.h #include asm/processor.h #include asm/thread_info.h +#include asm/epapr_hcalls.h /* 64-bit version only for now */ #ifdef CONFIG_PPC64 -_GLOBAL(book3e_idle) +.macro BOOK3E_IDLE name loop +_GLOBAL(\name) /* Save LR for later */ mflrr0 std r0,16(r1) @@ -67,7 +69,33 @@ _GLOBAL(book3e_idle) /* We can now re-enable hard interrupts and go to sleep */ wrteei 1 -1: PPC_WAIT(0) + \loop + +.endm + +.macro BOOK3E_IDLE_LOOP +1: + PPC_WAIT(0) b 1b +.endm + +/* epapr_ev_idle_start below is patched with the proper hcall + opcodes during kernel initialization */ +.macro EPAPR_EV_IDLE_LOOP +idle_loop: + LOAD_REG_IMMEDIATE(r11, EV_HCALL_TOKEN(EV_IDLE)) + +.global epapr_ev_idle_start +epapr_ev_idle_start: + li r3, -1 + nop + nop + nop + b idle_loop +.endm + +BOOK3E_IDLE epapr_ev_idle EPAPR_EV_IDLE_LOOP + +BOOK3E_IDLE book3e_idle BOOK3E_IDLE_LOOP #endif /* CONFIG_PPC64 */ -- 1.7.9.7 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH][v2] KVM: PPC: add paravirt idle loop for 64-bit book E
From: Stuart Yoder stuart.yo...@freescale.com Signed-off-by: Stuart Yoder stuart.yo...@freescale.com --- -v2 -macro'ized loop in idle_book3e.S to avoid code duplication, paravirt loop is now in idle_book3e.S arch/powerpc/kernel/epapr_hcalls.S |2 ++ arch/powerpc/kernel/idle_book3e.S | 30 -- 2 files changed, 30 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/kernel/epapr_hcalls.S b/arch/powerpc/kernel/epapr_hcalls.S index 62c0dc2..9f1ebf7 100644 --- a/arch/powerpc/kernel/epapr_hcalls.S +++ b/arch/powerpc/kernel/epapr_hcalls.S @@ -17,6 +17,7 @@ #include asm/asm-compat.h #include asm/asm-offsets.h +#ifndef CONFIG_PPC64 /* epapr_ev_idle() was derived from e500_idle() */ _GLOBAL(epapr_ev_idle) CURRENT_THREAD_INFO(r3, r1) @@ -42,6 +43,7 @@ epapr_ev_idle_start: * _TLF_NAPPING. */ b idle_loop +#endif /* Hypercall entry point. Will be patched with device tree instructions. */ .global epapr_hypercall_start diff --git a/arch/powerpc/kernel/idle_book3e.S b/arch/powerpc/kernel/idle_book3e.S index 4c7cb400..e1c9acd 100644 --- a/arch/powerpc/kernel/idle_book3e.S +++ b/arch/powerpc/kernel/idle_book3e.S @@ -16,11 +16,13 @@ #include asm/ppc-opcode.h #include asm/processor.h #include asm/thread_info.h +#include asm/epapr_hcalls.h /* 64-bit version only for now */ #ifdef CONFIG_PPC64 -_GLOBAL(book3e_idle) +.macro BOOK3E_IDLE name loop +_GLOBAL(\name) /* Save LR for later */ mflrr0 std r0,16(r1) @@ -67,7 +69,31 @@ _GLOBAL(book3e_idle) /* We can now re-enable hard interrupts and go to sleep */ wrteei 1 -1: PPC_WAIT(0) + \loop + +.endm + +.macro BOOK3E_IDLE_LOOP +1: + PPC_WAIT(0) b 1b +.endm + +.macro EPAPR_EV_IDLE_LOOP +idle_loop: + LOAD_REG_IMMEDIATE(r11, EV_HCALL_TOKEN(EV_IDLE)) + +.global epapr_ev_idle_start +epapr_ev_idle_start: + li r3, -1 + nop + nop + nop + b idle_loop +.endm + +BOOK3E_IDLE epapr_ev_idle, EPAPR_EV_IDLE_LOOP + +BOOK3E_IDLE book3e_idle BOOK3E_IDLE_LOOP #endif /* CONFIG_PPC64 */ -- 1.7.9.7 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] KVM: PPC: add paravirt idle loop for 64-bit book E
From: Stuart Yoder stuart.yo...@freescale.com loop was derived from book3e_idle() Signed-off-by: Stuart Yoder stuart.yo...@freescale.com --- arch/powerpc/kernel/epapr_hcalls.S | 63 1 file changed, 63 insertions(+) diff --git a/arch/powerpc/kernel/epapr_hcalls.S b/arch/powerpc/kernel/epapr_hcalls.S index 62c0dc2..6a46bfb 100644 --- a/arch/powerpc/kernel/epapr_hcalls.S +++ b/arch/powerpc/kernel/epapr_hcalls.S @@ -17,6 +17,68 @@ #include asm/asm-compat.h #include asm/asm-offsets.h +#ifdef CONFIG_PPC64 +/* epapr_ev_idle() was derived from book3e_idle() */ +_GLOBAL(epapr_ev_idle) + /* Save LR for later */ + mflrr0 + std r0,16(r1) + + /* Hard disable interrupts */ + wrteei 0 + + /* Now check if an interrupt came in while we were soft disabled +* since we may otherwise lose it (doorbells etc...). +*/ + lbz r3,PACAIRQHAPPENED(r13) + cmpwi cr0,r3,0 + bnelr + + /* Now we are going to mark ourselves as soft and hard enabled in +* order to be able to take interrupts while asleep. We inform lockdep +* of that. We don't actually turn interrupts on just yet tho. +*/ +#ifdef CONFIG_TRACE_IRQFLAGS + stdur1,-128(r1) + bl .trace_hardirqs_on + addir1,r1,128 +#endif + li r0,1 + stb r0,PACASOFTIRQEN(r13) + + /* Interrupts will make use return to LR, so get something we want +* in there +*/ + bl 1f + + /* And return (interrupts are on) */ + ld r0,16(r1) + mtlrr0 + blr + +1: /* Let's set the _TLF_NAPPING flag so interrupts make us return +* to the right spot + */ + CURRENT_THREAD_INFO(r11, r1) + ld r10,TI_LOCAL_FLAGS(r11) + ori r10,r10,_TLF_NAPPING + std r10,TI_LOCAL_FLAGS(r11) + + /* We can now re-enable hard interrupts and go to sleep */ + wrteei 1 +idle_loop: + LOAD_REG_IMMEDIATE(r11, EV_HCALL_TOKEN(EV_IDLE)) + +.global epapr_ev_idle_start +epapr_ev_idle_start: + li r3, -1 + nop + nop + nop + b idle_loop + +#else /* CONFIG_PPC64 */ + /* epapr_ev_idle() was derived from e500_idle() */ _GLOBAL(epapr_ev_idle) CURRENT_THREAD_INFO(r3, r1) @@ -42,6 +104,7 @@ epapr_ev_idle_start: * _TLF_NAPPING. */ b idle_loop +#endif /* Hypercall entry point. Will be patched with device tree instructions. */ .global epapr_hypercall_start -- 1.7.9.7 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc: set stack limit properly in crit_transfer_to_handler
From: Stuart Yoder stuart.yo...@freescale.com without setting the stack limit like this there is the possibility of stack overflow which corrupts the thread info but is not detected by stack overflow detection Signed-off-by: Stuart Yoder stuart.yo...@freescale.com --- arch/powerpc/kernel/entry_32.S | 12 ++-- 1 files changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S index 5207d5a..ead5016 100644 --- a/arch/powerpc/kernel/entry_32.S +++ b/arch/powerpc/kernel/entry_32.S @@ -89,10 +89,14 @@ crit_transfer_to_handler: mfspr r0,SPRN_SRR1 stw r0,_SRR1(r11) + /* set the stack limit to the current stack +* and set the limit to protect the thread_info +* struct +*/ mfspr r8,SPRN_SPRG_THREAD lwz r0,KSP_LIMIT(r8) stw r0,SAVED_KSP_LIMIT(r11) - CURRENT_THREAD_INFO(r0, r1) + rlwimi r0,r1,0,0,(31-THREAD_SHIFT) stw r0,KSP_LIMIT(r8) /* fall through */ #endif @@ -109,10 +113,14 @@ crit_transfer_to_handler: mfspr r0,SPRN_SRR1 stw r0,crit_srr1@l(0) + /* set the stack limit to the current stack +* and set the limit to protect the thread_info +* struct +*/ mfspr r8,SPRN_SPRG_THREAD lwz r0,KSP_LIMIT(r8) stw r0,saved_ksp_limit@l(0) - CURRENT_THREAD_INFO(r0, r1) + rlwimi r0,r1,0,0,(31-THREAD_SHIFT) stw r0,KSP_LIMIT(r8) /* fall through */ #endif -- 1.7.3.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v4] PPC: use CURRENT_THREAD_INFO instead of open coded assembly
From: Stuart Yoder stuart.yo...@freescale.com Signed-off-by: Stuart Yoder stuart.yo...@freescale.com --- -v4: fixed build issues in exception-64s.h and exceptions-64s.S arch/powerpc/include/asm/exception-64s.h |4 ++-- arch/powerpc/include/asm/thread_info.h |6 ++ arch/powerpc/kernel/entry_32.S | 24 arch/powerpc/kernel/entry_64.S | 14 +++--- arch/powerpc/kernel/exceptions-64e.S |2 +- arch/powerpc/kernel/exceptions-64s.S |2 +- arch/powerpc/kernel/head_fsl_booke.S |2 +- arch/powerpc/kernel/idle_6xx.S |4 ++-- arch/powerpc/kernel/idle_book3e.S|2 +- arch/powerpc/kernel/idle_e500.S |4 ++-- arch/powerpc/kernel/idle_power4.S|2 +- arch/powerpc/kernel/misc_32.S|4 ++-- arch/powerpc/kvm/bookehv_interrupts.S|6 +- arch/powerpc/mm/hash_low_32.S|8 arch/powerpc/sysdev/6xx-suspend.S|2 +- 15 files changed, 44 insertions(+), 42 deletions(-) diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h index d58fc4e..a43c147 100644 --- a/arch/powerpc/include/asm/exception-64s.h +++ b/arch/powerpc/include/asm/exception-64s.h @@ -293,7 +293,7 @@ label##_hv: \ #define RUNLATCH_ON\ BEGIN_FTR_SECTION \ - clrrdi r3,r1,THREAD_SHIFT; \ + CURRENT_THREAD_INFO(r3, r1);\ ld r4,TI_LOCAL_FLAGS(r3); \ andi. r0,r4,_TLF_RUNLATCH;\ beqlppc64_runlatch_on_trampoline; \ @@ -332,7 +332,7 @@ label##_common: \ #ifdef CONFIG_PPC_970_NAP #define FINISH_NAP \ BEGIN_FTR_SECTION \ - clrrdi r11,r1,THREAD_SHIFT;\ + CURRENT_THREAD_INFO(r11, r1); \ ld r9,TI_LOCAL_FLAGS(r11); \ andi. r10,r9,_TLF_NAPPING;\ bnelpower4_fixup_nap; \ diff --git a/arch/powerpc/include/asm/thread_info.h b/arch/powerpc/include/asm/thread_info.h index 68831e9..faf9352 100644 --- a/arch/powerpc/include/asm/thread_info.h +++ b/arch/powerpc/include/asm/thread_info.h @@ -22,6 +22,12 @@ #define THREAD_SIZE(1 THREAD_SHIFT) +#ifdef CONFIG_PPC64 +#define CURRENT_THREAD_INFO(dest, sp) clrrdi dest, sp, THREAD_SHIFT +#else +#define CURRENT_THREAD_INFO(dest, sp) rlwinm dest, sp, 0, 0, 31-THREAD_SHIFT +#endif + #ifndef __ASSEMBLY__ #include linux/cache.h #include asm/processor.h diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S index ba3aeb4..bad42e3 100644 --- a/arch/powerpc/kernel/entry_32.S +++ b/arch/powerpc/kernel/entry_32.S @@ -92,7 +92,7 @@ crit_transfer_to_handler: mfspr r8,SPRN_SPRG_THREAD lwz r0,KSP_LIMIT(r8) stw r0,SAVED_KSP_LIMIT(r11) - rlwimi r0,r1,0,0,(31-THREAD_SHIFT) + CURRENT_THREAD_INFO(r0, r1) stw r0,KSP_LIMIT(r8) /* fall through */ #endif @@ -112,7 +112,7 @@ crit_transfer_to_handler: mfspr r8,SPRN_SPRG_THREAD lwz r0,KSP_LIMIT(r8) stw r0,saved_ksp_limit@l(0) - rlwimi r0,r1,0,0,(31-THREAD_SHIFT) + CURRENT_THREAD_INFO(r0, r1) stw r0,KSP_LIMIT(r8) /* fall through */ #endif @@ -158,7 +158,7 @@ transfer_to_handler: tophys(r11,r11) addir11,r11,global_dbcr0@l #ifdef CONFIG_SMP - rlwinm r9,r1,0,0,(31-THREAD_SHIFT) + CURRENT_THREAD_INFO(r9, r1) lwz r9,TI_CPU(r9) slwir9,r9,3 add r11,r11,r9 @@ -179,7 +179,7 @@ transfer_to_handler: ble-stack_ovf /* then the kernel stack overflowed */ 5: #if defined(CONFIG_6xx) || defined(CONFIG_E500) - rlwinm r9,r1,0,0,31-THREAD_SHIFT + CURRENT_THREAD_INFO(r9, r1) tophys(r9,r9) /* check local flags */ lwz r12,TI_LOCAL_FLAGS(r9) mtcrf 0x01,r12 @@ -333,7 +333,7 @@ _GLOBAL(DoSyscall) mtmsr r11 1: #endif /* CONFIG_TRACE_IRQFLAGS */ - rlwinm r10,r1,0,0,(31-THREAD_SHIFT)/* current_thread_info() */ + CURRENT_THREAD_INFO(r10, r1) lwz r11,TI_FLAGS(r10) andi. r11,r11,_TIF_SYSCALL_T_OR_A bne-syscall_dotrace @@ -354,7 +354,7 @@ ret_from_syscall: bl do_show_syscall_exit #endif mr r6,r3 - rlwinm r12,r1,0,0,(31-THREAD_SHIFT)/* current_thread_info() */ + CURRENT_THREAD_INFO(r12, r1) /* disable interrupts so current_thread_info()-flags can't change */ LOAD_MSR_KERNEL(r10,MSR_KERNEL) /* doesn't include MSR_EE */ /* Note: We don't bother telling lockdep about it */ @@ -815,7 +815,7 @@ ret_from_except: user_exc_return
[PATCH][v3] PPC: use CURRENT_THREAD_INFO instead of open coded assembly
From: Stuart Yoder stuart.yo...@freescale.com Signed-off-by: Stuart Yoder stuart.yo...@freescale.com --- -v3 -moved CURRENT_THREAD_INFO out from under the assembly only #define as per comments on mailing list -reversed logic of 64-bit #ifdef for CURRENT_THREAD_INFO macro -this patch is a pre-requisite for the idle hcall which I am trying to get into Alex's KVM tree, so ideally would like Ben's ack and get this applied to Alex's tree -built/tested with a 32-bit booke kernel, built a 64-bit booke kernel arch/powerpc/include/asm/exception-64s.h |4 ++-- arch/powerpc/include/asm/thread_info.h |6 ++ arch/powerpc/kernel/entry_32.S | 24 arch/powerpc/kernel/entry_64.S | 14 +++--- arch/powerpc/kernel/exceptions-64e.S |2 +- arch/powerpc/kernel/exceptions-64s.S |2 +- arch/powerpc/kernel/head_fsl_booke.S |2 +- arch/powerpc/kernel/idle_6xx.S |4 ++-- arch/powerpc/kernel/idle_book3e.S|2 +- arch/powerpc/kernel/idle_e500.S |4 ++-- arch/powerpc/kernel/idle_power4.S|2 +- arch/powerpc/kernel/misc_32.S|4 ++-- arch/powerpc/kvm/bookehv_interrupts.S|6 +- arch/powerpc/mm/hash_low_32.S|8 arch/powerpc/sysdev/6xx-suspend.S|2 +- 15 files changed, 44 insertions(+), 42 deletions(-) diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h index d58fc4e..5dbd00d 100644 --- a/arch/powerpc/include/asm/exception-64s.h +++ b/arch/powerpc/include/asm/exception-64s.h @@ -293,7 +293,7 @@ label##_hv: \ #define RUNLATCH_ON\ BEGIN_FTR_SECTION \ - clrrdi r3,r1,THREAD_SHIFT; \ + CURRENT_THREAD_INFO(r3, r1) \ ld r4,TI_LOCAL_FLAGS(r3); \ andi. r0,r4,_TLF_RUNLATCH;\ beqlppc64_runlatch_on_trampoline; \ @@ -332,7 +332,7 @@ label##_common: \ #ifdef CONFIG_PPC_970_NAP #define FINISH_NAP \ BEGIN_FTR_SECTION \ - clrrdi r11,r1,THREAD_SHIFT;\ + CURRENT_THREAD_INFO(r11, r1)\ ld r9,TI_LOCAL_FLAGS(r11); \ andi. r10,r9,_TLF_NAPPING;\ bnelpower4_fixup_nap; \ diff --git a/arch/powerpc/include/asm/thread_info.h b/arch/powerpc/include/asm/thread_info.h index 68831e9..faf9352 100644 --- a/arch/powerpc/include/asm/thread_info.h +++ b/arch/powerpc/include/asm/thread_info.h @@ -22,6 +22,12 @@ #define THREAD_SIZE(1 THREAD_SHIFT) +#ifdef CONFIG_PPC64 +#define CURRENT_THREAD_INFO(dest, sp) clrrdi dest, sp, THREAD_SHIFT +#else +#define CURRENT_THREAD_INFO(dest, sp) rlwinm dest, sp, 0, 0, 31-THREAD_SHIFT +#endif + #ifndef __ASSEMBLY__ #include linux/cache.h #include asm/processor.h diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S index ba3aeb4..bad42e3 100644 --- a/arch/powerpc/kernel/entry_32.S +++ b/arch/powerpc/kernel/entry_32.S @@ -92,7 +92,7 @@ crit_transfer_to_handler: mfspr r8,SPRN_SPRG_THREAD lwz r0,KSP_LIMIT(r8) stw r0,SAVED_KSP_LIMIT(r11) - rlwimi r0,r1,0,0,(31-THREAD_SHIFT) + CURRENT_THREAD_INFO(r0, r1) stw r0,KSP_LIMIT(r8) /* fall through */ #endif @@ -112,7 +112,7 @@ crit_transfer_to_handler: mfspr r8,SPRN_SPRG_THREAD lwz r0,KSP_LIMIT(r8) stw r0,saved_ksp_limit@l(0) - rlwimi r0,r1,0,0,(31-THREAD_SHIFT) + CURRENT_THREAD_INFO(r0, r1) stw r0,KSP_LIMIT(r8) /* fall through */ #endif @@ -158,7 +158,7 @@ transfer_to_handler: tophys(r11,r11) addir11,r11,global_dbcr0@l #ifdef CONFIG_SMP - rlwinm r9,r1,0,0,(31-THREAD_SHIFT) + CURRENT_THREAD_INFO(r9, r1) lwz r9,TI_CPU(r9) slwir9,r9,3 add r11,r11,r9 @@ -179,7 +179,7 @@ transfer_to_handler: ble-stack_ovf /* then the kernel stack overflowed */ 5: #if defined(CONFIG_6xx) || defined(CONFIG_E500) - rlwinm r9,r1,0,0,31-THREAD_SHIFT + CURRENT_THREAD_INFO(r9, r1) tophys(r9,r9) /* check local flags */ lwz r12,TI_LOCAL_FLAGS(r9) mtcrf 0x01,r12 @@ -333,7 +333,7 @@ _GLOBAL(DoSyscall) mtmsr r11 1: #endif /* CONFIG_TRACE_IRQFLAGS */ - rlwinm r10,r1,0,0,(31-THREAD_SHIFT)/* current_thread_info() */ + CURRENT_THREAD_INFO(r10, r1) lwz r11,TI_FLAGS(r10) andi. r11,r11,_TIF_SYSCALL_T_OR_A bne-syscall_dotrace @@ -354,7 +354,7 @@ ret_from_syscall: bl do_show_syscall_exit #endif mr r6,r3 - rlwinm r12
[PATCH] PPC: use CURRENT_THREAD_INFO instead of open coded assembly
From: Stuart Yoder stuart.yo...@freescale.com Signed-off-by: Stuart Yoder stuart.yo...@freescale.com --- -this patch is a pre-requisite for the idle hcall which I am trying to get into Alex's KVM tree, so ideally would like Ben's ack and get this applied to Alex's tree -built/tested with a 32-bit booke kernel, built a 64-bit booke kernel arch/powerpc/include/asm/exception-64s.h |4 ++-- arch/powerpc/include/asm/thread_info.h |6 ++ arch/powerpc/kernel/entry_32.S | 24 arch/powerpc/kernel/entry_64.S | 14 +++--- arch/powerpc/kernel/exceptions-64e.S |2 +- arch/powerpc/kernel/exceptions-64s.S |2 +- arch/powerpc/kernel/head_fsl_booke.S |2 +- arch/powerpc/kernel/idle_6xx.S |4 ++-- arch/powerpc/kernel/idle_book3e.S|2 +- arch/powerpc/kernel/idle_e500.S |4 ++-- arch/powerpc/kernel/idle_power4.S|2 +- arch/powerpc/kernel/misc_32.S|4 ++-- arch/powerpc/kvm/bookehv_interrupts.S|6 +- arch/powerpc/mm/hash_low_32.S|8 arch/powerpc/sysdev/6xx-suspend.S|2 +- 15 files changed, 44 insertions(+), 42 deletions(-) diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h index d58fc4e..5dbd00d 100644 --- a/arch/powerpc/include/asm/exception-64s.h +++ b/arch/powerpc/include/asm/exception-64s.h @@ -293,7 +293,7 @@ label##_hv: \ #define RUNLATCH_ON\ BEGIN_FTR_SECTION \ - clrrdi r3,r1,THREAD_SHIFT; \ + CURRENT_THREAD_INFO(r3, r1) \ ld r4,TI_LOCAL_FLAGS(r3); \ andi. r0,r4,_TLF_RUNLATCH;\ beqlppc64_runlatch_on_trampoline; \ @@ -332,7 +332,7 @@ label##_common: \ #ifdef CONFIG_PPC_970_NAP #define FINISH_NAP \ BEGIN_FTR_SECTION \ - clrrdi r11,r1,THREAD_SHIFT;\ + CURRENT_THREAD_INFO(r11, r1)\ ld r9,TI_LOCAL_FLAGS(r11); \ andi. r10,r9,_TLF_NAPPING;\ bnelpower4_fixup_nap; \ diff --git a/arch/powerpc/include/asm/thread_info.h b/arch/powerpc/include/asm/thread_info.h index 68831e9..2e7bc3c 100644 --- a/arch/powerpc/include/asm/thread_info.h +++ b/arch/powerpc/include/asm/thread_info.h @@ -22,6 +22,12 @@ #define THREAD_SIZE(1 THREAD_SHIFT) +#ifndef CONFIG_PPC64 +#define CURRENT_THREAD_INFO(dest, sp) rlwinm dest, sp, 0, 0, 31-THREAD_SHIFT +#else +#define CURRENT_THREAD_INFO(dest, sp) clrrdi dest, sp, THREAD_SHIFT +#endif + #ifndef __ASSEMBLY__ #include linux/cache.h #include asm/processor.h diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S index ba3aeb4..bad42e3 100644 --- a/arch/powerpc/kernel/entry_32.S +++ b/arch/powerpc/kernel/entry_32.S @@ -92,7 +92,7 @@ crit_transfer_to_handler: mfspr r8,SPRN_SPRG_THREAD lwz r0,KSP_LIMIT(r8) stw r0,SAVED_KSP_LIMIT(r11) - rlwimi r0,r1,0,0,(31-THREAD_SHIFT) + CURRENT_THREAD_INFO(r0, r1) stw r0,KSP_LIMIT(r8) /* fall through */ #endif @@ -112,7 +112,7 @@ crit_transfer_to_handler: mfspr r8,SPRN_SPRG_THREAD lwz r0,KSP_LIMIT(r8) stw r0,saved_ksp_limit@l(0) - rlwimi r0,r1,0,0,(31-THREAD_SHIFT) + CURRENT_THREAD_INFO(r0, r1) stw r0,KSP_LIMIT(r8) /* fall through */ #endif @@ -158,7 +158,7 @@ transfer_to_handler: tophys(r11,r11) addir11,r11,global_dbcr0@l #ifdef CONFIG_SMP - rlwinm r9,r1,0,0,(31-THREAD_SHIFT) + CURRENT_THREAD_INFO(r9, r1) lwz r9,TI_CPU(r9) slwir9,r9,3 add r11,r11,r9 @@ -179,7 +179,7 @@ transfer_to_handler: ble-stack_ovf /* then the kernel stack overflowed */ 5: #if defined(CONFIG_6xx) || defined(CONFIG_E500) - rlwinm r9,r1,0,0,31-THREAD_SHIFT + CURRENT_THREAD_INFO(r9, r1) tophys(r9,r9) /* check local flags */ lwz r12,TI_LOCAL_FLAGS(r9) mtcrf 0x01,r12 @@ -333,7 +333,7 @@ _GLOBAL(DoSyscall) mtmsr r11 1: #endif /* CONFIG_TRACE_IRQFLAGS */ - rlwinm r10,r1,0,0,(31-THREAD_SHIFT)/* current_thread_info() */ + CURRENT_THREAD_INFO(r10, r1) lwz r11,TI_FLAGS(r10) andi. r11,r11,_TIF_SYSCALL_T_OR_A bne-syscall_dotrace @@ -354,7 +354,7 @@ ret_from_syscall: bl do_show_syscall_exit #endif mr r6,r3 - rlwinm r12,r1,0,0,(31-THREAD_SHIFT)/* current_thread_info() */ + CURRENT_THREAD_INFO(r12, r1) /* disable interrupts so current_thread_info()-flags can't change
[PATCH][v2] PPC: use CURRENT_THREAD_INFO instead of open coded assembly
From: Stuart Yoder stuart.yo...@freescale.com Signed-off-by: Stuart Yoder stuart.yo...@freescale.com --- -this patch is a pre-requisite for the idle hcall which I am trying to get into Alex's KVM tree, so ideally would like Ben's ack and get this applied to Alex's tree -built/tested with a 32-bit booke kernel, built a 64-bit booke kernel -v2 -moved CURRENT_THREAD_INFO under assembly only #ifdef arch/powerpc/include/asm/exception-64s.h |4 ++-- arch/powerpc/include/asm/thread_info.h |8 arch/powerpc/kernel/entry_32.S | 24 arch/powerpc/kernel/entry_64.S | 14 +++--- arch/powerpc/kernel/exceptions-64e.S |2 +- arch/powerpc/kernel/exceptions-64s.S |2 +- arch/powerpc/kernel/head_fsl_booke.S |2 +- arch/powerpc/kernel/idle_6xx.S |4 ++-- arch/powerpc/kernel/idle_book3e.S|2 +- arch/powerpc/kernel/idle_e500.S |4 ++-- arch/powerpc/kernel/idle_power4.S|2 +- arch/powerpc/kernel/misc_32.S|4 ++-- arch/powerpc/kvm/bookehv_interrupts.S|6 +- arch/powerpc/mm/hash_low_32.S|8 arch/powerpc/sysdev/6xx-suspend.S|2 +- 15 files changed, 46 insertions(+), 42 deletions(-) diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h index d58fc4e..5dbd00d 100644 --- a/arch/powerpc/include/asm/exception-64s.h +++ b/arch/powerpc/include/asm/exception-64s.h @@ -293,7 +293,7 @@ label##_hv: \ #define RUNLATCH_ON\ BEGIN_FTR_SECTION \ - clrrdi r3,r1,THREAD_SHIFT; \ + CURRENT_THREAD_INFO(r3, r1) \ ld r4,TI_LOCAL_FLAGS(r3); \ andi. r0,r4,_TLF_RUNLATCH;\ beqlppc64_runlatch_on_trampoline; \ @@ -332,7 +332,7 @@ label##_common: \ #ifdef CONFIG_PPC_970_NAP #define FINISH_NAP \ BEGIN_FTR_SECTION \ - clrrdi r11,r1,THREAD_SHIFT;\ + CURRENT_THREAD_INFO(r11, r1)\ ld r9,TI_LOCAL_FLAGS(r11); \ andi. r10,r9,_TLF_NAPPING;\ bnelpower4_fixup_nap; \ diff --git a/arch/powerpc/include/asm/thread_info.h b/arch/powerpc/include/asm/thread_info.h index 68831e9..3760620 100644 --- a/arch/powerpc/include/asm/thread_info.h +++ b/arch/powerpc/include/asm/thread_info.h @@ -74,6 +74,14 @@ static inline struct thread_info *current_thread_info(void) return (struct thread_info *)(sp ~(THREAD_SIZE-1)); } +#else + +#ifndef CONFIG_PPC64 +#define CURRENT_THREAD_INFO(dest, sp) rlwinm dest, sp, 0, 0, 31-THREAD_SHIFT +#else +#define CURRENT_THREAD_INFO(dest, sp) clrrdi dest, sp, THREAD_SHIFT +#endif + #endif /* __ASSEMBLY__ */ #define PREEMPT_ACTIVE 0x1000 diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S index ba3aeb4..bad42e3 100644 --- a/arch/powerpc/kernel/entry_32.S +++ b/arch/powerpc/kernel/entry_32.S @@ -92,7 +92,7 @@ crit_transfer_to_handler: mfspr r8,SPRN_SPRG_THREAD lwz r0,KSP_LIMIT(r8) stw r0,SAVED_KSP_LIMIT(r11) - rlwimi r0,r1,0,0,(31-THREAD_SHIFT) + CURRENT_THREAD_INFO(r0, r1) stw r0,KSP_LIMIT(r8) /* fall through */ #endif @@ -112,7 +112,7 @@ crit_transfer_to_handler: mfspr r8,SPRN_SPRG_THREAD lwz r0,KSP_LIMIT(r8) stw r0,saved_ksp_limit@l(0) - rlwimi r0,r1,0,0,(31-THREAD_SHIFT) + CURRENT_THREAD_INFO(r0, r1) stw r0,KSP_LIMIT(r8) /* fall through */ #endif @@ -158,7 +158,7 @@ transfer_to_handler: tophys(r11,r11) addir11,r11,global_dbcr0@l #ifdef CONFIG_SMP - rlwinm r9,r1,0,0,(31-THREAD_SHIFT) + CURRENT_THREAD_INFO(r9, r1) lwz r9,TI_CPU(r9) slwir9,r9,3 add r11,r11,r9 @@ -179,7 +179,7 @@ transfer_to_handler: ble-stack_ovf /* then the kernel stack overflowed */ 5: #if defined(CONFIG_6xx) || defined(CONFIG_E500) - rlwinm r9,r1,0,0,31-THREAD_SHIFT + CURRENT_THREAD_INFO(r9, r1) tophys(r9,r9) /* check local flags */ lwz r12,TI_LOCAL_FLAGS(r9) mtcrf 0x01,r12 @@ -333,7 +333,7 @@ _GLOBAL(DoSyscall) mtmsr r11 1: #endif /* CONFIG_TRACE_IRQFLAGS */ - rlwinm r10,r1,0,0,(31-THREAD_SHIFT)/* current_thread_info() */ + CURRENT_THREAD_INFO(r10, r1) lwz r11,TI_FLAGS(r10) andi. r11,r11,_TIF_SYSCALL_T_OR_A bne-syscall_dotrace @@ -354,7 +354,7 @@ ret_from_syscall: bl do_show_syscall_exit #endif mr r6,r3 - rlwinm r12,r1,0,0,(31-THREAD_SHIFT
Re: [PATCH] powerpc/booke64: Configurable lazy interrupt disabling
On Wed, Jan 18, 2012 at 3:10 PM, Benjamin Herrenschmidt b...@kernel.crashing.org wrote: On Wed, 2012-01-18 at 16:35 +0200, Laurentiu Tudor wrote: This patch adds a menuconfig option that allows controlling the lazy interrupt disabling feature implemented by this commit: commit d04c56f73c30a5e593202ecfcf25ed43d42363a2 Author: Paul Mackerras Date: Wed Oct 4 16:47:49 2006 +1000 [POWERPC] Lazy interrupt disabling for 64-bit machines The code in 'powerpc/include/asm/hw_irq.h' was rearranged and cleaned-up a bit in order to reduce the number of needed #ifdef's. It's still nasty. Do you have numbers showing that it's worth disabling on BookE ? It's not just about bare metal performance-- some platforms such as the Freescale Topaz hypervisor don't provide legacy IACK type interrupt acknowledgment, and expect the guest to support the external proxy mechanism. With Topaz, interrupts go directly to guests and we don't want to require a trap/hcall to do an IACK, as that adds potentially thousands of cycles of latency to every interrupt. As you know, with external proxy interrupts are acknowledged by the hardware and it becomes problematic to replay the interrupt in the context of lazy EE when interrupts are re-enabled. The interrupt will not fire again when you enable EE. That is currently the issue, as we can't run the 64-bit kernel on Topaz. Our option are: 1) to provide an option to disable lazy EE 2) do some kind of hack to replay interrupts with lazy EE 3) change Topaz to support legacy IACK, but this gets ugly for various reasons. Providing a config option to disable lazy EE seemed to be a good approach. Stuart ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc/booke64: Configurable lazy interrupt disabling
On Thu, Jan 19, 2012 at 1:21 PM, Stuart Yoder b08...@gmail.com wrote: On Wed, Jan 18, 2012 at 3:10 PM, Benjamin Herrenschmidt b...@kernel.crashing.org wrote: On Wed, 2012-01-18 at 16:35 +0200, Laurentiu Tudor wrote: This patch adds a menuconfig option that allows controlling the lazy interrupt disabling feature implemented by this commit: commit d04c56f73c30a5e593202ecfcf25ed43d42363a2 Author: Paul Mackerras Date: Wed Oct 4 16:47:49 2006 +1000 [POWERPC] Lazy interrupt disabling for 64-bit machines The code in 'powerpc/include/asm/hw_irq.h' was rearranged and cleaned-up a bit in order to reduce the number of needed #ifdef's. It's still nasty. Do you have numbers showing that it's worth disabling on BookE ? It's not just about bare metal performance-- some platforms such as the Freescale Topaz hypervisor don't provide legacy IACK type interrupt acknowledgment, and expect the guest to support the external proxy mechanism. With Topaz, interrupts go directly to guests and we don't want to require a trap/hcall to do an IACK, as that adds potentially thousands of cycles of latency to every interrupt. As you know, with external proxy interrupts are acknowledged by the hardware and it becomes problematic to replay the interrupt in the context of lazy EE when interrupts are re-enabled. The interrupt will not fire again when you enable EE. That is currently the issue, as we can't run the 64-bit kernel on Topaz. Our option are: 1) to provide an option to disable lazy EE 2) do some kind of hack to replay interrupts with lazy EE 3) change Topaz to support legacy IACK, but this gets ugly for various reasons. Providing a config option to disable lazy EE seemed to be a good approach. Also, Scott had posted an approach to do option #2 a while back, but as I recall there was some negative feedback about this. See: http://lists.ozlabs.org/pipermail/linuxppc-dev/2011-August/092103.html Stuart ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] update name of pic-no-reset property
From: Stuart Yoder stuart.yo...@freescale.com -changed name from 'no-reset' to 'pic-not-reset' be consisent with Meador Inge's open pic binding patch -update definition Signed-off-by: Stuart Yoder stuart.yo...@freescale.com --- Documentation/powerpc/dts-bindings/fsl/mpic.txt |7 +-- 1 files changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/powerpc/dts-bindings/fsl/mpic.txt b/Documentation/powerpc/dts-bindings/fsl/mpic.txt index fdf97c5..8b76e0f 100644 --- a/Documentation/powerpc/dts-bindings/fsl/mpic.txt +++ b/Documentation/powerpc/dts-bindings/fsl/mpic.txt @@ -44,7 +44,7 @@ PROPERTIES Value type: u32 Definition: Shall be 0. - - no-reset + - pic-no-reset Usage: optional Value type: empty Definition: The presence of this property specifies that the @@ -53,7 +53,10 @@ PROPERTIES configuration registers to a sane state-- masked or directed at other cores. This ensures that the client program will not receive interrupts for sources not belonging - to the client. + to the client. The presence of this property also mandates + that any initialization related to interrupt sources shall + be limited to sources explicitly referenced in the device tree. + INTERRUPT SPECIFIER DEFINITION -- 1.7.2.2 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH][v2] define binding for fsl mpic interrupt controllers
From: Stuart Yoder stuart.yo...@freescale.com define the binding for compatible = fsl,mpic, including the definition of 4-cell interrupt specifiers. The 3rd and 4th cells are needed to define additional types of interrupt source outside the normal external and internal interrupts in FSL SoCs. Define error interrupt, IPIs, and PIC timer sources. Signed-off-by: Stuart Yoder stuart.yo...@freescale.com --- -version 2 -fix some typos -move defintion of interrupt number to the interrupt type 0 -defined no-reset property -added some examples Documentation/powerpc/dts-bindings/fsl/mpic.txt | 251 +++ 1 files changed, 209 insertions(+), 42 deletions(-) diff --git a/Documentation/powerpc/dts-bindings/fsl/mpic.txt b/Documentation/powerpc/dts-bindings/fsl/mpic.txt index 71e39cf..a6160b5 100644 --- a/Documentation/powerpc/dts-bindings/fsl/mpic.txt +++ b/Documentation/powerpc/dts-bindings/fsl/mpic.txt @@ -1,42 +1,209 @@ -* OpenPIC and its interrupt numbers on Freescale's e500/e600 cores - -The OpenPIC specification does not specify which interrupt source has to -become which interrupt number. This is up to the software implementation -of the interrupt controller. The only requirement is that every -interrupt source has to have an unique interrupt number / vector number. -To accomplish this the current implementation assigns the number zero to -the first source, the number one to the second source and so on until -all interrupt sources have their unique number. -Usually the assigned vector number equals the interrupt number mentioned -in the documentation for a given core / CPU. This is however not true -for the e500 cores (MPC85XX CPUs) where the documentation distinguishes -between internal and external interrupt sources and starts counting at -zero for both of them. - -So what to write for external interrupt source X or internal interrupt -source Y into the device tree? Here is an example: - -The memory map for the interrupt controller in the MPC8544[0] shows, -that the first interrupt source starts at 0x5_ (PIC Register Address -Map-Interrupt Source Configuration Registers). This source becomes the -number zero therefore: - External interrupt 0 = interrupt number 0 - External interrupt 1 = interrupt number 1 - External interrupt 2 = interrupt number 2 - ... -Every interrupt number allocates 0x20 bytes register space. So to get -its number it is sufficient to shift the lower 16bits to right by five. -So for the external interrupt 10 we have: - 0x0140 5 = 10 - -After the external sources, the internal sources follow. The in core I2C -controller on the MPC8544 for instance has the internal source number -27. Oo obtain its interrupt number we take the lower 16bits of its memory -address (0x5_0560) and shift it right: - 0x0560 5 = 43 - -Therefore the I2C device node for the MPC8544 CPU has to have the -interrupt number 43 specified in the device tree. - -[0] MPC8544E PowerQUICCTM III, Integrated Host Processor Family Reference Manual -MPC8544ERM Rev. 1 10/2007 += +Freescale MPIC Interrupt Controller Node +Copyright (C) 2010,2011 Freescale Semiconductor Inc. += + +The Freescale MPIC interrupt controller is found on all PowerQUICC +and QorIQ processors and is compatible with the Open PIC. The +notable difference from Open PIC binding is the addition of 2 +additional cells in the interrupt specifier defining interrupt type +information. + +PROPERTIES + + - compatible + Usage: required + Value type: string + Definition: Shall include fsl,mpic. Freescale MPIC + controllers compatible with this binding have Block + Revision Registers BRR1 and BRR2 at offset 0x0 and + 0x10 in the MPIC. + + - reg + Usage: required + Value type: prop-encoded-array + Definition: A standard property. Specifies the physical + offset and length of the device's registers within the + CCSR address space. + + - interrupt-controller + Usage: required + Value type: empty + Definition: Specifies that this node is an interrupt + controller + + - #interrupt-cells + Usage: required + Value type: u32 + Definition: Shall be 2 or 4. A value of 2 means that interrupt + specifiers do not contain the interrupt-type or type-specific + information cells. + + - #address-cells + Usage: required + Value type: u32 + Definition: Shall be 0. + + - no-reset + Usage: optional + Value type: empty + Definition: The presence of this property specifies that the + MPIC must not be reset by the client program, and that + the boot program has initialized all interrupt source + configuration registers to a sane state-- masked or + directed at other cores. This ensures that the client
[PATCH] define binding for fsl mpic interrupt controllers
From: Stuart Yoder stuart.yo...@freescale.com define the binding for compatible = fsl,mpic, including the definition of 4-cell interrupt specifiers. The 3rd and 4th cells are needed to define additional types of interrupt source outside the normal external and internal interrupts in FSL SoCs. Define error interrupt, IPIs, and PIC timer sources. Signed-off-by: Stuart Yoder stuart.yo...@freescale.com --- Documentation/powerpc/dts-bindings/fsl/mpic.txt | 158 +-- 1 files changed, 116 insertions(+), 42 deletions(-) diff --git a/Documentation/powerpc/dts-bindings/fsl/mpic.txt b/Documentation/powerpc/dts-bindings/fsl/mpic.txt index 71e39cf..e1fe67c 100644 --- a/Documentation/powerpc/dts-bindings/fsl/mpic.txt +++ b/Documentation/powerpc/dts-bindings/fsl/mpic.txt @@ -1,42 +1,116 @@ -* OpenPIC and its interrupt numbers on Freescale's e500/e600 cores - -The OpenPIC specification does not specify which interrupt source has to -become which interrupt number. This is up to the software implementation -of the interrupt controller. The only requirement is that every -interrupt source has to have an unique interrupt number / vector number. -To accomplish this the current implementation assigns the number zero to -the first source, the number one to the second source and so on until -all interrupt sources have their unique number. -Usually the assigned vector number equals the interrupt number mentioned -in the documentation for a given core / CPU. This is however not true -for the e500 cores (MPC85XX CPUs) where the documentation distinguishes -between internal and external interrupt sources and starts counting at -zero for both of them. - -So what to write for external interrupt source X or internal interrupt -source Y into the device tree? Here is an example: - -The memory map for the interrupt controller in the MPC8544[0] shows, -that the first interrupt source starts at 0x5_ (PIC Register Address -Map-Interrupt Source Configuration Registers). This source becomes the -number zero therefore: - External interrupt 0 = interrupt number 0 - External interrupt 1 = interrupt number 1 - External interrupt 2 = interrupt number 2 - ... -Every interrupt number allocates 0x20 bytes register space. So to get -its number it is sufficient to shift the lower 16bits to right by five. -So for the external interrupt 10 we have: - 0x0140 5 = 10 - -After the external sources, the internal sources follow. The in core I2C -controller on the MPC8544 for instance has the internal source number -27. Oo obtain its interrupt number we take the lower 16bits of its memory -address (0x5_0560) and shift it right: - 0x0560 5 = 43 - -Therefore the I2C device node for the MPC8544 CPU has to have the -interrupt number 43 specified in the device tree. - -[0] MPC8544E PowerQUICCTM III, Integrated Host Processor Family Reference Manual -MPC8544ERM Rev. 1 10/2007 += +Freescale MPIC Interrupt Controller Node +Copyright (C) 2010,2011 Freescale Semiconductor Inc. += + +The Freescale MPIC interrupt controller is found on all PowerQUICC +and QorIQ processors and is compatible with the Open PIC. The +notable difference from Open PIC binding is the addition of 2 +additional cells in the interrupt specifier defining interrupt type +information. + +PROPERTIES + + - compatible + Usage: required + Value type: string + Definition: Shall include fsl,mpic. Freescale MPIC + controlers compatible with this binding have Block + Revision Registers BRR1 and BRR2 at offset 0x0 and + 0x10 in the MPIC. + + - reg + Usage: required + Value type: prop-encoded-array + Definition: A standard property. Specifies the physical + offset and length of the device's registers within the + CCSR address space. + + - interrupt-controller + Usage: required + Value type: empty + Definition: Specifies that this node is an interrupt + controller + + - #interrupt-cells + Usage: required + Value type: u32 + Definition: Shall be 2 or 4. A value of 2 means that interrupt + specifiers do not contain the interrupt-type or type-specific + information cells. + + - #address-cells + Usage: required + Value type: u32 + Definition: Shall be 0. + +INTERRUPT SPECIFIER DEFINITION + + Interrupt specifiers consists of 4 cells encoded as + follows: + + 1st-cellinterrupt-number + + Identifies the interrupt source. The MPIC + contains a block of registers referred + to as the Interrupt Source Configuration + Registers. Each source has 32-bytes of + registers (vector/priority and destination) + in this region. So interrupt 0 is at + offset 0x0, interrupt 1 is at offset 0x20
[PATCH][v2] fix of_flat_dt_is_compatible to match the full compatible string
From: Stuart Yoder stuart.yo...@freescale.com
With the previous string comparison, a device tree
compatible of foo-bar would match as compatible
with a driver looking for foo.
Signed-off-by: Stuart Yoder stuart.yo...@freescale.com
---
drivers/of/fdt.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
index dee4fb5..28c0c2b 100644
--- a/drivers/of/fdt.c
+++ b/drivers/of/fdt.c
@@ -169,7 +169,7 @@ int __init of_flat_dt_is_compatible(unsigned long node,
const char *compat)
if (cp == NULL)
return 0;
while (cplen 0) {
- if (strncasecmp(cp, compat, strlen(compat)) == 0)
+ if (!strcasecmp(cp, compat))
return 1;
l = strlen(cp) + 1;
cp += l;
--
1.6.2.5
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[PATCH] fix of_flat_dt_is_compatible to match the full compatible string
From: Stuart Yoder stuart.yo...@freescale.com
With the previous string comparison, a device tree
compatible of foo-bar would match as compatible
with a driver looking for foo.
Signed-off-by: Stuart Yoder stuart.yo...@freescale.com
---
drivers/of/fdt.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
index dee4fb5..f5239c0 100644
--- a/drivers/of/fdt.c
+++ b/drivers/of/fdt.c
@@ -169,7 +169,7 @@ int __init of_flat_dt_is_compatible(unsigned long node,
const char *compat)
if (cp == NULL)
return 0;
while (cplen 0) {
- if (strncasecmp(cp, compat, strlen(compat)) == 0)
+ if (!strcmp(cp, compat))
return 1;
l = strlen(cp) + 1;
cp += l;
--
1.6.2.5
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Re: [RFC] Clock binding
How about right here: http://fdt.secretlab.ca/ I've only just created the site. I'll fill in some documentation and structure in the next few days. Feel free to create an account and start adding stuff. We'll need to talk about how best to manage bindings and have some form of review/agreement before a binding is marked as stable. And the site URL could change as well. But in the meantime we've got a sandbox to start playing in. Unless there are better suggestions, your site is fine with me. One other thing-- we need to clarify how the content of the wiki is licensed. I assume (and hope) that the intent is for the content to be freely usable in the most flexible way. But, this has to be explicit. An issue we ran into with the ePAPR was that on the IEEE 1275 working group site (http://playground.sun.com/1275/home.html) that there were bindings that we wanted to include in the ePAPR, but the stuff on 1275 site was not copyrighted and no license was specified. This meant that we were in a legally murky situation if we cut and pasted anything from one of those document. My suggestion is to specify that all content of this wiki are released to the public domain. How to do this is a bit tricky but Creative Commons has a license called CC0 that does this by waving your copyright rights. Your wiki currently has the following statement above the commit message: Please note that all contributions to FDTWiki may be edited, altered, or removed by other contributors. If you do not want your writing to be edited mercilessly, then do not submit it here. You are also promising us that you wrote this yourself, or copied it from a public domain or similar free resource (see FDTWiki:Copyrights for details). Do not submit copyrighted work without permission! I would suggest appending the following statement to the above text: You irrevocably agree to release your contribution to the public domain. To the extent possible under law, you waive all copyright or neighboring rights to your contribution. See [CC0|link-to-CC0]. The above language comes from generated text of the CC0 tool from Creative Commons. Stuart ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [RFC] Clock binding
On Thu, Aug 27, 2009 at 9:43 PM, Benjamin Herrenschmidtb...@kernel.crashing.org wrote: On Thu, 2009-08-27 at 16:36 -1000, Mitch Bradley wrote: The idea of a wiki as a registration authority is a good one, but I'm not volunteering to maintain it :-) here goes my hope :-) Do we have wiki's we could use on power.org or should we aim for a community place ? Anybody has suggestions ? I wouldn't even try to maintain a web site myself, that would be irresponsible of anybody to let me do so ! There was an ePAPR wiki on power.org, that I had started developing, but it seems to have disappeared. I'm looking into what happened. Stuart ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [RFC] Clock binding
Lets *not* do it on power.org. I'd like to see the bindings used by more than just powerpc people, and power.org might become a bit of a mental barrier for non-powerpc folks. kernel.org would be a good host. So would ozlabs or infradead. Or I'd be happy to maintain one on secretlab. I think broadening it beyond power.org is good. Along those lines I'd prefer not having this on kernel.org, as device trees are not Linux-centric. There are other OS vendors I've interacted with that I'd like to see use device trees and separating it from Linux may be better IMO. We could also create a new domain like devicetree.org (?)..but it still would nee a host. Stuart ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH][POWERPC] document ipic level/sense info
document level and sense information for the Freescale IPIC interrupt controller Signed-off-by: Stuart Yoder [EMAIL PROTECTED] --- Documentation/powerpc/booting-without-of.txt | 20 +++- 1 files changed, 19 insertions(+), 1 deletions(-) diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/powerpc/booting-without-of.txt index c169299..d26e2bd 100644 --- a/Documentation/powerpc/booting-without-of.txt +++ b/Documentation/powerpc/booting-without-of.txt @@ -50,13 +50,14 @@ Table of Contents g) Freescale SOC SEC Security Engines h) Board Control and Status (BCSR) i) Freescale QUICC Engine module (QE) - g) Flash chip nodes + j) Flash chip nodes VII - Specifying interrupt information for devices 1) interrupts property 2) interrupt-parent property 3) OpenPIC Interrupt Controllers 4) ISA Interrupt Controllers +5) IPIC Interrupt Controllers Appendix A - Sample SOC node for MPC8540 @@ -1878,6 +1879,23 @@ encodings listed below: 2 = high to low edge sensitive type enabled 3 = low to high edge sensitive type enabled +5) Freescale IPIC Interrupt Controllers +--- + +IPIC interrupt controllers are specific to Freescale 83xx +SOCs. Two cells are required to encode interrupt information. +The first cell defines the interrupt number. The second cell +defines the sense and level information. + +Sense and level information follows the Linux convention +(specified in include/linux/interrupt.h) and should be encoded +as follows: + + 1 = low to high edge sensitive type enabled + 2 = high to low edge sensitive type enabled + 4 = active high level sensitive type enabled + 8 = active low level sensitive type enabled + Appendix A - Sample SOC node for MPC8540 -- 1.5.0.3 ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH v2][POWERPC] document ipic level/sense info
document level and sense information for the Freescale IPIC interrupt controller Signed-off-by: Stuart Yoder [EMAIL PROTECTED] --- Documentation/powerpc/booting-without-of.txt | 18 +- 1 files changed, 17 insertions(+), 1 deletions(-) diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/powerpc/booting-without-of.txt index c169299..7ad9e42 100644 --- a/Documentation/powerpc/booting-without-of.txt +++ b/Documentation/powerpc/booting-without-of.txt @@ -50,13 +50,14 @@ Table of Contents g) Freescale SOC SEC Security Engines h) Board Control and Status (BCSR) i) Freescale QUICC Engine module (QE) - g) Flash chip nodes + j) Flash chip nodes VII - Specifying interrupt information for devices 1) interrupts property 2) interrupt-parent property 3) OpenPIC Interrupt Controllers 4) ISA Interrupt Controllers +5) IPIC Interrupt Controllers Appendix A - Sample SOC node for MPC8540 @@ -1878,6 +1879,21 @@ encodings listed below: 2 = high to low edge sensitive type enabled 3 = low to high edge sensitive type enabled +5) Freescale IPIC Interrupt Controllers +--- + +IPIC interrupt controllers are specific to Freescale 83xx +SOCs. Two cells are required to encode interrupt information. +The first cell defines the interrupt number. The second cell +defines the sense and level information. + +Sense and level information follows the Linux convention +(specified in include/linux/interrupt.h) and should be encoded +as follows: + + 2 = high to low edge sensitive type enabled + 8 = active low level sensitive type enabled + Appendix A - Sample SOC node for MPC8540 -- 1.5.0.3 ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
