net/sch_generic.h does not need to be included, remove it.
Signed-off-by: Valentin Longchamp
---
drivers/net/ethernet/freescale/ucc_geth.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/net/ethernet/freescale/ucc_geth.c
b/drivers/net/ethernet/freescale/ucc_geth.c
index 552e7554a9f8
Le 23.05.2020 à 00:50, David Miller a écrit :
From: Valentin Longchamp
Date: Wed, 20 May 2020 17:53:50 +0200
ugeth_quiesce/activate are used to halt the controller when there is a
link change that requires to reconfigure the mac.
The previous implementation called netif_device_detach
tranmission. This allows to
perform mac config change required by the link change, without detaching
the corresponding netdevice and thus not preventing its initial
activation.
[1] https://lists.openwall.net/netdev/2020/01/08/201
Signed-off-by: Valentin Longchamp
Acked-by: Matteo Ghidoni
This removes the warnings about the fact that the 4 pci bridges (i.e.
the 4 pci hosts) don't have any ranges.
Signed-off-by: Valentin Longchamp
---
arch/powerpc/boot/dts/fsl/kmcent2.dts | 36 +++
1 file changed, 36 insertions(+)
diff --git a/arch/powerpc/boot/dts/fsl
Le mar. 30 juil. 2019 à 11:44, Madalin-cristian Bucur
a écrit :
>
> > -Original Message-
> >
> > > Le dim. 14 juil. 2019 à 22:05, Valentin Longchamp
> > > a écrit :
> > > >
> > > > Change all phy-connection-type properties to phy-
Le dim. 28 juil. 2019 à 21:26, Scott Wood a écrit :
> On Sun, 2019-07-28 at 18:01 +0200, Valentin Longchamp wrote:
> > Le dim. 14 juil. 2019 à 22:05, Valentin Longchamp
> > a écrit :
> > >
> > > Change all phy-connection-type properties to phy-mode that are b
?
Thanks a lot
Le dim. 14 juil. 2019 à 22:05, Valentin Longchamp
a écrit :
>
> Change all phy-connection-type properties to phy-mode that are better
> supported by the fman driver.
>
> Use the more readable fixed-link node for the 2 sgmii links.
>
> Change the RGMII link to
Change all phy-connection-type properties to phy-mode that are better
supported by the fman driver.
Use the more readable fixed-link node for the 2 sgmii links.
Change the RGMII link to rgmii-id as the clock delays are added by the
phy.
Signed-off-by: Valentin Longchamp
---
arch/powerpc/boot
From: Valentin Longchamp <valentin.longch...@keymile.com>
Sent: Thursday, November 30, 2017 10:16
To: o...@buserror.net; linuxppc-dev@lists.ozlabs.org
Cc: devicet...@vger.kernel.org; valentin.longch...@keymile.com
Subject: [PATCH] powerpc/kmcent2: update the ethernet nodes to the internal
The fman driver only calls of_get_phy_node, ignoring the
phy-connection-type field. While we're at it, update the fixed link to
the new more readable way to specify it and set phy-mode to rgmii-id for
the node with a phy.
Signed-off-by: Valentin Longchamp <valentin.longch...@keymile.
The fman driver only calls of_get_phy_node, ignoring the
phy-connection-type field. While we're at it, update the fixed link to
the new more readable way to specify it.
Signed-off-by: Valentin Longchamp <valentin.longch...@keymile.com>
---
arch/powerpc/boot/dts/fsl/kmcent2.dt
uf_info.regs is resource_size_t i.e. phys_addr_t that can be either u32
or u64 according to CONFIG_PHYS_ADDR_T_64BIT.
The printk format is thus adaptet to u64 and the regs value cast to u64
to take both u32 and u64 into account.
Signed-off-by: Valentin Longchamp <valentin.longch...@keymile.
Simple printk format warning for the the ucc registers address.
Signed-off-by: Valentin Longchamp <valentin.longch...@keymile.com>
---
drivers/net/ethernet/freescale/ucc_geth.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/freescale/ucc_get
It is required to build it as a module.
Signed-off-by: Valentin Longchamp <valentin.longch...@keymile.com>
---
drivers/net/wan/fsl_ucc_hdlc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/wan/fsl_ucc_hdlc.c b/drivers/net/wan/fsl_ucc_hdlc.c
index e38ce4d..1f38c06
20 MHz - divide by 5 - results in 16.666 MHz - divide by 6).
This patch fixes that by "forcing" the brg_clk to the nearest kHz when
the difference is below 2 integer rouding errors (i.e. 4).
Signed-off-by: Valentin Longchamp <valentin.longch...@keymile.com>
---
drivers/soc/
Testing the QE's UCC for our HDLC bus I noticed a few odd things and I have
fixed these in these 3 patches.
Valentin Longchamp (3):
soc/fsl/qe: round brg_freq to 1kHz granularity
soc/fsl/qe: only apply QE_General4 workaround on affected SoCs
soc/fsl/qe: add EXPORT_SYMBOL for the 2 qe_tdm
t;i2c: mpc: assign the
correct prescaler from SVR") in order to avoid changes in
the device tree nodes of the QE (with maybe a variant of the compatible
property), the PVR reg is read out to find out if the workaround must be
applied or not.
Signed-off-by: Valentin Longchamp <valentin.longch..
This allows to build the fsl_ucc_hdlc driver as a module.
Signed-off-by: Valentin Longchamp <valentin.longch...@keymile.com>
---
drivers/soc/fsl/qe/qe_tdm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/soc/fsl/qe/qe_tdm.c b/drivers/soc/fsl/qe/qe_tdm.c
index a1048b4..f
t;i2c: mpc: assign the
correct prescaler from SVR") in order to avoid changes in
the device tree nodes of the QE (with maybe a variant of the compatible
property), the PVR reg is read out to find out if the workaround must be
applied or not.
Signed-off-by: Valentin Longchamp <valentin.longch..
This allows to build the fsl_ucc_hdlc driver as a module.
Signed-off-by: Valentin Longchamp <valentin.longch...@keymile.com>
---
drivers/soc/fsl/qe/qe_tdm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/soc/fsl/qe/qe_tdm.c b/drivers/soc/fsl/qe/qe_tdm.c
index a1048b4..f
20 MHz - divide by 5 - results in 16.666 MHz - divide by 6).
This patch fixes that by "forcing" the brg_clk to the nearest kHz when
the difference is below 2 integer rouding errors (i.e. 4).
Signed-off-by: Valentin Longchamp <valentin.longch...@keymile.com>
---
drivers/soc/
Testing the QE's UCC for our HDLC bus I noticed a few odd things and I have
fixed these in these 3 patches.
Valentin Longchamp (3):
soc/fsl/qe: round brg_freq to 1kHz granularity
soc/fsl/qe: only apply QE_General4 workaround on affected SoCs
soc/fsl/qe: add EXPORT_SYMBOL for the 2 qe_tdm
On 15/12/16 15:00, Joakim Tjernlund wrote:
> On Thu, 2016-12-15 at 14:22 +0100, Valentin Longchamp wrote:
>> This board is built around Freescale's T1040 SoC.
>>
>> The peripherals used by this design are:
>> - DDR3 RAM with SPD support
>> - parallel NOR Flash as b
mgmt CPLD
- BFTIC chassis management CPLD
- 2 I2C buses
- 1 SPI bus
- HDLC bus with the QE's UCC1
- last but not least, the mandatory serial port
The board can be used with the corenet32_smp_defconfig.
Signed-off-by: Valentin Longchamp <valentin.longch...@keymile.com>
---
arch/powerpc/bo
It is not maintained and thus obsolete. corenet32_smp_defconfig can be
used as reference for the kmcoge4/kmp204x boards.
Signed-off-by: Valentin Longchamp <valentin.longch...@keymile.com>
---
arch/powerpc/configs/85xx/kmp204x_defconfig | 220
1 file change
This series contains some updates for the Keymile QorIQ boards.
There is a small fix for the kmcoge4 board DTS, the removal of the
kmp204x_defconfig file which is unmaintained (corenet32_smp_defconfig
can be used instead) and the addition of the kmcent2 board.
Valentin Longchamp (3):
powerpc
It is not implemented on the kmcoge4 hardware and if not disabled it
leads to error messages with the corenet32_smp_defconfig.
Signed-off-by: Valentin Longchamp <valentin.longch...@keymile.com>
---
arch/powerpc/boot/dts/fsl/kmcoge4.dts | 4
1 file changed, 4 insertions(+)
diff --git
Now that the FMAN mac driver has been merged the fman node is relevant.
The kmcoge4 board implements 3 ethernet interfaces, 1 with a RGMII phy
and 2 with fixed 1 Giga SGMII links.
Signed-off-by: Valentin Longchamp <valentin.longch...@keymile.com>
---
arch/powerpc/boot/dts/fsl/kmcoge4.dt
On 17/04/16 03:49, Scott Wood wrote:
> On Thu, 2016-04-07 at 08:14 +0200, Valentin Longchamp wrote:
>> On 06/04/16 23:49, Scott Wood wrote:
>>> On Wed, 2016-04-06 at 15:37 +0200, Valentin Longchamp wrote:
>>>> Now that the FMAN mac driver has been me
On 06/04/16 23:49, Scott Wood wrote:
> On Wed, 2016-04-06 at 15:37 +0200, Valentin Longchamp wrote:
>> Now that the FMAN mac driver has been merged the fman node is relevant.
>>
>> The kmcoge4 board implements 3 ethernet interfaces, 1 with a RGMII phy
>> and 2 wi
Now that the FMAN mac driver has been merged the fman node is relevant.
The kmcoge4 board implements 3 ethernet interfaces, 1 with a RGMII phy
and 2 with fixed 1 Giga SGMII links.
Signed-off-by: Valentin Longchamp <valentin.longch...@keymile.com>
---
arch/powerpc/boot/dts/fsl/kmcoge4.dt
On 04/01/2015 06:19 PM, Madalin Bucur wrote:
This is the second version of a patch series that adds
the Ethernet driver for the Freescale QorIQ Data Path
Acceleration Architecture (DPAA).
This second version includes the changes requested by
Kumar Gala. The PM ops patch was removed as the
Wolfgang, Scott,
On 12/11/2014 02:44 PM, Valentin Longchamp wrote:
Hi all,
Picking up this issue again.
On 11/26/2014 02:41 AM, Scott Wood wrote:
On Tue, 2014-11-25 at 19:13 +0100, Wolfram Sang wrote:
On Mon, Nov 17, 2014 at 07:28:03PM -0600, Scott Wood wrote:
On Fri, 2014-11-14 at 09
Hi all,
Picking up this issue again.
On 11/26/2014 02:41 AM, Scott Wood wrote:
On Tue, 2014-11-25 at 19:13 +0100, Wolfram Sang wrote:
On Mon, Nov 17, 2014 at 07:28:03PM -0600, Scott Wood wrote:
On Fri, 2014-11-14 at 09:28 +0100, Wolfram Sang wrote:
If we're going to change the device tree
On 11/13/2014 01:34 AM, Wolfram Sang wrote:
If we wanted to be on the safe side and strict (since we are not sure that
the
hardware is 100% compatible), we maybe should add a fsl,qoriq-i2c compatible
to
the driver that does the same as mpc8543-i2c.
Or you leave the driver as is and use
On 10/29/2014 12:08 AM, Scott Wood wrote:
On Fri, 2014-10-17 at 11:27 +0200, Valentin Longchamp wrote:
With fsl-i2c compatibility the i2c frequency is not set
correctly, because it sets no prescaler. According to the AN2919 from
Freescale and the QorIQ (P2041) documentation, the source clock
of the qoriq-i2c .dtsi files to pick the
mpc8543, which uses the same driver but sets the correct prescaler.
Signed-off-by: Rainer Boschung rainer.bosch...@keymile.com
Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com
---
arch/powerpc/boot/dts/fsl/qoriq-i2c-0.dtsi | 4 ++--
arch
The mux2 node is missing the clock-output-names field that is required
by the clk-ppc-corenet driver.
Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com
---
arch/powerpc/boot/dts/fsl/p2041si-post.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/boot/dts/fsl
machine and add kmcoge4 to the supported
boards instead of defining a new kmp204x machine
- set better and more precise device nodes for the spi devices
- remove the partion layout for the spi_flash@0
Valentin Longchamp (3):
devicetree: bindings: add Zarlink to the vendor prefixes
devcietree
Even though the company belongs to Microsemi, many chips are still
labeled as Zarlink. Among them is the family of network clock generators,
the zl3034x.
Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- add a patch so
that is
necessary because of the lowmem option that must be set higher due to
the number of PCIe devices with big ioremapped mem ranges on the boad.
Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com
---
Changes in v4:
- remove the partition layout for the NAND Flash as well
On 04/09/2014 02:44 AM, Scott Wood wrote:
On Tue, 2014-03-25 at 14:41 +0100, Valentin Longchamp wrote:
These are the bindings for 2 MFD devices used on some of the Keymile boards.
The first one is the chassis managmenet bfticu FPGA.
The second one is the board controller (reset, LEDs, GPIOs
Even though the company belongs to Microsemi, many chips are still
labeled as Zarlink. Among them is the family of network clock generators,
the zl3034x.
Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com
---
Changes in v3: None
Changes in v2:
- add a patch so that the Zarlink
that is
necessary because of the lowmem option that must be set higher due to
the number of PCIe devices with big ioremapped mem ranges on the boad.
Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com
---
Changes in v3:
- add the compatible strings for the localbus nodes
- remove the IRQ
machine and add kmcoge4 to the supported
boards instead of defining a new kmp204x machine
- set better and more precise device nodes for the spi devices
- remove the partion layout for the spi_flash@0
Valentin Longchamp (3):
devicetree: bindings: add Zarlink to the vendor prefixes
devcietree
.
Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com
---
Changes in v3:
- add a patch with the bindings for the KEYMILE FPGAs
Changes in v2: None
Documentation/devicetree/bindings/mfd/bfticu.txt | 26 ++
Documentation/devicetree/bindings/mfd/qriox.txt| 17
On 03/20/2014 12:08 AM, Scott Wood wrote:
On Tue, Feb 11, 2014 at 12:50:07PM +0100, Valentin Longchamp wrote:
+reset_cpld@1,0 {
+interrupt-controller;
+#interrupt-cells = 2;
+reg = 1 0 0x80
Hello Johannes,
On 03/19/2014 04:54 PM, Johannes Thumshirn wrote:
On Wed, Mar 19, 2014 at 01:46:37PM +0100, Valentin Longchamp wrote:
Hello,
We have a board that is based on Freescale's P2041 SoC. The boards has 2 PCIe
buses with this topology:
PCIe 0 --- PEX8505 switch --- 4 network
is defined
- add some nodes on the localbus CS when possible
- only use the corenet_generic machine and add kmcoge4 to the supported
boards instead of defining a new kmp204x machine
- set better and more precise device nodes for the spi devices
- remove the partion layout for the spi_flash@0
Valentin
Even though the company belongs to Microsemi, many chips are still
labeled as Zarlink. Among them is the family of network clock generators,
the zl3034x.
Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com
---
Changes in v2:
- add a patch so that the Zarlink vendor prefix
that is
necessary because of the lowmem option that must be set higher due to
the number of PCIe devices with big ioremapped mem ranges on the boad.
Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com
---
Changes in v2:
- add some nodes on the localbus CS when possible
- only use
On 01/21/2014 06:01 PM, Scott Wood wrote:
On Tue, 2014-01-21 at 17:34 +0100, Valentin Longchamp wrote:
On 01/20/2014 11:37 PM, Scott Wood wrote:
On Mon, 2014-01-20 at 17:38 +0100, Valentin Longchamp wrote:
On 01/17/2014 10:48 PM, Scott Wood wrote:
Why isn't the compatible keymile,kmcoge4
On 01/20/2014 11:37 PM, Scott Wood wrote:
On Mon, 2014-01-20 at 17:38 +0100, Valentin Longchamp wrote:
On 01/17/2014 10:48 PM, Scott Wood wrote:
On Fri, 2014-01-17 at 13:51 +0100, Valentin Longchamp wrote:
Hi Scott,
Thanks for you feedback.
On 01/17/2014 12:35 AM, Scott Wood wrote:
On Thu
On 01/17/2014 10:48 PM, Scott Wood wrote:
On Fri, 2014-01-17 at 13:51 +0100, Valentin Longchamp wrote:
Hi Scott,
Thanks for you feedback.
On 01/17/2014 12:35 AM, Scott Wood wrote:
On Thu, 2014-01-16 at 14:38 +0100, Valentin Longchamp wrote:
This patch introduces the support for Keymile's
Hi Scott,
Thanks for you feedback.
On 01/17/2014 12:35 AM, Scott Wood wrote:
On Thu, 2014-01-16 at 14:38 +0100, Valentin Longchamp wrote:
This patch introduces the support for Keymile's kmp204x reference
design. This design is based on Freescale's P2040/P2041 SoC.
The peripherals used
on this
reference design.
To try to avoid code duplication, the support was added directly to the
corenet_generic.c file.
Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com
---
arch/powerpc/boot/dts/kmcoge4.dts | 165 ++
arch/powerpc/configs/85xx
On 09/13/2013 04:53 PM, Kumar Gala wrote:
On Sep 13, 2013, at 4:14 AM, Valentin Longchamp wrote:
On 09/11/2013 08:58 AM, Prabhakar Kushwaha wrote:
+
+pci0 {
+ compatible = fsl,t1042-pcie, fsl,qoriq-pcie-v2.4, fsl,qoriq-pcie;
+ device_type = pci;
+ #size-cells = 2;
+ #address-cells
On 09/11/2013 08:58 AM, Prabhakar Kushwaha wrote:
The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
processor cores with high-performance data path acceleration architecture
and network peripheral interfaces required for networking
telecommunications.
T1042
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