Hi Ben and Paul,
I am sorry to trouble you. It seems that Kumar is busy recently.
Could you have a review on the following patches? These patches
implement the power management support on MPC85xx platform.
http://patchwork.ozlabs.org/patch/158484/
http://patchwork.ozlabs.org/patch/158485/
Hi Kumar,
There is no comment for these patches so far. Do you think these patches can be
merged?
We really want these patches to be merged in this merge window.
Thanks.
Best Regards,
Chenhui
-Original Message-
From: Zhao Chenhui-B35336
Sent: Friday, May 25, 2012 3:09 PM
To: Wood
Do hardware timebase sync. Firstly, stop all timebases, and transfer
the timebase value of the boot core to the other core. Finally,
start all timebases.
Only apply to dual-core chips, such as MPC8572, P2020, etc.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le
at runtime.
It supports 32-bit and 36-bit physical address.
Add generic_set_cpu_up() to set cpu_state as CPU_UP_PREPARE in kick_cpu().
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Jin Qing b24...@freescale.com
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
Changes for v5
b24...@freescale.com
Signed-off-by: Jerry Huang chang-ming.hu...@freescale.com
Cc: Scott Wood scottw...@freescale.com
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
Changes for v5:
* Rename flush_disable_L1 to __flush_disable_L1.
arch/powerpc/Kconfig |2 +-
arch
-by: Dave Liu dave...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Jerry Huang chang-ming.hu...@freescale.com
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
CC: Scott Wood scottw...@freescale.com
---
arch/powerpc/platforms/85xx/Makefile |1 +
arch/powerpc
at runtime.
It supports 32-bit and 36-bit physical address.
Add generic_set_cpu_up() to set cpu_state as CPU_UP_PREPARE in kick_cpu().
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Jin Qing b24...@freescale.com
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
Changes for v4
b24...@freescale.com
Signed-off-by: Jerry Huang chang-ming.hu...@freescale.com
Cc: Scott Wood scottw...@freescale.com
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
arch/powerpc/Kconfig |2 +-
arch/powerpc/include/asm/cacheflush.h |2 +
arch/powerpc/kernel
Add APIs for setting wakeup source and lossless Ethernet in low power modes.
These APIs can be used by wake-on-packet feature.
Signed-off-by: Dave Liu dave...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Jin Qing b24...@freescale.com
Signed-off-by: Zhao Chenhui
-by: Dave Liu dave...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Jerry Huang chang-ming.hu...@freescale.com
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
CC: Scott Wood scottw...@freescale.com
---
Changes for v4:
* Incorporated Scott's commets.
arch/powerpc
From: Li Yang le...@freescale.com
* Added compatible fsl,p1022-pmc.
* Added clock nodes to control the clock of wake-up source.
* Used fsl,pmc-handle property to connect device and clock node.
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
(), if the base which
is read from PCI_IO_BASE is equal to zero, the routine don't set
the I/O resource of the child bus.
To allow the legacy I/O space on the VIA southbridge to be accessed,
use the fixup to fix the PCI I/O space of the PCI bridge.
Signed-off-by: Zhao Chenhui chenhui.z
Chen g.c...@freescale.com
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
Changes for v2:
* add 8543, 8545 and 8547
arch/powerpc/include/asm/mpc85xx.h |1 +
arch/powerpc/sysdev/fsl_pci.c | 23 +++
2 files
.
Do not affect the functionality of the controller when the checking is disabled.
This errata exists in MPC8543, MPC8543E, MPC8545, MPC8545E, MPC8547, MPC8547E,
MPC8548 and MPC8548E. Refer to PCI 6 in MPC8548 errata document.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li
On Mar 6, 2012, at 3:10 AM, Zhao Chenhui wrote:
+ if ((fsl_svr_is(SVR_8548) || fsl_svr_is(SVR_8548_E))
Should this also have 8547, 8547E, 8545, 8545E, 8543, 8543E?
Yes. I will include these chips.
-Chenhui
+ !early_find_capability(hose, 0, 0
On Mar 6, 2012, at 3:05 AM, Zhao Chenhui wrote:
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
include/linux/pci_ids.h |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
Just merge this with the 2nd patch that actually uses the ID.
- k
Ok. I put it in the file
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c
b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
index 40f03da..c009c5b 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
@@ -3,7 +3,7 @@
*
* Maintained by Kumar Gala (see
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
include/linux/pci_ids.h |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 31d77af..8f026c0 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
(), if the base which
is read from PCI_IO_BASE is equal to zero, the routine don't set
the I/O resource of the child bus.
To allow the legacy I/O space on the VIA southbridge to be accessed,
use the fixup to fix the PCI I/O space of the PCI bridge.
Signed-off-by: Zhao Chenhui chenhui.z
From: chenhui zhao chenhui.z...@freescale.com
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
arch/powerpc/sysdev/fsl_85xx_l2ctlr.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/sysdev
From: chenhui zhao chenhui.z...@freescale.com
Remove FPGA(CADMUS) macros in code. Move it to dts.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
arch/powerpc/boot/dts/mpc8548cds.dts |8 -
arch/powerpc/platforms/85xx
From: chenhui zhao chenhui.z...@freescale.com
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
arch/powerpc/boot/dts/mpc8548cds.dts | 40 +-
1 files changed, 39 insertions(+), 1 deletions(-)
diff --git a/arch
From: chenhui zhao chenhui.z...@freescale.com
Enable RapidIO and add rapidio and rmu nodes to dts.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi | 16
arch/powerpc/boot/dts
Correct ethernet1 and add ethernet2 and ethernet3.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/boot/dts
* Create mpc8548cds.dtsi.
* Move lbc, soc and pci0 nodes to mpc8548cds_32b.dtsi.
* Change cuImage.mpc8548cds to cuImage.mpc8548cds_32b.
* Rename mpc8548cds.dts to mpc8548cds_32b.dts.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off
Create mpc8548cds_36b.dts. Support 36-bit mode.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
arch/powerpc/boot/dts/mpc8548cds_36b.dts | 86 ++
1 files changed, 86 insertions(+), 0 deletions(-)
create mode
From: chenhui zhao chenhui.z...@freescale.com
The workarounds need to detect the cpu type. Add these macros
and inline routines to help cpu type detection in runtime.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
arch/powerpc/include/asm
the combining
of crossing cacheline boundary requests into one burst transaction. Therefore,
it can prevent the errata scenario from occurring.
Refer to PCI 5 in MPC8548 errata document.
Signed-off-by: Gong Chen g.c...@freescale.com
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li
.
Do not affect the functionality of the controller when the checking is disabled.
Refer to PCI 6 in MPC8548 errata document.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
arch/powerpc/sysdev/fsl_pci.c | 16
arch/powerpc/sysdev
performance.
Refer to SRIO39 in MPC8548 errata document.
Signed-off-by: Gong Chen g.c...@freescale.com
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
arch/powerpc/sysdev/fsl_rio.c | 44 +
1 files
(), if the base which
is read from PCI_IO_BASE is equal to zero, the routine don't set
the I/O resource of the child bus.
To allow the legacy I/O space on the VIA southbridge to be accessed,
use the fixup to fix the PCI I/O space of the PCI bridge.
Signed-off-by: Zhao Chenhui chenhui.z
From: chenhui zhao chenhui.z...@freescale.com
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
arch/powerpc/sysdev/fsl_85xx_l2ctlr.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/sysdev
On 12/27/2011 05:25 AM, Zhao Chenhui wrote:
* The driver doesn't support MPC8536 Rev 1.0 due to a JOG erratum.
Subsequent revisions of MPC8536 have corrected the erratum.
Where do you check for this?
Nowhere. I just notify this patch don't support MPC8536 Rev 1.0.
+#define
the erratum.
Signed-off-by: Dave Liu dave...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Jerry Huang chang-ming.hu...@freescale.com
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
CC: Scott Wood scottw...@freescale.com
---
This patch depends on my previous patches
standby /sys/power/state or echo mem /sys/power/state
Ping from PC host to wake up the station:
ping 10.193.20.169
Signed-off-by: Dave Liu dave...@freescale.com
Signed-off-by: Jin Qing b24...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Zhao Chenhui chenhui.z
at runtime.
It supports 32-bit and 36-bit physical address.
Add generic_set_cpu_up() to set cpu_state as CPU_UP_PREPARE in kick_cpu().
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Jin Qing b24...@freescale.com
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
changes for v3
Add APIs for setting wakeup source and lossless Ethernet in low power modes.
These APIs can be used by wake-on-packet feature.
Signed-off-by: Dave Liu dave...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Jin Qing b24...@freescale.com
Signed-off-by: Zhao Chenhui
b24...@freescale.com
Signed-off-by: Jerry Huang chang-ming.hu...@freescale.com
Cc: Scott Wood scottw...@freescale.com
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
arch/powerpc/kernel/Makefile |3 +
arch/powerpc/kernel/l2cache_85xx.S | 53 +++
arch/powerpc/platforms/85xx
From: Li Yang le...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
.../devicetree/bindings/powerpc/fsl/pmc.txt| 63 +++
1 files changed, 36 insertions(+), 27 deletions(-)
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt
On Wed, Nov 16, 2011 at 12:42:14PM -0600, Scott Wood wrote:
On 11/16/2011 03:55 AM, Zhao Chenhui wrote:
From: Li Yang le...@freescale.com
The timebase sync is not only necessary when using KEXEC. It should also
be used by normal boot up and cpu hotplug. Remove the ifdef added
On Wed, Nov 16, 2011 at 06:17:56PM -0600, Scott Wood wrote:
On 11/16/2011 03:55 AM, Zhao Chenhui wrote:
From: Li Yang le...@freescale.com
Some 85xx silicons like MPC8536 and P1022 has the JOG PM feature.
P1023 as well -- any plan to support?
I see this in the p1022 and mpc8536
From: Li Yang le...@freescale.com
The timebase sync is not only necessary when using KEXEC. It should also
be used by normal boot up and cpu hotplug. Remove the ifdef added by
the KEXEC patch.
Signed-off-by: Jin Qing b24...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
at runtime.
It supports 32-bit and 36-bit physical address.
Add generic_set_cpu_up() to set cpu_state as CPU_UP_PREPARE in kick_cpu().
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Jin Qing b24...@freescale.com
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
Changes for v2:
- fix
Add APIs for setting wakeup source and lossless Ethernet in low power modes.
These APIs can be used by wake-on-packet feature.
Signed-off-by: Dave Liu dave...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Jin Qing b24...@freescale.com
Signed-off-by: Zhao Chenhui
and 4:1.
Signed-off-by: Dave Liu dave...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Jerry Huang chang-ming.hu...@freescale.com
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
Changes for v2:
- rework set_pll(). wakeup all cores before issuing a jog request
From: Li Yang le...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
.../devicetree/bindings/powerpc/fsl/pmc.txt| 63 +++
1 files changed, 36 insertions(+), 27 deletions(-)
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt
-Original Message-
From: Benjamin Herrenschmidt [mailto:b...@kernel.crashing.org]
Sent: Friday, November 11, 2011 12:23 PM
To: Zhao Chenhui-B35336
Cc: linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH 2/7] powerpc/85xx: add HOTPLUG_CPU support
On Fri, 2011-11-04 at 20:31 +0800
On Mon, Nov 07, 2011 at 12:50:24PM -0600, Scott Wood wrote:
On 11/07/2011 04:27 AM, Zhao Chenhui wrote:
On Fri, Nov 04, 2011 at 02:42:54PM -0500, Scott Wood wrote:
On 11/04/2011 07:36 AM, Zhao Chenhui wrote:
+ cpufreq_frequency_table_target(policy
On Fri, Nov 04, 2011 at 02:42:54PM -0500, Scott Wood wrote:
On 11/04/2011 07:36 AM, Zhao Chenhui wrote:
From: Li Yang le...@freescale.com
Some 85xx silicons like MPC8536 and P1022 has the JOG PM feature.
The patch adds the support to change CPU frequency using the standard
cpufreq
On Fri, Nov 04, 2011 at 07:08:24PM -0500, Tabi Timur-B04825 wrote:
On Fri, Nov 4, 2011 at 7:39 AM, Zhao Chenhui chenhui.z...@freescale.com
wrote:
+ if (!pmc_regs) {
+ printk(KERN_WARNING PMC is unavailable\n);
Use pr_warn() and the other pr_xxx functions
On Fri, Nov 04, 2011 at 04:14:25PM -0500, Scott Wood wrote:
On 11/04/2011 07:39 AM, Zhao Chenhui wrote:
@@ -45,6 +46,72 @@ static int has_lossless;
* code can be compatible with both 32-bit 36-bit */
extern void mpc85xx_enter_deep_sleep(u64 ccsrbar, u32 powmgtreq);
+#ifdef
From: Li Yang le...@freescale.com
The timebase sync is not only necessary when using KEXEC. It should also
be used by normal boot up and cpu hotplug. Remove the ifdef added by
the KEXEC patch.
Signed-off-by: Jin Qing b24...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
at runtime.
It supports 32-bit and 36-bit physical address.
Add delay in generic_cpu_die() to wait core reset.
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Jin Qing b24...@freescale.com
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
arch/powerpc/Kconfig |5
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
arch/powerpc/kernel/Makefile |1 +
arch/powerpc/kernel/l2cr_85xx.S | 53 +++
arch/powerpc/platforms/85xx/Makefile |1 +
arch/powerpc/platforms/85xx/sleep.S | 607 ++
arch/powerpc/sysdev
From: Li Yang le...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
.../devicetree/bindings/powerpc/fsl/pmc.txt| 63 +++
1 files changed, 36 insertions(+), 27 deletions(-)
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt
Signed-off-by: Dave Liu dave...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Jerry Huang chang-ming.hu...@freescale.com
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
arch/powerpc/platforms/85xx/Makefile |1 +
arch/powerpc/platforms/85xx/cpufreq.c | 255
Add APIs for setting wakeup source and lossless Ethernet in low power modes.
These APIs can be used by wake-on-packet feature.
Signed-off-by: Dave Liu dave...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Jin Qing b24...@freescale.com
Signed-off-by: Zhao Chenhui
...@freescale.com
Signed-off-by: Jin Qing b24...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Acked-by: Andy Fleming aflem...@freescale.com
---
.../devicetree/bindings/net/fsl-tsec-phy.txt |3 +
drivers/net/ethernet/freescale
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