Le 21/03/2015 01:47, Scott Wood a écrit :
On Tue, 2015-01-20 at 10:57 +0100, Christophe Leroy wrote:
By default, TASK_SIZE is set to 0x8000 for PPC_8xx, which is most likely
sufficient for most cases. However, kernel configuration allows to set TASK_SIZE
to another value, so the 8xx shall
Le 25/03/2015 01:45, Scott Wood a écrit :
On Fri, 2015-03-13 at 10:34 +1100, Michael Ellerman wrote:
On Thu, 2015-03-12 at 16:24 +0100, Christophe Leroy wrote:
Two config options exist to define powerpc MPC8xx:
* CONFIG_PPC_8xx
* CONFIG_8xx
In addition, CONFIG_PPC_8xx also defines CONFIG_CPM1
Le 06/03/2015 12:44, Mark Brown a écrit :
On Wed, Mar 04, 2015 at 09:00:39AM +0100, leroy christophe wrote:
Le 03/03/2015 19:44, Mark Brown a écrit :
Why are we using of_iomap() rather than a generic I/O mapping function
here?
because all drivers for powerpc seems to be using of_iomap
Le 06/03/2015 01:28, Herbert Xu a écrit :
On Thu, Mar 05, 2015 at 06:21:01PM -0600, Kim Phillips wrote:
On Thu, 5 Mar 2015 17:46:05 +0100
Christophe Leroy christophe.le...@c-s.fr wrote:
[15/17] crypto: talitos - Implementation of SEC1
...
[16/17] crypto: talitos - SEC1 bugs on 0 data hash
Le 06/03/2015 01:21, Kim Phillips a écrit :
On Thu, 5 Mar 2015 17:46:05 +0100
Christophe Leroy christophe.le...@c-s.fr wrote:
[15/17] crypto: talitos - Implementation of SEC1
...
[16/17] crypto: talitos - SEC1 bugs on 0 data hash
[17/17] crypto: talitos - Update DT bindings with SEC1
Le 03/03/2015 19:44, Mark Brown a écrit :
On Thu, Feb 26, 2015 at 05:11:42PM +0100, Christophe Leroy wrote:
On CPM2, the SPI parameter RAM is dynamically allocated in the dualport RAM
whereas in CPM1, it is statically allocated to a default address with
capability to relocate it somewhere else
In powerpc32 architecture there is a function called cacheable_memcpy()
which does same thing as memcpy() but using dcbz/dcbt instructions for
an optimised copy (just like __copy_tofrom_user())
What seems strange is that it is almost nowhere used (only used in
In powerpc32 architecture we have a function called cacheable_memcpy()
which does same thing as memcpy() but using dcbz/dcbt instructions for
an optimised copy (just like __copy_tofrom_user())
What seems strange is that it is almost nowhere used (only used in
Le 20/01/2015 12:09, David Laight a écrit :
From Christophe Leroy
Having a macro will help keep clear code.
It might remove an #if but it doesn't really help.
All it means is that anyone reading the code has to hunt for
the definition before proceeding.
Some comment about what (and why) the
Le 06/01/2015 13:08, David Laight a écrit :
On Tue, 2014-12-16 at 16:03 +0100, Christophe Leroy wrote:
All accessed to PGD entries are done via 0(r11).
By using lower part of swapper_pg_dir as load index to r11, we can remove the
ori instruction.
Signed-off-by: Christophe Leroy
Le 05/01/2015 19:12, Joakim Tjernlund a écrit :
On Mon, 2014-12-22 at 11:14 +0100, Christophe Leroy wrote:
On powerpc 8xx, in TLB entries, 0x400 bit is set to 1 for read-only pages
and is set to 0 for RW pages. So we should use _PAGE_RO instead of _PAGE_RW
Signed-off-by: Christophe Leroy
Le 05/01/2015 19:30, Joakim Tjernlund a écrit :
On Tue, 2014-12-16 at 16:03 +0100, Christophe Leroy wrote:
CR only needs to be preserved when checking if we are handling a kernel address.
So we can preserve CR in a register:
- In ITLBMiss, check is done only when CONFIG_MODULES is defined.
Le 18/12/2014 03:14, Scott Wood a écrit :
On Wed, 2014-12-17 at 10:14 +0100, Christophe Leroy wrote:
Some powerpc like the 8xx don't have a RW bit in PTE bits but a RO (Read Only)
bit.
This patch implements the handling of a _PAGE_RO flag to be used in place of
_PAGE_RW
Signed-off-by:
Le 18/12/2014 03:22, Scott Wood a écrit :
On Wed, 2014-12-17 at 10:14 +0100, Christophe Leroy wrote:
On powerpc 8xx, in TLB entries, 0x400 bit is set to 1 for read-only pages
and is set to 0 for RW pages. So we should use _PAGE_RO instead of _PAGE_RW
Signed-off-by: Christophe Leroy
Le 18/12/2014 03:14, Scott Wood a écrit :
On Wed, 2014-12-17 at 10:14 +0100, Christophe Leroy wrote:
Some powerpc like the 8xx don't have a RW bit in PTE bits but a RO (Read Only)
bit.
This patch implements the handling of a _PAGE_RO flag to be used in place of
_PAGE_RW
Signed-off-by:
Le 07/11/2014 04:37, Scott Wood a écrit :
On Fri, Sep 19, 2014 at 10:36:09AM +0200, LEROY Christophe wrote:
No need to re-set this bit at each TLB miss. Let's set it in the PTE.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
Changes in v2:
- None
Changes in v3:
- Removed PPC405
Many drivers use in_be16(), in_be32(), out_be16(), out_be32(), etc
to access to registrers in IO mapped memory.
What is the real purpose of those functions, and are they really needed ?
ioremap() maps the related areas as GUARDED, which means that accesses
can't be speculative. So what
LINK perf
libperf.a(skip-callchain-idx.o): In function `arch_skip_callchain_idx':
/root/gen/trunk/knl/tools/perf/arch/powerpc/util/skip-callchain-idx.c:250:
undefined reference to `pr_debug'
libperf.a(skip-callchain-idx.o): In function `check_return_addr':
Le 12/10/2014 18:22, Jochen Rollwagen a écrit :
This patch
https://lists.ozlabs.org/pipermail/linuxppc-dev/2014-September/121144.html
only compiles after putting an #ifndef ARCH_HAS_CSUM_ADD around the
definition in include/net/checksum.h
This is missing from the patch
This is already
Le 17/09/2014 22:34, Scott Wood a écrit :
On Wed, 2014-09-17 at 22:33 +0200, christophe leroy wrote:
Le 17/09/2014 18:40, Scott Wood a écrit :
On Wed, 2014-09-17 at 18:36 +0200, Christophe Leroy wrote:
This patchset:
1) provides several MMU TLB handling optimisation on MPC8xx.
2) adds
Le 07/10/2014 02:15, Scott Wood a écrit :
On Sat, 2014-10-04 at 14:02 +0200, christophe leroy wrote:
Le 03/10/2014 22:29, Scott Wood a écrit :
On Fri, 2014-10-03 at 18:49 +0200, Christophe Leroy wrote:
On CPM1, the SPI parameter RAM has a default location. In fsl_spi_cpm_get_pram()
there was
Le 07/10/2014 02:19, Scott Wood a écrit :
On Sat, 2014-10-04 at 12:15 +0200, christophe leroy wrote:
Le 03/10/2014 22:24, Scott Wood a écrit :
On Fri, 2014-10-03 at 22:15 +0200, christophe leroy wrote:
Le 03/10/2014 16:44, Mark Brown a écrit :
On Fri, Oct 03, 2014 at 02:56:09PM +0200,
Le 08/10/2014 22:03, David Miller a écrit :
From: Christophe Leroy christophe.le...@c-s.fr
Date: Tue, 7 Oct 2014 15:04:53 +0200 (CEST)
When using a MPC8xx as a router, 'perf' shows a significant time spent in
fs_enet_interrupt() and fs_enet_start_xmit().
'perf annotate' shows that the time
I'm looking for someone having some QMC driver and/or some experience
with the QMC (QUICC Multichannel Controlleur) on mpc8xx.
This is because we are trying to implement audio interface to codecs via
the TDM bus using the QUICC. At the time being we are facing a major
issue which is that after
Le 18/09/2014 22:02, Joakim Tjernlund a écrit :
christophe leroy christophe.le...@c-s.fr wrote on 2014/09/18 21:11:01:
Le 18/09/2014 20:12, Joakim Tjernlund a écrit :
leroy christophe christophe.le...@c-s.fr wrote on 2014/09/18
18:42:14:
Le 18/09/2014 17:15, Joakim Tjernlund a écrit
Le 18/09/2014 17:15, Joakim Tjernlund a écrit :
Christophe Leroy christophe.le...@c-s.fr wrote on 2014/09/17 18:36:57:
Exception InstructionAccess does not exist on MPC8xx. No need to branch
there from somewhere else.
Handling can be done directly in InstructionTLBError Exception.
-controller_state = cs;
--
cgit v0.10.1
Le 19/08/2014 11:21, leroy christophe a écrit :
Since Linux 3.16, for all drivers tied to SPI bus, I get the following
warning on a PowerPC 8xx.
It doesn't happen with Linux 3.15
What can be the reason / what should I look at ?
[3.086957] device: 'spi32766.1
Since Linux 3.16, for all drivers tied to SPI bus, I get the following
warning on a PowerPC 8xx.
It doesn't happen with Linux 3.15
What can be the reason / what should I look at ?
[3.086957] device: 'spi32766.1': device_add
[3.087179] bus: 'spi': add device spi32766.1
[3.087653]
Le 16/12/2013 23:57, Scott Wood a écrit :
On Wed, 2013-12-11 at 00:36 +0100, leroy christophe wrote:
Le 11/12/2013 00:18, Scott Wood a écrit :
There wasn't previously an ifdef specifically around the setting of
SPRN_MD_CTR. That's new. There was an ifdef around the entire block,
which has
Le 10/12/2013 23:24, Scott Wood a écrit :
On Tue, 2013-12-10 at 12:29 +0100, Christophe Leroy wrote:
Today, the only way to load kernels whose size is greater than 8Mbytes is to
activate CONFIG_PIN_TLB. Otherwise, the physical memory initially mapped is
limited to 8Mbytes. This patch adds the
Le 11/12/2013 00:18, Scott Wood a écrit :
On Wed, 2013-12-11 at 00:05 +0100, leroy christophe wrote:
Le 10/12/2013 23:24, Scott Wood a écrit :
On Tue, 2013-12-10 at 12:29 +0100, Christophe Leroy wrote:
Today, the only way to load kernels whose size is greater than 8Mbytes is to
activate
Le 01/12/2013 20:38, Guenter Roeck a écrit :
On 11/30/2013 07:33 AM, Christophe Leroy wrote:
Convert mpc8xxx_wdt.c to the new watchdog API.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
diff -ur a/drivers/watchdog/mpc8xxx_wdt.c
b/drivers/watchdog/mpc8xxx_wdt.c
---
Scott,
The patch Convert some mftb/mftbu into mfspr
(beb2dc0a7a84be003ce54e98b95d65cc66e6e536) breaks startup on MPC885.
The CPU traps (SoftwareEmulation trap) at sched_clock() when trying to
read TBU with mfspr.
Reverting the patch solves the issue.
What's the prefered way to fix this ?
Scott,
The patch Convert some mftb/mftbu into mfspr
(beb2dc0a7a84be003ce54e98b95d65cc66e6e536
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/arch/powerpc/include/asm/reg.h?id=beb2dc0a7a84be003ce54e98b95d65cc66e6e536)
breaks startup on MPC885.
The CPU traps
Le 11/10/2013 17:13, Joakim Tjernlund a écrit :
Linuxppc-dev
linuxppc-dev-bounces+joakim.tjernlund=transmode...@lists.ozlabs.org
wrote on 2013/10/11 14:56:40:
Activating CONFIG_PIN_TLB allows access to the 24 first Mbytes of memory
at
bootup instead of 8. It is needed for big kernels for
Le 20/09/2013 23:22, Scott Wood a écrit :
The hardware wants to decrement; why fight it?
I see your point.
However it is not clear in the documentation if the decrement is done
really after the update, or at xTLB interrupt. So I propose to still set
the CTR ourself as described in the
Le 16/09/2013 23:02, Scott Wood a écrit :
On Fri, 2013-09-13 at 07:04 +0200, leroy christophe wrote:
Le 12/09/2013 20:44, Scott Wood a écrit :
On Thu, 2013-09-12 at 20:25 +0200, Christophe Leroy wrote:
This is a reorganisation of the setup of the TLB at kernel startup, in order
to handle
Le 12/09/2013 20:44, Scott Wood a écrit :
On Thu, 2013-09-12 at 20:25 +0200, Christophe Leroy wrote:
This is a reorganisation of the setup of the TLB at kernel startup, in order
to handle the CONFIG_PIN_TLB case in accordance with chapter 8.10.3 of MPC866
and MPC885 reference manuals.
Le 12/09/2013 02:15, Benjamin Herrenschmidt a écrit :
On Wed, 2013-09-11 at 17:36 -0500, Scott Wood wrote:
I wonder why we don't start from entry 31 so we can actually make use of
that autodecrement. What will happen when we load the first normal TLB
entry later on? I don't see any setting
The mpc8xx powerpc has an errata identified CPU15 which is that whenever
the last instruction of a page is a conditional branch to the last
instruction of the next page, the CPU might do crazy things.
To work around this errata, one of the workarounds proposed by freescale is:
In the ITLB miss
Le 29/08/2013 19:57, Joakim Tjernlund a écrit :
Linuxppc-dev
linuxppc-dev-bounces+joakim.tjernlund=transmode...@lists.ozlabs.org
wrote on 2013/08/29 19:11:48:
The mpc8xx powerpc has an errata identified CPU15 which is that whenever
the last instruction of a page is a conditional branch to the
Le 26/06/2013 01:04, Scott Wood a écrit :
On Thu, Feb 28, 2013 at 09:52:22AM +0100, LEROY Christophe wrote:
This patch modifies the behaviour of the MPC8xx/8xxx watchdog. On the MPC8xx,
at 133Mhz, the maximum timeout of the watchdog timer is 1s, which means it must
be pinged twice a second
Hi Wim,
Le 27/02/2013 20:52, Wim Van Sebroeck a écrit :
The rest of the code is OK and when above comments are corrected,
I will add the patch to improve the userspace experience.
Kind regards,
Wim.
Ok, I'll fix and re-submit my patch according to your comments.
Best regards
Christophe
Le 16/08/2012 17:21, Alan Cox a écrit :
MAX_IDL: Maximum idle characters. When a character is received, the
receiver begins counting idle characters. If MAX_IDL idle characters
are received before the next data character, an idle timeout occurs
and the buffer is closed,
generating a maskable
Le 14/08/2012 16:52, Alan Cox a écrit :
On Tue, 14 Aug 2012 16:26:28 +0200
Christophe Leroy christophe.le...@c-s.fr wrote:
Hello,
I'm not sure who to address this Patch to either
It fixes a delay issue with CPM UART driver on Powerpc MPC8xx.
The problem is that with the actual code, the
Le 16/08/2012 16:29, Alan Cox a écrit :
The PowerPC CPM is working differently. It doesn't use a fifo but
buffers. Buffers are handed to the microprocessor only when they are
full or after a timeout period which is adjustable. In the driver, the
Which is different how - remembering we empty the
Hello,
Sometimes (but rather often) I get SPI tasks hanging.
I get the following trace, as if both tasks where blocking each other,
or they are waiting for a third task ?
Can someone help or tell what I should look at ?
[ 240.939898] INFO: task ff000a80.spi:197 blocked for more than 120
Hello,
When I build a kernel with DEBUG_LOCK_ALLOC set, I get a kernel which
has __bss_stop above the C080 limit, and then I get a bad page
exception during the zeroize of the __bss at startup, because the
initial MMU only maps the first 8Mbytes.
What can I do to fix that ?
Regards
C.
+844,6 @@
return spi_base_ofs;
}
- cpm_muram_free(spi_base_ofs);
return pram_ofs;
}
---BeginMessage---
On Tue, 7 Sep 2010 11:17:17 +0200
LEROY Christophe christophe.le...@c-s.fr wrote:
Dear Kumar,
I have a small issue in the init of spi_mpc8xxx.c
This patch applies to 2.6.34.7. It also applies to 2.6.35.4 althought
part of it is already included in 2.6.35.4
It fixed a problem with spi_mpc8xxx.c when transmitting or receiving
data bigger than PAGE_SIZE when doing a read only or write only operation
It also fixed an issue with the init
Hi,
I accordance with document MPC8xxRMAD the CPM of MPC8xx includes some
DSP functions.
However, it is not real clear if some additional microcode is needed or
not to operate it.
Does anyone know any implementation of that DSP functionality with Linux ?
Regards
C. Leroy
Dear Kumar,
I have a small issue in the init of spi_mpc8xxx.c with MPC866 (CPM1)
Unlike cpm_uart that maps the parameter ram directly using
of_iomap(np,1), spi_mpc8xxx.c uses cpm_muram_alloc_fixed().
This has two impacts in the .dts file:
* The driver must be declared with pram at 1d80
Hello,
I have a board with 2 PHYs attached to one FEC.
I want to implement some kind of main-standby attachment to LAN by
setting the ISOLATE bit on one on the two PHYs then monitoring the link
status and switch to the other PHY when the link status goes down.
What would be the most proper
Hello,
Is there a tutorial or an HOWTO out somewhere explaining the use of
those new of_platform_xxx() and other of_xxx() functions in the init of
drivers ? It looks like a very nice way to write drivers in Linux 2-6
but a little help would be welcomed.
Regards
Christophe
Hello,
I'm looking for an HDLC driver for the SCCs in MPC885 CPM.
Does anybody know where I could find such a driver for kernel 2.6.xx ?
Best regards
Christophe
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