the associated skiboot patch that implements this firmware
call? I haven't seen it on the skiboot list yet :)
Hi Stewart,
OPAL side code is under-developement. Will post the patches soon to
the skiboot mailing list.
Regards
Maddy
___
Linuxppc-dev mailing
On 7/11/19 10:23 AM, Michael Ellerman wrote:
Hi Maddy,
Madhavan Srinivasan writes:
diff --git a/arch/powerpc/platforms/powernv/opal-imc.c
b/arch/powerpc/platforms/powernv/opal-imc.c
index 186109bdd41b..e04b20625cb9 100644
--- a/arch/powerpc/platforms/powernv/opal-imc.c
+++ b/arch/powerpc
hread-imc pmu driver). It is populated and enabled only when any
of the thread
imc pmu events are monitored.
Maddy
Signed-off-by: Claudio Carvalho
Reviewed-by: Ram Pai
Reviewed-by: Ryan Grimm
Acked-by: Madhavan Srinivasan
Acked-by: Paul Mackerras
---
arch/powerpc/kvm/book3s_hv_rmhandle
default:
pr_warn("IMC Unknown Device type \n");
--
2.21.0
Does this need a Fixes: tag?
I was thinking of adding this commit as a fixes tag for fix patchset.
But if thats
not right, i can add the fixes tag along with a request to send to
Stable and post a v2
Maddy
On 11/13/19 9:40 PM, Kajol Jain wrote:
Many of the performance moniroting unit (PMU) SPRs are
exposed in the sysfs. "perf" API is the primary interface to program
PMU and collect counter data in the system. So expose these
PMU SPRs in the absence of CONFIG_PERF_EVENTS.
Patch adds a new CONFIG
On 10/1/19 2:51 PM, Kajol Jain wrote:
Perf is the primary interface to program performance monitoring
unit (pmu) and collect counter data in system.
But currently pmu register files are created in the
/sys/devices/system/cpu/cpu* without checking CONFIG_PERF_EVENTS
option. These includes PMC*
latency,
completion to retire latency and so on when using Fetch sampling.
So yes, will rework the struct definition to include data from ARM SPE
and AMD IBS also. Will post out a newer version soon.
Thanks for the comments
Maddy
ason = PERF_HAZ__SREASON_NA;
}
NAK, Don't touch anything outside of the first cacheline here.
My bad, should have looked at the comment in "struct perf_sample_data {".
Will move it to perf_prepare_sample().
Thanks for comments.
Maddy
On 1/21/20 3:47 PM, Anju T Sudhakar wrote:
commit <249fad734a25> ""powerpc/perf: Disable trace_imc pmu"
disables IMC(In-Memory Collection) trace-mode in kernel, since frequent
mode switching between accumulation mode and trace mode via the spr LDBAR
in the hardware can trigger a
On 1/21/20 3:47 PM, Anju T Sudhakar wrote:
IMC(In-memory Collection Counters) does performance monitoring in
two different modes, i.e accumulation mode(core-imc and thread-imc events),
and trace mode(trace-imc events). A cpu thread can either be in
accumulation-mode or trace-mode at a time
to interrupt pmu::event_init. Nice catch. Thanks for
pointing this out.
Looking at the code, per-cpu variable access are made to
check for constraints and for Branch Stack (BHRB). So could
wrap this block of pmu::event_init with local_irq_save/restore.
Will send a patch to fix it.
Maddy
Sebastian
On 2/14/20 4:33 PM, Kajol Jain wrote:
The hv_24×7 feature in IBM® POWER9™ processor-based servers provide the
facility to continuously collect large numbers of hardware performance
metrics efficiently and accurately.
This patch adds hv_24x7 json metric file for different Socket/chip
On 12/27/19 10:59 AM, Sukadev Bhattiprolu wrote:
Sukadev Bhattiprolu [suka...@linux.ibm.com] wrote:
Ultravisor disables some CPU features like BHRB, EBB and PMU in
secure virtual machines (SVMs). Skip accessing those registers
in SVMs to avoid getting a Program Interrupt.
Here is an updated
On 3/18/20 11:05 PM, Kim Phillips wrote:
Hi Maddy,
On 3/17/20 1:50 AM, maddy wrote:
On 3/13/20 4:08 AM, Kim Phillips wrote:
On 3/11/20 11:00 AM, Ravi Bangoria wrote:
On 3/6/20 3:36 AM, Kim Phillips wrote:
On 3/3/20 3:55 AM, Kim Phillips wrote:
On 3/2/20 2:21 PM, Stephane Eranian wrote
e vendor-independent
at record time by using SAMPLE_AUX, or SAMPLE_RAW even, which is
what IBS currently uses.
My bad. Not sure what you mean by this. We are trying to abstract
as much vendor specific data as possible with this (like perf-mem).
Maddy
Take a look at
commit 98dcf14d7f9c "p
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