[PATCH] kernel/watchdog: fix warning -Wunused-variable for watchdog_allowed_mask in ppc64
In ppc64 config if `CONFIG_SOFTLOCKUP_DETECTOR` is not set then it warns for unused declaration of `watchdog_allowed_mask` while building, move the declaration inside ifdef later in the code. ``` kernel/watchdog.c:47:23: warning: ‘watchdog_allowed_mask’ defined but not used [-Wunused-variable] static struct cpumask watchdog_allowed_mask __read_mostly; ``` Signed-off-by: Balamuruhan S --- kernel/watchdog.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/watchdog.c b/kernel/watchdog.c index 5abb5b22ad13..33c9b8a3d51b 100644 --- a/kernel/watchdog.c +++ b/kernel/watchdog.c @@ -44,7 +44,6 @@ int __read_mostly soft_watchdog_user_enabled = 1; int __read_mostly watchdog_thresh = 10; static int __read_mostly nmi_watchdog_available; -static struct cpumask watchdog_allowed_mask __read_mostly; struct cpumask watchdog_cpumask __read_mostly; unsigned long *watchdog_cpumask_bits = cpumask_bits(_cpumask); @@ -166,6 +165,7 @@ int __read_mostly sysctl_softlockup_all_cpu_backtrace; unsigned int __read_mostly softlockup_panic = CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE; +static struct cpumask watchdog_allowed_mask __read_mostly; static bool softlockup_initialized __read_mostly; static u64 __read_mostly sample_period; base-commit: a3a28c4451dff698d0c7ef5a3e80423aa5774e2b -- 2.24.1
[PATCH] kernel/watchdog: fix warning -Wunused-variable for watchdog_allowed_mask in ppc64
In ppc64 config if `CONFIG_SOFTLOCKUP_DETECTOR` is not set then it warns for unused declaration of `watchdog_allowed_mask` while building, move the declaration inside ifdef later in the code. ``` kernel/watchdog.c:47:23: warning: ‘watchdog_allowed_mask’ defined but not used [-Wunused-variable] static struct cpumask watchdog_allowed_mask __read_mostly; ``` Signed-off-by: Balamuruhan S --- kernel/watchdog.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/watchdog.c b/kernel/watchdog.c index 5abb5b22ad13..33c9b8a3d51b 100644 --- a/kernel/watchdog.c +++ b/kernel/watchdog.c @@ -44,7 +44,6 @@ int __read_mostly soft_watchdog_user_enabled = 1; int __read_mostly watchdog_thresh = 10; static int __read_mostly nmi_watchdog_available; -static struct cpumask watchdog_allowed_mask __read_mostly; struct cpumask watchdog_cpumask __read_mostly; unsigned long *watchdog_cpumask_bits = cpumask_bits(_cpumask); @@ -166,6 +165,7 @@ int __read_mostly sysctl_softlockup_all_cpu_backtrace; unsigned int __read_mostly softlockup_panic = CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE; +static struct cpumask watchdog_allowed_mask __read_mostly; static bool softlockup_initialized __read_mostly; static u64 __read_mostly sample_period; base-commit: a3a28c4451dff698d0c7ef5a3e80423aa5774e2b -- 2.24.1
[PATCH v3 4/4] powerpc sstep: add testcases for vsx load/store instructions
add testcases for vsx load/store vector paired instructions,
* Load VSX Vector Paired (lxvp)
* Load VSX Vector Paired Indexed (lxvpx)
* Prefixed Load VSX Vector Paired (plxvp)
* Store VSX Vector Paired (stxvp)
* Store VSX Vector Paired Indexed (stxvpx)
* Prefixed Store VSX Vector Paired (pstxvp)
Suggested-by: Ravi Bangoria
Signed-off-by: Balamuruhan S
---
arch/powerpc/lib/test_emulate_step.c | 252 +++
1 file changed, 252 insertions(+)
diff --git a/arch/powerpc/lib/test_emulate_step.c
b/arch/powerpc/lib/test_emulate_step.c
index d242e9f72e0c..f16934b80511 100644
--- a/arch/powerpc/lib/test_emulate_step.c
+++ b/arch/powerpc/lib/test_emulate_step.c
@@ -612,6 +612,255 @@ static void __init test_lxvd2x_stxvd2x(void)
}
#endif /* CONFIG_VSX */
+#ifdef CONFIG_VSX
+static void __init test_lxvp_stxvp(void)
+{
+ struct pt_regs regs;
+ union {
+ vector128 a;
+ u32 b[4];
+ } c[2];
+ u32 cached_b[8];
+ int stepped = -1;
+
+ init_pt_regs();
+
+ /*** lxvp ***/
+
+ cached_b[0] = c[0].b[0] = 18233;
+ cached_b[1] = c[0].b[1] = 34863571;
+ cached_b[2] = c[0].b[2] = 834;
+ cached_b[3] = c[0].b[3] = 6138911;
+ cached_b[4] = c[1].b[0] = 1234;
+ cached_b[5] = c[1].b[1] = 5678;
+ cached_b[6] = c[1].b[2] = 91011;
+ cached_b[7] = c[1].b[3] = 121314;
+
+ regs.gpr[4] = (unsigned long)[0].a;
+
+ /*
+* lxvp XTp,DQ(RA)
+* XTp = 32×TX + 2×Tp
+* let TX=1 Tp=1 RA=4 DQ=0
+*/
+ stepped = emulate_step(, ppc_inst(PPC_LXVP(1, 1, 4, 0)));
+
+ if (stepped == 1 && cpu_has_feature(CPU_FTR_VSX)) {
+ show_result("lxvp", "PASS");
+ } else {
+ if (!cpu_has_feature(CPU_FTR_VSX))
+ show_result("lxvp", "PASS (!CPU_FTR_VSX)");
+ else
+ show_result("lxvp", "FAIL");
+ }
+
+ /*** stxvp ***/
+
+ c[0].b[0] = 21379463;
+ c[0].b[1] = 87;
+ c[0].b[2] = 374234;
+ c[0].b[3] = 4;
+ c[1].b[0] = 90;
+ c[1].b[1] = 122;
+ c[1].b[2] = 555;
+ c[1].b[3] = 32144;
+
+ /*
+* stxvp XSp,DQ(RA)
+* XSp = 32×SX + 2×Sp
+* let SX=1 Sp=1 RA=4 DQ=0
+*/
+ stepped = emulate_step(, ppc_inst(PPC_STXVP(1, 1, 4, 0)));
+
+ if (stepped == 1 && cached_b[0] == c[0].b[0] && cached_b[1] ==
c[0].b[1] &&
+ cached_b[2] == c[0].b[2] && cached_b[3] == c[0].b[3] &&
+ cached_b[4] == c[1].b[0] && cached_b[5] == c[1].b[1] &&
+ cached_b[6] == c[1].b[2] && cached_b[7] == c[1].b[3] &&
+ cpu_has_feature(CPU_FTR_VSX)) {
+ show_result("stxvp", "PASS");
+ } else {
+ if (!cpu_has_feature(CPU_FTR_VSX))
+ show_result("stxvp", "PASS (!CPU_FTR_VSX)");
+ else
+ show_result("stxvp", "FAIL");
+ }
+}
+#else
+static void __init test_lxvp_stxvp(void)
+{
+ show_result("lxvp", "SKIP (CONFIG_VSX is not set)");
+ show_result("stxvp", "SKIP (CONFIG_VSX is not set)");
+}
+#endif /* CONFIG_VSX */
+
+#ifdef CONFIG_VSX
+static void __init test_lxvpx_stxvpx(void)
+{
+ struct pt_regs regs;
+ union {
+ vector128 a;
+ u32 b[4];
+ } c[2];
+ u32 cached_b[8];
+ int stepped = -1;
+
+ init_pt_regs();
+
+ /*** lxvpx ***/
+
+ cached_b[0] = c[0].b[0] = 18233;
+ cached_b[1] = c[0].b[1] = 34863571;
+ cached_b[2] = c[0].b[2] = 834;
+ cached_b[3] = c[0].b[3] = 6138911;
+ cached_b[4] = c[1].b[0] = 1234;
+ cached_b[5] = c[1].b[1] = 5678;
+ cached_b[6] = c[1].b[2] = 91011;
+ cached_b[7] = c[1].b[3] = 121314;
+
+ regs.gpr[3] = (unsigned long)[0].a;
+ regs.gpr[4] = 0;
+
+ /*
+* lxvpx XTp,RA,RB
+* XTp = 32×TX + 2×Tp
+* let TX=1 Tp=1 RA=3 RB=4
+*/
+ stepped = emulate_step(, ppc_inst(PPC_LXVPX(1, 1, 3, 4)));
+
+ if (stepped == 1 && cpu_has_feature(CPU_FTR_VSX)) {
+ show_result("lxvpx", "PASS");
+ } else {
+ if (!cpu_has_feature(CPU_FTR_VSX))
+ show_result("lxvpx", "PASS (!CPU_FTR_VSX)");
+ else
+ show_result("lxvpx", "FAIL");
+ }
+
+ /*** stxvpx ***/
+
+ c[0].b[0] = 21379463;
+ c[0].b[1] = 87;
+ c[0].b[2] = 374234;
+ c[0].b[3] = 4;
+ c[1].b[0] = 90;
+ c[1].b[1] = 122;
+ c[1].b[2] = 555;
+ c[1].b[3] = 32144;
+
+ /*
+*
[PATCH v3 3/4] powerpc ppc-opcode: add encoding macros for vsx vector paired instructions
add instruction encoding, extended opcodes, regs and DQ immediate macro for new vsx vector paired instructions, * Load VSX Vector Paired (lxvp) * Load VSX Vector Paired Indexed (lxvpx) * Prefixed Load VSX Vector Paired (plxvp) * Store VSX Vector Paired (stxvp) * Store VSX Vector Paired Indexed (stxvpx) * Prefixed Store VSX Vector Paired (pstxvp) Signed-off-by: Balamuruhan S --- arch/powerpc/include/asm/ppc-opcode.h | 17 + 1 file changed, 17 insertions(+) diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index 4c0bdafb6a7b..6ad23f47d06a 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -78,6 +78,7 @@ #define IMM_L(i) ((uintptr_t)(i) & 0x) #define IMM_DS(i) ((uintptr_t)(i) & 0xfffc) +#define IMM_DQ(i) (((uintptr_t)(i) & 0xfff) << 4) /* * 16-bit immediate helper macros: HA() is for use with sign-extending instrs @@ -272,6 +273,8 @@ #define PPC_INST_STFD 0xd800 #define PPC_PREFIX_MLS 0x0600 #define PPC_PREFIX_8LS 0x0400 +#define PPC_PLXVP_EX_OP0xe800 +#define PPC_PSTXVP_EX_OP 0xf800 /* Prefixed instructions */ #define PPC_INST_PLD 0xe400 @@ -296,6 +299,8 @@ #define __PPC_XS(s)s) & 0x1f) << 21) | (((s) & 0x20) >> 5)) #define __PPC_XT(s)__PPC_XS(s) #define __PPC_T_TLB(t) (((t) & 0x3) << 21) +#define __PPC_TP(tp) (((tp) & 0xf) << 22) +#define __PPC_TX(tx) (((tx) & 0x1) << 21) #define __PPC_WC(w)(((w) & 0x3) << 21) #define __PPC_WS(w)(((w) & 0x1f) << 11) #define __PPC_SH(s)__PPC_WS(s) @@ -387,6 +392,18 @@ #define PPC_RAW_STXVD2X(s, a, b) (0x7c000798 | VSX_XX1((s), a, b)) #define PPC_RAW_LXVD2X(s, a, b)(0x7c000698 | VSX_XX1((s), a, b)) #define PPC_RAW_MFVRD(a, t)(0x7c66 | VSX_XX1((t) + 32, a, R0)) +#define PPC_LXVP(tp, tx, a, i) \ + (0x1800 | __PPC_TP(tp) | __PPC_TX(tx) | ___PPC_RA(a) | IMM_DQ(i)) +#define PPC_STXVP(sp, sx, a, i) \ + (0x1801 | __PPC_TP(sp) | __PPC_TX(sx) | ___PPC_RA(a) | IMM_DQ(i) | 0x1) +#define PPC_LXVPX(tp, tx, a, b) \ + (0x7c00029a | __PPC_TP(tp) | __PPC_TX(tx) | ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_STXVPX(sp, sx, a, b) \ + (0x7c00039a | __PPC_TP(sp) | __PPC_TX(sx) | ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_PLXVP(a, i, pr, tp, tx) \ + ((PPC_PREFIX_8LS | __PPC_PRFX_R(pr) | IMM_H(i)) << 32 | (PPC_PLXVP_EX_OP | __PPC_TP(tp) | __PPC_TX(tx) | ___PPC_RA(a) | IMM_L(i))) +#define PPC_PSTXVP(a, i, pr, sp, sx) \ + ((PPC_PREFIX_8LS | __PPC_PRFX_R(pr) | IMM_H(i)) << 32 | (PPC_PSTXVP_EX_OP | __PPC_TP(sp) | __PPC_TX(sx) | ___PPC_RA(a) | IMM_L(i))) #define PPC_RAW_MTVRD(t, a)(0x7c000166 | VSX_XX1((t) + 32, a, R0)) #define PPC_RAW_VPMSUMW(t, a, b) (0x1488 | VSX_XX3((t), a, b)) #define PPC_RAW_VPMSUMD(t, a, b) (0x14c8 | VSX_XX3((t), a, b)) -- 2.24.1
[PATCH v3 2/4] powerpc/sstep: support emulation for vsx vector paired storage access instructions
add emulate_step() changes to support vsx vector paired storage
access instructions that provides octword operands loads/stores
between storage and set of 64 Vector Scalar Registers (VSRs).
Suggested-by: Ravi Bangoria
Suggested-by: Naveen N. Rao
Signed-off-by: Balamuruhan S
---
arch/powerpc/lib/sstep.c | 77 +++-
1 file changed, 60 insertions(+), 17 deletions(-)
diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index 22147257d74d..01e1a3adc406 100644
--- a/arch/powerpc/lib/sstep.c
+++ b/arch/powerpc/lib/sstep.c
@@ -280,6 +280,19 @@ static nokprobe_inline void do_byte_reverse(void *ptr, int
nb)
up[1] = tmp;
break;
}
+ case 32: {
+ unsigned long *up = (unsigned long *)ptr;
+ unsigned long tmp;
+
+ tmp = byterev_8(up[0]);
+ up[0] = byterev_8(up[3]);
+ up[3] = tmp;
+ tmp = byterev_8(up[2]);
+ up[2] = byterev_8(up[1]);
+ up[1] = tmp;
+ break;
+ }
+
#endif
default:
WARN_ON_ONCE(1);
@@ -710,6 +723,8 @@ void emulate_vsx_load(struct instruction_op *op, union
vsx_reg *reg,
reg->d[0] = reg->d[1] = 0;
switch (op->element_size) {
+ case 32:
+ /* [p]lxvp[x] */
case 16:
/* whole vector; lxv[x] or lxvl[l] */
if (size == 0)
@@ -718,7 +733,7 @@ void emulate_vsx_load(struct instruction_op *op, union
vsx_reg *reg,
if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
rev = !rev;
if (rev)
- do_byte_reverse(reg, 16);
+ do_byte_reverse(reg, size);
break;
case 8:
/* scalar loads, lxvd2x, lxvdsx */
@@ -794,6 +809,20 @@ void emulate_vsx_store(struct instruction_op *op, const
union vsx_reg *reg,
size = GETSIZE(op->type);
switch (op->element_size) {
+ case 32:
+ /* [p]stxvp[x] */
+ if (size == 0)
+ break;
+ if (rev) {
+ /* reverse 32 bytes */
+ buf.d[0] = byterev_8(reg->d[3]);
+ buf.d[1] = byterev_8(reg->d[2]);
+ buf.d[2] = byterev_8(reg->d[1]);
+ buf.d[3] = byterev_8(reg->d[0]);
+ reg =
+ }
+ memcpy(mem, reg, size);
+ break;
case 16:
/* stxv, stxvx, stxvl, stxvll */
if (size == 0)
@@ -862,28 +891,35 @@ static nokprobe_inline int do_vsx_load(struct
instruction_op *op,
bool cross_endian)
{
int reg = op->reg;
- u8 mem[16];
- union vsx_reg buf;
+ int i, nr_vsx_regs;
+ u8 mem[32];
+ union vsx_reg buf[2];
int size = GETSIZE(op->type);
if (!address_ok(regs, ea, size) || copy_mem_in(mem, ea, size, regs))
return -EFAULT;
- emulate_vsx_load(op, , mem, cross_endian);
+ nr_vsx_regs = size / sizeof(__vector128);
+ emulate_vsx_load(op, buf, mem, cross_endian);
preempt_disable();
if (reg < 32) {
/* FP regs + extensions */
if (regs->msr & MSR_FP) {
- load_vsrn(reg, );
+ for (i = 0; i < nr_vsx_regs; i++)
+ load_vsrn(reg + i, [i].v);
} else {
- current->thread.fp_state.fpr[reg][0] = buf.d[0];
- current->thread.fp_state.fpr[reg][1] = buf.d[1];
+ for (i = 0; i < nr_vsx_regs; i++) {
+ current->thread.fp_state.fpr[reg + i][0] =
buf[i].d[0];
+ current->thread.fp_state.fpr[reg + i][1] =
buf[i].d[1];
+ }
}
} else {
if (regs->msr & MSR_VEC)
- load_vsrn(reg, );
+ for (i = 0; i < nr_vsx_regs; i++)
+ load_vsrn(reg + i, [i].v);
else
- current->thread.vr_state.vr[reg - 32] = buf.v;
+ for (i = 0; i < nr_vsx_regs; i++)
+ current->thread.vr_state.vr[reg - 32 + i] =
buf[i].v;
}
preempt_enable();
return 0;
@@ -894,30 +930,37 @@ static nokprobe_inline int do_vsx_store(struct
instruction_op *op,
bool cross_endian)
{
int reg = op->reg;
- u8 mem[16];
- union vsx_reg buf;
+ int i, nr_vsx_regs;
+ u8 mem[32];
+ union vsx_reg buf[2];
int size = GETSIZE(op->type);
if (!address_
[PATCH v3 1/4] powerpc/sstep: support new VSX vector paired storage access instructions
VSX Vector Paired instructions loads/stores an octword (32 bytes)
from/to storage into two sequential VSRs. Add `analyse_instr()` support
to these new instructions,
* Load VSX Vector Paired (lxvp)
* Load VSX Vector Paired Indexed (lxvpx)
* Prefixed Load VSX Vector Paired (plxvp)
* Store VSX Vector Paired (stxvp)
* Store VSX Vector Paired Indexed (stxvpx)
* Prefixed Store VSX Vector Paired (pstxvp)
Suggested-by: Naveen N. Rao
Signed-off-by: Balamuruhan S
---
arch/powerpc/lib/sstep.c | 45
1 file changed, 45 insertions(+)
diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index c58ea9e787cb..22147257d74d 100644
--- a/arch/powerpc/lib/sstep.c
+++ b/arch/powerpc/lib/sstep.c
@@ -32,6 +32,10 @@ extern char system_call_vectored_emulate[];
#define XER_OV32 0x0008U
#define XER_CA32 0x0004U
+#ifdef CONFIG_VSX
+#define VSX_REGISTER_XTP(rd) rd) & 1) << 5) | ((rd) & 0xfe))
+#endif
+
#ifdef CONFIG_PPC_FPU
/*
* Functions in ldstfp.S
@@ -2386,6 +2390,14 @@ int analyse_instr(struct instruction_op *op, const
struct pt_regs *regs,
op->vsx_flags = VSX_SPLAT;
break;
+ case 333: /* lxvpx */
+ if (!cpu_has_feature(CPU_FTR_ARCH_31))
+ return -1;
+ op->reg = VSX_REGISTER_XTP(rd);
+ op->type = MKOP(LOAD_VSX, 0, 32);
+ op->element_size = 32;
+ break;
+
case 364: /* lxvwsx */
op->reg = rd | ((word & 1) << 5);
op->type = MKOP(LOAD_VSX, 0, 4);
@@ -2414,6 +2426,13 @@ int analyse_instr(struct instruction_op *op, const
struct pt_regs *regs,
VSX_CHECK_VEC;
break;
}
+ case 461: /* stxvpx */
+ if (!cpu_has_feature(CPU_FTR_ARCH_31))
+ return -1;
+ op->reg = VSX_REGISTER_XTP(rd);
+ op->type = MKOP(STORE_VSX, 0, 32);
+ op->element_size = 32;
+ break;
case 524: /* lxsspx */
op->reg = rd | ((word & 1) << 5);
op->type = MKOP(LOAD_VSX, 0, 4);
@@ -2655,6 +2674,22 @@ int analyse_instr(struct instruction_op *op, const
struct pt_regs *regs,
#endif
#ifdef CONFIG_VSX
+ case 6:
+ if (!cpu_has_feature(CPU_FTR_ARCH_31))
+ return -1;
+ op->ea = dqform_ea(word, regs);
+ op->reg = VSX_REGISTER_XTP(rd);
+ op->element_size = 32;
+ switch (word & 0xf) {
+ case 0: /* lxvp */
+ op->type = MKOP(LOAD_VSX, 0, 32);
+ break;
+ case 1: /* stxvp */
+ op->type = MKOP(STORE_VSX, 0, 32);
+ break;
+ }
+ break;
+
case 61:/* stfdp, lxv, stxsd, stxssp, stxv */
switch (word & 7) {
case 0: /* stfdp with LSB of DS field = 0 */
@@ -2783,12 +2818,22 @@ int analyse_instr(struct instruction_op *op, const
struct pt_regs *regs,
case 57:/* pld */
op->type = MKOP(LOAD, PREFIXED, 8);
break;
+ case 58:/* plxvp */
+ op->reg = VSX_REGISTER_XTP(rd);
+ op->type = MKOP(LOAD_VSX, PREFIXED, 32);
+ op->element_size = 32;
+ break;
case 60:/* stq */
op->type = MKOP(STORE, PREFIXED, 16);
break;
case 61:/* pstd */
op->type = MKOP(STORE, PREFIXED, 8);
break;
+ case 62:/* pstxvp */
+ op->reg = VSX_REGISTER_XTP(rd);
+ op->type = MKOP(STORE_VSX, PREFIXED, 32);
+ op->element_size = 32;
+ break;
}
break;
case 1: /* Type 01 Eight-Byte Register-to-Register */
--
2.24.1
[PATCH v3 0/4] VSX 32-byte vector paired load/store instructions
VSX vector paired instructions operates with octword (32-byte) operand for loads and stores between storage and a pair of two sequential Vector-Scalar Registers (VSRs). There are 4 word instructions and 2 prefixed instructions that provides this 32-byte storage access operations - lxvp, lxvpx, stxvp, stxvpx, plxvpx, pstxvpx. Emulation infrastructure doesn't have support for these instructions, to operate with 32-byte storage access and to operate with 2 VSX registers. This patch series enables the instruction emulation support and adds test cases for them respectively. Changes in v3: - Worked on review comments and suggestions from Ravi and Naveen, * Fix the do_vsx_load() to handle vsx instructions if MSR_FP/MSR_VEC cleared in exception conditions and it reaches to read/write to thread_struct member fp_state/vr_state respectively. * Fix wrongly used `__vector128 v[2]` in struct vsx_reg as it should hold a single vsx register size. * Remove unnecessary `VSX_CHECK_VEC` flag set and condition to check `VSX_LDLEFT` that is not applicable for these vsx instructions. * Fix comments in emulate_vsx_load() that were misleading. * Rebased on latest powerpc next branch. Changes in v2: - * Fix suggestion from Sandipan, wrap ISA 3.1 instructions with cpu_has_feature(CPU_FTR_ARCH_31) check. * Rebase on latest powerpc next branch. Balamuruhan S (4): powerpc/sstep: support new VSX vector paired storage access instructions powerpc/sstep: support emulation for vsx vector paired storage access instructions powerpc ppc-opcode: add encoding macros for vsx vector paired instructions powerpc sstep: add testcases for vsx load/store instructions arch/powerpc/include/asm/ppc-opcode.h | 17 ++ arch/powerpc/lib/sstep.c | 122 +++-- arch/powerpc/lib/test_emulate_step.c | 252 ++ 3 files changed, 374 insertions(+), 17 deletions(-) base-commit: 71d7bca373d5fa0ec977ca4814f49140621bd7ae -- 2.24.1
[PATCH v4 3/3] powerpc test_emulate_step: add testcases for divde[.] and divdeu[.] instructions
add testcases for divde, divde., divdeu, divdeu. emulated
instructions to cover few scenarios,
* with same dividend and divisor to have undefine RT
for divdeu[.]
* with divide by zero to have undefine RT for both
divde[.] and divdeu[.]
* with negative dividend to cover -|divisor| < r <= 0 if
the dividend is negative for divde[.]
* normal case with proper dividend and divisor for both
divde[.] and divdeu[.]
Reviewed-by: Sandipan Das
Signed-off-by: Balamuruhan S
Acked-by: Naveen N. Rao
---
arch/powerpc/lib/test_emulate_step.c | 156 +++
1 file changed, 156 insertions(+)
diff --git a/arch/powerpc/lib/test_emulate_step.c
b/arch/powerpc/lib/test_emulate_step.c
index d242e9f72e0c..0a201b771477 100644
--- a/arch/powerpc/lib/test_emulate_step.c
+++ b/arch/powerpc/lib/test_emulate_step.c
@@ -1019,6 +1019,162 @@ static struct compute_test compute_tests[] = {
}
}
},
+ {
+ .mnemonic = "divde",
+ .subtests = {
+ {
+ .descr = "RA = LONG_MIN, RB = LONG_MIN",
+ .instr = ppc_inst(PPC_RAW_DIVDE(20, 21, 22)),
+ .regs = {
+ .gpr[21] = LONG_MIN,
+ .gpr[22] = LONG_MIN,
+ }
+ },
+ {
+ .descr = "RA = 1L, RB = 0",
+ .instr = ppc_inst(PPC_RAW_DIVDE(20, 21, 22)),
+ .flags = IGNORE_GPR(20),
+ .regs = {
+ .gpr[21] = 1L,
+ .gpr[22] = 0,
+ }
+ },
+ {
+ .descr = "RA = LONG_MIN, RB = LONG_MAX",
+ .instr = ppc_inst(PPC_RAW_DIVDE(20, 21, 22)),
+ .regs = {
+ .gpr[21] = LONG_MIN,
+ .gpr[22] = LONG_MAX,
+ }
+ }
+ }
+ },
+ {
+ .mnemonic = "divde.",
+ .subtests = {
+ {
+ .descr = "RA = LONG_MIN, RB = LONG_MIN",
+ .instr = ppc_inst(PPC_RAW_DIVDE_DOT(20, 21,
22)),
+ .regs = {
+ .gpr[21] = LONG_MIN,
+ .gpr[22] = LONG_MIN,
+ }
+ },
+ {
+ .descr = "RA = 1L, RB = 0",
+ .instr = ppc_inst(PPC_RAW_DIVDE_DOT(20, 21,
22)),
+ .flags = IGNORE_GPR(20),
+ .regs = {
+ .gpr[21] = 1L,
+ .gpr[22] = 0,
+ }
+ },
+ {
+ .descr = "RA = LONG_MIN, RB = LONG_MAX",
+ .instr = ppc_inst(PPC_RAW_DIVDE_DOT(20, 21,
22)),
+ .regs = {
+ .gpr[21] = LONG_MIN,
+ .gpr[22] = LONG_MAX,
+ }
+ }
+ }
+ },
+ {
+ .mnemonic = "divdeu",
+ .subtests = {
+ {
+ .descr = "RA = LONG_MIN, RB = LONG_MIN",
+ .instr = ppc_inst(PPC_RAW_DIVDEU(20, 21, 22)),
+ .flags = IGNORE_GPR(20),
+ .regs = {
+ .gpr[21] = LONG_MIN,
+ .gpr[22] = LONG_MIN,
+ }
+ },
+ {
+ .descr = "RA = 1L, RB = 0",
+ .instr = ppc_inst(PPC_RAW_DIVDEU(20, 21, 22)),
+ .flags = IGNORE_GPR(20),
+ .regs = {
+ .gpr[21] = 1L,
+ .gpr[22] = 0,
+ }
+ },
+ {
+ .descr = "RA = LONG_MIN, RB = LONG_MAX",
+ .instr = ppc_inst(PPC_
[PATCH v4 2/3] powerpc sstep: add support for divde[.] and divdeu[.] instructions
This patch adds emulation support for divde, divdeu instructions, * Divide Doubleword Extended (divde[.]) * Divide Doubleword Extended Unsigned (divdeu[.]) Reviewed-by: Sandipan Das Signed-off-by: Balamuruhan S Acked-by: Naveen N. Rao --- arch/powerpc/lib/sstep.c | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c index c58ea9e787cb..caee8cc77e19 100644 --- a/arch/powerpc/lib/sstep.c +++ b/arch/powerpc/lib/sstep.c @@ -1806,7 +1806,18 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs, op->val = (int) regs->gpr[ra] / (int) regs->gpr[rb]; goto arith_done; - +#ifdef __powerpc64__ + case 425: /* divde[.] */ + asm volatile(PPC_DIVDE(%0, %1, %2) : + "=r" (op->val) : "r" (regs->gpr[ra]), + "r" (regs->gpr[rb])); + goto arith_done; + case 393: /* divdeu[.] */ + asm volatile(PPC_DIVDEU(%0, %1, %2) : + "=r" (op->val) : "r" (regs->gpr[ra]), + "r" (regs->gpr[rb])); + goto arith_done; +#endif case 755: /* darn */ if (!cpu_has_feature(CPU_FTR_ARCH_300)) return -1; -- 2.24.1
[PATCH v4 1/3] powerpc ppc-opcode: add divde and divdeu opcodes
include instruction opcodes for divde and divdeu as macros. Reviewed-by: Sandipan Das Signed-off-by: Balamuruhan S Acked-by: Naveen N. Rao --- arch/powerpc/include/asm/ppc-opcode.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index 4c0bdafb6a7b..a6e3700c4566 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -466,6 +466,10 @@ #define PPC_RAW_MULI(d, a, i) (0x1c00 | ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i)) #define PPC_RAW_DIVWU(d, a, b) (0x7c000396 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b)) #define PPC_RAW_DIVDU(d, a, b) (0x7c000392 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_RAW_DIVDE(t, a, b) (0x7c000352 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_RAW_DIVDE_DOT(t, a, b) (0x7c000352 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | 0x1) +#define PPC_RAW_DIVDEU(t, a, b)(0x7c000312 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_RAW_DIVDEU_DOT(t, a, b)(0x7c000312 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | 0x1) #define PPC_RAW_AND(d, a, b) (0x7c38 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(b)) #define PPC_RAW_ANDI(d, a, i) (0x7000 | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i)) #define PPC_RAW_AND_DOT(d, a, b) (0x7c39 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(b)) @@ -510,6 +514,8 @@ #define PPC_DARN(t, l) stringify_in_c(.long PPC_RAW_DARN(t, l)) #definePPC_DCBAL(a, b) stringify_in_c(.long PPC_RAW_DCBAL(a, b)) #definePPC_DCBZL(a, b) stringify_in_c(.long PPC_RAW_DCBZL(a, b)) +#definePPC_DIVDE(t, a, b) stringify_in_c(.long PPC_RAW_DIVDE(t, a, b)) +#definePPC_DIVDEU(t, a, b) stringify_in_c(.long PPC_RAW_DIVDEU(t, a, b)) #define PPC_LQARX(t, a, b, eh) stringify_in_c(.long PPC_RAW_LQARX(t, a, b, eh)) #define PPC_LDARX(t, a, b, eh) stringify_in_c(.long PPC_RAW_LDARX(t, a, b, eh)) #define PPC_LWARX(t, a, b, eh) stringify_in_c(.long PPC_RAW_LWARX(t, a, b, eh)) -- 2.24.1
[PATCH v4 0/3] Add support for divde[.] and divdeu[.] instruction emulation
Hi All, This patchset adds support to emulate divde, divde., divdeu and divdeu. instructions and testcases for it. Resend v4: rebased on latest powerpc next branch Changes in v4: - Fix review comments from Naveen, * replace TEST_DIVDEU() instead of wrongly used TEST_DIVDEU_DOT() in divdeu testcase. * Include `acked-by` tag from Naveen for the series. * Rebase it on latest mpe's merge tree. Changes in v3: - * Fix suggestion from Sandipan to remove `PPC_INST_DIVDE_DOT` and `PPC_INST_DIVDEU_DOT` opcode macros defined in ppc-opcode.h, reuse `PPC_INST_DIVDE` and `PPC_INST_DIVDEU` in test_emulate_step.c to derive them respectively. Changes in v2: - * Fix review comments from Paul to make divde_dot and divdeu_dot simple by using divde and divdeu, then goto `arith_done` instead of `compute_done`. * Include `Reviewed-by` tag from Sandipan Das. * Rebase with recent mpe's merge tree. I would request for your review and suggestions for making it better. Boot Log: :: :: :: :: 291494043: (291493996): [0.352649][T1] emulate_step_test: divde : RA = LONG_MIN, RB = LONG_MIN PASS 291517665: (291517580): [0.352695][T1] emulate_step_test: divde : RA = 1L, RB = 0PASS 291541357: (291541234): [0.352742][T1] emulate_step_test: divde : RA = LONG_MIN, RB = LONG_MAX PASS 291565107: (291564946): [0.352788][T1] emulate_step_test: divde. : RA = LONG_MIN, RB = LONG_MIN PASS 291588757: (291588558): [0.352834][T1] emulate_step_test: divde. : RA = 1L, RB = 0PASS 291612477: (291612240): [0.352881][T1] emulate_step_test: divde. : RA = LONG_MIN, RB = LONG_MAX PASS 291636201: (291635926): [0.352927][T1] emulate_step_test: divdeu : RA = LONG_MIN, RB = LONG_MIN PASS 291659830: (291659517): [0.352973][T1] emulate_step_test: divdeu : RA = 1L, RB = 0PASS 291683529: (291683178): [0.353019][T1] emulate_step_test: divdeu : RA = LONG_MIN, RB = LONG_MAX PASS 291707248: (291706859): [0.353066][T1] emulate_step_test: divdeu : RA = LONG_MAX - 1, RB = LONG_MAX PASS 291730962: (291730535): [0.353112][T1] emulate_step_test: divdeu : RA = LONG_MIN + 1, RB = LONG_MIN PASS 291754714: (291754249): [0.353158][T1] emulate_step_test: divdeu. : RA = LONG_MIN, RB = LONG_MIN PASS 291778371: (291777868): [0.353205][T1] emulate_step_test: divdeu. : RA = 1L, RB = 0PASS 291802098: (291801557): [0.353251][T1] emulate_step_test: divdeu. : RA = LONG_MIN, RB = LONG_MAX PASS 291825844: (291825265): [0.353297][T1] emulate_step_test: divdeu. : RA = LONG_MAX - 1, RB = LONG_MAX PASS 291849586: (291848969): [0.353344][T1] emulate_step_test: divdeu. : RA = LONG_MIN + 1, RB = LONG_MIN PASS :: :: :: :: 292520225: (292519608): [0.354654][T1] registered taskstats version 1 292584751: (292584134): [0.354780][T1] pstore: Using crash dump compression: deflate 296454422: (296453805): [0.362338][T1] Freeing unused kernel memory: 1408K 296467838: (296467221): [0.362364][T1] This architecture does not have kernel memory protection. 296485387: (296484770): [0.362398][T1] Run /init as init process 297987339: (297986761): [0.365332][ T46] mount (46) used greatest stack depth: 12512 bytes left 298889548: (29992): [0.367094][ T47] mount (47) used greatest stack depth: 11824 bytes left 355356256: (355355821): Welcome to Buildroot 355376898: (355376463): buildroot login: Balamuruhan S (3): powerpc ppc-opcode: add divde and divdeu opcodes powerpc sstep: add support for divde[.] and divdeu[.] instructions powerpc test_emulate_step: add testcases for divde[.] and divdeu[.] instructions arch/powerpc/include/asm/ppc-opcode.h | 6 + arch/powerpc/lib/sstep.c | 13 ++- arch/powerpc/lib/test_emulate_step.c | 156 ++ 3 files changed, 174 insertions(+), 1 deletion(-) base-commit: 7a9912e4cf048b607c8fafcfbdca750f1d78 -- 2.24.1
[PATCH v2 4/4] powerpc sstep: add testcases for vsx load/store instructions
add testcases for vsx load/store vector paired instructions,
* Load VSX Vector Paired (lxvp)
* Load VSX Vector Paired Indexed (lxvpx)
* Prefixed Load VSX Vector Paired (plxvp)
* Store VSX Vector Paired (stxvp)
* Store VSX Vector Paired Indexed (stxvpx)
* Prefixed Store VSX Vector Paired (pstxvp)
Signed-off-by: Balamuruhan S
---
arch/powerpc/include/asm/ppc-opcode.h | 7 +
arch/powerpc/lib/test_emulate_step.c | 273 ++
2 files changed, 280 insertions(+)
diff --git a/arch/powerpc/include/asm/ppc-opcode.h
b/arch/powerpc/include/asm/ppc-opcode.h
index f7ffbe11624e..aa688d13981a 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -389,6 +389,10 @@
#define PPC_INST_VCMPEQUD 0x10c7
#define PPC_INST_VCMPEQUB 0x1006
+/* Prefixes */
+#define PPC_PREFIX_MLS 0x0600
+#define PPC_PREFIX_8LS 0x0400
+
/* macros to insert fields into opcodes */
#define ___PPC_RA(a) (((a) & 0x1f) << 16)
#define ___PPC_RB(b) (((b) & 0x1f) << 11)
@@ -420,6 +424,9 @@
#define __PPC_CT(t)(((t) & 0x0f) << 21)
#define __PPC_SPR(r) r) & 0x1f) << 16) | r) >> 5) & 0x1f) << 11))
#define __PPC_RC21 (0x1 << 10)
+#define __PPC_PRFX_R(r)(((r) & 0x1) << 20)
+#define __PPC_TP(tp) (((tp) & 0xf) << 22)
+#define __PPC_TX(tx) (((tx) & 0x1) << 21)
/*
* Both low and high 16 bits are added as SIGNED additions, so if low 16 bits
diff --git a/arch/powerpc/lib/test_emulate_step.c
b/arch/powerpc/lib/test_emulate_step.c
index 46af80279ebc..98ecbc66bef8 100644
--- a/arch/powerpc/lib/test_emulate_step.c
+++ b/arch/powerpc/lib/test_emulate_step.c
@@ -14,7 +14,13 @@
#include
#define IMM_L(i) ((uintptr_t)(i) & 0x)
+#define IMM_H(i) (((uintptr_t)(i) >> 16) & 0x3)
#define IMM_DS(i) ((uintptr_t)(i) & 0xfffc)
+#define IMM_DQ(i) (((uintptr_t)(i) & 0xfff) << 4)
+
+#define PLXVP_EX_OP0xe800
+#define PSTXVP_EX_OP 0xf800
+
/*
* Defined with TEST_ prefix so it does not conflict with other
@@ -47,6 +53,21 @@
___PPC_RA(a) | ___PPC_RB(b))
#define TEST_LXVD2X(s, a, b) ppc_inst(PPC_INST_LXVD2X | VSX_XX1((s), R##a,
R##b))
#define TEST_STXVD2X(s, a, b) ppc_inst(PPC_INST_STXVD2X | VSX_XX1((s), R##a,
R##b))
+#define TEST_LXVP(tp, tx, a, i) \
+ (PPC_INST_LXVP | __PPC_TP(tp) | __PPC_TX(tx) | ___PPC_RA(a) | IMM_DQ(i))
+#define TEST_STXVP(sp, sx, a, i) \
+ (PPC_INST_STXVP | __PPC_TP(sp) | __PPC_TX(sx) | ___PPC_RA(a) |
IMM_DQ(i) | 0x1)
+#define TEST_LXVPX(tp, tx, a, b) \
+ (PPC_INST_LXVPX | __PPC_TP(tp) | __PPC_TX(tx) | ___PPC_RA(a) |
___PPC_RB(b))
+#define TEST_STXVPX(sp, sx, a, b) \
+ (PPC_INST_STXVPX | __PPC_TP(sp) | __PPC_TX(sx) | ___PPC_RA(a) |
___PPC_RB(b))
+#define TEST_PLXVP(a, i, pr, tp, tx) \
+ ((PPC_PREFIX_8LS | __PPC_PRFX_R(pr) | IMM_H(i)) << 32 | \
+(PLXVP_EX_OP | __PPC_TP(tp) | __PPC_TX(tx) | ___PPC_RA(a) | IMM_L(i)))
+#define TEST_PSTXVP(a, i, pr, sp, sx) \
+ ((PPC_PREFIX_8LS | __PPC_PRFX_R(pr) | IMM_H(i)) << 32 | \
+(PSTXVP_EX_OP | __PPC_TP(sp) | __PPC_TX(sx) | ___PPC_RA(a) | IMM_L(i)))
+
#define TEST_ADD(t, a, b) ppc_inst(PPC_INST_ADD | ___PPC_RT(t) |
\
___PPC_RA(a) | ___PPC_RB(b))
#define TEST_ADD_DOT(t, a, b) ppc_inst(PPC_INST_ADD | ___PPC_RT(t) |
\
@@ -444,6 +465,255 @@ static void __init test_lxvd2x_stxvd2x(void)
}
#endif /* CONFIG_VSX */
+#ifdef CONFIG_VSX
+static void __init test_lxvp_stxvp(void)
+{
+ struct pt_regs regs;
+ union {
+ vector128 a[2];
+ u32 b[8];
+ } c;
+ u32 cached_b[8];
+ int stepped = -1;
+
+ init_pt_regs();
+
+ /*** lxvp ***/
+
+ cached_b[0] = c.b[0] = 18233;
+ cached_b[1] = c.b[1] = 34863571;
+ cached_b[2] = c.b[2] = 834;
+ cached_b[3] = c.b[3] = 6138911;
+ cached_b[4] = c.b[4] = 1234;
+ cached_b[5] = c.b[5] = 5678;
+ cached_b[6] = c.b[6] = 91011;
+ cached_b[7] = c.b[7] = 121314;
+
+ regs.gpr[4] = (unsigned long)
+
+ /*
+* lxvp XTp,DQ(RA)
+* XTp = 32??TX + 2??Tp
+* let TX=1 Tp=1 RA=4 DQ=0
+*/
+ stepped = emulate_step(, ppc_inst(TEST_LXVP(1, 1, 4, 0)));
+
+ if (stepped == 1 && cpu_has_feature(CPU_FTR_VSX)) {
+ show_result("lxvp", "PASS");
+ } else {
+ if (!cpu_has_feature(CPU_FTR_VSX))
+ show_result("lxvp", "PASS (!CPU_FTR_VSX)");
+ else
+ show_result("lxvp", "FAIL");
+ }
[PATCH v2 3/4] powerpc ppc-opcode: add opcodes for vsx vector paired instructions
add instruction opcodes for new vsx vector paired instructions, * Load VSX Vector Paired (lxvp) * Load VSX Vector Paired Indexed (lxvpx) * Store VSX Vector Paired (stxvp) * Store VSX Vector Paired Indexed (stxvpx) Signed-off-by: Balamuruhan S --- arch/powerpc/include/asm/ppc-opcode.h | 4 1 file changed, 4 insertions(+) diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index 777d5056a71c..f7ffbe11624e 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -210,6 +210,10 @@ #define PPC_INST_ISEL 0x7c1e #define PPC_INST_ISEL_MASK 0xfc3e #define PPC_INST_LDARX 0x7ca8 +#define PPC_INST_LXVP 0x1800 +#define PPC_INST_LXVPX 0x7c00029a +#define PPC_INST_STXVP 0x1801 +#define PPC_INST_STXVPX0x7c00039a #define PPC_INST_STDCX 0x7c0001ad #define PPC_INST_LQARX 0x7c000228 #define PPC_INST_STQCX 0x7c00016d -- 2.24.1
[PATCH v2 2/4] powerpc/sstep: support emulation for vsx vector paired storage access instructions
add emulate_step() changes to support vsx vector paired storage
access instructions that provides octword operands loads/stores
between storage and set of 2 Vector Scalar Registers (VSRs).
Signed-off-by: Balamuruhan S
---
arch/powerpc/include/asm/sstep.h | 2 +-
arch/powerpc/lib/sstep.c | 58 +++-
2 files changed, 50 insertions(+), 10 deletions(-)
diff --git a/arch/powerpc/include/asm/sstep.h b/arch/powerpc/include/asm/sstep.h
index 3b01c69a44aa..a6c0b299bcc9 100644
--- a/arch/powerpc/include/asm/sstep.h
+++ b/arch/powerpc/include/asm/sstep.h
@@ -126,7 +126,7 @@ union vsx_reg {
unsigned long d[2];
float fp[4];
double dp[2];
- __vector128 v;
+ __vector128 v[2];
};
/*
diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index 1af8c1920b36..010ce81aeffb 100644
--- a/arch/powerpc/lib/sstep.c
+++ b/arch/powerpc/lib/sstep.c
@@ -279,6 +279,19 @@ static nokprobe_inline void do_byte_reverse(void *ptr, int
nb)
up[1] = tmp;
break;
}
+ case 32: {
+ unsigned long *up = (unsigned long *)ptr;
+ unsigned long tmp;
+
+ tmp = byterev_8(up[0]);
+ up[0] = byterev_8(up[3]);
+ up[3] = tmp;
+ tmp = byterev_8(up[2]);
+ up[2] = byterev_8(up[1]);
+ up[1] = tmp;
+ break;
+ }
+
#endif
default:
WARN_ON_ONCE(1);
@@ -709,6 +722,8 @@ void emulate_vsx_load(struct instruction_op *op, union
vsx_reg *reg,
reg->d[0] = reg->d[1] = 0;
switch (op->element_size) {
+ case 32:
+ /* [p]lxvp[x] or [p]stxvp[x] */
case 16:
/* whole vector; lxv[x] or lxvl[l] */
if (size == 0)
@@ -717,7 +732,7 @@ void emulate_vsx_load(struct instruction_op *op, union
vsx_reg *reg,
if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
rev = !rev;
if (rev)
- do_byte_reverse(reg, 16);
+ do_byte_reverse(reg, size);
break;
case 8:
/* scalar loads, lxvd2x, lxvdsx */
@@ -793,6 +808,22 @@ void emulate_vsx_store(struct instruction_op *op, const
union vsx_reg *reg,
size = GETSIZE(op->type);
switch (op->element_size) {
+ case 32:
+ /* [p]lxvp[x] or [p]stxvp[x] */
+ if (size == 0)
+ break;
+ if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
+ rev = !rev;
+ if (rev) {
+ /* reverse 32 bytes */
+ buf.d[0] = byterev_8(reg->d[3]);
+ buf.d[1] = byterev_8(reg->d[2]);
+ buf.d[2] = byterev_8(reg->d[1]);
+ buf.d[3] = byterev_8(reg->d[0]);
+ reg =
+ }
+ memcpy(mem, reg, size);
+ break;
case 16:
/* stxv, stxvx, stxvl, stxvll */
if (size == 0)
@@ -861,28 +892,33 @@ static nokprobe_inline int do_vsx_load(struct
instruction_op *op,
bool cross_endian)
{
int reg = op->reg;
- u8 mem[16];
+ int i, nr_vsx_regs;
+ u8 mem[32];
union vsx_reg buf;
int size = GETSIZE(op->type);
if (!address_ok(regs, ea, size) || copy_mem_in(mem, ea, size, regs))
return -EFAULT;
+ nr_vsx_regs = size / sizeof(__vector128);
emulate_vsx_load(op, , mem, cross_endian);
preempt_disable();
if (reg < 32) {
/* FP regs + extensions */
if (regs->msr & MSR_FP) {
- load_vsrn(reg, );
+ for (i = 0; i < nr_vsx_regs; i++)
+ load_vsrn(reg + i, [i]);
} else {
current->thread.fp_state.fpr[reg][0] = buf.d[0];
current->thread.fp_state.fpr[reg][1] = buf.d[1];
}
} else {
if (regs->msr & MSR_VEC)
- load_vsrn(reg, );
+ for (i = 0; i < nr_vsx_regs; i++)
+ load_vsrn(reg + i, [i]);
+
else
- current->thread.vr_state.vr[reg - 32] = buf.v;
+ current->thread.vr_state.vr[reg - 32] = buf.v[0];
}
preempt_enable();
return 0;
@@ -893,27 +929,31 @@ static nokprobe_inline int do_vsx_store(struct
instruction_op *op,
bool cross_endian)
{
int reg = op->reg;
- u8 mem[16];
+ int i, nr_vsx_regs;
+ u8 mem[32];
union vsx_reg buf;
int size = GETSIZE(op->type);
[PATCH v2 1/4] powerpc/sstep: support new VSX vector paired storage access instructions
VSX Vector Paired instructions loads/stores an octword (32 bytes)
from/to storage into two sequential VSRs. Add `analyse_instr()` support
to these new instructions,
* Load VSX Vector Paired (lxvp)
* Load VSX Vector Paired Indexed (lxvpx)
* Prefixed Load VSX Vector Paired (plxvp)
* Store VSX Vector Paired (stxvp)
* Store VSX Vector Paired Indexed (stxvpx)
* Prefixed Store VSX Vector Paired (pstxvp)
Signed-off-by: Balamuruhan S
---
arch/powerpc/lib/sstep.c | 52
1 file changed, 52 insertions(+)
diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index 5abe98216dc2..1af8c1920b36 100644
--- a/arch/powerpc/lib/sstep.c
+++ b/arch/powerpc/lib/sstep.c
@@ -31,6 +31,10 @@ extern char system_call_common[];
#define XER_OV32 0x0008U
#define XER_CA32 0x0004U
+#ifdef CONFIG_VSX
+#define VSX_REGISTER_XTP(rd) rd) & 1) << 5) | ((rd) & 0xfe))
+#endif
+
#ifdef CONFIG_PPC_FPU
/*
* Functions in ldstfp.S
@@ -2382,6 +2386,15 @@ int analyse_instr(struct instruction_op *op, const
struct pt_regs *regs,
op->vsx_flags = VSX_SPLAT;
break;
+ case 333: /* lxvpx */
+ if (!cpu_has_feature(CPU_FTR_ARCH_31))
+ return -1;
+ op->reg = VSX_REGISTER_XTP(rd);
+ op->type = MKOP(LOAD_VSX, 0, 32);
+ op->element_size = 32;
+ op->vsx_flags = VSX_CHECK_VEC;
+ break;
+
case 364: /* lxvwsx */
op->reg = rd | ((word & 1) << 5);
op->type = MKOP(LOAD_VSX, 0, 4);
@@ -2410,6 +2423,14 @@ int analyse_instr(struct instruction_op *op, const
struct pt_regs *regs,
VSX_CHECK_VEC;
break;
}
+ case 461: /* stxvpx */
+ if (!cpu_has_feature(CPU_FTR_ARCH_31))
+ return -1;
+ op->reg = VSX_REGISTER_XTP(rd);
+ op->type = MKOP(STORE_VSX, 0, 32);
+ op->element_size = 32;
+ op->vsx_flags = VSX_CHECK_VEC;
+ break;
case 524: /* lxsspx */
op->reg = rd | ((word & 1) << 5);
op->type = MKOP(LOAD_VSX, 0, 4);
@@ -2651,6 +2672,23 @@ int analyse_instr(struct instruction_op *op, const
struct pt_regs *regs,
#endif
#ifdef CONFIG_VSX
+ case 6:
+ if (!cpu_has_feature(CPU_FTR_ARCH_31))
+ return -1;
+ op->ea = dqform_ea(word, regs);
+ op->reg = VSX_REGISTER_XTP(rd);
+ op->element_size = 32;
+ op->vsx_flags = VSX_CHECK_VEC;
+ switch (word & 0xf) {
+ case 0: /* lxvp */
+ op->type = MKOP(LOAD_VSX, 0, 32);
+ break;
+ case 1: /* stxvp */
+ op->type = MKOP(STORE_VSX, 0, 32);
+ break;
+ }
+ break;
+
case 61:/* stfdp, lxv, stxsd, stxssp, stxv */
switch (word & 7) {
case 0: /* stfdp with LSB of DS field = 0 */
@@ -2715,6 +2753,8 @@ int analyse_instr(struct instruction_op *op, const struct
pt_regs *regs,
}
break;
case 1: /* Prefixed instructions */
+ if (!cpu_has_feature(CPU_FTR_ARCH_31))
+ return -1;
prefix_r = word & (1ul << 20);
ra = (suffix >> 16) & 0x1f;
op->update_reg = ra;
@@ -2779,12 +2819,24 @@ int analyse_instr(struct instruction_op *op, const
struct pt_regs *regs,
case 57:/* pld */
op->type = MKOP(LOAD, PREFIXED, 8);
break;
+ case 58:/* plxvp */
+ op->reg = VSX_REGISTER_XTP(rd);
+ op->type = MKOP(LOAD_VSX, PREFIXED, 32);
+ op->element_size = 32;
+ op->vsx_flags = VSX_CHECK_VEC;
+ break;
case 60:/* stq */
op->type = MKOP(STORE, PREFIXED, 16);
break;
case 61:/* pstd */
op->type = MKOP(STORE, PREFIXED, 8);
break;
+ case 62:/* pstxvp */
+
[PATCH v2 0/4] VSX 32-byte vector paired load/store instructions
VSX vector paired instructions operates with octword (32-byte) operand for loads and stores between storage and a pair of two sequential Vector-Scalar Registers (VSRs). There are 4 word instructions and 2 prefixed instructions that provides this 32-byte storage access operations - lxvp, lxvpx, stxvp, stxvpx, plxvpx, pstxvpx. Emulation infrastructure doesn't have support for these instructions, to operate with 32-byte storage access and to operate with 2 VSX registers. This patch series enables the instruction emulation support and adds test cases for them respectively. Changes in v2: - * Fix suggestion from Sandipan, wrap ISA 3.1 instructions with cpu_has_feature(CPU_FTR_ARCH_31) check. * Rebase on latest powerpc next branch. Balamuruhan S (4): powerpc/sstep: support new VSX vector paired storage access instructions powerpc/sstep: support emulation for vsx vector paired storage access instructions powerpc ppc-opcode: add opcodes for vsx vector paired instructions powerpc sstep: add testcases for vsx load/store instructions arch/powerpc/include/asm/ppc-opcode.h | 11 ++ arch/powerpc/include/asm/sstep.h | 2 +- arch/powerpc/lib/sstep.c | 110 ++- arch/powerpc/lib/test_emulate_step.c | 273 ++ 4 files changed, 386 insertions(+), 10 deletions(-) base-commit: b2b46304e9360f3dda49c9d8ba4a1478b9eecf1d -- 2.24.1
[PATCH 4/4] powerpc sstep: add testcases for vsx load/store instructions
add testcases for vsx load/store vector paired instructions,
* Load VSX Vector Paired (lxvp)
* Load VSX Vector Paired Indexed (lxvpx)
* Prefixed Load VSX Vector Paired (plxvp)
* Store VSX Vector Paired (stxvp)
* Store VSX Vector Paired Indexed (stxvpx)
* Prefixed Store VSX Vector Paired (pstxvp)
Signed-off-by: Balamuruhan S
---
arch/powerpc/include/asm/ppc-opcode.h | 7 +
arch/powerpc/lib/test_emulate_step.c | 273 ++
2 files changed, 280 insertions(+)
diff --git a/arch/powerpc/include/asm/ppc-opcode.h
b/arch/powerpc/include/asm/ppc-opcode.h
index 558efd25683b..9bc9b184db6e 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -384,6 +384,10 @@
#define PPC_INST_VCMPEQUD 0x10c7
#define PPC_INST_VCMPEQUB 0x1006
+/* Prefixes */
+#define PPC_PREFIX_MLS 0x0600
+#define PPC_PREFIX_8LS 0x0400
+
/* macros to insert fields into opcodes */
#define ___PPC_RA(a) (((a) & 0x1f) << 16)
#define ___PPC_RB(b) (((b) & 0x1f) << 11)
@@ -415,6 +419,9 @@
#define __PPC_CT(t)(((t) & 0x0f) << 21)
#define __PPC_SPR(r) r) & 0x1f) << 16) | r) >> 5) & 0x1f) << 11))
#define __PPC_RC21 (0x1 << 10)
+#define __PPC_PRFX_R(r)(((r) & 0x1) << 20)
+#define __PPC_TP(tp) (((tp) & 0xf) << 22)
+#define __PPC_TX(tx) (((tx) & 0x1) << 21)
/*
* Both low and high 16 bits are added as SIGNED additions, so if low 16 bits
diff --git a/arch/powerpc/lib/test_emulate_step.c
b/arch/powerpc/lib/test_emulate_step.c
index 46af80279ebc..98ecbc66bef8 100644
--- a/arch/powerpc/lib/test_emulate_step.c
+++ b/arch/powerpc/lib/test_emulate_step.c
@@ -14,7 +14,13 @@
#include
#define IMM_L(i) ((uintptr_t)(i) & 0x)
+#define IMM_H(i) (((uintptr_t)(i) >> 16) & 0x3)
#define IMM_DS(i) ((uintptr_t)(i) & 0xfffc)
+#define IMM_DQ(i) (((uintptr_t)(i) & 0xfff) << 4)
+
+#define PLXVP_EX_OP0xe800
+#define PSTXVP_EX_OP 0xf800
+
/*
* Defined with TEST_ prefix so it does not conflict with other
@@ -47,6 +53,21 @@
___PPC_RA(a) | ___PPC_RB(b))
#define TEST_LXVD2X(s, a, b) ppc_inst(PPC_INST_LXVD2X | VSX_XX1((s), R##a,
R##b))
#define TEST_STXVD2X(s, a, b) ppc_inst(PPC_INST_STXVD2X | VSX_XX1((s), R##a,
R##b))
+#define TEST_LXVP(tp, tx, a, i) \
+ (PPC_INST_LXVP | __PPC_TP(tp) | __PPC_TX(tx) | ___PPC_RA(a) | IMM_DQ(i))
+#define TEST_STXVP(sp, sx, a, i) \
+ (PPC_INST_STXVP | __PPC_TP(sp) | __PPC_TX(sx) | ___PPC_RA(a) |
IMM_DQ(i) | 0x1)
+#define TEST_LXVPX(tp, tx, a, b) \
+ (PPC_INST_LXVPX | __PPC_TP(tp) | __PPC_TX(tx) | ___PPC_RA(a) |
___PPC_RB(b))
+#define TEST_STXVPX(sp, sx, a, b) \
+ (PPC_INST_STXVPX | __PPC_TP(sp) | __PPC_TX(sx) | ___PPC_RA(a) |
___PPC_RB(b))
+#define TEST_PLXVP(a, i, pr, tp, tx) \
+ ((PPC_PREFIX_8LS | __PPC_PRFX_R(pr) | IMM_H(i)) << 32 | \
+(PLXVP_EX_OP | __PPC_TP(tp) | __PPC_TX(tx) | ___PPC_RA(a) | IMM_L(i)))
+#define TEST_PSTXVP(a, i, pr, sp, sx) \
+ ((PPC_PREFIX_8LS | __PPC_PRFX_R(pr) | IMM_H(i)) << 32 | \
+(PSTXVP_EX_OP | __PPC_TP(sp) | __PPC_TX(sx) | ___PPC_RA(a) | IMM_L(i)))
+
#define TEST_ADD(t, a, b) ppc_inst(PPC_INST_ADD | ___PPC_RT(t) |
\
___PPC_RA(a) | ___PPC_RB(b))
#define TEST_ADD_DOT(t, a, b) ppc_inst(PPC_INST_ADD | ___PPC_RT(t) |
\
@@ -444,6 +465,255 @@ static void __init test_lxvd2x_stxvd2x(void)
}
#endif /* CONFIG_VSX */
+#ifdef CONFIG_VSX
+static void __init test_lxvp_stxvp(void)
+{
+ struct pt_regs regs;
+ union {
+ vector128 a[2];
+ u32 b[8];
+ } c;
+ u32 cached_b[8];
+ int stepped = -1;
+
+ init_pt_regs();
+
+ /*** lxvp ***/
+
+ cached_b[0] = c.b[0] = 18233;
+ cached_b[1] = c.b[1] = 34863571;
+ cached_b[2] = c.b[2] = 834;
+ cached_b[3] = c.b[3] = 6138911;
+ cached_b[4] = c.b[4] = 1234;
+ cached_b[5] = c.b[5] = 5678;
+ cached_b[6] = c.b[6] = 91011;
+ cached_b[7] = c.b[7] = 121314;
+
+ regs.gpr[4] = (unsigned long)
+
+ /*
+* lxvp XTp,DQ(RA)
+* XTp = 32??TX + 2??Tp
+* let TX=1 Tp=1 RA=4 DQ=0
+*/
+ stepped = emulate_step(, ppc_inst(TEST_LXVP(1, 1, 4, 0)));
+
+ if (stepped == 1 && cpu_has_feature(CPU_FTR_VSX)) {
+ show_result("lxvp", "PASS");
+ } else {
+ if (!cpu_has_feature(CPU_FTR_VSX))
+ show_result("lxvp", "PASS (!CPU_FTR_VSX)");
+ else
+ show_result("lxvp", "FAIL");
+ }
[PATCH 3/4] powerpc ppc-opcode: add opcodes for vsx vector paired instructions
add instruction opcodes for new vsx vector paired instructions, * Load VSX Vector Paired (lxvp) * Load VSX Vector Paired Indexed (lxvpx) * Store VSX Vector Paired (stxvp) * Store VSX Vector Paired Indexed (stxvpx) Signed-off-by: Balamuruhan S --- arch/powerpc/include/asm/ppc-opcode.h | 4 1 file changed, 4 insertions(+) diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index 2a39c716c343..558efd25683b 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -210,6 +210,10 @@ #define PPC_INST_ISEL 0x7c1e #define PPC_INST_ISEL_MASK 0xfc3e #define PPC_INST_LDARX 0x7ca8 +#define PPC_INST_LXVP 0x1800 +#define PPC_INST_LXVPX 0x7c00029a +#define PPC_INST_STXVP 0x1801 +#define PPC_INST_STXVPX0x7c00039a #define PPC_INST_STDCX 0x7c0001ad #define PPC_INST_LQARX 0x7c000228 #define PPC_INST_STQCX 0x7c00016d -- 2.24.1
[PATCH 2/4] powerpc/sstep: support emulation for vsx vector paired storage access instructions
add emulate_step() changes to support vsx vector paired storage
access instructions that provides octword operands loads/stores
between storage and set of 64 Vector Scalar Registers (VSRs).
Signed-off-by: Balamuruhan S
---
arch/powerpc/include/asm/sstep.h | 2 +-
arch/powerpc/lib/sstep.c | 58 +++-
2 files changed, 50 insertions(+), 10 deletions(-)
diff --git a/arch/powerpc/include/asm/sstep.h b/arch/powerpc/include/asm/sstep.h
index 3b01c69a44aa..a6c0b299bcc9 100644
--- a/arch/powerpc/include/asm/sstep.h
+++ b/arch/powerpc/include/asm/sstep.h
@@ -126,7 +126,7 @@ union vsx_reg {
unsigned long d[2];
float fp[4];
double dp[2];
- __vector128 v;
+ __vector128 v[2];
};
/*
diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index c92890e71ca7..74c730cae7d8 100644
--- a/arch/powerpc/lib/sstep.c
+++ b/arch/powerpc/lib/sstep.c
@@ -279,6 +279,19 @@ static nokprobe_inline void do_byte_reverse(void *ptr, int
nb)
up[1] = tmp;
break;
}
+ case 32: {
+ unsigned long *up = (unsigned long *)ptr;
+ unsigned long tmp;
+
+ tmp = byterev_8(up[0]);
+ up[0] = byterev_8(up[3]);
+ up[3] = tmp;
+ tmp = byterev_8(up[2]);
+ up[2] = byterev_8(up[1]);
+ up[1] = tmp;
+ break;
+ }
+
#endif
default:
WARN_ON_ONCE(1);
@@ -709,6 +722,8 @@ void emulate_vsx_load(struct instruction_op *op, union
vsx_reg *reg,
reg->d[0] = reg->d[1] = 0;
switch (op->element_size) {
+ case 32:
+ /* [p]lxvp[x] or [p]stxvp[x] */
case 16:
/* whole vector; lxv[x] or lxvl[l] */
if (size == 0)
@@ -717,7 +732,7 @@ void emulate_vsx_load(struct instruction_op *op, union
vsx_reg *reg,
if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
rev = !rev;
if (rev)
- do_byte_reverse(reg, 16);
+ do_byte_reverse(reg, size);
break;
case 8:
/* scalar loads, lxvd2x, lxvdsx */
@@ -793,6 +808,22 @@ void emulate_vsx_store(struct instruction_op *op, const
union vsx_reg *reg,
size = GETSIZE(op->type);
switch (op->element_size) {
+ case 32:
+ /* [p]lxvp[x] or [p]stxvp[x] */
+ if (size == 0)
+ break;
+ if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
+ rev = !rev;
+ if (rev) {
+ /* reverse 32 bytes */
+ buf.d[0] = byterev_8(reg->d[3]);
+ buf.d[1] = byterev_8(reg->d[2]);
+ buf.d[2] = byterev_8(reg->d[1]);
+ buf.d[3] = byterev_8(reg->d[0]);
+ reg =
+ }
+ memcpy(mem, reg, size);
+ break;
case 16:
/* stxv, stxvx, stxvl, stxvll */
if (size == 0)
@@ -861,28 +892,33 @@ static nokprobe_inline int do_vsx_load(struct
instruction_op *op,
bool cross_endian)
{
int reg = op->reg;
- u8 mem[16];
+ int i, nr_vsx_regs;
+ u8 mem[32];
union vsx_reg buf;
int size = GETSIZE(op->type);
if (!address_ok(regs, ea, size) || copy_mem_in(mem, ea, size, regs))
return -EFAULT;
+ nr_vsx_regs = size / sizeof(__vector128);
emulate_vsx_load(op, , mem, cross_endian);
preempt_disable();
if (reg < 32) {
/* FP regs + extensions */
if (regs->msr & MSR_FP) {
- load_vsrn(reg, );
+ for (i = 0; i < nr_vsx_regs; i++)
+ load_vsrn(reg + i, [i]);
} else {
current->thread.fp_state.fpr[reg][0] = buf.d[0];
current->thread.fp_state.fpr[reg][1] = buf.d[1];
}
} else {
if (regs->msr & MSR_VEC)
- load_vsrn(reg, );
+ for (i = 0; i < nr_vsx_regs; i++)
+ load_vsrn(reg + i, [i]);
+
else
- current->thread.vr_state.vr[reg - 32] = buf.v;
+ current->thread.vr_state.vr[reg - 32] = buf.v[0];
}
preempt_enable();
return 0;
@@ -893,27 +929,31 @@ static nokprobe_inline int do_vsx_store(struct
instruction_op *op,
bool cross_endian)
{
int reg = op->reg;
- u8 mem[16];
+ int i, nr_vsx_regs;
+ u8 mem[32];
union vsx_reg buf;
int size = GETSIZE(op->type);
[PATCH 0/4] VSX 32-byte vector paired load/store instructions
VSX vector paired instructions operates with octword (32-byte) operand for loads and stores between storage and a pair of two sequential Vector-Scalar Registers (VSRs). There are 4 word instructions and 2 prefixed instructions that provides this 32-byte storage access operations - lxvp, lxvpx, stxvp, stxvpx, plxvpx, pstxvpx. Emulation infrastructure doesn't have support for these instructions, to operate with 32-byte storage access and to operate with 2 VSX registers. This patch series enables the instruction emulation support and adds test cases for them respectively. Balamuruhan S (4): powerpc/sstep: support new VSX vector paired storage access instructions powerpc/sstep: support emulation for vsx vector paired storage access instructions powerpc ppc-opcode: add opcodes for vsx vector paired instructions powerpc sstep: add testcases for vsx load/store instructions arch/powerpc/include/asm/ppc-opcode.h | 11 ++ arch/powerpc/include/asm/sstep.h | 2 +- arch/powerpc/lib/sstep.c | 102 +- arch/powerpc/lib/test_emulate_step.c | 273 ++ 4 files changed, 378 insertions(+), 10 deletions(-) base-commit: 6469e8962c20b580b471790fe42367750599 -- 2.24.1
[PATCH 1/4] powerpc/sstep: support new VSX vector paired storage access instructions
VSX Vector Paired instructions loads/stores an octword (32 bytes)
from/to storage into two sequential VSRs. Add `analyse_instr()` support
to these new instructions,
* Load VSX Vector Paired (lxvp)
* Load VSX Vector Paired Indexed (lxvpx)
* Prefixed Load VSX Vector Paired (plxvp)
* Store VSX Vector Paired (stxvp)
* Store VSX Vector Paired Indexed (stxvpx)
* Prefixed Store VSX Vector Paired (pstxvp)
Signed-off-by: Balamuruhan S
---
arch/powerpc/lib/sstep.c | 44
1 file changed, 44 insertions(+)
diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index 5abe98216dc2..c92890e71ca7 100644
--- a/arch/powerpc/lib/sstep.c
+++ b/arch/powerpc/lib/sstep.c
@@ -31,6 +31,10 @@ extern char system_call_common[];
#define XER_OV32 0x0008U
#define XER_CA32 0x0004U
+#ifdef CONFIG_VSX
+#define VSX_REGISTER_XTP(rd) rd) & 1) << 5) | ((rd) & 0xfe))
+#endif
+
#ifdef CONFIG_PPC_FPU
/*
* Functions in ldstfp.S
@@ -2382,6 +2386,13 @@ int analyse_instr(struct instruction_op *op, const
struct pt_regs *regs,
op->vsx_flags = VSX_SPLAT;
break;
+ case 333: /* lxvpx */
+ op->reg = VSX_REGISTER_XTP(rd);
+ op->type = MKOP(LOAD_VSX, 0, 32);
+ op->element_size = 32;
+ op->vsx_flags = VSX_CHECK_VEC;
+ break;
+
case 364: /* lxvwsx */
op->reg = rd | ((word & 1) << 5);
op->type = MKOP(LOAD_VSX, 0, 4);
@@ -2410,6 +2421,12 @@ int analyse_instr(struct instruction_op *op, const
struct pt_regs *regs,
VSX_CHECK_VEC;
break;
}
+ case 461: /* stxvpx */
+ op->reg = VSX_REGISTER_XTP(rd);
+ op->type = MKOP(STORE_VSX, 0, 32);
+ op->element_size = 32;
+ op->vsx_flags = VSX_CHECK_VEC;
+ break;
case 524: /* lxsspx */
op->reg = rd | ((word & 1) << 5);
op->type = MKOP(LOAD_VSX, 0, 4);
@@ -2651,6 +2668,21 @@ int analyse_instr(struct instruction_op *op, const
struct pt_regs *regs,
#endif
#ifdef CONFIG_VSX
+ case 6:
+ op->ea = dqform_ea(word, regs);
+ op->reg = VSX_REGISTER_XTP(rd);
+ op->element_size = 32;
+ op->vsx_flags = VSX_CHECK_VEC;
+ switch (word & 0xf) {
+ case 0: /* lxvp */
+ op->type = MKOP(LOAD_VSX, 0, 32);
+ break;
+ case 1: /* stxvp */
+ op->type = MKOP(STORE_VSX, 0, 32);
+ break;
+ }
+ break;
+
case 61:/* stfdp, lxv, stxsd, stxssp, stxv */
switch (word & 7) {
case 0: /* stfdp with LSB of DS field = 0 */
@@ -2779,12 +2811,24 @@ int analyse_instr(struct instruction_op *op, const
struct pt_regs *regs,
case 57:/* pld */
op->type = MKOP(LOAD, PREFIXED, 8);
break;
+ case 58:/* plxvp */
+ op->reg = VSX_REGISTER_XTP(rd);
+ op->type = MKOP(LOAD_VSX, PREFIXED, 32);
+ op->element_size = 32;
+ op->vsx_flags = VSX_CHECK_VEC;
+ break;
case 60:/* stq */
op->type = MKOP(STORE, PREFIXED, 16);
break;
case 61:/* pstd */
op->type = MKOP(STORE, PREFIXED, 8);
break;
+ case 62:/* pstxvp */
+ op->reg = VSX_REGISTER_XTP(rd);
+ op->type = MKOP(STORE_VSX, PREFIXED, 32);
+ op->element_size = 32;
+ op->vsx_flags = VSX_CHECK_VEC;
+ break;
}
break;
case 1: /* Type 01 Eight-Byte Register-to-Register */
base-commit: 6469e8962c20b580b471790fe42367750599
--
2.24.1
[PATCH v2 3/4] powerpc sstep: introduce macros to retrieve Prefix instruction operands
retrieve prefix instruction operands RA and pc relative bit R values
using macros and adopt it in sstep.c and test_emulate_step.c.
Signed-off-by: Balamuruhan S
---
arch/powerpc/include/asm/sstep.h | 4
arch/powerpc/lib/sstep.c | 12 ++--
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/include/asm/sstep.h b/arch/powerpc/include/asm/sstep.h
index 3b01c69a44aa..325975b4ef30 100644
--- a/arch/powerpc/include/asm/sstep.h
+++ b/arch/powerpc/include/asm/sstep.h
@@ -104,6 +104,10 @@ enum instruction_type {
#define MKOP(t, f, s) ((t) | (f) | SIZE(s))
+/* Prefix instruction operands */
+#define GET_PREFIX_RA(i) (((i) >> 16) & 0x1f)
+#define GET_PREFIX_R(i)((i) & (1ul << 20))
+
struct instruction_op {
int type;
int reg;
diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index 5abe98216dc2..fb4c5767663d 100644
--- a/arch/powerpc/lib/sstep.c
+++ b/arch/powerpc/lib/sstep.c
@@ -200,8 +200,8 @@ static nokprobe_inline unsigned long mlsd_8lsd_ea(unsigned
int instr,
unsigned int dd;
unsigned long ea, d0, d1, d;
- prefix_r = instr & (1ul << 20);
- ra = (suffix >> 16) & 0x1f;
+ prefix_r = GET_PREFIX_R(instr);
+ ra = GET_PREFIX_RA(suffix);
d0 = instr & 0x3;
d1 = suffix & 0x;
@@ -1339,8 +1339,8 @@ int analyse_instr(struct instruction_op *op, const struct
pt_regs *regs,
switch (opcode) {
#ifdef __powerpc64__
case 1:
- prefix_r = word & (1ul << 20);
- ra = (suffix >> 16) & 0x1f;
+ prefix_r = GET_PREFIX_R(word);
+ ra = GET_PREFIX_RA(suffix);
rd = (suffix >> 21) & 0x1f;
op->reg = rd;
op->val = regs->gpr[rd];
@@ -2715,8 +2715,8 @@ int analyse_instr(struct instruction_op *op, const struct
pt_regs *regs,
}
break;
case 1: /* Prefixed instructions */
- prefix_r = word & (1ul << 20);
- ra = (suffix >> 16) & 0x1f;
+ prefix_r = GET_PREFIX_R(word);
+ ra = GET_PREFIX_RA(suffix);
op->update_reg = ra;
rd = (suffix >> 21) & 0x1f;
op->reg = rd;
--
2.24.1
[PATCH v2 1/4] powerpc test_emulate_step: enhancement to test negative scenarios
add provision to declare test is a negative scenario, verify
whether emulation fails and avoid executing it.
Signed-off-by: Balamuruhan S
---
arch/powerpc/lib/test_emulate_step.c | 30 +++-
1 file changed, 21 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/lib/test_emulate_step.c
b/arch/powerpc/lib/test_emulate_step.c
index 0ca2b7cc8d8c..7c30a69c174f 100644
--- a/arch/powerpc/lib/test_emulate_step.c
+++ b/arch/powerpc/lib/test_emulate_step.c
@@ -118,6 +118,7 @@
#define IGNORE_GPR(n) (0x1UL << (n))
#define IGNORE_XER (0x1UL << 32)
#define IGNORE_CCR (0x1UL << 33)
+#define NEGATIVE_TEST (0x1UL << 63)
static void __init init_pt_regs(struct pt_regs *regs)
{
@@ -1202,8 +1203,10 @@ static struct compute_test compute_tests[] = {
};
static int __init emulate_compute_instr(struct pt_regs *regs,
- struct ppc_inst instr)
+ struct ppc_inst instr,
+ bool negative)
{
+ int analysed;
extern s32 patch__exec_instr;
struct instruction_op op;
@@ -1212,13 +1215,17 @@ static int __init emulate_compute_instr(struct pt_regs
*regs,
regs->nip = patch_site_addr(__exec_instr);
- if (analyse_instr(, regs, instr) != 1 ||
- GETTYPE(op.type) != COMPUTE) {
- pr_info("execution failed, instruction = %s\n",
ppc_inst_as_str(instr));
+ analysed = analyse_instr(, regs, instr);
+ if (analysed != 1 || GETTYPE(op.type) != COMPUTE) {
+ if (negative)
+ return -EFAULT;
+ pr_info("emulation failed, instruction = %s\n",
ppc_inst_as_str(instr));
return -EFAULT;
}
-
- emulate_update_regs(regs, );
+ if (analysed == 1 && negative)
+ pr_info("negative test failed, instruction = %s\n",
ppc_inst_as_str(instr));
+ if (!negative)
+ emulate_update_regs(regs, );
return 0;
}
@@ -1256,7 +1263,7 @@ static void __init run_tests_compute(void)
struct pt_regs *regs, exp, got;
unsigned int i, j, k;
struct ppc_inst instr;
- bool ignore_gpr, ignore_xer, ignore_ccr, passed;
+ bool ignore_gpr, ignore_xer, ignore_ccr, passed, rc, negative;
for (i = 0; i < ARRAY_SIZE(compute_tests); i++) {
test = _tests[i];
@@ -1270,6 +1277,7 @@ static void __init run_tests_compute(void)
instr = test->subtests[j].instr;
flags = test->subtests[j].flags;
regs = >subtests[j].regs;
+ negative = flags & NEGATIVE_TEST;
ignore_xer = flags & IGNORE_XER;
ignore_ccr = flags & IGNORE_CCR;
passed = true;
@@ -1284,8 +1292,12 @@ static void __init run_tests_compute(void)
exp.msr = MSR_KERNEL;
got.msr = MSR_KERNEL;
- if (emulate_compute_instr(, instr) ||
- execute_compute_instr(, instr)) {
+ rc = emulate_compute_instr(, instr, negative) != 0;
+ if (negative) {
+ /* skip executing instruction */
+ passed = rc;
+ goto print;
+ } else if (rc || execute_compute_instr(, instr)) {
passed = false;
goto print;
}
--
2.24.1
[PATCH v2 2/6] powerpc/ppc-opcode: move ppc instruction encoding from test_emulate_step
Few ppc instructions are encoded in test_emulate_step.c, consolidate them and use it from ppc-opcode.h Signed-off-by: Balamuruhan S Acked-by: Naveen N. Rao Tested-by: Naveen N. Rao Acked-by: Sandipan Das --- arch/powerpc/include/asm/ppc-opcode.h | 18 +++ arch/powerpc/lib/test_emulate_step.c | 155 ++ 2 files changed, 74 insertions(+), 99 deletions(-) diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index 360dc7d03a9b..c7d81bc473f0 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -76,6 +76,9 @@ #define__REGA0_R30 30 #define__REGA0_R31 31 +#define IMM_L(i) ((uintptr_t)(i) & 0x) +#define IMM_DS(i) ((uintptr_t)(i) & 0xfffc) + /* opcode and xopcode for instructions */ #define OP_TRAP 3 #define OP_TRAP_64 2 @@ -512,6 +515,21 @@ (PPC_INST_VCMPEQUD | ___PPC_RT(vrt) | ___PPC_RA(vra) | ___PPC_RB(vrb) | __PPC_RC21) #define PPC_RAW_VCMPEQUB_RC(vrt, vra, vrb) \ (PPC_INST_VCMPEQUB | ___PPC_RT(vrt) | ___PPC_RA(vra) | ___PPC_RB(vrb) | __PPC_RC21) +#define PPC_RAW_LD(r, base, i) (PPC_INST_LD | ___PPC_RT(r) | ___PPC_RA(base) | IMM_DS(i)) +#define PPC_RAW_LWZ(r, base, i)(PPC_INST_LWZ | ___PPC_RT(r) | ___PPC_RA(base) | IMM_L(i)) +#define PPC_RAW_LWZX(t, a, b) (PPC_INST_LWZX | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_RAW_STD(r, base, i)(PPC_INST_STD | ___PPC_RS(r) | ___PPC_RA(base) | IMM_DS(i)) +#define PPC_RAW_STDCX(s, a, b) (PPC_INST_STDCX | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_RAW_LFSX(t, a, b) (PPC_INST_LFSX | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_RAW_STFSX(s, a, b) (PPC_INST_STFSX | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_RAW_LFDX(t, a, b) (PPC_INST_LFDX | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_RAW_STFDX(s, a, b) (PPC_INST_STFDX | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_RAW_LVX(t, a, b) (PPC_INST_LVX | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_RAW_STVX(s, a, b) (PPC_INST_STVX | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_RAW_ADD(t, a, b) (PPC_INST_ADD | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_RAW_ADD_DOT(t, a, b) (PPC_INST_ADD | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | 0x1) +#define PPC_RAW_ADDC(t, a, b) (PPC_INST_ADDC | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_RAW_ADDC_DOT(t, a, b) (PPC_INST_ADDC | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | 0x1) /* Deal with instructions that older assemblers aren't aware of */ #definePPC_CP_ABORTstringify_in_c(.long PPC_INST_CP_ABORT) diff --git a/arch/powerpc/lib/test_emulate_step.c b/arch/powerpc/lib/test_emulate_step.c index 46af80279ebc..988c734e7370 100644 --- a/arch/powerpc/lib/test_emulate_step.c +++ b/arch/powerpc/lib/test_emulate_step.c @@ -13,49 +13,6 @@ #include #include -#define IMM_L(i) ((uintptr_t)(i) & 0x) -#define IMM_DS(i) ((uintptr_t)(i) & 0xfffc) - -/* - * Defined with TEST_ prefix so it does not conflict with other - * definitions. - */ -#define TEST_LD(r, base, i)ppc_inst(PPC_INST_LD | ___PPC_RT(r) | \ - ___PPC_RA(base) | IMM_DS(i)) -#define TEST_LWZ(r, base, i) ppc_inst(PPC_INST_LWZ | ___PPC_RT(r) | \ - ___PPC_RA(base) | IMM_L(i)) -#define TEST_LWZX(t, a, b) ppc_inst(PPC_INST_LWZX | ___PPC_RT(t) | \ - ___PPC_RA(a) | ___PPC_RB(b)) -#define TEST_STD(r, base, i) ppc_inst(PPC_INST_STD | ___PPC_RS(r) | \ - ___PPC_RA(base) | IMM_DS(i)) -#define TEST_LDARX(t, a, b, eh)ppc_inst(PPC_INST_LDARX | ___PPC_RT(t) |\ - ___PPC_RA(a) | ___PPC_RB(b) | \ - __PPC_EH(eh)) -#define TEST_STDCX(s, a, b)ppc_inst(PPC_INST_STDCX | ___PPC_RS(s) | \ - ___PPC_RA(a) | ___PPC_RB(b)) -#define TEST_LFSX(t, a, b) ppc_inst(PPC_INST_LFSX | ___PPC_RT(t) | \ - ___PPC_RA(a) | ___PPC_RB(b)) -#define TEST_STFSX(s, a, b)ppc_inst(PPC_INST_STFSX | ___PPC_RS(s) | \ - ___PPC_RA(a) | ___PPC_RB(b)) -#define TEST_LFDX(t, a, b) ppc_inst(PPC_INST_LFDX | ___PPC_RT(t) | \ - ___PPC_RA(a) | ___PPC_RB(b)) -#define TEST_STFDX(s, a, b)ppc_inst(PPC_INST_STFDX | ___PPC_RS(s) | \ - ___PPC_RA(a) | ___PPC_RB(b)) -#define TEST_LVX(t, a, b) ppc_inst(PPC_INST_L
[PATCH v2 1/6] powerpc/ppc-opcode: introduce PPC_RAW_* macros for base instruction encoding
Introduce PPC_RAW_* macros to have all the bare encoding of ppc instructions. Move `VSX_XX*()` and `TMRN()` macros up to reuse it. Signed-off-by: Balamuruhan S Acked-by: Naveen N. Rao Tested-by: Naveen N. Rao --- arch/powerpc/include/asm/ppc-opcode.h | 90 --- 1 file changed, 82 insertions(+), 8 deletions(-) diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index 2a39c716c343..360dc7d03a9b 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -431,6 +431,88 @@ #define __PPC_EH(eh) 0 #endif +/* Base instruction encoding */ +#define PPC_RAW_CP_ABORT (PPC_INST_CP_ABORT) +#define PPC_RAW_COPY(a, b) (PPC_INST_COPY | ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_RAW_DARN(t, l) (PPC_INST_DARN | ___PPC_RT(t) | (((l) & 0x3) << 16)) +#define PPC_RAW_DCBAL(a, b)(PPC_INST_DCBAL | __PPC_RA(a) | __PPC_RB(b)) +#define PPC_RAW_DCBZL(a, b)(PPC_INST_DCBZL | __PPC_RA(a) | __PPC_RB(b)) +#define PPC_RAW_LQARX(t, a, b, eh) (PPC_INST_LQARX | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | __PPC_EH(eh)) +#define PPC_RAW_LDARX(t, a, b, eh) (PPC_INST_LDARX | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | __PPC_EH(eh)) +#define PPC_RAW_LWARX(t, a, b, eh) (PPC_INST_LWARX | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | __PPC_EH(eh)) +#define PPC_RAW_STQCX(t, a, b) (PPC_INST_STQCX | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_RAW_MADDHD(t, a, b, c) (PPC_INST_MADDHD | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | ___PPC_RC(c)) +#define PPC_RAW_MADDHDU(t, a, b, c)(PPC_INST_MADDHDU | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | ___PPC_RC(c)) +#define PPC_RAW_MADDLD(t, a, b, c) (PPC_INST_MADDLD | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | ___PPC_RC(c)) +#define PPC_RAW_MSGSND(b) (PPC_INST_MSGSND | ___PPC_RB(b)) +#define PPC_RAW_MSGSYNC(PPC_INST_MSGSYNC) +#define PPC_RAW_MSGCLR(b) (PPC_INST_MSGCLR | ___PPC_RB(b)) +#define PPC_RAW_MSGSNDP(b) (PPC_INST_MSGSNDP | ___PPC_RB(b)) +#define PPC_RAW_MSGCLRP(b) (PPC_INST_MSGCLRP | ___PPC_RB(b)) +#define PPC_RAW_PASTE(a, b)(PPC_INST_PASTE | ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_RAW_POPCNTB(a, s) (PPC_INST_POPCNTB | __PPC_RA(a) | __PPC_RS(s)) +#define PPC_RAW_POPCNTD(a, s) (PPC_INST_POPCNTD | __PPC_RA(a) | __PPC_RS(s)) +#define PPC_RAW_POPCNTW(a, s) (PPC_INST_POPCNTW | __PPC_RA(a) | __PPC_RS(s)) +#define PPC_RAW_RFCI (PPC_INST_RFCI) +#define PPC_RAW_RFDI (PPC_INST_RFDI) +#define PPC_RAW_RFMCI (PPC_INST_RFMCI) +#define PPC_RAW_TLBILX(t, a, b)(PPC_INST_TLBILX | __PPC_T_TLB(t) | __PPC_RA0(a) | __PPC_RB(b)) +#define PPC_RAW_WAIT(w)(PPC_INST_WAIT | __PPC_WC(w)) +#define PPC_RAW_TLBIE(lp, a) (PPC_INST_TLBIE | ___PPC_RB(a) | ___PPC_RS(lp)) +#define PPC_RAW_TLBIE_5(rb, rs, ric, prs, r) \ + (PPC_INST_TLBIE | ___PPC_RB(rb) | ___PPC_RS(rs) | ___PPC_RIC(ric) | ___PPC_PRS(prs) | ___PPC_R(r)) +#define PPC_RAW_TLBIEL(rb, rs, ric, prs, r) \ + (PPC_INST_TLBIEL | ___PPC_RB(rb) | ___PPC_RS(rs) | ___PPC_RIC(ric) | ___PPC_PRS(prs) | ___PPC_R(r)) +#define PPC_RAW_TLBSRX_DOT(a, b) (PPC_INST_TLBSRX_DOT | __PPC_RA0(a) | __PPC_RB(b)) +#define PPC_RAW_TLBIVAX(a, b) (PPC_INST_TLBIVAX | __PPC_RA0(a) | __PPC_RB(b)) +#define PPC_RAW_ERATWE(s, a, w)(PPC_INST_ERATWE | __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w)) +#define PPC_RAW_ERATRE(s, a, w)(PPC_INST_ERATRE | __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w)) +#define PPC_RAW_ERATILX(t, a, b) (PPC_INST_ERATILX | __PPC_T_TLB(t) | __PPC_RA0(a) | __PPC_RB(b)) +#define PPC_RAW_ERATIVAX(s, a, b) (PPC_INST_ERATIVAX | __PPC_RS(s) | __PPC_RA0(a) | __PPC_RB(b)) +#define PPC_RAW_ERATSX(t, a, w)(PPC_INST_ERATSX | __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b)) +#define PPC_RAW_ERATSX_DOT(t, a, w)(PPC_INST_ERATSX_DOT | __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b)) +#define PPC_RAW_SLBFEE_DOT(t, b) (PPC_INST_SLBFEE | __PPC_RT(t) | __PPC_RB(b)) +#define __PPC_RAW_SLBFEE_DOT(t, b) (PPC_INST_SLBFEE | ___PPC_RT(t) | ___PPC_RB(b)) +#define PPC_RAW_ICBT(c, a, b) (PPC_INST_ICBT | __PPC_CT(c) | __PPC_RA0(a) | __PPC_RB(b)) +#define PPC_RAW_LBZCIX(t, a, b)(PPC_INST_LBZCIX | __PPC_RT(t) | __PPC_RA(a) | __PPC_RB(b)) +#define PPC_RAW_STBCIX(s, a, b)(PPC_INST_STBCIX | __PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b)) +/* + * Define what the VSX XX1 form instructions will look like, then add + * the 128 bit load store instructions based on that. + */ +#define VSX_XX1(s, a, b) (__PPC_XS(s) | __PPC_RA(a) | __PPC_RB(b)) +#define VSX_XX3(t, a, b) (__PPC_XT(t) | __PPC_XA(a) | __PPC_XB(b)) +#define PPC_RAW
[PATCH v2 0/6] consolidate PowerPC instruction encoding macros
ppc-opcode.h have base instruction encoding wrapped with stringify_in_c() for raw encoding to have compatibility. But there are redundant macros for base instruction encodings in bpf, instruction emulation test infrastructure and powerpc selftests. Currently PPC_INST_* macros are used for encoding instruction opcode and PPC_* for raw instuction encoding, this rfc patchset introduces PPC_RAW_* macros for base instruction encoding and reuse it from elsewhere. With this change we can avoid redundant macro definitions in multiple files and start adding new instructions in ppc-opcode.h in future. Changes in v2: - * Fixed review comments from mpe by not wrapping the macro definitions * Include Acked-by from Sandipan * Rebase on master branch of linuxppc tree, to avoid conflict with prefixed instruction support Changes in v1: - * Drop the patch that had changes in stringloops Makefile. * Include Acked-by and Tested-by tag from Naveen. * Rebased on next branch of linuxppc tree. Changes in rfc v2: - Fix review comments/suggestions from Naveen and Michael Ellerman, * Rename PPC_ENCODE_* to PPC_RAW_* for base instruction encoding macros. * Split the patches that does mass renaming and make them simpler that just adds new macros. * Keep the patch to update all the existing names later (patch 6). * Lot of PPC_INST_* macros are used only in ppc-opcode.h for PPC_* macros, fold PPC_INST_* encoding into PPC_RAW_* to avoid using them accidentally. * Fixed clipped macros that was due to a typo/copy-paste * Consolidated all the instruction encoding macros from bpf_jit.h to ppc-opcode.h * squashed patch that removes the duplicate macro PPC_MR() in bpf_jit.h * merge few changes in bpf_jit files from patch 2 into patch 3 * few fixes in powerpc selftest stringloops Makefile * build tested for ppc64le_defconfig, ppc64e_defconfig and pmac32_defconfig * Rebased on next branch of linuxppc tree Testing: --- * Tested it by compiling vmlinux and comparing objdump of it with and without the patchset and observed that it remains same, # diff vmlinux_objdump vmlinux_rfc_objdump 2c2 < vmlinux: file format elf64-powerpcle --- > vmlinux_rfc: file format elf64-powerpcle * Tested building it with this changes for Fedora30 config, booted VM with powerpc next and powerpc next + patchset to run powerpc selftest and ftrace selftest. There were couple of failures that were common and patchset did not introduce any new failures. ftrace selftest: --- # # of passed: 96 # # of failed: 1 # # of unresolved: 7 # # of untested: 0 # # of unsupported: 1 # # of xfailed: 1 # # of undefined(test bug): 0 not ok 1 selftests: ftrace: ftracetest # exit=1 powerpc selftest: not ok 7 selftests: powerpc/dscr: dscr_sysfs_thread_test # exit=1 not ok 20 selftests: powerpc/pmu/ebb: lost_exception_test # TIMEOUT not ok 2 selftests: powerpc/security: spectre_v2 # exit=1 Thanks to Naveen, Sandipan and Michael on overall suggestions/improvements. I would request for review and suggestions to make it better. v1: https://lists.ozlabs.org/pipermail/linuxppc-dev/2020-May/211441.html rfc v2: https://lists.ozlabs.org/pipermail/linuxppc-dev/2020-April/209395.html rfc v1: https://lists.ozlabs.org/pipermail/linuxppc-dev/2020-March/206494.html Balamuruhan S (6): powerpc/ppc-opcode: introduce PPC_RAW_* macros for base instruction encoding powerpc/ppc-opcode: move ppc instruction encoding from test_emulate_step powerpc/bpf_jit: reuse instruction macros from ppc-opcode.h powerpc/ppc-opcode: consolidate powerpc instructions from bpf_jit.h powerpc/ppc-opcode: reuse raw instruction macros to stringify powerpc/ppc-opcode: fold PPC_INST_* macros into PPC_RAW_* macros arch/powerpc/include/asm/ppc-opcode.h | 541 -- arch/powerpc/lib/test_emulate_step.c | 155 +++- arch/powerpc/net/bpf_jit.h| 184 + arch/powerpc/net/bpf_jit32.h | 34 +- arch/powerpc/net/bpf_jit64.h | 16 +- arch/powerpc/net/bpf_jit_comp.c | 134 +++ arch/powerpc/net/bpf_jit_comp64.c | 298 +++--- 7 files changed, 568 insertions(+), 794 deletions(-) base-commit: 6469e8962c20b580b471790fe42367750599 -- 2.24.1
[PATCH 6/6] powerpc test_emulate_step: move extern declaration to sstep.h
fix checkpatch.pl warnings by moving extern declaration from source
file to headerfile.
Signed-off-by: Balamuruhan S
---
arch/powerpc/include/asm/sstep.h | 2 ++
arch/powerpc/lib/test_emulate_step.c | 2 --
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/sstep.h b/arch/powerpc/include/asm/sstep.h
index 325975b4ef30..c8e37ef060c1 100644
--- a/arch/powerpc/include/asm/sstep.h
+++ b/arch/powerpc/include/asm/sstep.h
@@ -108,6 +108,8 @@ enum instruction_type {
#define GET_PREFIX_RA(i) (((i) >> 16) & 0x1f)
#define GET_PREFIX_R(i)((i) & (1ul << 20))
+extern s32 patch__exec_instr;
+
struct instruction_op {
int type;
int reg;
diff --git a/arch/powerpc/lib/test_emulate_step.c
b/arch/powerpc/lib/test_emulate_step.c
index f1a447026b6e..386245607568 100644
--- a/arch/powerpc/lib/test_emulate_step.c
+++ b/arch/powerpc/lib/test_emulate_step.c
@@ -1217,7 +1217,6 @@ static int __init emulate_compute_instr(struct pt_regs
*regs,
bool negative)
{
int prefix_r, ra, analysed;
- extern s32 patch__exec_instr;
struct instruction_op op;
if (!regs || !ppc_inst_val(instr))
@@ -1268,7 +1267,6 @@ static int __init execute_compute_instr(struct pt_regs
*regs,
struct ppc_inst instr)
{
extern int exec_instr(struct pt_regs *regs);
- extern s32 patch__exec_instr;
if (!regs || !ppc_inst_val(instr))
return -EINVAL;
--
2.24.1
[PATCH 5/6] powerpc sstep: introduce macros to retrieve Prefix instruction operands
retrieve prefix instruction operands RA and pc relative bit R values
using macros and adopt it in sstep.c and test_emulate_step.c.
Signed-off-by: Balamuruhan S
---
arch/powerpc/include/asm/sstep.h | 4
arch/powerpc/lib/sstep.c | 12 ++--
arch/powerpc/lib/test_emulate_step.c | 4 ++--
3 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/include/asm/sstep.h b/arch/powerpc/include/asm/sstep.h
index 3b01c69a44aa..325975b4ef30 100644
--- a/arch/powerpc/include/asm/sstep.h
+++ b/arch/powerpc/include/asm/sstep.h
@@ -104,6 +104,10 @@ enum instruction_type {
#define MKOP(t, f, s) ((t) | (f) | SIZE(s))
+/* Prefix instruction operands */
+#define GET_PREFIX_RA(i) (((i) >> 16) & 0x1f)
+#define GET_PREFIX_R(i)((i) & (1ul << 20))
+
struct instruction_op {
int type;
int reg;
diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index 5abe98216dc2..fb4c5767663d 100644
--- a/arch/powerpc/lib/sstep.c
+++ b/arch/powerpc/lib/sstep.c
@@ -200,8 +200,8 @@ static nokprobe_inline unsigned long mlsd_8lsd_ea(unsigned
int instr,
unsigned int dd;
unsigned long ea, d0, d1, d;
- prefix_r = instr & (1ul << 20);
- ra = (suffix >> 16) & 0x1f;
+ prefix_r = GET_PREFIX_R(instr);
+ ra = GET_PREFIX_RA(suffix);
d0 = instr & 0x3;
d1 = suffix & 0x;
@@ -1339,8 +1339,8 @@ int analyse_instr(struct instruction_op *op, const struct
pt_regs *regs,
switch (opcode) {
#ifdef __powerpc64__
case 1:
- prefix_r = word & (1ul << 20);
- ra = (suffix >> 16) & 0x1f;
+ prefix_r = GET_PREFIX_R(word);
+ ra = GET_PREFIX_RA(suffix);
rd = (suffix >> 21) & 0x1f;
op->reg = rd;
op->val = regs->gpr[rd];
@@ -2715,8 +2715,8 @@ int analyse_instr(struct instruction_op *op, const struct
pt_regs *regs,
}
break;
case 1: /* Prefixed instructions */
- prefix_r = word & (1ul << 20);
- ra = (suffix >> 16) & 0x1f;
+ prefix_r = GET_PREFIX_R(word);
+ ra = GET_PREFIX_RA(suffix);
op->update_reg = ra;
rd = (suffix >> 21) & 0x1f;
op->reg = rd;
diff --git a/arch/powerpc/lib/test_emulate_step.c
b/arch/powerpc/lib/test_emulate_step.c
index f9825c275c31..f1a447026b6e 100644
--- a/arch/powerpc/lib/test_emulate_step.c
+++ b/arch/powerpc/lib/test_emulate_step.c
@@ -1229,8 +1229,8 @@ static int __init emulate_compute_instr(struct pt_regs
*regs,
* instruction
*/
if (ppc_inst_prefixed(instr)) {
- prefix_r = ppc_inst_val(instr) & (1UL << 20);
- ra = (ppc_inst_suffix(instr) >> 16) & 0x1f;
+ prefix_r = GET_PREFIX_R(ppc_inst_val(instr));
+ ra = GET_PREFIX_RA(ppc_inst_suffix(instr));
if (prefix_r && !ra)
regs->nip = patch_site_addr(__exec_instr);
}
--
2.24.1
[PATCH 4/6] powerpc test_emulate_step: add negative tests for prefixed addi
testcases for `paddi` instruction to cover the negative case,
if R is equal to 1 and RA is not equal to 0, the instruction
form is invalid.
Signed-off-by: Balamuruhan S
---
arch/powerpc/lib/test_emulate_step.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/powerpc/lib/test_emulate_step.c
b/arch/powerpc/lib/test_emulate_step.c
index 79acc899a618..f9825c275c31 100644
--- a/arch/powerpc/lib/test_emulate_step.c
+++ b/arch/powerpc/lib/test_emulate_step.c
@@ -1197,6 +1197,16 @@ static struct compute_test compute_tests[] = {
.regs = {
.gpr[21] = 0,
}
+ },
+ /* Invalid instruction form with R = 1 and RA != 0 */
+ {
+ .descr = "RA = R22(0), SI = 0, R = 1",
+ .instr = TEST_PADDI(21, 22, 0, 1),
+ .negative = true,
+ .regs = {
+ .gpr[21] = 0,
+ .gpr[22] = 0,
+ }
}
}
}
--
2.24.1
[PATCH 3/6] powerpc test_emulate_step: enhancement to test negative scenarios
add provision to declare test is a negative scenario, verify
whether emulation fails and avoid executing it.
Signed-off-by: Balamuruhan S
---
arch/powerpc/lib/test_emulate_step.c | 46 ++--
1 file changed, 36 insertions(+), 10 deletions(-)
diff --git a/arch/powerpc/lib/test_emulate_step.c
b/arch/powerpc/lib/test_emulate_step.c
index e3b1797adfae..79acc899a618 100644
--- a/arch/powerpc/lib/test_emulate_step.c
+++ b/arch/powerpc/lib/test_emulate_step.c
@@ -703,6 +703,7 @@ struct compute_test {
unsigned long flags;
struct ppc_inst instr;
struct pt_regs regs;
+ bool negative;
} subtests[MAX_SUBTESTS + 1];
};
@@ -1202,9 +1203,10 @@ static struct compute_test compute_tests[] = {
};
static int __init emulate_compute_instr(struct pt_regs *regs,
- struct ppc_inst instr)
+ struct ppc_inst instr,
+ bool negative)
{
- int prefix_r, ra;
+ int prefix_r, ra, analysed;
extern s32 patch__exec_instr;
struct instruction_op op;
@@ -1223,8 +1225,10 @@ static int __init emulate_compute_instr(struct pt_regs
*regs,
regs->nip = patch_site_addr(__exec_instr);
}
- if (analyse_instr(, regs, instr) != 1 ||
- GETTYPE(op.type) != COMPUTE) {
+ analysed = analyse_instr(, regs, instr);
+ if (analysed != 1 || GETTYPE(op.type) != COMPUTE) {
+ if (negative)
+ return -EFAULT;
if (!ppc_inst_prefixed(instr)) {
pr_info("emulation failed, instruction = 0x%08x\n",
ppc_inst_val(instr));
@@ -1235,8 +1239,18 @@ static int __init emulate_compute_instr(struct pt_regs
*regs,
}
return -EFAULT;
}
-
- emulate_update_regs(regs, );
+ if (analysed == 1 && negative) {
+ if (!ppc_inst_prefixed(instr)) {
+ pr_info("negative test failed, instruction = 0x%08x\n",
+ ppc_inst_val(instr));
+ } else {
+ pr_info("negative test failed, instruction = 0x%08x
0x%08x\n",
+ ppc_inst_val(instr),
+ ppc_inst_suffix(instr));
+ }
+ }
+ if (!negative)
+ emulate_update_regs(regs, );
return 0;
}
@@ -1252,7 +1266,14 @@ static int __init execute_compute_instr(struct pt_regs
*regs,
/* Patch the NOP with the actual instruction */
patch_instruction_site(__exec_instr, instr);
if (exec_instr(regs)) {
- pr_info("execution failed, instruction = 0x%08x\n",
ppc_inst_val(instr));
+ if (!ppc_inst_prefixed(instr)) {
+ pr_info("execution failed, instruction = 0x%08x\n",
+ ppc_inst_val(instr));
+ } else {
+ pr_info("execution failed, instruction = 0x%08x
0x%08x\n",
+ ppc_inst_val(instr),
+ ppc_inst_suffix(instr));
+ }
return -EFAULT;
}
@@ -1274,7 +1295,7 @@ static void __init run_tests_compute(void)
struct pt_regs *regs, exp, got;
unsigned int i, j, k;
struct ppc_inst instr;
- bool ignore_gpr, ignore_xer, ignore_ccr, passed;
+ bool ignore_gpr, ignore_xer, ignore_ccr, passed, rc, negative;
for (i = 0; i < ARRAY_SIZE(compute_tests); i++) {
test = _tests[i];
@@ -1288,6 +1309,7 @@ static void __init run_tests_compute(void)
instr = test->subtests[j].instr;
flags = test->subtests[j].flags;
regs = >subtests[j].regs;
+ negative = test->subtests[j].negative;
ignore_xer = flags & IGNORE_XER;
ignore_ccr = flags & IGNORE_CCR;
passed = true;
@@ -1302,8 +1324,12 @@ static void __init run_tests_compute(void)
exp.msr = MSR_KERNEL;
got.msr = MSR_KERNEL;
- if (emulate_compute_instr(, instr) ||
- execute_compute_instr(, instr)) {
+ rc = emulate_compute_instr(, instr, negative) != 0;
+ if (negative) {
+ /* skip executing instruction */
+ passed = rc;
+ goto print;
+ } else if (rc || execute_compute_instr(, instr)) {
passed = false;
goto print;
}
--
2.24.1
[PATCH 2/6] powerpc test_emulate_step: fix pr_info() to print 8-byte for prefixed instruction
On test failure, `pr_log()` prints 4 bytes instruction
irrespective of word/prefix instruction, fix it by printing
them appropriately.
Signed-off-by: Balamuruhan S
---
arch/powerpc/lib/test_emulate_step.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/lib/test_emulate_step.c
b/arch/powerpc/lib/test_emulate_step.c
index d5902b7b4e5c..e3b1797adfae 100644
--- a/arch/powerpc/lib/test_emulate_step.c
+++ b/arch/powerpc/lib/test_emulate_step.c
@@ -1225,7 +1225,14 @@ static int __init emulate_compute_instr(struct pt_regs
*regs,
if (analyse_instr(, regs, instr) != 1 ||
GETTYPE(op.type) != COMPUTE) {
- pr_info("emulation failed, instruction = 0x%08x\n",
ppc_inst_val(instr));
+ if (!ppc_inst_prefixed(instr)) {
+ pr_info("emulation failed, instruction = 0x%08x\n",
+ ppc_inst_val(instr));
+ } else {
+ pr_info("emulation failed, instruction = 0x%08x
0x%08x\n",
+ ppc_inst_val(instr),
+ ppc_inst_suffix(instr));
+ }
return -EFAULT;
}
--
2.24.1
[PATCH 1/6] powerpc test_emulate_step: update nip with patched instruction address
pt_regs are initialized to zero in the test infrastructure, R bit
in prefixed instruction form is used to specify whether the effective
address of the storage operand is computed relative to the address
of the instruction.
If R = 1 and RA = R0|0, the sum of the address of the instruction
and the value SI is placed into register RT. So to assert the emulated
instruction with executed instruction, update nip of emulated pt_regs.
Signed-off-by: Balamuruhan S
---
arch/powerpc/lib/test_emulate_step.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/lib/test_emulate_step.c
b/arch/powerpc/lib/test_emulate_step.c
index 33a72b7d2764..d5902b7b4e5c 100644
--- a/arch/powerpc/lib/test_emulate_step.c
+++ b/arch/powerpc/lib/test_emulate_step.c
@@ -1204,13 +1204,24 @@ static struct compute_test compute_tests[] = {
static int __init emulate_compute_instr(struct pt_regs *regs,
struct ppc_inst instr)
{
+ int prefix_r, ra;
extern s32 patch__exec_instr;
struct instruction_op op;
if (!regs || !ppc_inst_val(instr))
return -EINVAL;
- regs->nip = patch_site_addr(__exec_instr);
+ /*
+* If R=1 and RA=0 in Prefixed instruction form, calculate the address
+* of the instruction and update nip to assert with executed
+* instruction
+*/
+ if (ppc_inst_prefixed(instr)) {
+ prefix_r = ppc_inst_val(instr) & (1UL << 20);
+ ra = (ppc_inst_suffix(instr) >> 16) & 0x1f;
+ if (prefix_r && !ra)
+ regs->nip = patch_site_addr(__exec_instr);
+ }
if (analyse_instr(, regs, instr) != 1 ||
GETTYPE(op.type) != COMPUTE) {
--
2.24.1
[PATCH 0/6] Prefixed instruction tests to cover negative cases
This patchset adds support to test negative scenarios and adds testcase for paddi with few fixes. It is based on powerpc/next and on top of Jordan's tests for prefixed instructions patchset, https://lists.ozlabs.org/pipermail/linuxppc-dev/2020-May/211394.html Balamuruhan S (6): powerpc test_emulate_step: update nip with patched instruction address powerpc test_emulate_step: fix pr_info() to print 8-byte for prefixed instruction powerpc test_emulate_step: enhancement to test negative scenarios powerpc test_emulate_step: add negative tests for prefixed addi powerpc sstep: introduce macros to retrieve Prefix instruction operands powerpc test_emulate_step: move extern declaration to sstep.h arch/powerpc/include/asm/sstep.h | 6 +++ arch/powerpc/lib/sstep.c | 12 ++--- arch/powerpc/lib/test_emulate_step.c | 78 +++- 3 files changed, 77 insertions(+), 19 deletions(-) -- 2.24.1
[PATCH 6/6] powerpc/ppc-opcode: fold PPC_INST_* macros into PPC_RAW_* macros
Lot of PPC_INST_* macros are used only ever in PPC_* macros, fold those PPC_INST_* into PPC_RAW_* to avoid using PPC_INST_* accidentally. Signed-off-by: Balamuruhan S Acked-by: Naveen N. Rao Tested-by: Naveen N. Rao --- arch/powerpc/include/asm/ppc-opcode.h | 381 +- 1 file changed, 125 insertions(+), 256 deletions(-) diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index c8d71a8bef46..bbb77f998f19 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -208,56 +208,27 @@ #define OP_LQ56 /* sorted alphabetically */ -#define PPC_INST_BHRBE 0x7c00025c -#define PPC_INST_CLRBHRB 0x7c00035c #define PPC_INST_COPY 0x7c20060c -#define PPC_INST_CP_ABORT 0x7c00068c -#define PPC_INST_DARN 0x7c0005e6 #define PPC_INST_DCBA 0x7c0005ec #define PPC_INST_DCBA_MASK 0xfc0007fe -#define PPC_INST_DCBAL 0x7c2005ec -#define PPC_INST_DCBZL 0x7c2007ec -#define PPC_INST_ICBT 0x7c2c -#define PPC_INST_ICSWX 0x7c00032d -#define PPC_INST_ICSWEPX 0x7c00076d #define PPC_INST_ISEL 0x7c1e #define PPC_INST_ISEL_MASK 0xfc3e -#define PPC_INST_LDARX 0x7ca8 -#define PPC_INST_STDCX 0x7c0001ad -#define PPC_INST_LQARX 0x7c000228 -#define PPC_INST_STQCX 0x7c00016d #define PPC_INST_LSWI 0x7c0004aa #define PPC_INST_LSWX 0x7c00042a -#define PPC_INST_LWARX 0x7c28 -#define PPC_INST_STWCX 0x7c00012d #define PPC_INST_LWSYNC0x7c2004ac #define PPC_INST_SYNC 0x7c0004ac #define PPC_INST_SYNC_MASK 0xfc0007fe #define PPC_INST_ISYNC 0x4c00012c -#define PPC_INST_LXVD2X0x7c000698 #define PPC_INST_MCRXR 0x7c000400 #define PPC_INST_MCRXR_MASK0xfc0007fe #define PPC_INST_MFSPR_PVR 0x7c1f42a6 #define PPC_INST_MFSPR_PVR_MASK0xfc1e -#define PPC_INST_MFTMR 0x7c0002dc -#define PPC_INST_MSGSND0x7c00019c -#define PPC_INST_MSGCLR0x7c0001dc -#define PPC_INST_MSGSYNC 0x7c0006ec -#define PPC_INST_MSGSNDP 0x7c00011c -#define PPC_INST_MSGCLRP 0x7c00015c #define PPC_INST_MTMSRD0x7c000164 -#define PPC_INST_MTTMR 0x7c0003dc #define PPC_INST_NOP 0x6000 -#define PPC_INST_PASTE 0x7c20070d #define PPC_INST_POPCNTB 0x7cf4 #define PPC_INST_POPCNTB_MASK 0xfc0007fe -#define PPC_INST_POPCNTD 0x7c0003f4 -#define PPC_INST_POPCNTW 0x7c0002f4 #define PPC_INST_RFEBB 0x4c000124 -#define PPC_INST_RFCI 0x4c66 -#define PPC_INST_RFDI 0x4c4e #define PPC_INST_RFID 0x4c24 -#define PPC_INST_RFMCI 0x4c4c #define PPC_INST_MFSPR 0x7c0002a6 #define PPC_INST_MFSPR_DSCR0x7c1102a6 #define PPC_INST_MFSPR_DSCR_MASK 0xfc1e @@ -267,131 +238,30 @@ #define PPC_INST_MFSPR_DSCR_USER_MASK 0xfc1e #define PPC_INST_MTSPR_DSCR_USER 0x7c0303a6 #define PPC_INST_MTSPR_DSCR_USER_MASK 0xfc1e -#define PPC_INST_MFVSRD0x7c66 -#define PPC_INST_MTVSRD0x7c000166 #define PPC_INST_SC0x4402 -#define PPC_INST_SLBFEE0x7c0007a7 -#define PPC_INST_SLBIA 0x7c0003e4 - #define PPC_INST_STRING0x7c00042a #define PPC_INST_STRING_MASK 0xfc0007fe #define PPC_INST_STRING_GEN_MASK 0xfc00067e - #define PPC_INST_STSWI 0x7c0005aa #define PPC_INST_STSWX 0x7c00052a -#define PPC_INST_STXVD2X 0x7c000798 -#define PPC_INST_TLBIE 0x7c000264 -#define PPC_INST_TLBIEL0x7c000224 -#define PPC_INST_TLBILX0x7c24 -#define PPC_INST_WAIT 0x7c7c -#define PPC_INST_TLBIVAX 0x7c000624 -#define PPC_INST_TLBSRX_DOT0x7c0006a5 -#define PPC_INST_VPMSUMW 0x1488 -#define PPC_INST_VPMSUMD 0x14c8 -#define PPC_INST_VPERMXOR 0x102d -#define PPC_INST_XXLOR 0xf490 -#define PPC_INST_XXSWAPD 0xf250 -#define PPC_INST_XVCPSGNDP 0xf780 #define PPC_INST_TRECHKPT 0x7c0007dd #define PPC_INST_TRECLAIM 0x7c00075d -#define PPC_INST_TABORT0x7c00071d #define PPC_INST_TSR
[PATCH 5/6] powerpc/ppc-opcode: reuse raw instruction macros to stringify
Wrap existing stringify macros to reuse raw instruction encoding macros that are newly added. Signed-off-by: Balamuruhan S Acked-by: Naveen N. Rao Tested-by: Naveen N. Rao --- arch/powerpc/include/asm/ppc-opcode.h | 220 +- 1 file changed, 71 insertions(+), 149 deletions(-) diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index 94b889d89395..c8d71a8bef46 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -781,166 +781,92 @@ ___PPC_RA(a)) /* Deal with instructions that older assemblers aren't aware of */ -#definePPC_CP_ABORTstringify_in_c(.long PPC_INST_CP_ABORT) -#definePPC_COPY(a, b) stringify_in_c(.long PPC_INST_COPY | \ - ___PPC_RA(a) | ___PPC_RB(b)) -#define PPC_DARN(t, l) stringify_in_c(.long PPC_INST_DARN | \ - ___PPC_RT(t) | \ - (((l) & 0x3) << 16)) -#definePPC_DCBAL(a, b) stringify_in_c(.long PPC_INST_DCBAL | \ - __PPC_RA(a) | __PPC_RB(b)) -#definePPC_DCBZL(a, b) stringify_in_c(.long PPC_INST_DCBZL | \ - __PPC_RA(a) | __PPC_RB(b)) -#define PPC_LQARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LQARX | \ - ___PPC_RT(t) | ___PPC_RA(a) | \ - ___PPC_RB(b) | __PPC_EH(eh)) -#define PPC_LDARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LDARX | \ - ___PPC_RT(t) | ___PPC_RA(a) | \ - ___PPC_RB(b) | __PPC_EH(eh)) -#define PPC_LWARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LWARX | \ - ___PPC_RT(t) | ___PPC_RA(a) | \ - ___PPC_RB(b) | __PPC_EH(eh)) -#define PPC_STQCX(t, a, b) stringify_in_c(.long PPC_INST_STQCX | \ - ___PPC_RT(t) | ___PPC_RA(a) | \ - ___PPC_RB(b)) -#define PPC_MADDHD(t, a, b, c) stringify_in_c(.long PPC_INST_MADDHD | \ - ___PPC_RT(t) | ___PPC_RA(a) | \ - ___PPC_RB(b) | ___PPC_RC(c)) -#define PPC_MADDHDU(t, a, b, c)stringify_in_c(.long PPC_INST_MADDHDU | \ - ___PPC_RT(t) | ___PPC_RA(a) | \ - ___PPC_RB(b) | ___PPC_RC(c)) -#define PPC_MADDLD(t, a, b, c) stringify_in_c(.long PPC_INST_MADDLD | \ - ___PPC_RT(t) | ___PPC_RA(a) | \ - ___PPC_RB(b) | ___PPC_RC(c)) -#define PPC_MSGSND(b) stringify_in_c(.long PPC_INST_MSGSND | \ - ___PPC_RB(b)) -#define PPC_MSGSYNCstringify_in_c(.long PPC_INST_MSGSYNC) -#define PPC_MSGCLR(b) stringify_in_c(.long PPC_INST_MSGCLR | \ - ___PPC_RB(b)) -#define PPC_MSGSNDP(b) stringify_in_c(.long PPC_INST_MSGSNDP | \ - ___PPC_RB(b)) -#define PPC_MSGCLRP(b) stringify_in_c(.long PPC_INST_MSGCLRP | \ - ___PPC_RB(b)) -#define PPC_PASTE(a, b)stringify_in_c(.long PPC_INST_PASTE | \ - ___PPC_RA(a) | ___PPC_RB(b)) -#define PPC_POPCNTB(a, s) stringify_in_c(.long PPC_INST_POPCNTB | \ - __PPC_RA(a) | __PPC_RS(s)) -#define PPC_POPCNTD(a, s) stringify_in_c(.long PPC_INST_POPCNTD | \ - __PPC_RA(a) | __PPC_RS(s)) -#define PPC_POPCNTW(a, s) stringify_in_c(.long PPC_INST_POPCNTW | \ - __PPC_RA(a) | __PPC_RS(s)) -#define PPC_RFCI stringify_in_c(.long PPC_INST_RFCI) -#define PPC_RFDI stringify_in_c(.long PPC_INST_RFDI) -#define PPC_RFMCI stringify_in_c(.long PPC_INST_RFMCI) -#define PPC_TLBILX(t, a, b)stringify_in_c(.long PPC_INST_TLBILX | \ - __PPC_T_TLB(t) | __PPC_RA0(a) | __PPC_RB(b)) +#definePPC_CP_ABORTstringify_in_c(.long PPC_RAW_CP_ABORT) +#definePPC_COPY(a, b) stringify_in_c(.long PPC_RAW_COPY(a, b)) +#define PPC_DARN(t, l) stringify_in_c(.long PPC_RAW_DARN(t, l)) +#definePPC_DCBAL(a, b) stringify_in_c(.long PPC_RAW_DCBAL(a, b)) +#definePPC_DCBZL(a, b) stringify_in_c(.long PPC_RAW_DCBZL(a, b)) +#define PPC_LQARX(t, a, b, eh) stringify_in_c(.long PPC_RAW_LQARX(t, a, b, eh)) +#define PPC_LDARX(t, a, b, eh) stringify_in_c(.long PPC_RAW_LDARX(t, a, b, eh)
[PATCH 4/6] powerpc/ppc-opcode: consolidate powerpc instructions from bpf_jit.h
move macro definitions of powerpc instructions from bpf_jit.h to ppc-opcode.h and adopt the users of the macros accordingly. `PPC_MR()` is defined twice in bpf_jit.h, remove the duplicate one. Signed-off-by: Balamuruhan S Acked-by: Naveen N. Rao Tested-by: Naveen N. Rao --- arch/powerpc/include/asm/ppc-opcode.h | 139 + arch/powerpc/net/bpf_jit.h| 166 ++- arch/powerpc/net/bpf_jit32.h | 24 +-- arch/powerpc/net/bpf_jit64.h | 12 +- arch/powerpc/net/bpf_jit_comp.c | 132 ++-- arch/powerpc/net/bpf_jit_comp64.c | 278 +- 6 files changed, 378 insertions(+), 373 deletions(-) diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index ca3f0351b878..94b889d89395 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -79,6 +79,16 @@ #define IMM_L(i) ((uintptr_t)(i) & 0x) #define IMM_DS(i) ((uintptr_t)(i) & 0xfffc) +/* + * 16-bit immediate helper macros: HA() is for use with sign-extending instrs + * (e.g. LD, ADDI). If the bottom 16 bits is "-ve", add another bit into the + * top half to negate the effect (i.e. 0x + 1 = 0x(1)). + */ +#define IMM_H(i)((uintptr_t)(i)>>16) +#define IMM_HA(i) (((uintptr_t)(i)>>16) + \ + (((uintptr_t)(i) & 0x8000) >> 15)) + + /* opcode and xopcode for instructions */ #define OP_TRAP 3 #define OP_TRAP_64 2 @@ -640,6 +650,135 @@ #define PPC_RAW_ADDC_DOT(t, a, b) (PPC_INST_ADDC | ___PPC_RT(t) | \ ___PPC_RA(a) | ___PPC_RB(b) | \ 0x1) +#define PPC_RAW_NOP() (PPC_INST_NOP) +#define PPC_RAW_BLR() (PPC_INST_BLR) +#define PPC_RAW_BLRL() (PPC_INST_BLRL) +#define PPC_RAW_MTLR(r)(PPC_INST_MTLR | ___PPC_RT(r)) +#define PPC_RAW_BCTR() (PPC_INST_BCTR) +#define PPC_RAW_MTCTR(r) (PPC_INST_MTCTR | ___PPC_RT(r)) +#define PPC_RAW_ADDI(d, a, i) (PPC_INST_ADDI | ___PPC_RT(d) | \ + ___PPC_RA(a) | IMM_L(i)) +#define PPC_RAW_LI(r, i) PPC_RAW_ADDI(r, 0, i) +#define PPC_RAW_ADDIS(d, a, i) (PPC_INST_ADDIS | \ + ___PPC_RT(d) | ___PPC_RA(a) | \ + IMM_L(i)) +#define PPC_RAW_LIS(r, i) PPC_RAW_ADDIS(r, 0, i) +#define PPC_RAW_STDX(r, base, b) (PPC_INST_STDX | ___PPC_RS(r) | \ + ___PPC_RA(base) | ___PPC_RB(b)) +#define PPC_RAW_STDU(r, base, i) (PPC_INST_STDU | ___PPC_RS(r) | \ + ___PPC_RA(base) | \ + ((i) & 0xfffc)) +#define PPC_RAW_STW(r, base, i)(PPC_INST_STW | ___PPC_RS(r) | \ + ___PPC_RA(base) | IMM_L(i)) +#define PPC_RAW_STWU(r, base, i) (PPC_INST_STWU | ___PPC_RS(r) | \ + ___PPC_RA(base) | IMM_L(i)) +#define PPC_RAW_STH(r, base, i)(PPC_INST_STH | ___PPC_RS(r) | \ + ___PPC_RA(base) | IMM_L(i)) +#define PPC_RAW_STB(r, base, i)(PPC_INST_STB | ___PPC_RS(r) | \ + ___PPC_RA(base) | IMM_L(i)) +#define PPC_RAW_LBZ(r, base, i)(PPC_INST_LBZ | ___PPC_RT(r) | \ + ___PPC_RA(base) | IMM_L(i)) +#define PPC_RAW_LDX(r, base, b)(PPC_INST_LDX | ___PPC_RT(r) | \ + ___PPC_RA(base) | ___PPC_RB(b)) +#define PPC_RAW_LHZ(r, base, i)(PPC_INST_LHZ | ___PPC_RT(r) | \ + ___PPC_RA(base) | IMM_L(i)) +#define PPC_RAW_LHBRX(r, base, b) (PPC_INST_LHBRX | ___PPC_RT(r) | \ + ___PPC_RA(base) | ___PPC_RB(b)) +#define PPC_RAW_LDBRX(r, base, b) (PPC_INST_LDBRX | ___PPC_RT(r) | \ + ___PPC_RA(base) | ___PPC_RB(b)) +#define PPC_RAW_STWCX(s, a, b) (PPC_INST_STWCX | ___PPC_RS(s) | \ + ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_RAW_CMPWI(a, i)(PPC_INST_CMPWI | ___PPC_RA(a) | IMM_L(i)) +#define PPC_RAW_CMPDI(a, i)(PPC_INST_CMPDI | ___PPC_RA(a) | IMM_L(i)) +#define PPC_RAW_CMPW(a, b) (PPC_INST_CMPW | ___PPC_RA(a) | \ + ___PPC_RB(b)) +#define PPC_RAW_CMPD(a, b) (PPC_INST_CMPD | ___PPC_RA(a) | \ +
[PATCH 3/6] powerpc/bpf_jit: reuse instruction macros from ppc-opcode.h
remove duplicate macro definitions from bpf_jit.h and reuse the macros from
ppc-opcode.h
Signed-off-by: Balamuruhan S
Acked-by: Naveen N. Rao
Tested-by: Naveen N. Rao
---
arch/powerpc/net/bpf_jit.h| 18 +-
arch/powerpc/net/bpf_jit32.h | 10 +-
arch/powerpc/net/bpf_jit64.h | 4 ++--
arch/powerpc/net/bpf_jit_comp.c | 2 +-
arch/powerpc/net/bpf_jit_comp64.c | 20 ++--
5 files changed, 19 insertions(+), 35 deletions(-)
diff --git a/arch/powerpc/net/bpf_jit.h b/arch/powerpc/net/bpf_jit.h
index 55d4377ccfae..535d1de4dfee 100644
--- a/arch/powerpc/net/bpf_jit.h
+++ b/arch/powerpc/net/bpf_jit.h
@@ -11,6 +11,7 @@
#ifndef __ASSEMBLY__
#include
+#include
#ifdef PPC64_ELF_ABI_v1
#define FUNCTION_DESCR_SIZE24
@@ -26,7 +27,6 @@
#define IMM_H(i) ((uintptr_t)(i)>>16)
#define IMM_HA(i) (((uintptr_t)(i)>>16) + \
(((uintptr_t)(i) & 0x8000) >> 15))
-#define IMM_L(i) ((uintptr_t)(i) & 0x)
#define PLANT_INSTR(d, idx, instr) \
do { if (d) { (d)[idx] = instr; } idx++; } while (0)
@@ -45,8 +45,6 @@
#define PPC_ADDIS(d, a, i) EMIT(PPC_INST_ADDIS | \
___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i))
#define PPC_LIS(r, i) PPC_ADDIS(r, 0, i)
-#define PPC_STD(r, base, i)EMIT(PPC_INST_STD | ___PPC_RS(r) |\
-___PPC_RA(base) | ((i) & 0xfffc))
#define PPC_STDX(r, base, b) EMIT(PPC_INST_STDX | ___PPC_RS(r) | \
___PPC_RA(base) | ___PPC_RB(b))
#define PPC_STDU(r, base, i) EMIT(PPC_INST_STDU | ___PPC_RS(r) | \
@@ -62,12 +60,8 @@
#define PPC_LBZ(r, base, i)EMIT(PPC_INST_LBZ | ___PPC_RT(r) |\
___PPC_RA(base) | IMM_L(i))
-#define PPC_LD(r, base, i) EMIT(PPC_INST_LD | ___PPC_RT(r) | \
-___PPC_RA(base) | ((i) & 0xfffc))
#define PPC_LDX(r, base, b)EMIT(PPC_INST_LDX | ___PPC_RT(r) |\
___PPC_RA(base) | ___PPC_RB(b))
-#define PPC_LWZ(r, base, i)EMIT(PPC_INST_LWZ | ___PPC_RT(r) |\
-___PPC_RA(base) | IMM_L(i))
#define PPC_LHZ(r, base, i)EMIT(PPC_INST_LHZ | ___PPC_RT(r) |\
___PPC_RA(base) | IMM_L(i))
#define PPC_LHBRX(r, base, b) EMIT(PPC_INST_LHBRX | ___PPC_RT(r) | \
@@ -75,16 +69,8 @@
#define PPC_LDBRX(r, base, b) EMIT(PPC_INST_LDBRX | ___PPC_RT(r) | \
___PPC_RA(base) | ___PPC_RB(b))
-#define PPC_BPF_LDARX(t, a, b, eh) EMIT(PPC_INST_LDARX | ___PPC_RT(t) |
\
- ___PPC_RA(a) | ___PPC_RB(b) | \
- __PPC_EH(eh))
-#define PPC_BPF_LWARX(t, a, b, eh) EMIT(PPC_INST_LWARX | ___PPC_RT(t) |
\
- ___PPC_RA(a) | ___PPC_RB(b) | \
- __PPC_EH(eh))
#define PPC_BPF_STWCX(s, a, b) EMIT(PPC_INST_STWCX | ___PPC_RS(s) | \
___PPC_RA(a) | ___PPC_RB(b))
-#define PPC_BPF_STDCX(s, a, b) EMIT(PPC_INST_STDCX | ___PPC_RS(s) | \
- ___PPC_RA(a) | ___PPC_RB(b))
#define PPC_CMPWI(a, i)EMIT(PPC_INST_CMPWI | ___PPC_RA(a) |
IMM_L(i))
#define PPC_CMPDI(a, i)EMIT(PPC_INST_CMPDI | ___PPC_RA(a) |
IMM_L(i))
#define PPC_CMPW(a, b) EMIT(PPC_INST_CMPW | ___PPC_RA(a) | \
@@ -100,8 +86,6 @@
#define PPC_SUB(d, a, b) EMIT(PPC_INST_SUB | ___PPC_RT(d) |\
___PPC_RB(a) | ___PPC_RA(b))
-#define PPC_ADD(d, a, b) EMIT(PPC_INST_ADD | ___PPC_RT(d) |\
-___PPC_RA(a) | ___PPC_RB(b))
#define PPC_MULD(d, a, b) EMIT(PPC_INST_MULLD | ___PPC_RT(d) | \
___PPC_RA(a) | ___PPC_RB(b))
#define PPC_MULW(d, a, b) EMIT(PPC_INST_MULLW | ___PPC_RT(d) | \
diff --git a/arch/powerpc/net/bpf_jit32.h b/arch/powerpc/net/bpf_jit32.h
index 4ec2a9f14f84..753c244a7cf9 100644
--- a/arch/powerpc/net/bpf_jit32.h
+++ b/arch/powerpc/net/bpf_jit32.h
@@ -76,13 +76,13 @@ DECLARE_LOAD_FUNC(sk_load_byte_msh);
else { PPC_ADDIS(r, base, IMM_HA(i));\
PPC_LBZ(r, r, IMM_L(i)); } } while(0)
-#define PPC_LD_OFFS(r, base, i) do { if ((i) < 32768) PPC_LD(r, base, i); \
+#define PPC_LD_OFFS(r, base, i) do { if ((i) < 32768) EMIT(PPC_RAW_LD(r, base,
i)); \
[PATCH 2/6] powerpc/ppc-opcode: move ppc instruction encoding from test_emulate_step
Few ppc instructions are encoded in test_emulate_step.c, consolidate them and use it from ppc-opcode.h Signed-off-by: Balamuruhan S Acked-by: Naveen N. Rao Tested-by: Naveen N. Rao --- arch/powerpc/include/asm/ppc-opcode.h | 35 ++ arch/powerpc/lib/test_emulate_step.c | 155 ++ 2 files changed, 91 insertions(+), 99 deletions(-) diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index e3540be1fc17..ca3f0351b878 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -76,6 +76,9 @@ #define__REGA0_R30 30 #define__REGA0_R31 31 +#define IMM_L(i) ((uintptr_t)(i) & 0x) +#define IMM_DS(i) ((uintptr_t)(i) & 0xfffc) + /* opcode and xopcode for instructions */ #define OP_TRAP 3 #define OP_TRAP_64 2 @@ -605,6 +608,38 @@ ___PPC_RT(vrt) | \ ___PPC_RA(vra) | \ ___PPC_RB(vrb) | __PPC_RC21) +#define PPC_RAW_LD(r, base, i) (PPC_INST_LD | ___PPC_RT(r) | \ + ___PPC_RA(base) | IMM_DS(i)) +#define PPC_RAW_LWZ(r, base, i)(PPC_INST_LWZ | ___PPC_RT(r) | \ + ___PPC_RA(base) | IMM_L(i)) +#define PPC_RAW_LWZX(t, a, b) (PPC_INST_LWZX | ___PPC_RT(t) | \ + ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_RAW_STD(r, base, i)(PPC_INST_STD | ___PPC_RS(r) | \ + ___PPC_RA(base) | IMM_DS(i)) +#define PPC_RAW_STDCX(s, a, b) (PPC_INST_STDCX | ___PPC_RS(s) | \ + ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_RAW_LFSX(t, a, b) (PPC_INST_LFSX | ___PPC_RT(t) | \ + ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_RAW_STFSX(s, a, b) (PPC_INST_STFSX | ___PPC_RS(s) | \ + ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_RAW_LFDX(t, a, b) (PPC_INST_LFDX | ___PPC_RT(t) | \ + ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_RAW_STFDX(s, a, b) (PPC_INST_STFDX | ___PPC_RS(s) | \ + ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_RAW_LVX(t, a, b) (PPC_INST_LVX | ___PPC_RT(t) | \ + ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_RAW_STVX(s, a, b) (PPC_INST_STVX | ___PPC_RS(s) | \ + ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_RAW_ADD(t, a, b) (PPC_INST_ADD | ___PPC_RT(t) | \ + ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_RAW_ADD_DOT(t, a, b) (PPC_INST_ADD | ___PPC_RT(t) | \ + ___PPC_RA(a) | ___PPC_RB(b) | \ + 0x1) +#define PPC_RAW_ADDC(t, a, b) (PPC_INST_ADDC | ___PPC_RT(t) | \ + ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_RAW_ADDC_DOT(t, a, b) (PPC_INST_ADDC | ___PPC_RT(t) | \ + ___PPC_RA(a) | ___PPC_RB(b) | \ + 0x1) /* Deal with instructions that older assemblers aren't aware of */ #definePPC_CP_ABORTstringify_in_c(.long PPC_INST_CP_ABORT) diff --git a/arch/powerpc/lib/test_emulate_step.c b/arch/powerpc/lib/test_emulate_step.c index 46af80279ebc..e508290eb15d 100644 --- a/arch/powerpc/lib/test_emulate_step.c +++ b/arch/powerpc/lib/test_emulate_step.c @@ -13,49 +13,6 @@ #include #include -#define IMM_L(i) ((uintptr_t)(i) & 0x) -#define IMM_DS(i) ((uintptr_t)(i) & 0xfffc) - -/* - * Defined with TEST_ prefix so it does not conflict with other - * definitions. - */ -#define TEST_LD(r, base, i)ppc_inst(PPC_INST_LD | ___PPC_RT(r) | \ - ___PPC_RA(base) | IMM_DS(i)) -#define TEST_LWZ(r, base, i) ppc_inst(PPC_INST_LWZ | ___PPC_RT(r) | \ - ___PPC_RA(base) | IMM_L(i)) -#define TEST_LWZX(t, a, b) ppc_inst(PPC_INST_LWZX | ___PPC_RT(t) | \ - ___PPC_RA(a) | ___PPC_RB(b)) -#define TEST_STD(r, base, i) ppc_inst(PPC_INST_STD | ___PPC_RS(r) | \ - ___PPC_RA(base) | IMM_DS(i)) -#define TEST_LDARX(t, a, b, eh)ppc_inst(PPC_INST_LDARX | ___PPC_RT(t) |\ - ___PPC_RA(a) | ___PPC_RB(b) | \ - __PPC_EH(eh)) -#define TEST_STDCX(s, a, b)ppc_ins
[PATCH 1/6] powerpc/ppc-opcode: introduce PPC_RAW_* macros for base instruction encoding
Introduce PPC_RAW_* macros to have all the bare encoding of ppc instructions. Move `VSX_XX*()` and `TMRN()` macros up to reuse it. Signed-off-by: Balamuruhan S Acked-by: Naveen N. Rao Tested-by: Naveen N. Rao --- arch/powerpc/include/asm/ppc-opcode.h | 183 -- 1 file changed, 175 insertions(+), 8 deletions(-) diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index 2a39c716c343..e3540be1fc17 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -431,6 +431,181 @@ #define __PPC_EH(eh) 0 #endif +/* Base instruction encoding */ +#define PPC_RAW_CP_ABORT (PPC_INST_CP_ABORT) +#define PPC_RAW_COPY(a, b) (PPC_INST_COPY | ___PPC_RA(a) | \ + ___PPC_RB(b)) +#define PPC_RAW_DARN(t, l) (PPC_INST_DARN | ___PPC_RT(t) | \ + (((l) & 0x3) << 16)) +#define PPC_RAW_DCBAL(a, b)(PPC_INST_DCBAL | __PPC_RA(a) | \ + __PPC_RB(b)) +#define PPC_RAW_DCBZL(a, b)(PPC_INST_DCBZL | __PPC_RA(a) | \ + __PPC_RB(b)) +#define PPC_RAW_LQARX(t, a, b, eh) (PPC_INST_LQARX | ___PPC_RT(t) | \ + ___PPC_RA(a) | \ + ___PPC_RB(b) | __PPC_EH(eh)) +#define PPC_RAW_LDARX(t, a, b, eh) (PPC_INST_LDARX | ___PPC_RT(t) | \ + ___PPC_RA(a) | \ + ___PPC_RB(b) | __PPC_EH(eh)) +#define PPC_RAW_LWARX(t, a, b, eh) (PPC_INST_LWARX | \ + ___PPC_RT(t) | ___PPC_RA(a) | \ + ___PPC_RB(b) | __PPC_EH(eh)) +#define PPC_RAW_STQCX(t, a, b) (PPC_INST_STQCX | \ + ___PPC_RT(t) | ___PPC_RA(a) | \ + ___PPC_RB(b)) +#define PPC_RAW_MADDHD(t, a, b, c) (PPC_INST_MADDHD | \ + ___PPC_RT(t) | ___PPC_RA(a) | \ + ___PPC_RB(b) | ___PPC_RC(c)) +#define PPC_RAW_MADDHDU(t, a, b, c)(PPC_INST_MADDHDU | \ + ___PPC_RT(t) | ___PPC_RA(a) | \ + ___PPC_RB(b) | ___PPC_RC(c)) +#define PPC_RAW_MADDLD(t, a, b, c) (PPC_INST_MADDLD | \ + ___PPC_RT(t) | ___PPC_RA(a) | \ + ___PPC_RB(b) | ___PPC_RC(c)) +#define PPC_RAW_MSGSND(b) (PPC_INST_MSGSND | ___PPC_RB(b)) +#define PPC_RAW_MSGSYNC(PPC_INST_MSGSYNC) +#define PPC_RAW_MSGCLR(b) (PPC_INST_MSGCLR | ___PPC_RB(b)) +#define PPC_RAW_MSGSNDP(b) (PPC_INST_MSGSNDP | ___PPC_RB(b)) +#define PPC_RAW_MSGCLRP(b) (PPC_INST_MSGCLRP | ___PPC_RB(b)) +#define PPC_RAW_PASTE(a, b)(PPC_INST_PASTE | ___PPC_RA(a) | \ + ___PPC_RB(b)) +#define PPC_RAW_POPCNTB(a, s) (PPC_INST_POPCNTB | __PPC_RA(a) | \ + __PPC_RS(s)) +#define PPC_RAW_POPCNTD(a, s) (PPC_INST_POPCNTD | __PPC_RA(a) | \ + __PPC_RS(s)) +#define PPC_RAW_POPCNTW(a, s) (PPC_INST_POPCNTW | __PPC_RA(a) | \ + __PPC_RS(s)) +#define PPC_RAW_RFCI (PPC_INST_RFCI) +#define PPC_RAW_RFDI (PPC_INST_RFDI) +#define PPC_RAW_RFMCI (PPC_INST_RFMCI) +#define PPC_RAW_TLBILX(t, a, b)(PPC_INST_TLBILX | \ + __PPC_T_TLB(t) | \ + __PPC_RA0(a) | \ + __PPC_RB(b)) +#define PPC_RAW_WAIT(w)(PPC_INST_WAIT | __PPC_WC(w)) +#define PPC_RAW_TLBIE(lp, a) (PPC_INST_TLBIE | ___PPC_RB(a) | \ + ___PPC_RS(lp)) +#define PPC_RAW_TLBIE_5(rb, rs, ric, prs, r) \ + (PPC_INST_TLBIE | \ + ___PPC_RB(rb) | \ + ___PPC_RS(rs) | \ + ___PPC_RIC(ric) | \ + ___PPC_PRS(prs) | \ + ___PPC_R(r)) +#define PPC_RAW_TLBIEL(rb, rs, ric, prs, r) \ + (PPC_INST_TLBIEL | \ + ___PPC_RB(rb) | \ + __
[PATCH 0/6] consolidate PowerPC instruction encoding macros
ppc-opcode.h have base instruction encoding wrapped with stringify_in_c() for raw encoding to have compatibility. But there are redundant macros for base instruction encodings in bpf, instruction emulation test infrastructure and powerpc selftests. Currently PPC_INST_* macros are used for encoding instruction opcode and PPC_* for raw instuction encoding, this rfc patchset introduces PPC_RAW_* macros for base instruction encoding and reuse it from elsewhere. With this change we can avoid redundant macro definitions in multiple files and start adding new instructions in ppc-opcode.h in future. Changes in v1: - * Drop the patch that had changes in stringloops Makefile. * Include Acked-by and Tested-by tag from Naveen. * Rebased on next branch of linuxppc tree. Changes in rfc v2: - Fix review comments/suggestions from Naveen and Michael Ellerman, * Rename PPC_ENCODE_* to PPC_RAW_* for base instruction encoding macros. * Split the patches that does mass renaming and make them simpler that just adds new macros. * Keep the patch to update all the existing names later (patch 6). * Lot of PPC_INST_* macros are used only in ppc-opcode.h for PPC_* macros, fold PPC_INST_* encoding into PPC_RAW_* to avoid using them accidentally. * Fixed clipped macros that was due to a typo/copy-paste * Consolidated all the instruction encoding macros from bpf_jit.h to ppc-opcode.h * squashed patch that removes the duplicate macro PPC_MR() in bpf_jit.h * merge few changes in bpf_jit files from patch 2 into patch 3 * few fixes in powerpc selftest stringloops Makefile * build tested for ppc64le_defconfig, ppc64e_defconfig and pmac32_defconfig * Rebased on next branch of linuxppc tree Testing: --- * Tested it by compiling vmlinux and comparing objdump of it with and without the patchset and observed that it remains same, # diff vmlinux_objdump vmlinux_rfc_objdump 2c2 < vmlinux: file format elf64-powerpcle --- > vmlinux_rfc: file format elf64-powerpcle * Tested building it with this changes for Fedora30 config, booted VM with powerpc next and powerpc next + patchset to run powerpc selftest and ftrace selftest. There were couple of failures that were common and patchset did not introduce any new failures. ftrace selftest: --- # # of passed: 96 # # of failed: 1 # # of unresolved: 7 # # of untested: 0 # # of unsupported: 1 # # of xfailed: 1 # # of undefined(test bug): 0 not ok 1 selftests: ftrace: ftracetest # exit=1 powerpc selftest: not ok 7 selftests: powerpc/dscr: dscr_sysfs_thread_test # exit=1 not ok 20 selftests: powerpc/pmu/ebb: lost_exception_test # TIMEOUT not ok 2 selftests: powerpc/security: spectre_v2 # exit=1 Thanks to Naveen, Sandipan and Michael on overall suggestions/improvements. I would request for review and suggestions to make it better. rfc v2: https://lists.ozlabs.org/pipermail/linuxppc-dev/2020-April/209395.html rfc v1: https://lists.ozlabs.org/pipermail/linuxppc-dev/2020-March/206494.html Balamuruhan S (6): powerpc/ppc-opcode: introduce PPC_RAW_* macros for base instruction encoding powerpc/ppc-opcode: move ppc instruction encoding from test_emulate_step powerpc/bpf_jit: reuse instruction macros from ppc-opcode.h powerpc/ppc-opcode: consolidate powerpc instructions from bpf_jit.h powerpc/ppc-opcode: reuse raw instruction macros to stringify powerpc/ppc-opcode: fold PPC_INST_* macros into PPC_RAW_* macros arch/powerpc/include/asm/ppc-opcode.h | 706 +++--- arch/powerpc/lib/test_emulate_step.c | 155 ++ arch/powerpc/net/bpf_jit.h| 184 +-- arch/powerpc/net/bpf_jit32.h | 34 +- arch/powerpc/net/bpf_jit64.h | 16 +- arch/powerpc/net/bpf_jit_comp.c | 134 ++--- arch/powerpc/net/bpf_jit_comp64.c | 298 +-- 7 files changed, 733 insertions(+), 794 deletions(-) base-commit: 30df74d67d48949da87e3a5b57c381763e8fd526 -- 2.24.1
Re: [RFC PATCH v2 7/7] powerpc/selftest: reuse ppc-opcode macros to avoid redundancy
On Thu, 2020-04-30 at 17:27 +0530, Naveen N. Rao wrote: > Michael Ellerman wrote: > > "Naveen N. Rao" writes: > > > Michael Ellerman wrote: > > > > Balamuruhan S writes: > > > > > Avoid redefining macros to encode ppc instructions instead reuse it > > > > > from > > > > > ppc-opcode.h, Makefile changes are necessary to compile memcmp_64.S > > > > > with > > > > > __ASSEMBLY__ defined from selftests. > > > > > > > > > > Signed-off-by: Balamuruhan S > > > > > --- > > > > > .../selftests/powerpc/stringloops/Makefile| 34 ++--- > > > > > - > > > > > .../powerpc/stringloops/asm/asm-const.h | 1 + > > > > > .../powerpc/stringloops/asm/ppc-opcode.h | 36 +-- > > > > > > > > > > 3 files changed, 29 insertions(+), 42 deletions(-) > > > > > create mode 12 > > > > > tools/testing/selftests/powerpc/stringloops/asm/asm-const.h > > > > > mode change 100644 => 12 > > > > > tools/testing/selftests/powerpc/stringloops/asm/ppc-opcode.h > > > > > > > > > > diff --git a/tools/testing/selftests/powerpc/stringloops/Makefile > > > > > b/tools/testing/selftests/powerpc/stringloops/Makefile > > > > > index 7fc0623d85c3..efe76c5a5b94 100644 > > > > > --- a/tools/testing/selftests/powerpc/stringloops/Makefile > > > > > +++ b/tools/testing/selftests/powerpc/stringloops/Makefile > > > > > @@ -1,26 +1,44 @@ > > > > > # SPDX-License-Identifier: GPL-2.0 > > > > > # The loops are all 64-bit code > > > > > -CFLAGS += -I$(CURDIR) > > > > > +GIT_VERSION = $(shell git describe --always --long --dirty || echo > > > > > "unknown") > > > > > +CFLAGS += -DGIT_VERSION='"$(GIT_VERSION)"' -I$(CURDIR) > > > > > -I$(CURDIR)/../include > > > > > > > > > > EXTRA_SOURCES := ../harness.c > > > > > > > > > > build_32bit = $(shell if ($(CC) $(CFLAGS) -m32 -o /dev/null memcmp.c > > > > > >/dev/null 2>&1) then echo "1"; fi) > > > > > > > > > > +ifneq ($(build_32bit),1) > > > > > TEST_GEN_PROGS := memcmp_64 strlen > > > > > +TEST_GEN_FILES := memcmp.o memcmp_64.o memcmp_64 > > > > > +MEMCMP := $(OUTPUT)/memcmp.o > > > > > +MEMCMP_64 := $(OUTPUT)/memcmp_64.o > > > > > +HARNESS := $(OUTPUT)/../harness.o > > > > > +CFLAGS += -m64 -maltivec > > > > > > > > > > -$(OUTPUT)/memcmp_64: memcmp.c > > > > > -$(OUTPUT)/memcmp_64: CFLAGS += -m64 -maltivec > > > > > +OVERRIDE_TARGETS := 1 > > > > > +include ../../lib.mk > > > > > > > > > > -ifeq ($(build_32bit),1) > > > > > +$(OUTPUT)/memcmp_64: $(MEMCMP_64) $(MEMCMP) $(HARNESS) > > > > > + $(CC) $(CFLAGS) memcmp.o memcmp_64.o ../harness.o -o memcmp_64 > > > > > + > > > > > +$(MEMCMP_64): memcmp_64.S > > > > > + $(CC) $(CFLAGS) -D__ASSEMBLY__ -o memcmp_64.o -c memcmp_64.S > > > > > + > > > > > +$(MEMCMP): memcmp.c > > > > > + $(CC) $(CFLAGS) -o memcmp.o -c memcmp.c > > > > > + > > > > > +$(HARNESS): $(EXTRA_SOURCES) > > > > > + $(CC) $(CFLAGS) -DGIT_VERSION='"$(GIT_VERSION)"' -o > > > > > ../harness.o -c $(EXTRA_SOURCES) > > > > > > > > What are you actually trying to do here? Is it just that you need to > > > > define __ASSEMBLY__ for memcmp_64.S? > > > > > > Adding __ASSEMBLY__ while building memcmp_64.S would be the goal, so as > > > to reuse ppc-opcode.h. However, asm/ppc-opcode.h under stringloops test > > > is tiny and doesn't seem to justify the change. Okay, I will drop the last patch that have changes for stringloops Makefile. make and make clean is not working from inside stringloops directory which is fixed with this change. > > > > I don't see ppc-opcode.h testing __ASSEMBLY__ though, so I don't think > > we even need to define it? > > Right -- it's rather 'stringify_in_c' which tests it. 'asm/ppc-opcode.h' > under stringloops/ unconditionally defines 'stringify_in_c' this way: > # define stringify_in_c(...) __VA_ARGS__ > It is expecting __ASSEMBLY__ through ppc-opcode.h -> asm-const.h to raw encode the instruction in assembly file instead to stringify it for c file. we observe this Assembler messages without defining __ASSEMBLY__, memcmp_64.S: Assembler messages: memcmp_64.S:473: Error: unknown pseudo-op: `.long (0x10c7 | (((0) & 0x1f) << 21) | (((0) & 0x1f) << 16) | (((1) & 0x1f) << 11) | (0x1 << 10))' memcmp_64.S:477: Error: unknown pseudo-op: `.long (0x10c7 | (((0) & 0x1f) << 21) | (((0) & 0x1f) << 16) | (((1) & 0x1f) << 11) | (0x1 << 10))' memcmp_64.S:586: Error: unknown pseudo-op: `.long (0x1006 | (((7) & 0x1f) << 21) | (((9) & 0x1f) << 16) | (((10) & 0x1f) << 11) | (0x1 << 10))' memcmp_64.S:607: Error: unknown pseudo-op: `.long (0x1006 | (((7) & 0x1f) << 21) | (((9) & 0x1f) << 16) | (((10) & 0x1f) << 11) | (0x1 << 10))' memcmp_64.S:616: Error: unknown pseudo-op: `.long (0x1006 | (((7) & 0x1f) << 21) | (((9) & 0x1f) << 16) | (((10) & 0x1f) << 11) | (0x1 << 10))' make[1]: *** [../../lib.mk:148: /home/bala/linux/tools/testing/selftests/powerpc/stringloops/memcmp_64] Error 1 -- Bala > > - Naveen >
Re: [PATCH v6 00/28] Initial Prefixed Instruction support
On Tue, 2020-04-28 at 11:57 +1000, Jordan Niethe wrote:
> A future revision of the ISA will introduce prefixed instructions. A
> prefixed instruction is composed of a 4-byte prefix followed by a
> 4-byte suffix.
>
> All prefixes have the major opcode 1. A prefix will never be a valid
> word instruction. A suffix may be an existing word instruction or a
> new instruction.
>
> This series enables prefixed instructions and extends the instruction
> emulation to support them. Then the places where prefixed instructions
> might need to be emulated are updated.
Hi Jordan,
I tried to test Kprobes with prefixed instruction on this patchset and
observed that kprobe/uprobe enablement patches are missing from v4.
Till v3 it were available,
https://patchwork.ozlabs.org/project/linuxppc-dev/patch/20200211053355.21574-11-jniet...@gmail.com/
https://patchwork.ozlabs.org/project/linuxppc-dev/patch/20200211053355.21574-12-jniet...@gmail.com/
was it missed for any dependencies/reason ? or will you plan it include in next
version ?
please let me know if you need help on it.
-- Bala
>
> v6 is based on feedback from Balamuruhan Suriyakumar, Alistair Popple,
> Christophe Leroy and Segher Boessenkool.
> The major changes:
> - Use the instruction type in more places that had been missed before
> - Fix issues with ppc32
> - Introduce new self tests for code patching and feature fixups
>
> v5 is based on feedback from Nick Piggins, Michael Ellerman, Balamuruhan
> Suriyakumar and Alistair Popple.
> The major changes:
> - The ppc instruction type is now a struct
> - Series now just based on next
> - ppc_inst_masked() dropped
> - Space for xmon breakpoints allocated in an assembly file
> - "Add prefixed instructions to instruction data type" patch seperated in
> to smaller patches
> - Calling convention for create_branch() is changed
> - Some places which had not been updated to use the data type are now
> updated
>
> v4 is based on feedback from Nick Piggins, Christophe Leroy and Daniel
> Axtens.
> The major changes:
> - Move xmon breakpoints from data section to text section
> - Introduce a data type for instructions on powerpc
>
> v3 is based on feedback from Christophe Leroy. The major changes:
> - Completely replacing store_inst() with patch_instruction() in
> xmon
> - Improve implementation of mread_instr() to not use mread().
> - Base the series on top of
> https://patchwork.ozlabs.org/patch/1232619/ as this will effect
> kprobes.
> - Some renaming and simplification of conditionals.
>
> v2 incorporates feedback from Daniel Axtens and and Balamuruhan
> S. The major changes are:
> - Squashing together all commits about SRR1 bits
> - Squashing all commits for supporting prefixed load stores
> - Changing abbreviated references to sufx/prfx -> suffix/prefix
> - Introducing macros for returning the length of an instruction
> - Removing sign extension flag from pstd/pld in sstep.c
> - Dropping patch "powerpc/fault: Use analyse_instr() to check for
> store with updates to sp" from the series, it did not really fit
> with prefixed enablement in the first place and as reported by Greg
> Kurz did not work correctly.
>
> Alistair Popple (1):
> powerpc: Enable Prefixed Instructions
>
> Jordan Niethe (27):
> powerpc/xmon: Remove store_inst() for patch_instruction()
> powerpc/xmon: Move breakpoint instructions to own array
> powerpc/xmon: Move breakpoints to text section
> powerpc/xmon: Use bitwise calculations in_breakpoint_table()
> powerpc: Change calling convention for create_branch() et. al.
> powerpc: Use a macro for creating instructions from u32s
> powerpc: Use an accessor for instructions
> powerpc: Use a function for getting the instruction op code
> powerpc: Use a function for byte swapping instructions
> powerpc: Introduce functions for instruction equality
> powerpc: Use a datatype for instructions
> powerpc: Use a function for reading instructions
> powerpc: Add a probe_user_read_inst() function
> powerpc: Add a probe_kernel_read_inst() function
> powerpc/kprobes: Use patch_instruction()
> powerpc: Define and use __get_user_instr{,inatomic}()
> powerpc: Introduce a function for reporting instruction length
> powerpc/xmon: Use a function for reading instructions
> powerpc/xmon: Move insertion of breakpoint for xol'ing
> powerpc: Make test_translate_branch() independent of instruction
> length
> powerpc: Define new SRR1 bits for a future ISA version
> powerpc: Add prefixed instructions to instruction data type
> powerpc: Test prefixed code patch
[RFC PATCH v2 7/7] powerpc/selftest: reuse ppc-opcode macros to avoid redundancy
Avoid redefining macros to encode ppc instructions instead reuse it from ppc-opcode.h, Makefile changes are necessary to compile memcmp_64.S with __ASSEMBLY__ defined from selftests. Signed-off-by: Balamuruhan S --- .../selftests/powerpc/stringloops/Makefile| 34 ++ .../powerpc/stringloops/asm/asm-const.h | 1 + .../powerpc/stringloops/asm/ppc-opcode.h | 36 +-- 3 files changed, 29 insertions(+), 42 deletions(-) create mode 12 tools/testing/selftests/powerpc/stringloops/asm/asm-const.h mode change 100644 => 12 tools/testing/selftests/powerpc/stringloops/asm/ppc-opcode.h diff --git a/tools/testing/selftests/powerpc/stringloops/Makefile b/tools/testing/selftests/powerpc/stringloops/Makefile index 7fc0623d85c3..efe76c5a5b94 100644 --- a/tools/testing/selftests/powerpc/stringloops/Makefile +++ b/tools/testing/selftests/powerpc/stringloops/Makefile @@ -1,26 +1,44 @@ # SPDX-License-Identifier: GPL-2.0 # The loops are all 64-bit code -CFLAGS += -I$(CURDIR) +GIT_VERSION = $(shell git describe --always --long --dirty || echo "unknown") +CFLAGS += -DGIT_VERSION='"$(GIT_VERSION)"' -I$(CURDIR) -I$(CURDIR)/../include EXTRA_SOURCES := ../harness.c build_32bit = $(shell if ($(CC) $(CFLAGS) -m32 -o /dev/null memcmp.c >/dev/null 2>&1) then echo "1"; fi) +ifneq ($(build_32bit),1) TEST_GEN_PROGS := memcmp_64 strlen +TEST_GEN_FILES := memcmp.o memcmp_64.o memcmp_64 +MEMCMP := $(OUTPUT)/memcmp.o +MEMCMP_64 := $(OUTPUT)/memcmp_64.o +HARNESS := $(OUTPUT)/../harness.o +CFLAGS += -m64 -maltivec -$(OUTPUT)/memcmp_64: memcmp.c -$(OUTPUT)/memcmp_64: CFLAGS += -m64 -maltivec +OVERRIDE_TARGETS := 1 +include ../../lib.mk -ifeq ($(build_32bit),1) +$(OUTPUT)/memcmp_64: $(MEMCMP_64) $(MEMCMP) $(HARNESS) + $(CC) $(CFLAGS) memcmp.o memcmp_64.o ../harness.o -o memcmp_64 + +$(MEMCMP_64): memcmp_64.S + $(CC) $(CFLAGS) -D__ASSEMBLY__ -o memcmp_64.o -c memcmp_64.S + +$(MEMCMP): memcmp.c + $(CC) $(CFLAGS) -o memcmp.o -c memcmp.c + +$(HARNESS): $(EXTRA_SOURCES) + $(CC) $(CFLAGS) -DGIT_VERSION='"$(GIT_VERSION)"' -o ../harness.o -c $(EXTRA_SOURCES) +else $(OUTPUT)/memcmp_32: memcmp.c $(OUTPUT)/memcmp_32: CFLAGS += -m32 TEST_GEN_PROGS += memcmp_32 endif -$(OUTPUT)/strlen: strlen.c string.c - -ifeq ($(build_32bit),1) +ifneq ($(build_32bit),1) +$(OUTPUT)/strlen: string.c +else $(OUTPUT)/strlen_32: strlen.c $(OUTPUT)/strlen_32: CFLAGS += -m32 @@ -30,6 +48,8 @@ endif ASFLAGS = $(CFLAGS) top_srcdir = ../../../../.. +ifeq ($(build_32bit),1) include ../../lib.mk +endif $(TEST_GEN_PROGS): $(EXTRA_SOURCES) diff --git a/tools/testing/selftests/powerpc/stringloops/asm/asm-const.h b/tools/testing/selftests/powerpc/stringloops/asm/asm-const.h new file mode 12 index ..18d8be13e67f --- /dev/null +++ b/tools/testing/selftests/powerpc/stringloops/asm/asm-const.h @@ -0,0 +1 @@ +../../../../../../arch/powerpc/include/asm/asm-const.h \ No newline at end of file diff --git a/tools/testing/selftests/powerpc/stringloops/asm/ppc-opcode.h b/tools/testing/selftests/powerpc/stringloops/asm/ppc-opcode.h deleted file mode 100644 index 3edd1a1d9128.. --- a/tools/testing/selftests/powerpc/stringloops/asm/ppc-opcode.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright 2009 Freescale Semiconductor, Inc. - * - * provides masks and opcode images for use by code generation, emulation - * and for instructions that older assemblers might not know about - */ -#ifndef _ASM_POWERPC_PPC_OPCODE_H -#define _ASM_POWERPC_PPC_OPCODE_H - - -# define stringify_in_c(...) __VA_ARGS__ -# define ASM_CONST(x) x - - -#define PPC_INST_VCMPEQUD_RC 0x10c7 -#define PPC_INST_VCMPEQUB_RC 0x1006 - -#define __PPC_RC21 (0x1 << 10) - -/* macros to insert fields into opcodes */ -#define ___PPC_RA(a) (((a) & 0x1f) << 16) -#define ___PPC_RB(b) (((b) & 0x1f) << 11) -#define ___PPC_RS(s) (((s) & 0x1f) << 21) -#define ___PPC_RT(t) ___PPC_RS(t) - -#define VCMPEQUD_RC(vrt, vra, vrb) stringify_in_c(.long PPC_INST_VCMPEQUD_RC | \ - ___PPC_RT(vrt) | ___PPC_RA(vra) | \ - ___PPC_RB(vrb) | __PPC_RC21) - -#define VCMPEQUB_RC(vrt, vra, vrb) stringify_in_c(.long PPC_INST_VCMPEQUB_RC | \ - ___PPC_RT(vrt) | ___PPC_RA(vra) | \ - ___PPC_RB(vrb) | __PPC_RC21) - -#endif /* _ASM_POWERPC_PPC_OPCODE_H */ diff --git a/tools/testing/selftests/powerpc/stringloops/asm/ppc-opcode.h b/tools/testing/selftests/powerpc/stringloops/asm/ppc-opcode.h new file mode 12 index ..f9b1f27ac335 --- /dev/null +++ b/tools/testing/selftests/powerpc/stringloops/asm/ppc-opcode.h @@ -0,0 +1 @@ +../../../../../../arch/powerpc/include/asm/ppc-opcode.h \ No newline at end of file -- 2.24.1
[RFC PATCH v2 5/7] powerpc/ppc-opcode: reuse raw instruction macros to stringify
Wrap existing stringify macros to reuse raw instruction encoding macros that are newly added. Signed-off-by: Balamuruhan S --- arch/powerpc/include/asm/ppc-opcode.h | 220 +- 1 file changed, 71 insertions(+), 149 deletions(-) diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index 6b9a891884be..34584df0ebc4 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -778,166 +778,92 @@ ___PPC_RA(a)) /* Deal with instructions that older assemblers aren't aware of */ -#definePPC_CP_ABORTstringify_in_c(.long PPC_INST_CP_ABORT) -#definePPC_COPY(a, b) stringify_in_c(.long PPC_INST_COPY | \ - ___PPC_RA(a) | ___PPC_RB(b)) -#define PPC_DARN(t, l) stringify_in_c(.long PPC_INST_DARN | \ - ___PPC_RT(t) | \ - (((l) & 0x3) << 16)) -#definePPC_DCBAL(a, b) stringify_in_c(.long PPC_INST_DCBAL | \ - __PPC_RA(a) | __PPC_RB(b)) -#definePPC_DCBZL(a, b) stringify_in_c(.long PPC_INST_DCBZL | \ - __PPC_RA(a) | __PPC_RB(b)) -#define PPC_LQARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LQARX | \ - ___PPC_RT(t) | ___PPC_RA(a) | \ - ___PPC_RB(b) | __PPC_EH(eh)) -#define PPC_LDARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LDARX | \ - ___PPC_RT(t) | ___PPC_RA(a) | \ - ___PPC_RB(b) | __PPC_EH(eh)) -#define PPC_LWARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LWARX | \ - ___PPC_RT(t) | ___PPC_RA(a) | \ - ___PPC_RB(b) | __PPC_EH(eh)) -#define PPC_STQCX(t, a, b) stringify_in_c(.long PPC_INST_STQCX | \ - ___PPC_RT(t) | ___PPC_RA(a) | \ - ___PPC_RB(b)) -#define PPC_MADDHD(t, a, b, c) stringify_in_c(.long PPC_INST_MADDHD | \ - ___PPC_RT(t) | ___PPC_RA(a) | \ - ___PPC_RB(b) | ___PPC_RC(c)) -#define PPC_MADDHDU(t, a, b, c)stringify_in_c(.long PPC_INST_MADDHDU | \ - ___PPC_RT(t) | ___PPC_RA(a) | \ - ___PPC_RB(b) | ___PPC_RC(c)) -#define PPC_MADDLD(t, a, b, c) stringify_in_c(.long PPC_INST_MADDLD | \ - ___PPC_RT(t) | ___PPC_RA(a) | \ - ___PPC_RB(b) | ___PPC_RC(c)) -#define PPC_MSGSND(b) stringify_in_c(.long PPC_INST_MSGSND | \ - ___PPC_RB(b)) -#define PPC_MSGSYNCstringify_in_c(.long PPC_INST_MSGSYNC) -#define PPC_MSGCLR(b) stringify_in_c(.long PPC_INST_MSGCLR | \ - ___PPC_RB(b)) -#define PPC_MSGSNDP(b) stringify_in_c(.long PPC_INST_MSGSNDP | \ - ___PPC_RB(b)) -#define PPC_MSGCLRP(b) stringify_in_c(.long PPC_INST_MSGCLRP | \ - ___PPC_RB(b)) -#define PPC_PASTE(a, b)stringify_in_c(.long PPC_INST_PASTE | \ - ___PPC_RA(a) | ___PPC_RB(b)) -#define PPC_POPCNTB(a, s) stringify_in_c(.long PPC_INST_POPCNTB | \ - __PPC_RA(a) | __PPC_RS(s)) -#define PPC_POPCNTD(a, s) stringify_in_c(.long PPC_INST_POPCNTD | \ - __PPC_RA(a) | __PPC_RS(s)) -#define PPC_POPCNTW(a, s) stringify_in_c(.long PPC_INST_POPCNTW | \ - __PPC_RA(a) | __PPC_RS(s)) -#define PPC_RFCI stringify_in_c(.long PPC_INST_RFCI) -#define PPC_RFDI stringify_in_c(.long PPC_INST_RFDI) -#define PPC_RFMCI stringify_in_c(.long PPC_INST_RFMCI) -#define PPC_TLBILX(t, a, b)stringify_in_c(.long PPC_INST_TLBILX | \ - __PPC_T_TLB(t) | __PPC_RA0(a) | __PPC_RB(b)) +#definePPC_CP_ABORTstringify_in_c(.long PPC_RAW_CP_ABORT) +#definePPC_COPY(a, b) stringify_in_c(.long PPC_RAW_COPY(a, b)) +#define PPC_DARN(t, l) stringify_in_c(.long PPC_RAW_DARN(t, l)) +#definePPC_DCBAL(a, b) stringify_in_c(.long PPC_RAW_DCBAL(a, b)) +#definePPC_DCBZL(a, b) stringify_in_c(.long PPC_RAW_DCBZL(a, b)) +#define PPC_LQARX(t, a, b, eh) stringify_in_c(.long PPC_RAW_LQARX(t, a, b, eh)) +#define PPC_LDARX(t, a, b, eh) stringify_in_c(.long PPC_RAW_LDARX(t, a, b, eh)) +#define PPC_LWARX(t, a, b, eh) stringify_
[RFC PATCH v2 6/7] powerpc/ppc-opcode: fold PPC_INST_* macros into PPC_RAW_* macros
Lot of PPC_INST_* macros are used only ever in PPC_* macros, fold those PPC_INST_* into PPC_RAW_* to avoid using PPC_INST_* accidentally. Signed-off-by: Balamuruhan S --- arch/powerpc/include/asm/ppc-opcode.h | 381 +- 1 file changed, 125 insertions(+), 256 deletions(-) diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index 34584df0ebc4..1ffdd0e69e77 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -205,56 +205,27 @@ #define OP_LQ56 /* sorted alphabetically */ -#define PPC_INST_BHRBE 0x7c00025c -#define PPC_INST_CLRBHRB 0x7c00035c #define PPC_INST_COPY 0x7c20060c -#define PPC_INST_CP_ABORT 0x7c00068c -#define PPC_INST_DARN 0x7c0005e6 #define PPC_INST_DCBA 0x7c0005ec #define PPC_INST_DCBA_MASK 0xfc0007fe -#define PPC_INST_DCBAL 0x7c2005ec -#define PPC_INST_DCBZL 0x7c2007ec -#define PPC_INST_ICBT 0x7c2c -#define PPC_INST_ICSWX 0x7c00032d -#define PPC_INST_ICSWEPX 0x7c00076d #define PPC_INST_ISEL 0x7c1e #define PPC_INST_ISEL_MASK 0xfc3e -#define PPC_INST_LDARX 0x7ca8 -#define PPC_INST_STDCX 0x7c0001ad -#define PPC_INST_LQARX 0x7c000228 -#define PPC_INST_STQCX 0x7c00016d #define PPC_INST_LSWI 0x7c0004aa #define PPC_INST_LSWX 0x7c00042a -#define PPC_INST_LWARX 0x7c28 -#define PPC_INST_STWCX 0x7c00012d #define PPC_INST_LWSYNC0x7c2004ac #define PPC_INST_SYNC 0x7c0004ac #define PPC_INST_SYNC_MASK 0xfc0007fe #define PPC_INST_ISYNC 0x4c00012c -#define PPC_INST_LXVD2X0x7c000698 #define PPC_INST_MCRXR 0x7c000400 #define PPC_INST_MCRXR_MASK0xfc0007fe #define PPC_INST_MFSPR_PVR 0x7c1f42a6 #define PPC_INST_MFSPR_PVR_MASK0xfc1e -#define PPC_INST_MFTMR 0x7c0002dc -#define PPC_INST_MSGSND0x7c00019c -#define PPC_INST_MSGCLR0x7c0001dc -#define PPC_INST_MSGSYNC 0x7c0006ec -#define PPC_INST_MSGSNDP 0x7c00011c -#define PPC_INST_MSGCLRP 0x7c00015c #define PPC_INST_MTMSRD0x7c000164 -#define PPC_INST_MTTMR 0x7c0003dc #define PPC_INST_NOP 0x6000 -#define PPC_INST_PASTE 0x7c20070d #define PPC_INST_POPCNTB 0x7cf4 #define PPC_INST_POPCNTB_MASK 0xfc0007fe -#define PPC_INST_POPCNTD 0x7c0003f4 -#define PPC_INST_POPCNTW 0x7c0002f4 #define PPC_INST_RFEBB 0x4c000124 -#define PPC_INST_RFCI 0x4c66 -#define PPC_INST_RFDI 0x4c4e #define PPC_INST_RFID 0x4c24 -#define PPC_INST_RFMCI 0x4c4c #define PPC_INST_MFSPR 0x7c0002a6 #define PPC_INST_MFSPR_DSCR0x7c1102a6 #define PPC_INST_MFSPR_DSCR_MASK 0xfc1e @@ -264,131 +235,30 @@ #define PPC_INST_MFSPR_DSCR_USER_MASK 0xfc1e #define PPC_INST_MTSPR_DSCR_USER 0x7c0303a6 #define PPC_INST_MTSPR_DSCR_USER_MASK 0xfc1e -#define PPC_INST_MFVSRD0x7c66 -#define PPC_INST_MTVSRD0x7c000166 #define PPC_INST_SC0x4402 -#define PPC_INST_SLBFEE0x7c0007a7 -#define PPC_INST_SLBIA 0x7c0003e4 - #define PPC_INST_STRING0x7c00042a #define PPC_INST_STRING_MASK 0xfc0007fe #define PPC_INST_STRING_GEN_MASK 0xfc00067e - #define PPC_INST_STSWI 0x7c0005aa #define PPC_INST_STSWX 0x7c00052a -#define PPC_INST_STXVD2X 0x7c000798 -#define PPC_INST_TLBIE 0x7c000264 -#define PPC_INST_TLBIEL0x7c000224 -#define PPC_INST_TLBILX0x7c24 -#define PPC_INST_WAIT 0x7c7c -#define PPC_INST_TLBIVAX 0x7c000624 -#define PPC_INST_TLBSRX_DOT0x7c0006a5 -#define PPC_INST_VPMSUMW 0x1488 -#define PPC_INST_VPMSUMD 0x14c8 -#define PPC_INST_VPERMXOR 0x102d -#define PPC_INST_XXLOR 0xf490 -#define PPC_INST_XXSWAPD 0xf250 -#define PPC_INST_XVCPSGNDP 0xf780 #define PPC_INST_TRECHKPT 0x7c0007dd #define PPC_INST_TRECLAIM 0x7c00075d -#define PPC_INST_TABORT0x7c00071d #define PPC_INST_TSR 0x7c0005dd - -#define PPC_INST_NAP
[RFC PATCH v2 4/7] powerpc/ppc-opcode: consolidate powerpc instructions from bpf_jit.h
move macro definitions of powerpc instructions from bpf_jit.h to ppc-opcode.h and adopt the users of the macros accordingly. `PPC_MR()` is defined twice in bpf_jit.h, remove the duplicate one. Signed-off-by: Balamuruhan S --- arch/powerpc/include/asm/ppc-opcode.h | 139 + arch/powerpc/net/bpf_jit.h| 166 ++- arch/powerpc/net/bpf_jit32.h | 24 +-- arch/powerpc/net/bpf_jit64.h | 12 +- arch/powerpc/net/bpf_jit_comp.c | 132 ++-- arch/powerpc/net/bpf_jit_comp64.c | 278 +- 6 files changed, 378 insertions(+), 373 deletions(-) diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index 2ae0afc5c2bb..6b9a891884be 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -79,6 +79,16 @@ #define IMM_L(i) ((uintptr_t)(i) & 0x) #define IMM_DS(i) ((uintptr_t)(i) & 0xfffc) +/* + * 16-bit immediate helper macros: HA() is for use with sign-extending instrs + * (e.g. LD, ADDI). If the bottom 16 bits is "-ve", add another bit into the + * top half to negate the effect (i.e. 0x + 1 = 0x(1)). + */ +#define IMM_H(i)((uintptr_t)(i)>>16) +#define IMM_HA(i) (((uintptr_t)(i)>>16) + \ + (((uintptr_t)(i) & 0x8000) >> 15)) + + /* opcode and xopcode for instructions */ #define OP_TRAP 3 #define OP_TRAP_64 2 @@ -637,6 +647,135 @@ #define PPC_RAW_ADDC_DOT(t, a, b) (PPC_INST_ADDC | ___PPC_RT(t) | \ ___PPC_RA(a) | ___PPC_RB(b) | \ 0x1) +#define PPC_RAW_NOP() (PPC_INST_NOP) +#define PPC_RAW_BLR() (PPC_INST_BLR) +#define PPC_RAW_BLRL() (PPC_INST_BLRL) +#define PPC_RAW_MTLR(r)(PPC_INST_MTLR | ___PPC_RT(r)) +#define PPC_RAW_BCTR() (PPC_INST_BCTR) +#define PPC_RAW_MTCTR(r) (PPC_INST_MTCTR | ___PPC_RT(r)) +#define PPC_RAW_ADDI(d, a, i) (PPC_INST_ADDI | ___PPC_RT(d) | \ + ___PPC_RA(a) | IMM_L(i)) +#define PPC_RAW_LI(r, i) PPC_RAW_ADDI(r, 0, i) +#define PPC_RAW_ADDIS(d, a, i) (PPC_INST_ADDIS | \ + ___PPC_RT(d) | ___PPC_RA(a) | \ + IMM_L(i)) +#define PPC_RAW_LIS(r, i) PPC_RAW_ADDIS(r, 0, i) +#define PPC_RAW_STDX(r, base, b) (PPC_INST_STDX | ___PPC_RS(r) | \ + ___PPC_RA(base) | ___PPC_RB(b)) +#define PPC_RAW_STDU(r, base, i) (PPC_INST_STDU | ___PPC_RS(r) | \ + ___PPC_RA(base) | \ + ((i) & 0xfffc)) +#define PPC_RAW_STW(r, base, i)(PPC_INST_STW | ___PPC_RS(r) | \ + ___PPC_RA(base) | IMM_L(i)) +#define PPC_RAW_STWU(r, base, i) (PPC_INST_STWU | ___PPC_RS(r) | \ + ___PPC_RA(base) | IMM_L(i)) +#define PPC_RAW_STH(r, base, i)(PPC_INST_STH | ___PPC_RS(r) | \ + ___PPC_RA(base) | IMM_L(i)) +#define PPC_RAW_STB(r, base, i)(PPC_INST_STB | ___PPC_RS(r) | \ + ___PPC_RA(base) | IMM_L(i)) +#define PPC_RAW_LBZ(r, base, i)(PPC_INST_LBZ | ___PPC_RT(r) | \ + ___PPC_RA(base) | IMM_L(i)) +#define PPC_RAW_LDX(r, base, b)(PPC_INST_LDX | ___PPC_RT(r) | \ + ___PPC_RA(base) | ___PPC_RB(b)) +#define PPC_RAW_LHZ(r, base, i)(PPC_INST_LHZ | ___PPC_RT(r) | \ + ___PPC_RA(base) | IMM_L(i)) +#define PPC_RAW_LHBRX(r, base, b) (PPC_INST_LHBRX | ___PPC_RT(r) | \ + ___PPC_RA(base) | ___PPC_RB(b)) +#define PPC_RAW_LDBRX(r, base, b) (PPC_INST_LDBRX | ___PPC_RT(r) | \ + ___PPC_RA(base) | ___PPC_RB(b)) +#define PPC_RAW_STWCX(s, a, b) (PPC_INST_STWCX | ___PPC_RS(s) | \ + ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_RAW_CMPWI(a, i)(PPC_INST_CMPWI | ___PPC_RA(a) | IMM_L(i)) +#define PPC_RAW_CMPDI(a, i)(PPC_INST_CMPDI | ___PPC_RA(a) | IMM_L(i)) +#define PPC_RAW_CMPW(a, b) (PPC_INST_CMPW | ___PPC_RA(a) | \ + ___PPC_RB(b)) +#define PPC_RAW_CMPD(a, b) (PPC_INST_CMPD | ___PPC_RA(a) | \ +
[RFC PATCH v2 3/7] powerpc/bpf_jit: reuse instruction macros from ppc-opcode.h
remove duplicate macro definitions from bpf_jit.h and reuse the macros from
ppc-opcode.h
Signed-off-by: Balamuruhan S
---
arch/powerpc/net/bpf_jit.h| 18 +-
arch/powerpc/net/bpf_jit32.h | 10 +-
arch/powerpc/net/bpf_jit64.h | 4 ++--
arch/powerpc/net/bpf_jit_comp.c | 2 +-
arch/powerpc/net/bpf_jit_comp64.c | 20 ++--
5 files changed, 19 insertions(+), 35 deletions(-)
diff --git a/arch/powerpc/net/bpf_jit.h b/arch/powerpc/net/bpf_jit.h
index 55d4377ccfae..535d1de4dfee 100644
--- a/arch/powerpc/net/bpf_jit.h
+++ b/arch/powerpc/net/bpf_jit.h
@@ -11,6 +11,7 @@
#ifndef __ASSEMBLY__
#include
+#include
#ifdef PPC64_ELF_ABI_v1
#define FUNCTION_DESCR_SIZE24
@@ -26,7 +27,6 @@
#define IMM_H(i) ((uintptr_t)(i)>>16)
#define IMM_HA(i) (((uintptr_t)(i)>>16) + \
(((uintptr_t)(i) & 0x8000) >> 15))
-#define IMM_L(i) ((uintptr_t)(i) & 0x)
#define PLANT_INSTR(d, idx, instr) \
do { if (d) { (d)[idx] = instr; } idx++; } while (0)
@@ -45,8 +45,6 @@
#define PPC_ADDIS(d, a, i) EMIT(PPC_INST_ADDIS | \
___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i))
#define PPC_LIS(r, i) PPC_ADDIS(r, 0, i)
-#define PPC_STD(r, base, i)EMIT(PPC_INST_STD | ___PPC_RS(r) |\
-___PPC_RA(base) | ((i) & 0xfffc))
#define PPC_STDX(r, base, b) EMIT(PPC_INST_STDX | ___PPC_RS(r) | \
___PPC_RA(base) | ___PPC_RB(b))
#define PPC_STDU(r, base, i) EMIT(PPC_INST_STDU | ___PPC_RS(r) | \
@@ -62,12 +60,8 @@
#define PPC_LBZ(r, base, i)EMIT(PPC_INST_LBZ | ___PPC_RT(r) |\
___PPC_RA(base) | IMM_L(i))
-#define PPC_LD(r, base, i) EMIT(PPC_INST_LD | ___PPC_RT(r) | \
-___PPC_RA(base) | ((i) & 0xfffc))
#define PPC_LDX(r, base, b)EMIT(PPC_INST_LDX | ___PPC_RT(r) |\
___PPC_RA(base) | ___PPC_RB(b))
-#define PPC_LWZ(r, base, i)EMIT(PPC_INST_LWZ | ___PPC_RT(r) |\
-___PPC_RA(base) | IMM_L(i))
#define PPC_LHZ(r, base, i)EMIT(PPC_INST_LHZ | ___PPC_RT(r) |\
___PPC_RA(base) | IMM_L(i))
#define PPC_LHBRX(r, base, b) EMIT(PPC_INST_LHBRX | ___PPC_RT(r) | \
@@ -75,16 +69,8 @@
#define PPC_LDBRX(r, base, b) EMIT(PPC_INST_LDBRX | ___PPC_RT(r) | \
___PPC_RA(base) | ___PPC_RB(b))
-#define PPC_BPF_LDARX(t, a, b, eh) EMIT(PPC_INST_LDARX | ___PPC_RT(t) |
\
- ___PPC_RA(a) | ___PPC_RB(b) | \
- __PPC_EH(eh))
-#define PPC_BPF_LWARX(t, a, b, eh) EMIT(PPC_INST_LWARX | ___PPC_RT(t) |
\
- ___PPC_RA(a) | ___PPC_RB(b) | \
- __PPC_EH(eh))
#define PPC_BPF_STWCX(s, a, b) EMIT(PPC_INST_STWCX | ___PPC_RS(s) | \
___PPC_RA(a) | ___PPC_RB(b))
-#define PPC_BPF_STDCX(s, a, b) EMIT(PPC_INST_STDCX | ___PPC_RS(s) | \
- ___PPC_RA(a) | ___PPC_RB(b))
#define PPC_CMPWI(a, i)EMIT(PPC_INST_CMPWI | ___PPC_RA(a) |
IMM_L(i))
#define PPC_CMPDI(a, i)EMIT(PPC_INST_CMPDI | ___PPC_RA(a) |
IMM_L(i))
#define PPC_CMPW(a, b) EMIT(PPC_INST_CMPW | ___PPC_RA(a) | \
@@ -100,8 +86,6 @@
#define PPC_SUB(d, a, b) EMIT(PPC_INST_SUB | ___PPC_RT(d) |\
___PPC_RB(a) | ___PPC_RA(b))
-#define PPC_ADD(d, a, b) EMIT(PPC_INST_ADD | ___PPC_RT(d) |\
-___PPC_RA(a) | ___PPC_RB(b))
#define PPC_MULD(d, a, b) EMIT(PPC_INST_MULLD | ___PPC_RT(d) | \
___PPC_RA(a) | ___PPC_RB(b))
#define PPC_MULW(d, a, b) EMIT(PPC_INST_MULLW | ___PPC_RT(d) | \
diff --git a/arch/powerpc/net/bpf_jit32.h b/arch/powerpc/net/bpf_jit32.h
index 4ec2a9f14f84..753c244a7cf9 100644
--- a/arch/powerpc/net/bpf_jit32.h
+++ b/arch/powerpc/net/bpf_jit32.h
@@ -76,13 +76,13 @@ DECLARE_LOAD_FUNC(sk_load_byte_msh);
else { PPC_ADDIS(r, base, IMM_HA(i));\
PPC_LBZ(r, r, IMM_L(i)); } } while(0)
-#define PPC_LD_OFFS(r, base, i) do { if ((i) < 32768) PPC_LD(r, base, i); \
+#define PPC_LD_OFFS(r, base, i) do { if ((i) < 32768) EMIT(PPC_RAW_LD(r, base,
i)); \
else { PPC_ADDIS(r, base, IMM_HA(i));\
-
[RFC PATCH v2 1/7] powerpc/ppc-opcode: introduce PPC_RAW_* macros for base instruction encoding
Introduce PPC_RAW_* macros to have all the bare encoding of ppc instructions. Move `VSX_XX*()` and `TMRN()` macros up to reuse it. Signed-off-by: Balamuruhan S --- arch/powerpc/include/asm/ppc-opcode.h | 183 -- 1 file changed, 175 insertions(+), 8 deletions(-) diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index c1df75edde44..c5ec2ea283f1 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -428,6 +428,181 @@ #define __PPC_EH(eh) 0 #endif +/* Base instruction encoding */ +#define PPC_RAW_CP_ABORT (PPC_INST_CP_ABORT) +#define PPC_RAW_COPY(a, b) (PPC_INST_COPY | ___PPC_RA(a) | \ + ___PPC_RB(b)) +#define PPC_RAW_DARN(t, l) (PPC_INST_DARN | ___PPC_RT(t) | \ + (((l) & 0x3) << 16)) +#define PPC_RAW_DCBAL(a, b)(PPC_INST_DCBAL | __PPC_RA(a) | \ + __PPC_RB(b)) +#define PPC_RAW_DCBZL(a, b)(PPC_INST_DCBZL | __PPC_RA(a) | \ + __PPC_RB(b)) +#define PPC_RAW_LQARX(t, a, b, eh) (PPC_INST_LQARX | ___PPC_RT(t) | \ + ___PPC_RA(a) | \ + ___PPC_RB(b) | __PPC_EH(eh)) +#define PPC_RAW_LDARX(t, a, b, eh) (PPC_INST_LDARX | ___PPC_RT(t) | \ + ___PPC_RA(a) | \ + ___PPC_RB(b) | __PPC_EH(eh)) +#define PPC_RAW_LWARX(t, a, b, eh) (PPC_INST_LWARX | \ + ___PPC_RT(t) | ___PPC_RA(a) | \ + ___PPC_RB(b) | __PPC_EH(eh)) +#define PPC_RAW_STQCX(t, a, b) (PPC_INST_STQCX | \ + ___PPC_RT(t) | ___PPC_RA(a) | \ + ___PPC_RB(b)) +#define PPC_RAW_MADDHD(t, a, b, c) (PPC_INST_MADDHD | \ + ___PPC_RT(t) | ___PPC_RA(a) | \ + ___PPC_RB(b) | ___PPC_RC(c)) +#define PPC_RAW_MADDHDU(t, a, b, c)(PPC_INST_MADDHDU | \ + ___PPC_RT(t) | ___PPC_RA(a) | \ + ___PPC_RB(b) | ___PPC_RC(c)) +#define PPC_RAW_MADDLD(t, a, b, c) (PPC_INST_MADDLD | \ + ___PPC_RT(t) | ___PPC_RA(a) | \ + ___PPC_RB(b) | ___PPC_RC(c)) +#define PPC_RAW_MSGSND(b) (PPC_INST_MSGSND | ___PPC_RB(b)) +#define PPC_RAW_MSGSYNC(PPC_INST_MSGSYNC) +#define PPC_RAW_MSGCLR(b) (PPC_INST_MSGCLR | ___PPC_RB(b)) +#define PPC_RAW_MSGSNDP(b) (PPC_INST_MSGSNDP | ___PPC_RB(b)) +#define PPC_RAW_MSGCLRP(b) (PPC_INST_MSGCLRP | ___PPC_RB(b)) +#define PPC_RAW_PASTE(a, b)(PPC_INST_PASTE | ___PPC_RA(a) | \ + ___PPC_RB(b)) +#define PPC_RAW_POPCNTB(a, s) (PPC_INST_POPCNTB | __PPC_RA(a) | \ + __PPC_RS(s)) +#define PPC_RAW_POPCNTD(a, s) (PPC_INST_POPCNTD | __PPC_RA(a) | \ + __PPC_RS(s)) +#define PPC_RAW_POPCNTW(a, s) (PPC_INST_POPCNTW | __PPC_RA(a) | \ + __PPC_RS(s)) +#define PPC_RAW_RFCI (PPC_INST_RFCI) +#define PPC_RAW_RFDI (PPC_INST_RFDI) +#define PPC_RAW_RFMCI (PPC_INST_RFMCI) +#define PPC_RAW_TLBILX(t, a, b)(PPC_INST_TLBILX | \ + __PPC_T_TLB(t) | \ + __PPC_RA0(a) | \ + __PPC_RB(b)) +#define PPC_RAW_WAIT(w)(PPC_INST_WAIT | __PPC_WC(w)) +#define PPC_RAW_TLBIE(lp, a) (PPC_INST_TLBIE | ___PPC_RB(a) | \ + ___PPC_RS(lp)) +#define PPC_RAW_TLBIE_5(rb, rs, ric, prs, r) \ + (PPC_INST_TLBIE | \ + ___PPC_RB(rb) | \ + ___PPC_RS(rs) | \ + ___PPC_RIC(ric) | \ + ___PPC_PRS(prs) | \ + ___PPC_R(r)) +#define PPC_RAW_TLBIEL(rb, rs, ric, prs, r) \ + (PPC_INST_TLBIEL | \ + ___PPC_RB(rb) | \ + __
[RFC PATCH v2 2/7] powerpc/ppc-opcode: move ppc instruction encoding from test_emulate_step
Few ppc instructions are encoded in test_emulate_step.c, consolidate them and use it from ppc-opcode.h Signed-off-by: Balamuruhan S --- arch/powerpc/include/asm/ppc-opcode.h | 35 ++ arch/powerpc/lib/test_emulate_step.c | 155 ++ 2 files changed, 91 insertions(+), 99 deletions(-) diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index c5ec2ea283f1..2ae0afc5c2bb 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -76,6 +76,9 @@ #define__REGA0_R30 30 #define__REGA0_R31 31 +#define IMM_L(i) ((uintptr_t)(i) & 0x) +#define IMM_DS(i) ((uintptr_t)(i) & 0xfffc) + /* opcode and xopcode for instructions */ #define OP_TRAP 3 #define OP_TRAP_64 2 @@ -602,6 +605,38 @@ ___PPC_RT(vrt) | \ ___PPC_RA(vra) | \ ___PPC_RB(vrb) | __PPC_RC21) +#define PPC_RAW_LD(r, base, i) (PPC_INST_LD | ___PPC_RT(r) | \ + ___PPC_RA(base) | IMM_DS(i)) +#define PPC_RAW_LWZ(r, base, i)(PPC_INST_LWZ | ___PPC_RT(r) | \ + ___PPC_RA(base) | IMM_L(i)) +#define PPC_RAW_LWZX(t, a, b) (PPC_INST_LWZX | ___PPC_RT(t) | \ + ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_RAW_STD(r, base, i)(PPC_INST_STD | ___PPC_RS(r) | \ + ___PPC_RA(base) | IMM_DS(i)) +#define PPC_RAW_STDCX(s, a, b) (PPC_INST_STDCX | ___PPC_RS(s) | \ + ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_RAW_LFSX(t, a, b) (PPC_INST_LFSX | ___PPC_RT(t) | \ + ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_RAW_STFSX(s, a, b) (PPC_INST_STFSX | ___PPC_RS(s) | \ + ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_RAW_LFDX(t, a, b) (PPC_INST_LFDX | ___PPC_RT(t) | \ + ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_RAW_STFDX(s, a, b) (PPC_INST_STFDX | ___PPC_RS(s) | \ + ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_RAW_LVX(t, a, b) (PPC_INST_LVX | ___PPC_RT(t) | \ + ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_RAW_STVX(s, a, b) (PPC_INST_STVX | ___PPC_RS(s) | \ + ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_RAW_ADD(t, a, b) (PPC_INST_ADD | ___PPC_RT(t) | \ + ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_RAW_ADD_DOT(t, a, b) (PPC_INST_ADD | ___PPC_RT(t) | \ + ___PPC_RA(a) | ___PPC_RB(b) | \ + 0x1) +#define PPC_RAW_ADDC(t, a, b) (PPC_INST_ADDC | ___PPC_RT(t) | \ + ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_RAW_ADDC_DOT(t, a, b) (PPC_INST_ADDC | ___PPC_RT(t) | \ + ___PPC_RA(a) | ___PPC_RB(b) | \ + 0x1) /* Deal with instructions that older assemblers aren't aware of */ #definePPC_CP_ABORTstringify_in_c(.long PPC_INST_CP_ABORT) diff --git a/arch/powerpc/lib/test_emulate_step.c b/arch/powerpc/lib/test_emulate_step.c index 53df4146dd32..7a703bec3061 100644 --- a/arch/powerpc/lib/test_emulate_step.c +++ b/arch/powerpc/lib/test_emulate_step.c @@ -12,49 +12,6 @@ #include #include -#define IMM_L(i) ((uintptr_t)(i) & 0x) -#define IMM_DS(i) ((uintptr_t)(i) & 0xfffc) - -/* - * Defined with TEST_ prefix so it does not conflict with other - * definitions. - */ -#define TEST_LD(r, base, i)(PPC_INST_LD | ___PPC_RT(r) | \ - ___PPC_RA(base) | IMM_DS(i)) -#define TEST_LWZ(r, base, i) (PPC_INST_LWZ | ___PPC_RT(r) | \ - ___PPC_RA(base) | IMM_L(i)) -#define TEST_LWZX(t, a, b) (PPC_INST_LWZX | ___PPC_RT(t) | \ - ___PPC_RA(a) | ___PPC_RB(b)) -#define TEST_STD(r, base, i) (PPC_INST_STD | ___PPC_RS(r) | \ - ___PPC_RA(base) | IMM_DS(i)) -#define TEST_LDARX(t, a, b, eh)(PPC_INST_LDARX | ___PPC_RT(t) | \ - ___PPC_RA(a) | ___PPC_RB(b) | \ - __PPC_EH(eh)) -#define TEST_STDCX(s, a, b)(PPC_INST_STDCX | ___PPC_RS(s) |\ - ___PPC_RA(a) | ___PPC
[RFC PATCH v2 0/7] consolidate PowerPC instruction encoding macros
ppc-opcode.h have base instruction encoding wrapped with stringify_in_c() for raw encoding to have compatibility. But there are redundant macros for base instruction encodings in bpf, instruction emulation test infrastructure and powerpc selftests. Currently PPC_INST_* macros are used for encoding instruction opcode and PPC_* for raw instuction encoding, this rfc patchset introduces PPC_RAW_* macros for base instruction encoding and reuse it from elsewhere. With this change we can avoid redundant macro definitions in multiple files and start adding new instructions in ppc-opcode.h in future. Changes in v2: - Fix review comments/suggestions from Naveen and Michael Ellerman, * Rename PPC_ENCODE_* to PPC_RAW_* for base instruction encoding macros. * Split the patches that does mass renaming and make them simpler that just adds new macros. * Keep the patch to update all the existing names later (patch 6). * Lot of PPC_INST_* macros are used only in ppc-opcode.h for PPC_* macros, fold PPC_INST_* encoding into PPC_RAW_* to avoid using them accidentally. * Fixed clipped macros that was due to a typo/copy-paste * Consolidated all the instruction encoding macros from bpf_jit.h to ppc-opcode.h * squashed patch that removes the duplicate macro PPC_MR() in bpf_jit.h * merge few changes in bpf_jit files from patch 2 into patch 3 * few fixes in powerpc selftest stringloops Makefile * build tested for ppc64le_defconfig, ppc64e_defconfig and pmac32_defconfig * Rebased on next branch of linuxppc tree Testing: --- * Tested it by compiling vmlinux and comparing objdump of it with and without the patchset and observed that it remains same, # diff vmlinux_objdump vmlinux_rfc_objdump 2c2 < vmlinux: file format elf64-powerpcle --- > vmlinux_rfc: file format elf64-powerpcle * Tested building it with this changes for Fedora30 config, booted VM with powerpc next and powerpc next + patchset to run powerpc selftest and ftrace selftest. There were couple of failures that were common and patchset did not introduce any new failures. ftrace selftest: --- # # of passed: 96 # # of failed: 1 # # of unresolved: 7 # # of untested: 0 # # of unsupported: 1 # # of xfailed: 1 # # of undefined(test bug): 0 not ok 1 selftests: ftrace: ftracetest # exit=1 powerpc selftest: not ok 7 selftests: powerpc/dscr: dscr_sysfs_thread_test # exit=1 not ok 20 selftests: powerpc/pmu/ebb: lost_exception_test # TIMEOUT not ok 2 selftests: powerpc/security: spectre_v2 # exit=1 Thanks to Naveen, Sandipan and Michael on overall suggestions/improvements. I would request for review and suggestions to make it better. v1: https://lists.ozlabs.org/pipermail/linuxppc-dev/2020-March/206494.html Balamuruhan S (7): powerpc/ppc-opcode: introduce PPC_RAW_* macros for base instruction encoding powerpc/ppc-opcode: move ppc instruction encoding from test_emulate_step powerpc/bpf_jit: reuse instruction macros from ppc-opcode.h powerpc/ppc-opcode: consolidate powerpc instructions from bpf_jit.h powerpc/ppc-opcode: reuse raw instruction macros to stringify powerpc/ppc-opcode: fold PPC_INST_* macros into PPC_RAW_* macros powerpc/selftest: reuse ppc-opcode macros to avoid redundancy arch/powerpc/include/asm/ppc-opcode.h | 706 +++--- arch/powerpc/lib/test_emulate_step.c | 155 ++-- arch/powerpc/net/bpf_jit.h| 184 + arch/powerpc/net/bpf_jit32.h | 34 +- arch/powerpc/net/bpf_jit64.h | 16 +- arch/powerpc/net/bpf_jit_comp.c | 134 ++-- arch/powerpc/net/bpf_jit_comp64.c | 298 .../selftests/powerpc/stringloops/Makefile| 34 +- .../powerpc/stringloops/asm/asm-const.h | 1 + .../powerpc/stringloops/asm/ppc-opcode.h | 36 +- 10 files changed, 762 insertions(+), 836 deletions(-) create mode 12 tools/testing/selftests/powerpc/stringloops/asm/asm-const.h mode change 100644 => 12 tools/testing/selftests/powerpc/stringloops/asm/ppc-opcode.h base-commit: 45591da765885f7320a111d290b3a28a23eed359 -- 2.24.1
Re: [PATCH v5 18/21] powerpc64: Add prefixed instructions to instruction data type
On Wed, 2020-04-15 at 14:40 +1000, Jordan Niethe wrote:
> On Mon, Apr 13, 2020 at 10:04 PM Balamuruhan S wrote:
> > On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> > > For powerpc64, redefine the ppc_inst type so both word and prefixed
> > > instructions can be represented. On powerpc32 the type will remain the
> > > same. Update places which had assumed instructions to be 4 bytes long.
> > >
> > > Signed-off-by: Jordan Niethe
> > > ---
> > > v4: New to series
> > > v5: - Distinguish normal instructions from prefixed instructions with a
> > >0xff marker for the suffix.
> > > - __patch_instruction() using std for prefixed instructions
> > > ---
> > > arch/powerpc/include/asm/inst.h | 71 ++--
> > > arch/powerpc/include/asm/kprobes.h | 2 +-
> > > arch/powerpc/include/asm/uaccess.h | 31 ++--
> > > arch/powerpc/include/asm/uprobes.h | 2 +-
> > > arch/powerpc/kernel/optprobes.c | 42
> > > arch/powerpc/kernel/optprobes_head.S | 3 ++
> > > arch/powerpc/kernel/trace/ftrace.c | 26 +-
> > > arch/powerpc/lib/code-patching.c | 19 +---
> > > arch/powerpc/lib/feature-fixups.c| 5 +-
> > > arch/powerpc/lib/sstep.c | 4 +-
> > > arch/powerpc/xmon/xmon.c | 6 +--
> > > arch/powerpc/xmon/xmon_bpts.S| 4 +-
> > > 12 files changed, 171 insertions(+), 44 deletions(-)
> > >
> > > diff --git a/arch/powerpc/include/asm/inst.h
> > > b/arch/powerpc/include/asm/inst.h
> > > index 70b37a35a91a..7e23e7146c66 100644
> > > --- a/arch/powerpc/include/asm/inst.h
> > > +++ b/arch/powerpc/include/asm/inst.h
> > > @@ -8,23 +8,67 @@
> > >
> > > struct ppc_inst {
> > > u32 val;
> > > +#ifdef __powerpc64__
> > > +u32 suffix;
> > > +#endif /* __powerpc64__ */
> > > } __packed;
> > >
> > > -#define ppc_inst(x) ((struct ppc_inst){ .val = x })
> > > +static inline int ppc_inst_opcode(struct ppc_inst x)
> > > +{
> > > + return x.val >> 26;
> >
> > why don't we wrap here and in `ppc_inst_opcode()` in patch 9 using
> > `ppc_inst_val()` ?
> Will do.
> >
> > > +}
> > >
> > > static inline u32 ppc_inst_val(struct ppc_inst x)
> >
> > There is another same definition below for the same function in
> > #else part of __powerpc64__ ifdef.
> Thanks
> >
> > > {
> > > return x.val;
> > > }
> > >
> > > -static inline bool ppc_inst_len(struct ppc_inst x)
> > > +#ifdef __powerpc64__
> > > +#define ppc_inst(x) ((struct ppc_inst){ .val = (x), .suffix = 0xff })
> > > +
> > > +#define ppc_inst_prefix(x, y) ((struct ppc_inst){ .val = (x), .suffix =
> > > (y)
> > > })
> > > +
> > > +static inline u32 ppc_inst_suffix(struct ppc_inst x)
> > > {
> > > - return sizeof(struct ppc_inst);
> > > + return x.suffix;
> > > }
> > >
> > > -static inline int ppc_inst_opcode(struct ppc_inst x)
> > > +static inline bool ppc_inst_prefixed(struct ppc_inst x) {
> > > + return ((ppc_inst_val(x) >> 26) == 1) && ppc_inst_suffix(x) !=
> > > 0xff;
> > > +}
> > > +
> > > +static inline struct ppc_inst ppc_inst_swab(struct ppc_inst x)
> > > {
> > > - return x.val >> 26;
> > > + return ppc_inst_prefix(swab32(ppc_inst_val(x)),
> > > +swab32(ppc_inst_suffix(x)));
> > > +}
> > > +
> > > +static inline struct ppc_inst ppc_inst_read(const struct ppc_inst *ptr)
> > > +{
> > > + u32 val, suffix = 0xff;
> > > + val = *(u32 *)ptr;
> > > + if ((val >> 26) == 1)
> > > + suffix = *((u32 *)ptr + 1);
> > > + return ppc_inst_prefix(val, suffix);
> > > +}
> > > +
> > > +static inline void ppc_inst_write(struct ppc_inst *ptr, struct ppc_inst
> > > x)
> > > +{
> > > + if (ppc_inst_prefixed(x)) {
> > > + *(u32 *)ptr = x.val;
> > > + *((u32 *)ptr + 1) = x.suffix;
> > > + } else {
> > > + *(u32 *)ptr = x.val;
> >
> > can we wrap here as well with `ppc_inst_val()` and `ppc_inst_suffix()` ?
> Yeah no reason not too.
> >
> > > + }
> &
Re: [PATCH v5 18/21] powerpc64: Add prefixed instructions to instruction data type
On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> For powerpc64, redefine the ppc_inst type so both word and prefixed
> instructions can be represented. On powerpc32 the type will remain the
> same. Update places which had assumed instructions to be 4 bytes long.
>
> Signed-off-by: Jordan Niethe
> ---
> v4: New to series
> v5: - Distinguish normal instructions from prefixed instructions with a
>0xff marker for the suffix.
> - __patch_instruction() using std for prefixed instructions
> ---
> arch/powerpc/include/asm/inst.h | 71 ++--
> arch/powerpc/include/asm/kprobes.h | 2 +-
> arch/powerpc/include/asm/uaccess.h | 31 ++--
> arch/powerpc/include/asm/uprobes.h | 2 +-
> arch/powerpc/kernel/optprobes.c | 42
> arch/powerpc/kernel/optprobes_head.S | 3 ++
> arch/powerpc/kernel/trace/ftrace.c | 26 +-
> arch/powerpc/lib/code-patching.c | 19 +---
> arch/powerpc/lib/feature-fixups.c| 5 +-
> arch/powerpc/lib/sstep.c | 4 +-
> arch/powerpc/xmon/xmon.c | 6 +--
> arch/powerpc/xmon/xmon_bpts.S| 4 +-
> 12 files changed, 171 insertions(+), 44 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/inst.h
> b/arch/powerpc/include/asm/inst.h
> index 70b37a35a91a..7e23e7146c66 100644
> --- a/arch/powerpc/include/asm/inst.h
> +++ b/arch/powerpc/include/asm/inst.h
> @@ -8,23 +8,67 @@
>
> struct ppc_inst {
> u32 val;
> +#ifdef __powerpc64__
> +u32 suffix;
> +#endif /* __powerpc64__ */
> } __packed;
>
> -#define ppc_inst(x) ((struct ppc_inst){ .val = x })
> +static inline int ppc_inst_opcode(struct ppc_inst x)
> +{
> + return x.val >> 26;
why don't we wrap here and in `ppc_inst_opcode()` in patch 9 using
`ppc_inst_val()` ?
> +}
>
> static inline u32 ppc_inst_val(struct ppc_inst x)
There is another same definition below for the same function in
#else part of __powerpc64__ ifdef.
> {
> return x.val;
> }
>
> -static inline bool ppc_inst_len(struct ppc_inst x)
> +#ifdef __powerpc64__
> +#define ppc_inst(x) ((struct ppc_inst){ .val = (x), .suffix = 0xff })
> +
> +#define ppc_inst_prefix(x, y) ((struct ppc_inst){ .val = (x), .suffix = (y)
> })
> +
> +static inline u32 ppc_inst_suffix(struct ppc_inst x)
> {
> - return sizeof(struct ppc_inst);
> + return x.suffix;
> }
>
> -static inline int ppc_inst_opcode(struct ppc_inst x)
> +static inline bool ppc_inst_prefixed(struct ppc_inst x) {
> + return ((ppc_inst_val(x) >> 26) == 1) && ppc_inst_suffix(x) != 0xff;
> +}
> +
> +static inline struct ppc_inst ppc_inst_swab(struct ppc_inst x)
> {
> - return x.val >> 26;
> + return ppc_inst_prefix(swab32(ppc_inst_val(x)),
> +swab32(ppc_inst_suffix(x)));
> +}
> +
> +static inline struct ppc_inst ppc_inst_read(const struct ppc_inst *ptr)
> +{
> + u32 val, suffix = 0xff;
> + val = *(u32 *)ptr;
> + if ((val >> 26) == 1)
> + suffix = *((u32 *)ptr + 1);
> + return ppc_inst_prefix(val, suffix);
> +}
> +
> +static inline void ppc_inst_write(struct ppc_inst *ptr, struct ppc_inst x)
> +{
> + if (ppc_inst_prefixed(x)) {
> + *(u32 *)ptr = x.val;
> + *((u32 *)ptr + 1) = x.suffix;
> + } else {
> + *(u32 *)ptr = x.val;
can we wrap here as well with `ppc_inst_val()` and `ppc_inst_suffix()` ?
> + }
> +}
> +
> +#else
> +
> +#define ppc_inst(x) ((struct ppc_inst){ .val = x })
> +
> +static inline bool ppc_inst_prefixed(ppc_inst x)
> +{
> + return 0;
Is it return !!0 or return false ?
> }
>
> static inline struct ppc_inst ppc_inst_swab(struct ppc_inst x)
> @@ -32,14 +76,31 @@ static inline struct ppc_inst ppc_inst_swab(struct
> ppc_inst x)
> return ppc_inst(swab32(ppc_inst_val(x)));
> }
>
> +static inline u32 ppc_inst_val(struct ppc_inst x)
[...] duplicate definition that is defined outside __powerpc64__ above.
> +{
> + return x.val;
> +}
> +
> static inline struct ppc_inst ppc_inst_read(const struct ppc_inst *ptr)
> {
> return *ptr;
> }
>
> +static inline void ppc_inst_write(struct ppc_inst *ptr, struct ppc_inst x)
> +{
> + *ptr = x;
> +}
> +
> +#endif /* __powerpc64__ */
> +
> static inline bool ppc_inst_equal(struct ppc_inst x, struct ppc_inst y)
> {
> return !memcmp(, , sizeof(struct ppc_inst));
> }
>
> +static inline int ppc_inst_len(struct ppc_inst x)
> +{
> + return (ppc_inst_prefixed(x)) ? 8 : 4;
> +}
> +
> #endif /* _ASM_INST_H */
> diff --git a/arch/powerpc/include/asm/kprobes.h
> b/arch/powerpc/include/asm/kprobes.h
> index 66b3f2983b22..4fc0e15e23a5 100644
> --- a/arch/powerpc/include/asm/kprobes.h
> +++ b/arch/powerpc/include/asm/kprobes.h
> @@ -43,7 +43,7 @@ extern kprobe_opcode_t optprobe_template_ret[];
> extern kprobe_opcode_t optprobe_template_end[];
>
> /* Fixed instruction size for powerpc */
> -#define MAX_INSN_SIZE1
> +#define
Re: [PATCH v5 13/21] powerpc/xmon: Use a function for reading instructions
On Wed, 2020-04-08 at 12:18 +1000, Jordan Niethe wrote:
> On Tue, Apr 7, 2020 at 9:31 PM Balamuruhan S wrote:
> > On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> > > Currently in xmon, mread() is used for reading instructions. In
> > > preparation for prefixed instructions, create and use a new function,
> > > mread_instr(), especially for reading instructions.
> > >
> > > Signed-off-by: Jordan Niethe
> > > ---
> > > v5: New to series, seperated from "Add prefixed instructions to
> > > instruction data type"
> > > ---
> > > arch/powerpc/xmon/xmon.c | 24
> > > 1 file changed, 20 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
> > > index 5e3949322a6c..6f4cf01a58c1 100644
> > > --- a/arch/powerpc/xmon/xmon.c
> > > +++ b/arch/powerpc/xmon/xmon.c
> > > @@ -125,6 +125,7 @@ extern unsigned int bpt_table[NBPTS * BPT_WORDS];
> > > static int cmds(struct pt_regs *);
> > > static int mread(unsigned long, void *, int);
> > > static int mwrite(unsigned long, void *, int);
> > > +static int mread_instr(unsigned long, struct ppc_inst *);
> > > static int handle_fault(struct pt_regs *);
> > > static void byterev(unsigned char *, int);
> > > static void memex(void);
> > > @@ -899,7 +900,7 @@ static void insert_bpts(void)
> > > for (i = 0; i < NBPTS; ++i, ++bp) {
> > > if ((bp->enabled & (BP_TRAP|BP_CIABR)) == 0)
> > > continue;
> > > - if (mread(bp->address, , 4) != 4) {
> > > + if (!mread_instr(bp->address, )) {
> >
> > Are these checks made based on whether `ppc_inst_len()` returns bool from
> > mread_instr() ?
> No, it was meant to be the length itself returned with a length of 0
> indicating an error. I will need to fix that.
I doubt it would return 0, whether we read instruction or not ppc_inst_len()
would always return sizeof(struct ppc_inst).
can we do something like,
static int
mread_instr(unsigned long adrs, struct ppc_inst *instr)
{
int size = 0;
if (setjmp(bus_error_jmp) == 0) {
catch_memory_errors = 1;
sync();
*instr = ppc_inst_read((struct ppc_inst *)adrs);
sync();
/* wait a little while to see if we get a machine check */
__delay(200);
size = ppc_inst_len(instr);
}
catch_memory_errors = 0;
return size;
}
-- Bala
> > -- Bala
> >
> >
> > > printf("Couldn't read instruction at %lx, "
> > > "disabling breakpoint there\n", bp-
> > > >address);
> > > bp->enabled = 0;
> > > @@ -949,7 +950,7 @@ static void remove_bpts(void)
> > > for (i = 0; i < NBPTS; ++i, ++bp) {
> > > if ((bp->enabled & (BP_TRAP|BP_CIABR)) != BP_TRAP)
> > > continue;
> > > - if (mread(bp->address, , 4) == 4
> > > + if (mread_instr(bp->address, )
> > > && ppc_inst_equal(instr, ppc_inst(bpinstr))
> > > && patch_instruction(
> > > (struct ppc_inst *)bp->address, ppc_inst_read(bp-
> > > > instr)) != 0)
> > > @@ -1165,7 +1166,7 @@ static int do_step(struct pt_regs *regs)
> > > force_enable_xmon();
> > > /* check we are in 64-bit kernel mode, translation enabled */
> > > if ((regs->msr & (MSR_64BIT|MSR_PR|MSR_IR)) == (MSR_64BIT|MSR_IR))
> > > {
> > > - if (mread(regs->nip, , 4) == 4) {
> > > + if (mread_instr(regs->nip, )) {
> > > stepped = emulate_step(regs, instr);
> > > if (stepped < 0) {
> > > printf("Couldn't single-step %s
> > > instruction\n",
> > > @@ -1332,7 +1333,7 @@ static long check_bp_loc(unsigned long addr)
> > > printf("Breakpoints may only be placed at kernel
> > > addresses\n");
> > > return 0;
> > > }
> > > - if (!mread(addr, , sizeof(instr))) {
> > > + if (!mread_instr(addr, )) {
> > > printf("Can't read instruction at address %lx\n", addr);
> > > return 0;
> > > }
> > > @@ -2125,6 +2126,21 @@ mwrite(unsigned long adrs, void *buf, int size)
> > > return n;
> > > }
> > >
> > > +static int
> > > +mread_instr(unsigned long adrs, struct ppc_inst *instr)
> > > +{
> > > + if (setjmp(bus_error_jmp) == 0) {
> > > + catch_memory_errors = 1;
> > > + sync();
> > > + *instr = ppc_inst_read((struct ppc_inst *)adrs);
> > > + sync();
> > > + /* wait a little while to see if we get a machine check */
> > > + __delay(200);
> > > + }
> > > + catch_memory_errors = 0;
> > > + return ppc_inst_len(*instr);
> > > +}
> > > +
> > > static int fault_type;
> > > static int fault_except;
> > > static char *fault_chars[] = { "--", "**", "##" };
Re: [PATCH v5 13/21] powerpc/xmon: Use a function for reading instructions
On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> Currently in xmon, mread() is used for reading instructions. In
> preparation for prefixed instructions, create and use a new function,
> mread_instr(), especially for reading instructions.
>
> Signed-off-by: Jordan Niethe
> ---
> v5: New to series, seperated from "Add prefixed instructions to
> instruction data type"
> ---
> arch/powerpc/xmon/xmon.c | 24
> 1 file changed, 20 insertions(+), 4 deletions(-)
>
> diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
> index 5e3949322a6c..6f4cf01a58c1 100644
> --- a/arch/powerpc/xmon/xmon.c
> +++ b/arch/powerpc/xmon/xmon.c
> @@ -125,6 +125,7 @@ extern unsigned int bpt_table[NBPTS * BPT_WORDS];
> static int cmds(struct pt_regs *);
> static int mread(unsigned long, void *, int);
> static int mwrite(unsigned long, void *, int);
> +static int mread_instr(unsigned long, struct ppc_inst *);
> static int handle_fault(struct pt_regs *);
> static void byterev(unsigned char *, int);
> static void memex(void);
> @@ -899,7 +900,7 @@ static void insert_bpts(void)
> for (i = 0; i < NBPTS; ++i, ++bp) {
> if ((bp->enabled & (BP_TRAP|BP_CIABR)) == 0)
> continue;
> - if (mread(bp->address, , 4) != 4) {
> + if (!mread_instr(bp->address, )) {
Are these checks made based on whether `ppc_inst_len()` returns bool from
mread_instr() ?
-- Bala
> printf("Couldn't read instruction at %lx, "
> "disabling breakpoint there\n", bp->address);
> bp->enabled = 0;
> @@ -949,7 +950,7 @@ static void remove_bpts(void)
> for (i = 0; i < NBPTS; ++i, ++bp) {
> if ((bp->enabled & (BP_TRAP|BP_CIABR)) != BP_TRAP)
> continue;
> - if (mread(bp->address, , 4) == 4
> + if (mread_instr(bp->address, )
> && ppc_inst_equal(instr, ppc_inst(bpinstr))
> && patch_instruction(
> (struct ppc_inst *)bp->address, ppc_inst_read(bp-
> >instr)) != 0)
> @@ -1165,7 +1166,7 @@ static int do_step(struct pt_regs *regs)
> force_enable_xmon();
> /* check we are in 64-bit kernel mode, translation enabled */
> if ((regs->msr & (MSR_64BIT|MSR_PR|MSR_IR)) == (MSR_64BIT|MSR_IR)) {
> - if (mread(regs->nip, , 4) == 4) {
> + if (mread_instr(regs->nip, )) {
> stepped = emulate_step(regs, instr);
> if (stepped < 0) {
> printf("Couldn't single-step %s instruction\n",
> @@ -1332,7 +1333,7 @@ static long check_bp_loc(unsigned long addr)
> printf("Breakpoints may only be placed at kernel addresses\n");
> return 0;
> }
> - if (!mread(addr, , sizeof(instr))) {
> + if (!mread_instr(addr, )) {
> printf("Can't read instruction at address %lx\n", addr);
> return 0;
> }
> @@ -2125,6 +2126,21 @@ mwrite(unsigned long adrs, void *buf, int size)
> return n;
> }
>
> +static int
> +mread_instr(unsigned long adrs, struct ppc_inst *instr)
> +{
> + if (setjmp(bus_error_jmp) == 0) {
> + catch_memory_errors = 1;
> + sync();
> + *instr = ppc_inst_read((struct ppc_inst *)adrs);
> + sync();
> + /* wait a little while to see if we get a machine check */
> + __delay(200);
> + }
> + catch_memory_errors = 0;
> + return ppc_inst_len(*instr);
> +}
> +
> static int fault_type;
> static int fault_except;
> static char *fault_chars[] = { "--", "**", "##" };
Re: [PATCH v5 12/21] powerpc: Introduce a function for reporting instruction length
On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> Currently all instructions have the same length, but in preparation for
> prefixed instructions introduce a function for returning instruction
> length.
>
> Signed-off-by: Jordan Niethe
> ---
> arch/powerpc/include/asm/inst.h | 5 +
> arch/powerpc/kernel/kprobes.c | 6 --
> arch/powerpc/kernel/uprobes.c | 2 +-
> 3 files changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/inst.h
> b/arch/powerpc/include/asm/inst.h
> index 369b35ce964c..70b37a35a91a 100644
> --- a/arch/powerpc/include/asm/inst.h
> +++ b/arch/powerpc/include/asm/inst.h
> @@ -17,6 +17,11 @@ static inline u32 ppc_inst_val(struct ppc_inst x)
> return x.val;
> }
>
> +static inline bool ppc_inst_len(struct ppc_inst x)
return type shouldn't be a bool, `size_t` instead.
-- Bala
> +{
> + return sizeof(struct ppc_inst);
> +}
> +
> static inline int ppc_inst_opcode(struct ppc_inst x)
> {
> return x.val >> 26;
> diff --git a/arch/powerpc/kernel/kprobes.c b/arch/powerpc/kernel/kprobes.c
> index ff53e5ef7e40..8d17cfdcdc54 100644
> --- a/arch/powerpc/kernel/kprobes.c
> +++ b/arch/powerpc/kernel/kprobes.c
> @@ -474,14 +474,16 @@ NOKPROBE_SYMBOL(trampoline_probe_handler);
> */
> int kprobe_post_handler(struct pt_regs *regs)
> {
> + int len;
> struct kprobe *cur = kprobe_running();
> struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
>
> if (!cur || user_mode(regs))
> return 0;
>
> + len = ppc_inst_len(ppc_inst_read((struct ppc_inst *)cur->ainsn.insn));
> /* make sure we got here for instruction we have a kprobe on */
> - if (((unsigned long)cur->ainsn.insn + 4) != regs->nip)
> + if (((unsigned long)cur->ainsn.insn + len) != regs->nip)
> return 0;
>
> if ((kcb->kprobe_status != KPROBE_REENTER) && cur->post_handler) {
> @@ -490,7 +492,7 @@ int kprobe_post_handler(struct pt_regs *regs)
> }
>
> /* Adjust nip to after the single-stepped instruction */
> - regs->nip = (unsigned long)cur->addr + 4;
> + regs->nip = (unsigned long)cur->addr + len;
> regs->msr |= kcb->kprobe_saved_msr;
>
> /*Restore back the original saved kprobes variables and continue. */
> diff --git a/arch/powerpc/kernel/uprobes.c b/arch/powerpc/kernel/uprobes.c
> index 31c870287f2b..8e63afa012ba 100644
> --- a/arch/powerpc/kernel/uprobes.c
> +++ b/arch/powerpc/kernel/uprobes.c
> @@ -112,7 +112,7 @@ int arch_uprobe_post_xol(struct arch_uprobe *auprobe,
> struct pt_regs *regs)
>* support doesn't exist and have to fix-up the next instruction
>* to be executed.
>*/
> - regs->nip = utask->vaddr + MAX_UINSN_BYTES;
> + regs->nip = utask->vaddr + ppc_inst_len(auprobe->insn);
>
> user_disable_single_step(current);
> return 0;
Re: [PATCH v5 11/21] powerpc: Define and use __get_user_instr{, inatomic}()
On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> Define specific __get_user_instr() and __get_user_instr_inatomic()
> macros for reading instructions from user space.
>
> Signed-off-by: Jordan Niethe
> ---
> arch/powerpc/include/asm/uaccess.h | 5 +
> arch/powerpc/kernel/align.c | 2 +-
> arch/powerpc/kernel/hw_breakpoint.c | 2 +-
> arch/powerpc/kernel/vecemu.c| 2 +-
> 4 files changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/uaccess.h
> b/arch/powerpc/include/asm/uaccess.h
> index 2f500debae21..c0a35e4586a5 100644
> --- a/arch/powerpc/include/asm/uaccess.h
> +++ b/arch/powerpc/include/asm/uaccess.h
> @@ -105,6 +105,11 @@ static inline int __access_ok(unsigned long addr,
> unsigned long size,
> #define __put_user_inatomic(x, ptr) \
> __put_user_nosleep((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)))
>
> +#define __get_user_instr(x, ptr) \
> + __get_user_nocheck((x).val, (u32 *)(ptr), sizeof(u32), true)
> +
> +#define __get_user_instr_inatomic(x, ptr) \
> + __get_user_nosleep((x).val, (u32 *)(ptr), sizeof(u32))
should we use ppc_inst_val() ?
-- Bala
> extern long __put_user_bad(void);
>
> /*
> diff --git a/arch/powerpc/kernel/align.c b/arch/powerpc/kernel/align.c
> index 66a6d1de7799..65cdfd41e3a1 100644
> --- a/arch/powerpc/kernel/align.c
> +++ b/arch/powerpc/kernel/align.c
> @@ -304,7 +304,7 @@ int fix_alignment(struct pt_regs *regs)
>*/
> CHECK_FULL_REGS(regs);
>
> - if (unlikely(__get_user(instr.val, (unsigned int __user *)regs->nip)))
> + if (unlikely(__get_user_instr(instr, (void __user *)regs->nip)))
> return -EFAULT;
> if ((regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE)) {
> /* We don't handle PPC little-endian any more... */
> diff --git a/arch/powerpc/kernel/hw_breakpoint.c
> b/arch/powerpc/kernel/hw_breakpoint.c
> index 542f65ccf68b..cebab14e2788 100644
> --- a/arch/powerpc/kernel/hw_breakpoint.c
> +++ b/arch/powerpc/kernel/hw_breakpoint.c
> @@ -249,7 +249,7 @@ static bool stepping_handler(struct pt_regs *regs, struct
> perf_event *bp,
> struct instruction_op op;
> unsigned long addr = info->address;
>
> - if (__get_user_inatomic(instr.val, (unsigned int *)regs->nip))
> + if (__get_user_instr_inatomic(instr, (void __user *)regs->nip))
> goto fail;
>
> ret = analyse_instr(, regs, instr);
> diff --git a/arch/powerpc/kernel/vecemu.c b/arch/powerpc/kernel/vecemu.c
> index bbf536e10902..c82ede46d71b 100644
> --- a/arch/powerpc/kernel/vecemu.c
> +++ b/arch/powerpc/kernel/vecemu.c
> @@ -266,7 +266,7 @@ int emulate_altivec(struct pt_regs *regs)
> unsigned int va, vb, vc, vd;
> vector128 *vrs;
>
> - if (get_user(instr.val, (unsigned int __user *) regs->nip))
> + if (__get_user_instr(instr, (void __user *) regs->nip))
> return -EFAULT;
>
> word = ppc_inst_val(instr);
Re: [PATCH v5 10/21] powerpc: Use a function for reading instructions
On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> Prefixed instructions will mean there are instructions of different
> length. As a result dereferencing a pointer to an instruction will not
> necessarily give the desired result. Introduce a function for reading
> instructions from memory into the instruction data type.
>
> Signed-off-by: Jordan Niethe
> ---
> v4: New to series
> v5: - Rename read_inst() -> probe_kernel_read_inst()
> - No longer modify uprobe probe type in this patch
> ---
> arch/powerpc/include/asm/inst.h| 5 +
> arch/powerpc/kernel/kprobes.c | 11 --
> arch/powerpc/kernel/mce_power.c| 2 +-
> arch/powerpc/kernel/optprobes.c| 4 ++--
> arch/powerpc/kernel/trace/ftrace.c | 33 +++---
> arch/powerpc/lib/code-patching.c | 23 ++---
> arch/powerpc/lib/feature-fixups.c | 2 +-
> arch/powerpc/xmon/xmon.c | 6 +++---
> 8 files changed, 48 insertions(+), 38 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/inst.h
> b/arch/powerpc/include/asm/inst.h
> index a71decf5f871..369b35ce964c 100644
> --- a/arch/powerpc/include/asm/inst.h
> +++ b/arch/powerpc/include/asm/inst.h
> @@ -27,6 +27,11 @@ static inline struct ppc_inst ppc_inst_swab(struct
> ppc_inst x)
> return ppc_inst(swab32(ppc_inst_val(x)));
> }
>
> +static inline struct ppc_inst ppc_inst_read(const struct ppc_inst *ptr)
> +{
> + return *ptr;
> +}
> +
> static inline bool ppc_inst_equal(struct ppc_inst x, struct ppc_inst y)
> {
> return !memcmp(, , sizeof(struct ppc_inst));
> diff --git a/arch/powerpc/kernel/kprobes.c b/arch/powerpc/kernel/kprobes.c
> index 9ed996cb0589..ff53e5ef7e40 100644
> --- a/arch/powerpc/kernel/kprobes.c
> +++ b/arch/powerpc/kernel/kprobes.c
> @@ -106,7 +106,7 @@ kprobe_opcode_t *kprobe_lookup_name(const char *name,
> unsigned int offset)
> int arch_prepare_kprobe(struct kprobe *p)
> {
> int ret = 0;
> - struct ppc_inst insn = *(struct ppc_inst *)p->addr;
> + struct ppc_inst insn = ppc_inst_read((struct ppc_inst *)p->addr);
>
> if ((unsigned long)p->addr & 0x03) {
> printk("Attempt to register kprobe at an unaligned address\n");
> @@ -125,11 +125,8 @@ int arch_prepare_kprobe(struct kprobe *p)
> }
>
> if (!ret) {
> - memcpy(p->ainsn.insn, p->addr,
> - MAX_INSN_SIZE * sizeof(kprobe_opcode_t));
> - p->opcode = *p->addr;
> - flush_icache_range((unsigned long)p->ainsn.insn,
> - (unsigned long)p->ainsn.insn +
> sizeof(kprobe_opcode_t));
> + patch_instruction((struct ppc_inst *)p->ainsn.insn, insn);
> + p->opcode = ppc_inst_val(insn);
This is a different change from this commit
-- Bala
> }
>
> p->ainsn.boostable = 0;
> @@ -217,7 +214,7 @@ NOKPROBE_SYMBOL(arch_prepare_kretprobe);
> static int try_to_emulate(struct kprobe *p, struct pt_regs *regs)
> {
> int ret;
> - struct ppc_inst insn = *(struct ppc_inst *)p->ainsn.insn;
> + struct ppc_inst insn = ppc_inst_read((struct ppc_inst *)p->ainsn.insn);
>
> /* regs->nip is also adjusted if emulate_step returns 1 */
> ret = emulate_step(regs, insn);
> diff --git a/arch/powerpc/kernel/mce_power.c
> b/arch/powerpc/kernel/mce_power.c
> index 7118b46a6543..859b602fa270 100644
> --- a/arch/powerpc/kernel/mce_power.c
> +++ b/arch/powerpc/kernel/mce_power.c
> @@ -374,7 +374,7 @@ static int mce_find_instr_ea_and_phys(struct pt_regs
> *regs, uint64_t *addr,
> pfn = addr_to_pfn(regs, regs->nip);
> if (pfn != ULONG_MAX) {
> instr_addr = (pfn << PAGE_SHIFT) + (regs->nip & ~PAGE_MASK);
> - instr = *(struct ppc_inst *)(instr_addr);
> + instr = ppc_inst_read((struct ppc_inst *)instr_addr);
> if (!analyse_instr(, , instr)) {
> pfn = addr_to_pfn(regs, op.ea);
> *addr = op.ea;
> diff --git a/arch/powerpc/kernel/optprobes.c
> b/arch/powerpc/kernel/optprobes.c
> index b61bbcee84f4..684640b8fa2e 100644
> --- a/arch/powerpc/kernel/optprobes.c
> +++ b/arch/powerpc/kernel/optprobes.c
> @@ -100,8 +100,8 @@ static unsigned long can_optimize(struct kprobe *p)
>* Ensure that the instruction is not a conditional branch,
>* and that can be emulated.
>*/
> - if (!is_conditional_branch(*(struct ppc_inst *)p->ainsn.insn) &&
> - analyse_instr(, , *(struct ppc_inst *)p-
> >ainsn.insn) == 1) {
> + if (!is_conditional_branch(ppc_inst_read((struct ppc_inst *)p-
> >ainsn.insn)) &&
> + analyse_instr(, , ppc_inst_read((struct
> ppc_inst *)p->ainsn.insn)) == 1) {
> emulate_update_regs(, );
> nip = regs.nip;
> }
> diff --git a/arch/powerpc/kernel/trace/ftrace.c
> b/arch/powerpc/kernel/trace/ftrace.c
> index 442c62fb68ff..e78742613b36 100644
> --- a/arch/powerpc/kernel/trace/ftrace.c
>
Re: [PATCH v5 09/21] powerpc: Use a datatype for instructions
On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> Currently unsigned ints are used to represent instructions on powerpc.
> This has worked well as instructions have always been 4 byte words.
> However, a future ISA version will introduce some changes to
> instructions that mean this scheme will no longer work as well. This
> change is Prefixed Instructions. A prefixed instruction is made up of a
> word prefix followed by a word suffix to make an 8 byte double word
> instruction. No matter the endianess of the system the prefix always
> comes first. Prefixed instructions are only planned for powerpc64.
>
> Introduce a ppc_inst type to represent both prefixed and word
> instructions on powerpc64 while keeping it possible to exclusively have
> word instructions on powerpc32, A latter patch will expand the type to
> include prefixed instructions but for now just typedef it to a u32.
>
> Later patches will introduce helper functions and macros for
> manipulating the instructions so that powerpc64 and powerpc32 might
> maintain separate type definitions.
>
> Signed-off-by: Jordan Niethe
> ---
> v4: New to series
> v5: Add to epapr_paravirt.c, kgdb.c
> ---
> arch/powerpc/include/asm/code-patching.h | 32 -
> arch/powerpc/include/asm/inst.h | 20 +++---
> arch/powerpc/include/asm/sstep.h | 5 +-
> arch/powerpc/include/asm/uprobes.h | 5 +-
> arch/powerpc/kernel/align.c | 4 +-
> arch/powerpc/kernel/epapr_paravirt.c | 4 +-
> arch/powerpc/kernel/hw_breakpoint.c | 4 +-
> arch/powerpc/kernel/jump_label.c | 2 +-
> arch/powerpc/kernel/kgdb.c | 4 +-
> arch/powerpc/kernel/kprobes.c| 8 +--
> arch/powerpc/kernel/mce_power.c | 5 +-
> arch/powerpc/kernel/optprobes.c | 40 ++--
> arch/powerpc/kernel/setup_32.c | 2 +-
> arch/powerpc/kernel/trace/ftrace.c | 83
> arch/powerpc/kernel/vecemu.c | 5 +-
> arch/powerpc/lib/code-patching.c | 69 ++--
> arch/powerpc/lib/feature-fixups.c| 48 +++---
> arch/powerpc/lib/sstep.c | 4 +-
> arch/powerpc/lib/test_emulate_step.c | 9 +--
> arch/powerpc/perf/core-book3s.c | 4 +-
> arch/powerpc/xmon/xmon.c | 24 +++
> 21 files changed, 196 insertions(+), 185 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/code-patching.h
> b/arch/powerpc/include/asm/code-patching.h
> index 48e021957ee5..eacc9102c251 100644
> --- a/arch/powerpc/include/asm/code-patching.h
> +++ b/arch/powerpc/include/asm/code-patching.h
> @@ -23,33 +23,33 @@
> #define BRANCH_ABSOLUTE 0x2
>
> bool is_offset_in_branch_range(long offset);
> -int create_branch(unsigned int *instr, const unsigned int *addr,
> +int create_branch(struct ppc_inst *instr, const struct ppc_inst *addr,
> unsigned long target, int flags);
> -int create_cond_branch(unsigned int *instr, const unsigned int *addr,
> +int create_cond_branch(struct ppc_inst *instr, const struct ppc_inst *addr,
> unsigned long target, int flags);
> -int patch_branch(unsigned int *addr, unsigned long target, int flags);
> -int patch_instruction(unsigned int *addr, unsigned int instr);
> -int raw_patch_instruction(unsigned int *addr, unsigned int instr);
> +int patch_branch(struct ppc_inst *addr, unsigned long target, int flags);
> +int patch_instruction(struct ppc_inst *addr, struct ppc_inst instr);
> +int raw_patch_instruction(struct ppc_inst *addr, struct ppc_inst instr);
>
> static inline unsigned long patch_site_addr(s32 *site)
> {
> return (unsigned long)site + *site;
> }
>
> -static inline int patch_instruction_site(s32 *site, unsigned int instr)
> +static inline int patch_instruction_site(s32 *site, struct ppc_inst instr)
> {
> - return patch_instruction((unsigned int *)patch_site_addr(site), instr);
> + return patch_instruction((struct ppc_inst *)patch_site_addr(site),
> instr);
> }
>
> static inline int patch_branch_site(s32 *site, unsigned long target, int
> flags)
> {
> - return patch_branch((unsigned int *)patch_site_addr(site), target,
> flags);
> + return patch_branch((struct ppc_inst *)patch_site_addr(site), target,
> flags);
> }
>
> static inline int modify_instruction(unsigned int *addr, unsigned int clr,
>unsigned int set)
> {
> - return patch_instruction(addr, ppc_inst((*addr & ~clr) | set));
> + return patch_instruction((struct ppc_inst *)addr, ppc_inst((*addr &
> ~clr) | set));
> }
>
> static inline int modify_instruction_site(s32 *site, unsigned int clr,
> unsigned int set)
> @@ -57,13 +57,13 @@ static inline int modify_instruction_site(s32 *site,
> unsigned int clr, unsigned
> return modify_instruction((unsigned int *)patch_site_addr(site), clr,
> set);
> }
>
> -int instr_is_relative_branch(unsigned int instr);
> -int
Re: [PATCH v5 07/21] powerpc: Use a function for byte swapping instructions
On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> Use a function for byte swapping instructions in preparation of a more
> complicated instruction type.
Reviewed-by: Balamuruhan S
>
> Signed-off-by: Jordan Niethe
> ---
> arch/powerpc/include/asm/inst.h | 5 +
> arch/powerpc/kernel/align.c | 2 +-
> 2 files changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/arch/powerpc/include/asm/inst.h
> b/arch/powerpc/include/asm/inst.h
> index 15f570bef936..78eb1481f1f6 100644
> --- a/arch/powerpc/include/asm/inst.h
> +++ b/arch/powerpc/include/asm/inst.h
> @@ -18,4 +18,9 @@ static inline int ppc_inst_opcode(u32 x)
> return x >> 26;
> }
>
> +static inline u32 ppc_inst_swab(u32 x)
> +{
> + return ppc_inst(swab32(ppc_inst_val(x)));
> +}
> +
> #endif /* _ASM_INST_H */
> diff --git a/arch/powerpc/kernel/align.c b/arch/powerpc/kernel/align.c
> index a83d32c6513d..46870cf6a6dc 100644
> --- a/arch/powerpc/kernel/align.c
> +++ b/arch/powerpc/kernel/align.c
> @@ -310,7 +310,7 @@ int fix_alignment(struct pt_regs *regs)
> /* We don't handle PPC little-endian any more... */
> if (cpu_has_feature(CPU_FTR_PPC_LE))
> return -EIO;
> - instr = swab32(instr);
> + instr = ppc_inst_swab(instr);
> }
>
> #ifdef CONFIG_SPE
Re: [PATCH v5 08/21] powerpc: Introduce functions for instruction equality
On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> In preparation for an instruction data type that can not be directly
> used with the '==' operator use functions for checking equality.
LGTM except one comment below, otherwise
Reviewed-by: Balamuruhan S
>
> Signed-off-by: Jordan Niethe
> ---
> v5: Remove ppc_inst_null()
> ---
> arch/powerpc/include/asm/inst.h | 5 +
> arch/powerpc/kernel/trace/ftrace.c | 15 ---
> arch/powerpc/lib/code-patching.c | 12 ++--
> arch/powerpc/lib/test_emulate_step.c | 2 +-
> arch/powerpc/xmon/xmon.c | 4 ++--
> 5 files changed, 22 insertions(+), 16 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/inst.h
> b/arch/powerpc/include/asm/inst.h
> index 78eb1481f1f6..54ee46b0a7c9 100644
> --- a/arch/powerpc/include/asm/inst.h
> +++ b/arch/powerpc/include/asm/inst.h
> @@ -23,4 +23,9 @@ static inline u32 ppc_inst_swab(u32 x)
> return ppc_inst(swab32(ppc_inst_val(x)));
> }
>
> +static inline bool ppc_inst_equal(u32 x, u32 y)
> +{
> + return x == y;
> +}
> +
> #endif /* _ASM_INST_H */
> diff --git a/arch/powerpc/kernel/trace/ftrace.c
> b/arch/powerpc/kernel/trace/ftrace.c
> index 62ff429bddc4..784b5746cc55 100644
> --- a/arch/powerpc/kernel/trace/ftrace.c
> +++ b/arch/powerpc/kernel/trace/ftrace.c
> @@ -72,7 +72,7 @@ ftrace_modify_code(unsigned long ip, unsigned int old,
> unsigned int new)
> return -EFAULT;
>
> /* Make sure it is what we expect it to be */
> - if (replaced != old) {
> + if (!ppc_inst_equal(replaced, old)) {
> pr_err("%p: replaced (%#x) != old (%#x)",
> (void *)ip, ppc_inst_val(replaced), ppc_inst_val(old));
> return -EINVAL;
> @@ -170,7 +170,8 @@ __ftrace_make_nop(struct module *mod,
> }
>
> /* We expect either a mflr r0, or a std r0, LRSAVE(r1) */
> - if (op != ppc_inst(PPC_INST_MFLR) && op != ppc_inst(PPC_INST_STD_LR)) {
> + if (!ppc_inst_equal(op, ppc_inst(PPC_INST_MFLR)) &&
> + !ppc_inst_equal(op, ppc_inst(PPC_INST_STD_LR))) {
> pr_err("Unexpected instruction %08x around bl _mcount\n",
> ppc_inst_val(op));
> return -EINVAL;
> }
> @@ -200,7 +201,7 @@ __ftrace_make_nop(struct module *mod,
> return -EFAULT;
> }
>
> - if (op != ppc_inst(PPC_INST_LD_TOC)) {
> + if (!ppc_inst_equal(op, ppc_inst(PPC_INST_LD_TOC))) {
> pr_err("Expected %08x found %08x\n", PPC_INST_LD_TOC,
> ppc_inst_val(op));
> return -EINVAL;
> }
> @@ -497,7 +498,7 @@ expected_nop_sequence(void *ip, unsigned int op0,
> unsigned int op1)
>* The load offset is different depending on the ABI. For simplicity
>* just mask it out when doing the compare.
>*/
> - if ((op0 != ppc_inst(0x4808)) || (ppc_inst_val(op1) & 0x)
> != 0xe841)
> + if ((!ppc_inst_equal(op0), ppc_inst(0x4808)) || (ppc_inst_val(op1)
> & 0x) != 0xe841)
> return 0;
> return 1;
> }
> @@ -506,7 +507,7 @@ static int
> expected_nop_sequence(void *ip, unsigned int op0, unsigned int op1)
> {
> /* look for patched "NOP" on ppc64 with -mprofile-kernel */
> - if (op0 != ppc_inst(PPC_INST_NOP))
> + if (!ppc_inst_equal(op0, ppc_inst(PPC_INST_NOP)))
> return 0;
> return 1;
> }
> @@ -589,7 +590,7 @@ __ftrace_make_call(struct dyn_ftrace *rec, unsigned long
> addr)
> return -EFAULT;
>
> /* It should be pointing to a nop */
> - if (op != ppc_inst(PPC_INST_NOP)) {
> + if (!ppc_inst_equal(op, ppc_inst(PPC_INST_NOP))) {
> pr_err("Expected NOP but have %x\n", op);
> return -EINVAL;
> }
> @@ -646,7 +647,7 @@ static int __ftrace_make_call_kernel(struct dyn_ftrace
> *rec, unsigned long addr)
> return -EFAULT;
> }
>
> - if (op != ppc_inst(PPC_INST_NOP)) {
> + if (!ppc_inst_equal(op, ppc_inst(PPC_INST_NOP))) {
> pr_err("Unexpected call sequence at %p: %x\n", ip,
> ppc_inst_val(op));
> return -EINVAL;
> }
> diff --git a/arch/powerpc/lib/code-patching.c b/arch/powerpc/lib/code-
> patching.c
> index 3f88d2a4400c..33654c6334a9 100644
> --- a/arch/powerpc/lib/code-patching.c
> +++ b/arch/powerpc/lib/code-patching.c
> @@ -478,7 +478,7 @@ static void __init test_branch_iform(void)
> /* Check flags are masked correctly */
> err = create_branch(, , addr, 0xFFFC);
> check(instr_is_branch_to_addr(, addr));
Re: [PATCH v5 05/21] powerpc: Use a function for getting the instruction op code
On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> In preparation for using a data type for instructions that can not be
> directly used with the '>>' operator use a function for getting the op
> code of an instruction.
vecemu.c and sstep.c will need ppc_inst_opcode().
-- Bala
>
> Signed-off-by: Jordan Niethe
> ---
> v4: New to series
> ---
> arch/powerpc/include/asm/inst.h | 5 +
> arch/powerpc/kernel/align.c | 2 +-
> arch/powerpc/lib/code-patching.c | 4 ++--
> 3 files changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/inst.h
> b/arch/powerpc/include/asm/inst.h
> index 5298ba33b6e5..93959016fe4b 100644
> --- a/arch/powerpc/include/asm/inst.h
> +++ b/arch/powerpc/include/asm/inst.h
> @@ -8,4 +8,9 @@
>
> #define ppc_inst(x) (x)
>
> +static inline int ppc_inst_opcode(u32 x)
> +{
> + return x >> 26;
> +}
> +
> #endif /* _ASM_INST_H */
> diff --git a/arch/powerpc/kernel/align.c b/arch/powerpc/kernel/align.c
> index 86e9bf62f18c..691013aa9f3c 100644
> --- a/arch/powerpc/kernel/align.c
> +++ b/arch/powerpc/kernel/align.c
> @@ -314,7 +314,7 @@ int fix_alignment(struct pt_regs *regs)
> }
>
> #ifdef CONFIG_SPE
> - if ((instr >> 26) == 0x4) {
> + if (ppc_inst_opcode(instr) == 0x4) {
> int reg = (instr >> 21) & 0x1f;
> PPC_WARN_ALIGNMENT(spe, regs);
> return emulate_spe(regs, reg, instr);
> diff --git a/arch/powerpc/lib/code-patching.c b/arch/powerpc/lib/code-
> patching.c
> index fdf0d6ea3575..099a515202aa 100644
> --- a/arch/powerpc/lib/code-patching.c
> +++ b/arch/powerpc/lib/code-patching.c
> @@ -231,7 +231,7 @@ bool is_offset_in_branch_range(long offset)
> */
> bool is_conditional_branch(unsigned int instr)
> {
> - unsigned int opcode = instr >> 26;
> + unsigned int opcode = ppc_inst_opcode(instr);
>
> if (opcode == 16) /* bc, bca, bcl, bcla */
> return true;
> @@ -289,7 +289,7 @@ int create_cond_branch(unsigned int *instr, const
> unsigned int *addr,
>
> static unsigned int branch_opcode(unsigned int instr)
> {
> - return (instr >> 26) & 0x3F;
> + return ppc_inst_opcode(instr) & 0x3F;
> }
>
> static int instr_is_branch_iform(unsigned int instr)
Re: [PATCH v5 03/21] powerpc: Change calling convention for create_branch() et. al.
On Tue, 2020-04-07 at 16:35 +1000, Jordan Niethe wrote: > On Tue, Apr 7, 2020 at 4:10 PM Balamuruhan S wrote: > > On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote: > > > create_branch(), create_cond_branch() and translate_branch() return the > > > instruction that they create, or return 0 to signal an error. Seperate > > > > s/seperate/separate > thanks. > > > these concerns in preparation for an instruction type that is not just > > > an unsigned int. Fill the created instruction to a pointer passed as > > > the first parameter to the function and use a non-zero return value to > > > signify an error. > > > > > > Signed-off-by: Jordan Niethe > > > --- > > > v5: New to series > > > --- > > > arch/powerpc/include/asm/code-patching.h | 12 +- > > > arch/powerpc/kernel/optprobes.c | 24 ++-- > > > arch/powerpc/kernel/setup_32.c | 2 +- > > > arch/powerpc/kernel/trace/ftrace.c | 24 ++-- > > > arch/powerpc/lib/code-patching.c | 133 +-- > > > arch/powerpc/lib/feature-fixups.c| 5 +- > > > 6 files changed, 117 insertions(+), 83 deletions(-) > > > > > > diff --git a/arch/powerpc/include/asm/code-patching.h > > > b/arch/powerpc/include/asm/code-patching.h > > > index 898b54262881..351dda7215b6 100644 > > > --- a/arch/powerpc/include/asm/code-patching.h > > > +++ b/arch/powerpc/include/asm/code-patching.h > > > @@ -22,10 +22,10 @@ > > > #define BRANCH_ABSOLUTE 0x2 > > > > > > bool is_offset_in_branch_range(long offset); > > > -unsigned int create_branch(const unsigned int *addr, > > > -unsigned long target, int flags); > > > -unsigned int create_cond_branch(const unsigned int *addr, > > > - unsigned long target, int flags); > > > +int create_branch(unsigned int *instr, const unsigned int *addr, > > > + unsigned long target, int flags); > > > +int create_cond_branch(unsigned int *instr, const unsigned int *addr, > > > +unsigned long target, int flags); > > > int patch_branch(unsigned int *addr, unsigned long target, int flags); > > > int patch_instruction(unsigned int *addr, unsigned int instr); > > > int raw_patch_instruction(unsigned int *addr, unsigned int instr); > > > @@ -60,8 +60,8 @@ int instr_is_relative_branch(unsigned int instr); > > > int instr_is_relative_link_branch(unsigned int instr); > > > int instr_is_branch_to_addr(const unsigned int *instr, unsigned long > > > addr); > > > unsigned long branch_target(const unsigned int *instr); > > > -unsigned int translate_branch(const unsigned int *dest, > > > - const unsigned int *src); > > > +int translate_branch(unsigned int *instr, const unsigned int *dest, > > > + const unsigned int *src); > > > extern bool is_conditional_branch(unsigned int instr); > > > #ifdef CONFIG_PPC_BOOK3E_64 > > > void __patch_exception(int exc, unsigned long addr); > > > diff --git a/arch/powerpc/kernel/optprobes.c > > > b/arch/powerpc/kernel/optprobes.c > > > index 024f7aad1952..445b3dad82dc 100644 > > > --- a/arch/powerpc/kernel/optprobes.c > > > +++ b/arch/powerpc/kernel/optprobes.c > > > @@ -251,15 +251,17 @@ int arch_prepare_optimized_kprobe(struct > > > optimized_kprobe *op, struct kprobe *p) > > > goto error; > > > } > > > > > > - branch_op_callback = create_branch((unsigned int *)buff + > > > TMPL_CALL_HDLR_IDX, > > > - (unsigned long)op_callback_addr, > > > - BRANCH_SET_LINK); > > > + rc = create_branch(_op_callback, > > > +(unsigned int *)buff + TMPL_CALL_HDLR_IDX, > > > +(unsigned long)op_callback_addr, > > > +BRANCH_SET_LINK); > > > > > > - branch_emulate_step = create_branch((unsigned int *)buff + > > > TMPL_EMULATE_IDX, > > > - (unsigned long)emulate_step_addr, > > > - BRANCH_SET_LINK); > > > + rc |= create_branch(_emulate_step, > > > + (unsigned int *)buff + TMPL_EMULATE_IDX, > > > + (unsigned long)emulate_step_addr, &g
Re: [PATCH v5 02/21] powerpc/xmon: Move out-of-line instructions to text section
On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> To execute an instruction out of line after a breakpoint, the NIP is set
> to the address of struct bpt::instr. Here a copy of the instruction that
> was replaced with a breakpoint is kept, along with a trap so normal flow
> can be resumed after XOLing. The struct bpt's are located within the
> data section. This is problematic as the data section may be marked as
> no execute.
>
> Instead of each struct bpt holding the instructions to be XOL'd, make a
> new array, bpt_table[], with enough space to hold instructions for the
> number of supported breakpoints. Place this array in the text section.
> Make struct bpt::instr a pointer to the instructions in bpt_table[]
> associated with that breakpoint. This association is a simple mapping:
> bpts[n] -> bpt_table[n * words per breakpoint]. Currently we only need
> the copied instruction followed by a trap, so 2 words per breakpoint.
we do 2 things here and we discussed to split it into 2 commits, may be
it is up to your thoughts and leave it to you. But otherwise rest looks
good to me.
-- Bala
>
> Signed-off-by: Jordan Niethe
> ---
> v4: New to series
> v5: - Do not use __section(), use a .space directive in .S file
> - Simplify in_breakpoint_table() calculation
> - Define BPT_SIZE
> ---
> arch/powerpc/xmon/Makefile| 2 +-
> arch/powerpc/xmon/xmon.c | 23 +--
> arch/powerpc/xmon/xmon_bpts.S | 8
> arch/powerpc/xmon/xmon_bpts.h | 8
> 4 files changed, 30 insertions(+), 11 deletions(-)
> create mode 100644 arch/powerpc/xmon/xmon_bpts.S
> create mode 100644 arch/powerpc/xmon/xmon_bpts.h
>
> diff --git a/arch/powerpc/xmon/Makefile b/arch/powerpc/xmon/Makefile
> index c3842dbeb1b7..515a13ea6f28 100644
> --- a/arch/powerpc/xmon/Makefile
> +++ b/arch/powerpc/xmon/Makefile
> @@ -21,7 +21,7 @@ endif
>
> ccflags-$(CONFIG_PPC64) := $(NO_MINIMAL_TOC)
>
> -obj-y+= xmon.o nonstdio.o spr_access.o
> +obj-y+= xmon.o nonstdio.o spr_access.o xmon_bpts.o
>
> ifdef CONFIG_XMON_DISASSEMBLY
> obj-y+= ppc-dis.o ppc-opc.o
> diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
> index 02e3bd62cab4..049375206510 100644
> --- a/arch/powerpc/xmon/xmon.c
> +++ b/arch/powerpc/xmon/xmon.c
> @@ -62,6 +62,7 @@
>
> #include "nonstdio.h"
> #include "dis-asm.h"
> +#include "xmon_bpts.h"
>
> #ifdef CONFIG_SMP
> static cpumask_t cpus_in_xmon = CPU_MASK_NONE;
> @@ -97,7 +98,7 @@ static long *xmon_fault_jmp[NR_CPUS];
> /* Breakpoint stuff */
> struct bpt {
> unsigned long address;
> - unsigned intinstr[2];
> + unsigned int*instr;
> atomic_tref_count;
> int enabled;
> unsigned long pad;
> @@ -108,7 +109,6 @@ struct bpt {
> #define BP_TRAP 2
> #define BP_DABR 4
>
> -#define NBPTS256
> static struct bpt bpts[NBPTS];
> static struct bpt dabr;
> static struct bpt *iabr;
> @@ -116,6 +116,10 @@ static unsigned bpinstr = 0x7fe8;/* trap */
>
> #define BP_NUM(bp) ((bp) - bpts + 1)
>
> +#define BPT_SIZE (sizeof(unsigned int) * 2)
> +#define BPT_WORDS(BPT_SIZE / sizeof(unsigned int))
> +extern unsigned int bpt_table[NBPTS * BPT_WORDS];
> +
> /* Prototypes */
> static int cmds(struct pt_regs *);
> static int mread(unsigned long, void *, int);
> @@ -853,15 +857,13 @@ static struct bpt *in_breakpoint_table(unsigned long
> nip, unsigned long *offp)
> {
> unsigned long off;
>
> - off = nip - (unsigned long) bpts;
> - if (off >= sizeof(bpts))
> + off = nip - (unsigned long) bpt_table;
> + if (off >= sizeof(bpt_table))
> return NULL;
> - off %= sizeof(struct bpt);
> - if (off != offsetof(struct bpt, instr[0])
> - && off != offsetof(struct bpt, instr[1]))
> + *offp = off % BPT_SIZE;
> + if (*offp != 0 && *offp != 4)
> return NULL;
> - *offp = off - offsetof(struct bpt, instr[0]);
> - return (struct bpt *) (nip - off);
> + return bpts + (off / BPT_SIZE);
> }
>
> static struct bpt *new_breakpoint(unsigned long a)
> @@ -876,7 +878,8 @@ static struct bpt *new_breakpoint(unsigned long a)
> for (bp = bpts; bp < [NBPTS]; ++bp) {
> if (!bp->enabled && atomic_read(>ref_count) == 0) {
> bp->address = a;
> - patch_instruction(>instr[1], bpinstr);
> + bp->instr = bpt_table + ((bp - bpts) * BPT_WORDS);
> + patch_instruction(bp->instr + 1, bpinstr);
> return bp;
> }
> }
> diff --git a/arch/powerpc/xmon/xmon_bpts.S b/arch/powerpc/xmon/xmon_bpts.S
> new file mode 100644
> index ..ebb2dbc70ca8
> --- /dev/null
> +++ b/arch/powerpc/xmon/xmon_bpts.S
> @@ -0,0 +1,8 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +#include
> +#include
>
Re: [PATCH v5 04/21] powerpc: Use a macro for creating instructions from u32s
On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> In preparation for instructions having a more complex data type start
> using a macro, ppc_inst(), for making an instruction out of a u32. A
> macro is used so that instructions can be used as initializer elements.
> Currently this does nothing, but it will allow for creating a data type
> that can represent prefixed instructions.
>
> Signed-off-by: Jordan Niethe
> ---
> v4: New to series
> v5: - Rename PPC_INST() -> ppc_inst().
> - Use on epapr_paravirt.c, kgdb.c
> ---
> arch/powerpc/include/asm/code-patching.h | 3 +-
> arch/powerpc/include/asm/inst.h | 11 +
> arch/powerpc/kernel/align.c | 1 +
> arch/powerpc/kernel/epapr_paravirt.c | 5 ++-
> arch/powerpc/kernel/hw_breakpoint.c | 3 +-
> arch/powerpc/kernel/jump_label.c | 3 +-
> arch/powerpc/kernel/kgdb.c | 5 ++-
> arch/powerpc/kernel/kprobes.c| 5 ++-
> arch/powerpc/kernel/module_64.c | 3 +-
> arch/powerpc/kernel/optprobes.c | 31 ++---
> arch/powerpc/kernel/security.c | 9 ++--
> arch/powerpc/kernel/trace/ftrace.c | 25 ++-
> arch/powerpc/kernel/uprobes.c| 1 +
> arch/powerpc/kvm/emulate_loadstore.c | 2 +-
> arch/powerpc/lib/code-patching.c | 57
> arch/powerpc/lib/feature-fixups.c| 39
> arch/powerpc/lib/test_emulate_step.c | 39
> arch/powerpc/xmon/xmon.c | 7 +--
> 18 files changed, 138 insertions(+), 111 deletions(-)
> create mode 100644 arch/powerpc/include/asm/inst.h
>
> diff --git a/arch/powerpc/include/asm/code-patching.h
> b/arch/powerpc/include/asm/code-patching.h
> index 351dda7215b6..48e021957ee5 100644
> --- a/arch/powerpc/include/asm/code-patching.h
> +++ b/arch/powerpc/include/asm/code-patching.h
> @@ -11,6 +11,7 @@
> #include
> #include
> #include
> +#include
>
> /* Flags for create_branch:
> * "b" == create_branch(addr, target, 0);
> @@ -48,7 +49,7 @@ static inline int patch_branch_site(s32 *site, unsigned
> long target, int flags)
> static inline int modify_instruction(unsigned int *addr, unsigned int clr,
>unsigned int set)
> {
> - return patch_instruction(addr, (*addr & ~clr) | set);
> + return patch_instruction(addr, ppc_inst((*addr & ~clr) | set));
> }
>
> static inline int modify_instruction_site(s32 *site, unsigned int clr,
> unsigned int set)
> diff --git a/arch/powerpc/include/asm/inst.h
> b/arch/powerpc/include/asm/inst.h
> new file mode 100644
> index ..5298ba33b6e5
> --- /dev/null
> +++ b/arch/powerpc/include/asm/inst.h
> @@ -0,0 +1,11 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +#ifndef _ASM_INST_H
> +#define _ASM_INST_H
> +
> +/*
> + * Instruction data type for POWER
> + */
> +
> +#define ppc_inst(x) (x)
> +
> +#endif /* _ASM_INST_H */
> diff --git a/arch/powerpc/kernel/align.c b/arch/powerpc/kernel/align.c
> index 92045ed64976..86e9bf62f18c 100644
> --- a/arch/powerpc/kernel/align.c
> +++ b/arch/powerpc/kernel/align.c
> @@ -24,6 +24,7 @@
> #include
> #include
> #include
> +#include
>
> struct aligninfo {
> unsigned char len;
> diff --git a/arch/powerpc/kernel/epapr_paravirt.c
> b/arch/powerpc/kernel/epapr_paravirt.c
> index 9d32158ce36f..c53e863fb484 100644
> --- a/arch/powerpc/kernel/epapr_paravirt.c
> +++ b/arch/powerpc/kernel/epapr_paravirt.c
> @@ -11,6 +11,7 @@
> #include
> #include
> #include
> +#include
>
> #if !defined(CONFIG_64BIT) || defined(CONFIG_PPC_BOOK3E_64)
> extern void epapr_ev_idle(void);
> @@ -37,9 +38,9 @@ static int __init early_init_dt_scan_epapr(unsigned long
> node,
>
> for (i = 0; i < (len / 4); i++) {
> u32 inst = be32_to_cpu(insts[i]);
> - patch_instruction(epapr_hypercall_start + i, inst);
> + patch_instruction(epapr_hypercall_start + i, ppc_inst(inst));
> #if !defined(CONFIG_64BIT) || defined(CONFIG_PPC_BOOK3E_64)
> - patch_instruction(epapr_ev_idle_start + i, inst);
> + patch_instruction(epapr_ev_idle_start + i, ppc_inst(inst));
can we do it once while assigning inst ?
u32 inst = ppc_inst(be32_to_cpu(insts[i]));
-- Bala
> #endif
> }
>
> diff --git a/arch/powerpc/kernel/hw_breakpoint.c
> b/arch/powerpc/kernel/hw_breakpoint.c
> index 2462cd7c565c..79f51f182a83 100644
> --- a/arch/powerpc/kernel/hw_breakpoint.c
> +++ b/arch/powerpc/kernel/hw_breakpoint.c
> @@ -24,6 +24,7 @@
> #include
> #include
> #include
> +#include
> #include
>
> /*
> @@ -243,7 +244,7 @@ dar_range_overlaps(unsigned long dar, int size, struct
> arch_hw_breakpoint *info)
> static bool stepping_handler(struct pt_regs *regs, struct perf_event *bp,
>struct arch_hw_breakpoint *info)
> {
> - unsigned int instr = 0;
> + unsigned int instr = ppc_inst(0);
> int ret, type,
Re: [PATCH v5 03/21] powerpc: Change calling convention for create_branch() et. al.
On Mon, 2020-04-06 at 18:09 +1000, Jordan Niethe wrote:
> create_branch(), create_cond_branch() and translate_branch() return the
> instruction that they create, or return 0 to signal an error. Seperate
s/seperate/separate
> these concerns in preparation for an instruction type that is not just
> an unsigned int. Fill the created instruction to a pointer passed as
> the first parameter to the function and use a non-zero return value to
> signify an error.
>
> Signed-off-by: Jordan Niethe
> ---
> v5: New to series
> ---
> arch/powerpc/include/asm/code-patching.h | 12 +-
> arch/powerpc/kernel/optprobes.c | 24 ++--
> arch/powerpc/kernel/setup_32.c | 2 +-
> arch/powerpc/kernel/trace/ftrace.c | 24 ++--
> arch/powerpc/lib/code-patching.c | 133 +--
> arch/powerpc/lib/feature-fixups.c| 5 +-
> 6 files changed, 117 insertions(+), 83 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/code-patching.h
> b/arch/powerpc/include/asm/code-patching.h
> index 898b54262881..351dda7215b6 100644
> --- a/arch/powerpc/include/asm/code-patching.h
> +++ b/arch/powerpc/include/asm/code-patching.h
> @@ -22,10 +22,10 @@
> #define BRANCH_ABSOLUTE 0x2
>
> bool is_offset_in_branch_range(long offset);
> -unsigned int create_branch(const unsigned int *addr,
> -unsigned long target, int flags);
> -unsigned int create_cond_branch(const unsigned int *addr,
> - unsigned long target, int flags);
> +int create_branch(unsigned int *instr, const unsigned int *addr,
> + unsigned long target, int flags);
> +int create_cond_branch(unsigned int *instr, const unsigned int *addr,
> +unsigned long target, int flags);
> int patch_branch(unsigned int *addr, unsigned long target, int flags);
> int patch_instruction(unsigned int *addr, unsigned int instr);
> int raw_patch_instruction(unsigned int *addr, unsigned int instr);
> @@ -60,8 +60,8 @@ int instr_is_relative_branch(unsigned int instr);
> int instr_is_relative_link_branch(unsigned int instr);
> int instr_is_branch_to_addr(const unsigned int *instr, unsigned long addr);
> unsigned long branch_target(const unsigned int *instr);
> -unsigned int translate_branch(const unsigned int *dest,
> - const unsigned int *src);
> +int translate_branch(unsigned int *instr, const unsigned int *dest,
> + const unsigned int *src);
> extern bool is_conditional_branch(unsigned int instr);
> #ifdef CONFIG_PPC_BOOK3E_64
> void __patch_exception(int exc, unsigned long addr);
> diff --git a/arch/powerpc/kernel/optprobes.c
> b/arch/powerpc/kernel/optprobes.c
> index 024f7aad1952..445b3dad82dc 100644
> --- a/arch/powerpc/kernel/optprobes.c
> +++ b/arch/powerpc/kernel/optprobes.c
> @@ -251,15 +251,17 @@ int arch_prepare_optimized_kprobe(struct
> optimized_kprobe *op, struct kprobe *p)
> goto error;
> }
>
> - branch_op_callback = create_branch((unsigned int *)buff +
> TMPL_CALL_HDLR_IDX,
> - (unsigned long)op_callback_addr,
> - BRANCH_SET_LINK);
> + rc = create_branch(_op_callback,
> +(unsigned int *)buff + TMPL_CALL_HDLR_IDX,
> +(unsigned long)op_callback_addr,
> +BRANCH_SET_LINK);
>
> - branch_emulate_step = create_branch((unsigned int *)buff +
> TMPL_EMULATE_IDX,
> - (unsigned long)emulate_step_addr,
> - BRANCH_SET_LINK);
> + rc |= create_branch(_emulate_step,
> + (unsigned int *)buff + TMPL_EMULATE_IDX,
> + (unsigned long)emulate_step_addr,
> + BRANCH_SET_LINK);
>
> - if (!branch_op_callback || !branch_emulate_step)
> + if (rc)
> goto error;
>
> patch_instruction(buff + TMPL_CALL_HDLR_IDX, branch_op_callback);
> @@ -305,6 +307,7 @@ int arch_check_optimized_kprobe(struct optimized_kprobe
> *op)
>
> void arch_optimize_kprobes(struct list_head *oplist)
> {
> + unsigned int instr;
> struct optimized_kprobe *op;
> struct optimized_kprobe *tmp;
>
> @@ -315,9 +318,10 @@ void arch_optimize_kprobes(struct list_head *oplist)
>*/
> memcpy(op->optinsn.copied_insn, op->kp.addr,
> RELATIVEJUMP_SIZE);
> - patch_instruction(op->kp.addr,
> - create_branch((unsigned int *)op->kp.addr,
> - (unsigned long)op->optinsn.insn, 0));
> + create_branch(,
> + (unsigned int *)op->kp.addr,
> + (unsigned long)op->optinsn.insn, 0);
> + patch_instruction(op->kp.addr, instr);
> list_del_init(>list);
> }
> }
> diff --git a/arch/powerpc/kernel/setup_32.c
Re: [RFC PATCH 3/4] powerpc ppc-opcode: move ppc instuction encoding from test_emulate_step
On Thu, 2020-04-02 at 12:34 +0530, Naveen N. Rao wrote:
> Michael Ellerman wrote:
> > "Naveen N. Rao" writes:
> > > Balamuruhan S wrote:
> > > > Few ppc instructions are encoded in test_emulate_step.c, consolidate
> > > > them to
> > > > ppc-opcode.h, fix redefintion errors in bpf_jit caused due to this
> > > > consolidation.
> > > > Reuse the macros from ppc-opcode.h
> > ...
> > > > diff --git a/arch/powerpc/net/bpf_jit32.h
> > > > b/arch/powerpc/net/bpf_jit32.h
> > > > index 4ec2a9f14f84..8a9f16a7262e 100644
> > > > --- a/arch/powerpc/net/bpf_jit32.h
> > > > +++ b/arch/powerpc/net/bpf_jit32.h
> > > > @@ -76,13 +76,13 @@ DECLARE_LOAD_FUNC(sk_load_byte_msh);
> > > > else { PPC_ADDIS(r, base, IMM_HA(i));
> > > > \
> > > > PPC_LBZ(r, r, IMM_L(i)); } } while(0)
> > > >
> > > > -#define PPC_LD_OFFS(r, base, i) do { if ((i) < 32768) PPC_LD(r, base,
> > > > i); \
> > > > +#define _OFFS(r, base, i) do { if ((i) < 32768) EMIT(PPC_ENCODE_LD(r,
> > > > base, i)); \
> > > ^
> > > Should be PPC_LD_OFFS. For the next version, please also build ppc32 and
> > > booke codebase to confirm that your changes in those areas are fine.
> > >
> > > PPC_ENCODE_* also looks quite verbose, so perhaps PPC_ENC_* might be
> > > better. Otherwise, this patchset looks good to me and should help reuse
> > > some of those macros, especially from the eBPF codebase.
> > >
> > > Michael,
> > > Can you let us know if this looks ok to you? Based on your feedback, we
> > > will also update the eBPF codebase.
> >
> > I didn't really like the first patch which does the mass renaming. It
> > creates a huge amount of churn.
sorry for that.
> >
> > I think I'd be happier if this series just did what it needs, and then
> > maybe at the end there's a patch to update all the existing names, which
> > I may or may not take.
>
> Ok.
I will work on it.
>
> > As far as the naming, currently we have:
> >
> > PPC_INST_FOO - just the opcode
> >
> > PPC_FOO(x) - macro to encode the opcode with x and (usually) also emit a
> > .long and stringify.
> >
> > And you need an in-between that gives you the full instruction but
> > without the .long and stringify, right?
>
> Yes.
>
> > So how about PPC_RAW_FOO() for just the numeric value, without the .long
> > and stringify.
>
> Sure, thanks for the feedback -- that makes sense.
Thanks for the feedback.
>
> > We also seem to have a lot of PPC_INST_FOO's that are only ever used in
> > the PPC_INST macro. I'm inclined to fold those into the PPC_INST macro,
> > to avoid people accidentally using the PPC_INST version when they don't
> > mean to. But that's a separate issue.
>
> Good point -- I do see many uses of PPC_INST_FOO that can be replaced
> with PPC_RAW_FOO once we introduce that. We will take a stab at doing
> this cleanup as a separate patch at the end.
Will make the changes as suggested.
-- Bala
>
>
> Thanks,
> Naveen
>
[PATCH v4 3/3] powerpc test_emulate_step: add testcases for divde[.] and divdeu[.] instructions
add testcases for divde, divde., divdeu, divdeu. emulated
instructions to cover few scenarios,
* with same dividend and divisor to have undefine RT
for divdeu[.]
* with divide by zero to have undefine RT for both
divde[.] and divdeu[.]
* with negative dividend to cover -|divisor| < r <= 0 if
the dividend is negative for divde[.]
* normal case with proper dividend and divisor for both
divde[.] and divdeu[.]
Reviewed-by: Sandipan Das
Signed-off-by: Balamuruhan S
Acked-by: Naveen N. Rao
---
arch/powerpc/lib/test_emulate_step.c | 164 +++
1 file changed, 164 insertions(+)
diff --git a/arch/powerpc/lib/test_emulate_step.c
b/arch/powerpc/lib/test_emulate_step.c
index 53df4146dd32..eb1dea47a637 100644
--- a/arch/powerpc/lib/test_emulate_step.c
+++ b/arch/powerpc/lib/test_emulate_step.c
@@ -54,6 +54,14 @@
___PPC_RA(a) | ___PPC_RB(b))
#define TEST_ADDC_DOT(t, a, b) (PPC_INST_ADDC | ___PPC_RT(t) | \
___PPC_RA(a) | ___PPC_RB(b) | 0x1)
+#define TEST_DIVDE(t, a, b)(PPC_INST_DIVDE | ___PPC_RT(t) |\
+ ___PPC_RA(a) | ___PPC_RB(b))
+#define TEST_DIVDE_DOT(t, a, b)(PPC_INST_DIVDE | ___PPC_RT(t) |
\
+ ___PPC_RA(a) | ___PPC_RB(b) | 0x1)
+#define TEST_DIVDEU(t, a, b) (PPC_INST_DIVDEU | ___PPC_RT(t) | \
+ ___PPC_RA(a) | ___PPC_RB(b))
+#define TEST_DIVDEU_DOT(t, a, b)(PPC_INST_DIVDEU | ___PPC_RT(t) | \
+ ___PPC_RA(a) | ___PPC_RB(b) | 0x1)
#define MAX_SUBTESTS 16
@@ -838,6 +846,162 @@ static struct compute_test compute_tests[] = {
}
}
}
+ },
+ {
+ .mnemonic = "divde",
+ .subtests = {
+ {
+ .descr = "RA = LONG_MIN, RB = LONG_MIN",
+ .instr = TEST_DIVDE(20, 21, 22),
+ .regs = {
+ .gpr[21] = LONG_MIN,
+ .gpr[22] = LONG_MIN,
+ }
+ },
+ {
+ .descr = "RA = 1L, RB = 0",
+ .instr = TEST_DIVDE(20, 21, 22),
+ .flags = IGNORE_GPR(20),
+ .regs = {
+ .gpr[21] = 1L,
+ .gpr[22] = 0,
+ }
+ },
+ {
+ .descr = "RA = LONG_MIN, RB = LONG_MAX",
+ .instr = TEST_DIVDE(20, 21, 22),
+ .regs = {
+ .gpr[21] = LONG_MIN,
+ .gpr[22] = LONG_MAX,
+ }
+ }
+ }
+ },
+ {
+ .mnemonic = "divde.",
+ .subtests = {
+ {
+ .descr = "RA = LONG_MIN, RB = LONG_MIN",
+ .instr = TEST_DIVDE_DOT(20, 21, 22),
+ .regs = {
+ .gpr[21] = LONG_MIN,
+ .gpr[22] = LONG_MIN,
+ }
+ },
+ {
+ .descr = "RA = 1L, RB = 0",
+ .instr = TEST_DIVDE_DOT(20, 21, 22),
+ .flags = IGNORE_GPR(20),
+ .regs = {
+ .gpr[21] = 1L,
+ .gpr[22] = 0,
+ }
+ },
+ {
+ .descr = "RA = LONG_MIN, RB = LONG_MAX",
+ .instr = TEST_DIVDE_DOT(20, 21, 22),
+ .regs = {
+ .gpr[21] = LONG_MIN,
+ .gpr[22] = LONG_MAX,
+ }
+ }
+ }
+ },
+ {
+ .mnemonic = "divdeu",
+ .subtests = {
+ {
+ .descr = "RA = LONG_MIN, RB = LONG_MIN",
+ .instr = TEST_DIVDEU(20, 21, 22),
+ .flags = IGNORE_GPR(20),
+ .regs = {
+
[PATCH v4 2/3] powerpc sstep: add support for divde[.] and divdeu[.] instructions
This patch adds emulation support for divde, divdeu instructions, * Divide Doubleword Extended (divde[.]) * Divide Doubleword Extended Unsigned (divdeu[.]) Reviewed-by: Sandipan Das Signed-off-by: Balamuruhan S Acked-by: Naveen N. Rao --- arch/powerpc/lib/sstep.c | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c index 5f3a7bd9d90d..c9036a75730c 100644 --- a/arch/powerpc/lib/sstep.c +++ b/arch/powerpc/lib/sstep.c @@ -1736,7 +1736,18 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs, op->val = (int) regs->gpr[ra] / (int) regs->gpr[rb]; goto arith_done; - +#ifdef __powerpc64__ + case 425: /* divde[.] */ + asm volatile(PPC_DIVDE(%0, %1, %2) : + "=r" (op->val) : "r" (regs->gpr[ra]), + "r" (regs->gpr[rb])); + goto arith_done; + case 393: /* divdeu[.] */ + asm volatile(PPC_DIVDEU(%0, %1, %2) : + "=r" (op->val) : "r" (regs->gpr[ra]), + "r" (regs->gpr[rb])); + goto arith_done; +#endif case 755: /* darn */ if (!cpu_has_feature(CPU_FTR_ARCH_300)) return -1; -- 2.24.1
[PATCH v4 1/3] powerpc ppc-opcode: add divde and divdeu opcodes
include instruction opcodes for divde and divdeu as macros. Reviewed-by: Sandipan Das Signed-off-by: Balamuruhan S Acked-by: Naveen N. Rao --- arch/powerpc/include/asm/ppc-opcode.h | 8 1 file changed, 8 insertions(+) diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index c1df75edde44..9c9a604f30a6 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -339,6 +339,8 @@ #define PPC_INST_DIVWU 0x7c000396 #define PPC_INST_DIVD 0x7c0003d2 #define PPC_INST_DIVDU 0x7c000392 +#define PPC_INST_DIVDE 0x7c000352 +#define PPC_INST_DIVDEU0x7c000312 #define PPC_INST_RLWINM0x5400 #define PPC_INST_RLWINM_DOT0x5401 #define PPC_INST_RLWIMI0x5000 @@ -439,6 +441,12 @@ __PPC_RA(a) | __PPC_RB(b)) #definePPC_DCBZL(a, b) stringify_in_c(.long PPC_INST_DCBZL | \ __PPC_RA(a) | __PPC_RB(b)) +#define PPC_DIVDE(t, a, b) stringify_in_c(.long PPC_INST_DIVDE | \ + ___PPC_RT(t) | ___PPC_RA(a) | \ + ___PPC_RB(b)) +#define PPC_DIVDEU(t, a, b)stringify_in_c(.long PPC_INST_DIVDEU| \ + ___PPC_RT(t) | ___PPC_RA(a) | \ + ___PPC_RB(b)) #define PPC_LQARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LQARX | \ ___PPC_RT(t) | ___PPC_RA(a) | \ ___PPC_RB(b) | __PPC_EH(eh)) -- 2.24.1
[PATCH v4 0/3] Add support for divde[.] and divdeu[.] instruction emulation
Hi All, This patchset adds support to emulate divde, divde., divdeu and divdeu. instructions and testcases for it. Changes in v4: - Fix review comments from Naveen, * replace TEST_DIVDEU() instead of wrongly used TEST_DIVDEU_DOT() in divdeu testcase. * Include `acked-by` tag from Naveen for the series. * Rebase it on latest mpe's merge tree. Changes in v3: - * Fix suggestion from Sandipan to remove `PPC_INST_DIVDE_DOT` and `PPC_INST_DIVDEU_DOT` opcode macros defined in ppc-opcode.h, reuse `PPC_INST_DIVDE` and `PPC_INST_DIVDEU` in test_emulate_step.c to derive them respectively. Changes in v2: - * Fix review comments from Paul to make divde_dot and divdeu_dot simple by using divde and divdeu, then goto `arith_done` instead of `compute_done`. * Include `Reviewed-by` tag from Sandipan Das. * Rebase with recent mpe's merge tree. I would request for your review and suggestions for making it better. Boot Log: :: :: :: :: [2.777518] emulate_step_test: divde : RA = LONG_MIN, RB = LONG_MIN PASS [2.777882] emulate_step_test: divde : RA = 1L, RB = 0 PASS [2.778432] emulate_step_test: divde : RA = LONG_MIN, RB = LONG_MAX PASS [2.778880] emulate_step_test: divde. : RA = LONG_MIN, RB = LONG_MIN PASS [2.780172] emulate_step_test: divde. : RA = 1L, RB = 0 PASS [2.780582] emulate_step_test: divde. : RA = LONG_MIN, RB = LONG_MAX PASS [2.780983] emulate_step_test: divdeu : RA = LONG_MIN, RB = LONG_MIN PASS [2.781276] emulate_step_test: divdeu : RA = 1L, RB = 0 PASS [2.781579] emulate_step_test: divdeu : RA = LONG_MIN, RB = LONG_MAX PASS [2.781820] emulate_step_test: divdeu : RA = LONG_MAX - 1, RB = LONG_MAX PASS [2.782056] emulate_step_test: divdeu : RA = LONG_MIN + 1, RB = LONG_MIN PASS [2.782296] emulate_step_test: divdeu.: RA = LONG_MIN, RB = LONG_MIN PASS [2.782556] emulate_step_test: divdeu.: RA = 1L, RB = 0 PASS [2.783502] emulate_step_test: divdeu.: RA = LONG_MIN, RB = LONG_MAX PASS [2.783748] emulate_step_test: divdeu.: RA = LONG_MAX - 1, RB = LONG_MAX PASS [2.783973] emulate_step_test: divdeu.: RA = LONG_MIN + 1, RB = LONG_MIN PASS [2.789617] registered taskstats version 1 [2.794779] printk: console [netcon0] enabled [2.794931] netconsole: network logging started [2.795327] hctosys: unable to open rtc device (rtc0) [2.953449] Freeing unused kernel memory: 5120K [2.953639] This architecture does not have kernel memory protection. [2.953918] Run /init as init process [3.173573] mount (54) used greatest stack depth: 12576 bytes left [3.252465] mount (55) used greatest stack depth: 12544 bytes left Welcome to Buildroot buildroot login: Balamuruhan S (3): powerpc ppc-opcode: add divde and divdeu opcodes powerpc sstep: add support for divde[.] and divdeu[.] instructions powerpc test_emulate_step: add testcases for divde[.] and divdeu[.] instructions arch/powerpc/include/asm/ppc-opcode.h | 8 ++ arch/powerpc/lib/sstep.c | 13 +- arch/powerpc/lib/test_emulate_step.c | 164 ++ 3 files changed, 184 insertions(+), 1 deletion(-) base-commit: 9c17a47d827c00401c2ff2ba71d7ecf08ed5b677 -- 2.24.1
Re: [PATCH v3 3/3] powerpc test_emulate_step: add testcases for divde[.] and divdeu[.] instructions
On Wed, 2020-04-01 at 16:26 +0530, Naveen N. Rao wrote:
> Balamuruhan S wrote:
> > add testcases for divde, divde., divdeu, divdeu. emulated
> > instructions to cover few scenarios,
> > * with same dividend and divisor to have undefine RT
> > for divdeu[.]
> > * with divide by zero to have undefine RT for both
> > divde[.] and divdeu[.]
> > * with negative dividend to cover -|divisor| < r <= 0 if
> > the dividend is negative for divde[.]
> > * normal case with proper dividend and divisor for both
> > divde[.] and divdeu[.]
> >
> > Reviewed-by: Sandipan Das
> > Signed-off-by: Balamuruhan S
> > ---
> > arch/powerpc/lib/test_emulate_step.c | 164
> > +++
> > 1 file changed, 164 insertions(+)
> >
> > diff --git a/arch/powerpc/lib/test_emulate_step.c
> > b/arch/powerpc/lib/test_emulate_step.c
> > index 42347067739c..ffeb9b68a31d 100644
> > --- a/arch/powerpc/lib/test_emulate_step.c
> > +++ b/arch/powerpc/lib/test_emulate_step.c
> > @@ -53,6 +53,14 @@
> > ___PPC_RA(a) | ___PPC_RB(b))
> > #define TEST_ADDC_DOT(t, a, b) (PPC_INST_ADDC | ___PPC_RT(t) |
> > \
> > ___PPC_RA(a) | ___PPC_RB(b) | 0x1)
> > +#define TEST_DIVDE(t, a, b)(PPC_INST_DIVDE | ___PPC_RT(t) |
> > \
> > + ___PPC_RA(a) | ___PPC_RB(b))
> > +#define TEST_DIVDE_DOT(t, a, b)(PPC_INST_DIVDE | ___PPC_RT(t) |
> > \
> > + ___PPC_RA(a) | ___PPC_RB(b) | 0x1)
> > +#define TEST_DIVDEU(t, a, b) (PPC_INST_DIVDEU | ___PPC_RT(t) |
> > \
> > + ___PPC_RA(a) | ___PPC_RB(b))
> > +#define TEST_DIVDEU_DOT(t, a, b)(PPC_INST_DIVDEU | ___PPC_RT(t) | \
> > + ___PPC_RA(a) | ___PPC_RB(b) | 0x1)
> >
> > #define MAX_SUBTESTS 16
> >
> > @@ -837,6 +845,162 @@ static struct compute_test compute_tests[] = {
> > }
> > }
> > }
> > + },
> > + {
> > + .mnemonic = "divde",
> > + .subtests = {
> > + {
> > + .descr = "RA = LONG_MIN, RB = LONG_MIN",
> > + .instr = TEST_DIVDE(20, 21, 22),
> > + .regs = {
> > + .gpr[21] = LONG_MIN,
> > + .gpr[22] = LONG_MIN,
> > + }
> > + },
> > + {
> > + .descr = "RA = 1L, RB = 0",
> > + .instr = TEST_DIVDE(20, 21, 22),
> > + .flags = IGNORE_GPR(20),
> > + .regs = {
> > + .gpr[21] = 1L,
> > + .gpr[22] = 0,
> > + }
> > + },
> > + {
> > + .descr = "RA = LONG_MIN, RB = LONG_MAX",
> > + .instr = TEST_DIVDE(20, 21, 22),
> > + .regs = {
> > + .gpr[21] = LONG_MIN,
> > + .gpr[22] = LONG_MAX,
> > + }
> > + }
> > + }
> > + },
> > + {
> > + .mnemonic = "divde.",
> > + .subtests = {
> > + {
> > + .descr = "RA = LONG_MIN, RB = LONG_MIN",
> > + .instr = TEST_DIVDE_DOT(20, 21, 22),
> > + .regs = {
> > + .gpr[21] = LONG_MIN,
> > + .gpr[22] = LONG_MIN,
> > + }
> > + },
> > + {
> > + .descr = "RA = 1L, RB = 0",
> > + .instr = TEST_DIVDE_DOT(20, 21, 22),
> > + .flags = IGNORE_GPR(20),
> > + .regs = {
> > + .gpr[21] = 1L,
> > + .gpr[22] = 0,
> > + }
> > + },
Re: [PATCH v4 03/16] powerpc: Use a datatype for instructions
On Fri, 2020-03-20 at 16:17 +1100, Jordan Niethe wrote:
> Currently unsigned ints are used to represent instructions on powerpc.
> This has worked well as instructions have always been 4 byte words.
> However, a future ISA version will introduce some changes to
> instructions that mean this scheme will no longer work as well. This
> change is Prefixed Instructions. A prefixed instruction is made up of a
> word prefix followed by a word suffix to make an 8 byte double word
> instruction. No matter the endianess of the system the prefix always
> comes first. Prefixed instructions are only planned for powerpc64.
>
> Introduce a ppc_inst type to represent both prefixed and word
> instructions on powerpc64 while keeping it possible to exclusively have
> word instructions on powerpc32, A latter patch will expand the type to
> include prefixed instructions but for now just typedef it to a u32.
>
> Later patches will introduce helper functions and macros for
> manipulating the instructions so that powerpc64 and powerpc32 might
> maintain separate type definitions.
>
> Signed-off-by: Jordan Niethe
> ---
> arch/powerpc/include/asm/code-patching.h | 31 +--
> arch/powerpc/include/asm/inst.h | 53 +++
> arch/powerpc/include/asm/sstep.h | 5 +-
> arch/powerpc/kernel/align.c | 2 +-
> arch/powerpc/kernel/hw_breakpoint.c | 3 +-
> arch/powerpc/kernel/kprobes.c| 2 +-
> arch/powerpc/kernel/mce_power.c | 5 +-
> arch/powerpc/kernel/optprobes.c | 10 ++--
> arch/powerpc/kernel/trace/ftrace.c | 66
> arch/powerpc/kvm/emulate_loadstore.c | 1 +
> arch/powerpc/lib/code-patching.c | 54 +--
> arch/powerpc/lib/sstep.c | 4 +-
> arch/powerpc/lib/test_emulate_step.c | 9 ++--
> arch/powerpc/xmon/xmon.c | 12 ++---
> 14 files changed, 160 insertions(+), 97 deletions(-)
> create mode 100644 arch/powerpc/include/asm/inst.h
>
> diff --git a/arch/powerpc/include/asm/code-patching.h
> b/arch/powerpc/include/asm/code-patching.h
> index 898b54262881..cb5106f92d67 100644
> --- a/arch/powerpc/include/asm/code-patching.h
> +++ b/arch/powerpc/include/asm/code-patching.h
> @@ -11,6 +11,7 @@
> #include
> #include
> #include
> +#include
>
> /* Flags for create_branch:
> * "b" == create_branch(addr, target, 0);
> @@ -22,27 +23,27 @@
> #define BRANCH_ABSOLUTE 0x2
>
> bool is_offset_in_branch_range(long offset);
> -unsigned int create_branch(const unsigned int *addr,
> +ppc_inst create_branch(const ppc_inst *addr,
> unsigned long target, int flags);
> -unsigned int create_cond_branch(const unsigned int *addr,
> +unsigned int create_cond_branch(const ppc_inst *addr,
> unsigned long target, int flags);
> -int patch_branch(unsigned int *addr, unsigned long target, int flags);
> -int patch_instruction(unsigned int *addr, unsigned int instr);
> -int raw_patch_instruction(unsigned int *addr, unsigned int instr);
> +int patch_branch(ppc_inst *addr, unsigned long target, int flags);
> +int patch_instruction(ppc_inst *addr, ppc_inst instr);
we need to handle this change for its user in epapr_paravirt.c,
arch/powerpc/kernel/epapr_paravirt.c: In function 'early_init_dt_scan_epapr':
arch/powerpc/kernel/epapr_paravirt.c:40:48: error: incompatible type for
argument 2 of 'patch_instruction'
40 | patch_instruction(epapr_hypercall_start + i, inst);
|^~~~
||
|u32 {aka unsigned int}
In file included from arch/powerpc/kernel/epapr_paravirt.c:12:
./arch/powerpc/include/asm/code-patching.h:31:44: note: expected 'ppc_inst'
{aka 'struct ppc_inst'} but argument is of type 'u32' {aka 'unsigned int'}
31 | int patch_instruction(void *addr, ppc_inst instr);
| ~^
make[2]: *** [scripts/Makefile.build:268: arch/powerpc/kernel/epapr_paravirt.o]
Error 1
make[1]: *** [scripts/Makefile.build:505: arch/powerpc/kernel] Error 2
make: *** [Makefile:1683: arch/powerpc] Error 2
-- Bala
> +int raw_patch_instruction(ppc_inst *addr, ppc_inst instr);
>
> static inline unsigned long patch_site_addr(s32 *site)
> {
> return (unsigned long)site + *site;
> }
>
> -static inline int patch_instruction_site(s32 *site, unsigned int instr)
> +static inline int patch_instruction_site(s32 *site, ppc_inst instr)
> {
> - return patch_instruction((unsigned int *)patch_site_addr(site), instr);
> + return patch_instruction((ppc_inst *)patch_site_addr(site), instr);
> }
>
> static inline int patch_branch_site(s32 *site, unsigned long target, int
> flags)
> {
> - return patch_branch((unsigned int *)patch_site_addr(site), target,
> flags);
> + return patch_branch((ppc_inst
Re: [PATCH v5 03/13] powerpc/ptrace: drop unnecessary #ifdefs CONFIG_PPC64
On Fri, 2020-02-28 at 00:14 +, Christophe Leroy wrote:
> Drop a bunch of #ifdefs CONFIG_PPC64 that are not vital.
>
> Signed-off-by: Christophe Leroy
> ---
> arch/powerpc/include/asm/ptrace.h | 2 ++
> arch/powerpc/kernel/ptrace/ptrace.c | 18 +++---
> 2 files changed, 5 insertions(+), 15 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/ptrace.h
> b/arch/powerpc/include/asm/ptrace.h
> index ee3ada66deb5..8e1953d99353 100644
> --- a/arch/powerpc/include/asm/ptrace.h
> +++ b/arch/powerpc/include/asm/ptrace.h
> @@ -276,6 +276,8 @@ static inline unsigned long
> regs_get_kernel_stack_nth(struct pt_regs *regs,
> #endif /* __ASSEMBLY__ */
>
> #ifndef __powerpc64__
> +/* We need PT_SOFTE defined at all time to avoid #ifdefs */
> +#define PT_SOFTE PT_MQ
> #else /* __powerpc64__ */
> #define PT_FPSCR32 (PT_FPR0 + 2*32 + 1) /* each FP reg occupies 2 32-
> bit userspace slots */
> #define PT_VR0_32 164/* each Vector reg occupies 4 slots in 32-bit
> */
> diff --git a/arch/powerpc/kernel/ptrace/ptrace.c
> b/arch/powerpc/kernel/ptrace/ptrace.c
> index 7ed54dbb2d7e..3dd94c296ac7 100644
> --- a/arch/powerpc/kernel/ptrace/ptrace.c
> +++ b/arch/powerpc/kernel/ptrace/ptrace.c
> @@ -274,17 +274,15 @@ int ptrace_get_reg(struct task_struct *task, int regno,
> unsigned long *data)
> if (regno == PT_DSCR)
> return get_user_dscr(task, data);
>
> -#ifdef CONFIG_PPC64
> /*
>* softe copies paca->irq_soft_mask variable state. Since irq_soft_mask
> is
>* no more used as a flag, lets force usr to alway see the softe value
> as 1
>* which means interrupts are not soft disabled.
>*/
> - if (regno == PT_SOFTE) {
> + if (IS_ENABLED(CONFIG_PPC64) && regno == PT_SOFTE) {
> *data = 1;
> return 0;
> }
> -#endif
>
> regs_max = sizeof(struct user_pt_regs) / sizeof(unsigned long);
> if (regno < regs_max) {
> @@ -1998,7 +1996,6 @@ static const struct user_regset_view
> user_ppc_native_view = {
> .regsets = native_regsets, .n = ARRAY_SIZE(native_regsets)
> };
>
> -#ifdef CONFIG_PPC64
should we care for this ?
/*
* These are the regset flavors matching the CONFIG_PPC32 native set.
*/
static const struct user_regset compat_regsets[] = {
[REGSET_GPR] = {
.core_note_type = NT_PRSTATUS, .n = ELF_NGREG,
.size = sizeof(compat_long_t), .align = sizeof(compat_long_t),
.get = gpr32_get, .set = gpr32_set
},
[REGSET_FPR] = {
.core_note_type = NT_PRFPREG, .n = ELF_NFPREG,
.size = sizeof(double), .align = sizeof(double),
.get = fpr_get, .set = fpr_set
},
> #include
can we move it to head if we do not need the ifdef ?
rest looks good to me.
-- Bala
>
> static int gpr32_get_common(struct task_struct *target,
> @@ -2272,14 +2269,11 @@ static const struct user_regset_view
> user_ppc_compat_view = {
> .name = "ppc", .e_machine = EM_PPC, .ei_osabi = ELF_OSABI,
> .regsets = compat_regsets, .n = ARRAY_SIZE(compat_regsets)
> };
> -#endif /* CONFIG_PPC64 */
>
> const struct user_regset_view *task_user_regset_view(struct task_struct
> *task)
> {
> -#ifdef CONFIG_PPC64
> - if (test_tsk_thread_flag(task, TIF_32BIT))
> + if (IS_ENABLED(CONFIG_PPC64) && test_tsk_thread_flag(task, TIF_32BIT))
> return _ppc_compat_view;
> -#endif
> return _ppc_native_view;
> }
>
> @@ -3063,11 +3057,7 @@ long arch_ptrace(struct task_struct *child, long
> request,
> else
> dbginfo.num_data_bps = 0;
> dbginfo.num_condition_regs = 0;
> -#ifdef CONFIG_PPC64
> - dbginfo.data_bp_alignment = 8;
> -#else
> - dbginfo.data_bp_alignment = 4;
> -#endif
> + dbginfo.data_bp_alignment = sizeof(long);
> dbginfo.sizeof_condition = 0;
> #ifdef CONFIG_HAVE_HW_BREAKPOINT
> dbginfo.features = PPC_DEBUG_FEATURE_DATA_BP_RANGE;
> @@ -3304,12 +3294,10 @@ long do_syscall_trace_enter(struct pt_regs *regs)
> if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
> trace_sys_enter(regs, regs->gpr[0]);
>
> -#ifdef CONFIG_PPC64
> if (!is_32bit_task())
> audit_syscall_entry(regs->gpr[0], regs->gpr[3], regs->gpr[4],
> regs->gpr[5], regs->gpr[6]);
> else
> -#endif
> audit_syscall_entry(regs->gpr[0],
> regs->gpr[3] & 0x,
> regs->gpr[4] & 0x,
[PATCH v3] powerpc xmon: use `dcbf` inplace of `dcbi` instruction for 64bit Book3S
Data Cache Block Invalidate (dcbi) instruction implemented back in
PowerPC architecture version 2.03. But as per Power Processor Users Manual
it is obsolete and not supported by POWER8/POWER9 core. Attempt to use of
this illegal instruction results in a hypervisor emulation assistance
interrupt. So, ifdef it out the option `i` in xmon for 64bit Book3S.
0:mon> fi
cpu 0x0: Vector: 700 (Program Check) at [c3be74a0]
pc: c0102030: cacheflush+0x180/0x1a0
lr: c0101f3c: cacheflush+0x8c/0x1a0
sp: c3be7730
msr: 80081033
current = 0xc35e5c00
paca= 0xc191 irqmask: 0x03 irq_happened: 0x01
pid = 1025, comm = bash
Linux version 5.6.0-rc5-g5aa19adac (root@ltc-wspoon6) (gcc version 7.4.0
(Ubuntu 7.4.0-1ubuntu1~18.04.1)) #1 SMP Tue Mar 10 04:38:41 CDT 2020
cpu 0x0: Exception 700 (Program Check) in xmon, returning to main loop
[c3be7c50] c084abb0 __handle_sysrq+0xf0/0x2a0
[c3be7d00] c084b3c0 write_sysrq_trigger+0xb0/0xe0
[c3be7d30] c04d1edc proc_reg_write+0x8c/0x130
[c3be7d60] c040dc7c __vfs_write+0x3c/0x70
[c3be7d80] c0410e70 vfs_write+0xd0/0x210
[c3be7dd0] c041126c ksys_write+0xdc/0x130
[c3be7e20] c000b9d0 system_call+0x5c/0x68
--- Exception: c01 (System Call) at 7fffa345e420
SP (70b08ab0) is in userspace
Signed-off-by: Balamuruhan S
---
arch/powerpc/xmon/xmon.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
---
changes in v3:
-
Fix Christophe's review comments and rebase it on latest mpe's merge
tree,
* mention the dcbi obsolete statement based on Power processor
users manual in commit message.
* make #ifdef in a more simple way.
changes in v2:
-
Fix review comments from Segher and Michael,
* change incorrect architecture version 2.01 to 2.03 in commit
message.
* ifdef it out the option `i` for PPC_BOOK3S_64 instead to drop
it and change the commit message accordingly.
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index ea303b7e4e29..7b62d5dcc4a1 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -1808,7 +1808,7 @@ static void cacheflush(void)
catch_memory_errors = 1;
sync();
- if (cmd != 'i') {
+ if (cmd != 'i' || IS_ENABLED(CONFIG_PPC_BOOK3S_64)) {
for (; nflush > 0; --nflush, adrs += L1_CACHE_BYTES)
cflush((void *) adrs);
} else {
base-commit: 1ad3b5ebe084246ad593a22707cd91ef6418c31e
--
2.24.1
Re: [PATCH v2] powerpc xmon: use `dcbf` inplace of `dcbi` instruction for 64bit Book3S
On Fri, 2020-03-27 at 16:12 +0100, Christophe Leroy wrote:
>
> Le 27/03/2020 à 10:03, Balamuruhan S a écrit :
> > On Fri, 2020-03-27 at 07:48 +0100, Christophe Leroy wrote:
> > > Le 26/03/2020 à 07:15, Balamuruhan S a écrit :
> > > > Data Cache Block Invalidate (dcbi) instruction was implemented back in
> > > > PowerPC
> > > > architecture version 2.03. It is obsolete and attempt to use of this
> > > > illegal
> > > > instruction results in a hypervisor emulation assistance interrupt. So,
> > > > ifdef
> > > > it out the option `i` in xmon for 64bit Book3S.
> > >
> > > I don't understand. You say two contradictory things:
> > > 1/ You say it _was_ added back.
> > > 2/ You say it _is_ obsolete.
> > >
> > > How can it be obsolete if it was added back ?
> >
> > I actually learnt it from P8 and P9 User Manual,
> >
> > The POWER8/POWER9 core does not provide support for the following optional
> > or
> > obsolete instructions (attempted use of these results in a hypervisor
> > emulation
> > assistance interrupt):
> > • tlbia - TLB invalidate all
> > • tlbiex - TLB invalidate entry by index (obsolete)
> > • slbiex - SLB invalidate entry by index (obsolete)
> > • dcba - Data cache block allocate (Book II; obsolete)
> > • dcbi - Data cache block invalidate (obsolete)
> > • rfi - Return from interrupt (32-bit; obsolete)
> >
>
> Then that's exactly what you have to say in the coming log.
Sure, I will change the commit log in next version along with your suggested
way to ifdef.
>
> Maybe you could also change invalidate_dcache_range():
>
> for (i = 0; i < size >> shift; i++, addr += bytes) {
> if (IS_ENABLED(CONFIG_PPC_BOOK3S_64))
> dcbf(addr);
> else
> dcbi(addr);
> }
I will leave this as is based on the discussion.
Thank you Christophe and Segher.
-- Bala
>
>
>
>
> Christophe
Re: [PATCH v2] powerpc xmon: use `dcbf` inplace of `dcbi` instruction for 64bit Book3S
On Fri, 2020-03-27 at 07:48 +0100, Christophe Leroy wrote:
>
> Le 26/03/2020 à 07:15, Balamuruhan S a écrit :
> > Data Cache Block Invalidate (dcbi) instruction was implemented back in
> > PowerPC
> > architecture version 2.03. It is obsolete and attempt to use of this
> > illegal
> > instruction results in a hypervisor emulation assistance interrupt. So,
> > ifdef
> > it out the option `i` in xmon for 64bit Book3S.
>
> I don't understand. You say two contradictory things:
> 1/ You say it _was_ added back.
> 2/ You say it _is_ obsolete.
>
> How can it be obsolete if it was added back ?
I actually learnt it from P8 and P9 User Manual,
The POWER8/POWER9 core does not provide support for the following optional or
obsolete instructions (attempted use of these results in a hypervisor emulation
assistance interrupt):
• tlbia - TLB invalidate all
• tlbiex - TLB invalidate entry by index (obsolete)
• slbiex - SLB invalidate entry by index (obsolete)
• dcba - Data cache block allocate (Book II; obsolete)
• dcbi - Data cache block invalidate (obsolete)
• rfi - Return from interrupt (32-bit; obsolete)
>
> [...]
>
> > diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
> > index 0ec9640335bb..bfd5a97689cd 100644
> > --- a/arch/powerpc/xmon/xmon.c
> > +++ b/arch/powerpc/xmon/xmon.c
> > @@ -335,10 +335,12 @@ static inline void cflush(void *p)
> > asm volatile ("dcbf 0,%0; icbi 0,%0" : : "r" (p));
> > }
> >
> > +#ifndef CONFIG_PPC_BOOK3S_64
>
> You don't need that #ifndef. Keeping it should be harmless.
okay.
>
> > static inline void cinval(void *p)
> > {
> > asm volatile ("dcbi 0,%0; icbi 0,%0" : : "r" (p));
> > }
> > +#endif
> >
> > /**
> >* write_ciabr() - write the CIABR SPR
> > @@ -1791,8 +1793,9 @@ static void prregs(struct pt_regs *fp)
> >
> > static void cacheflush(void)
> > {
> > - int cmd;
> > unsigned long nflush;
> > +#ifndef CONFIG_PPC_BOOK3S_64
>
> Don't make it so complex, see below
>
> > + int cmd;
> >
> > cmd = inchar();
> > if (cmd != 'i')
> > @@ -1800,13 +1803,14 @@ static void cacheflush(void)
> > scanhex((void *));
> > if (termch != '\n')
> > termch = 0;
> > +#endif
> > nflush = 1;
> > scanhex();
> > nflush = (nflush + L1_CACHE_BYTES - 1) / L1_CACHE_BYTES;
> > if (setjmp(bus_error_jmp) == 0) {
> > catch_memory_errors = 1;
> > sync();
> > -
> > +#ifndef CONFIG_PPC_BOOK3S_64
>
> You don't need that ifndef, just ensure below that regardless of cmd,
> book3s/64 calls cflush and not cinval.
>
> > if (cmd != 'i') {
>
> The only thing you have to do is to replace the above test by:
>
> if (cmd != 'i' || IS_ENABLED(CONFIG_PPC_BOOK3S_64)) {
yes, this is the better way.
>
> > for (; nflush > 0; --nflush, adrs += L1_CACHE_BYTES)
> > cflush((void *) adrs);
> > @@ -1814,6 +1818,10 @@ static void cacheflush(void)
> > for (; nflush > 0; --nflush, adrs += L1_CACHE_BYTES)
> > cinval((void *) adrs);
> > }
> > +#else
>
> Don't need that at all, it's a duplication of the above.
sure :+1:
Thanks for reviewing.
-- Bala
>
> > + for (; nflush > 0; --nflush, adrs += L1_CACHE_BYTES)
> > + cflush((void *)adrs);
> > +#endif
> > sync();
> > /* wait a little while to see if we get a machine check */
> > __delay(200);
> >
> > base-commit: a87b93bdf800a4d7a42d95683624a4516e516b4f
> >
>
> Christophe
[PATCH v2] powerpc xmon: use `dcbf` inplace of `dcbi` instruction for 64bit Book3S
Data Cache Block Invalidate (dcbi) instruction was implemented back in PowerPC
architecture version 2.03. It is obsolete and attempt to use of this illegal
instruction results in a hypervisor emulation assistance interrupt. So, ifdef
it out the option `i` in xmon for 64bit Book3S.
0:mon> fi
cpu 0x0: Vector: 700 (Program Check) at [c3be74a0]
pc: c0102030: cacheflush+0x180/0x1a0
lr: c0101f3c: cacheflush+0x8c/0x1a0
sp: c3be7730
msr: 80081033
current = 0xc35e5c00
paca= 0xc191 irqmask: 0x03 irq_happened: 0x01
pid = 1025, comm = bash
Linux version 5.6.0-rc5-g5aa19adac (root@ltc-wspoon6) (gcc version 7.4.0
(Ubuntu 7.4.0-1ubuntu1~18.04.1)) #1 SMP Tue Mar 10 04:38:41 CDT 2020
cpu 0x0: Exception 700 (Program Check) in xmon, returning to main loop
[c3be7c50] c084abb0 __handle_sysrq+0xf0/0x2a0
[c3be7d00] c084b3c0 write_sysrq_trigger+0xb0/0xe0
[c3be7d30] c04d1edc proc_reg_write+0x8c/0x130
[c3be7d60] c040dc7c __vfs_write+0x3c/0x70
[c3be7d80] c0410e70 vfs_write+0xd0/0x210
[c3be7dd0] c041126c ksys_write+0xdc/0x130
[c3be7e20] c000b9d0 system_call+0x5c/0x68
--- Exception: c01 (System Call) at 7fffa345e420
SP (70b08ab0) is in userspace
Signed-off-by: Balamuruhan S
---
arch/powerpc/xmon/xmon.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
---
changes in v2:
-
Fix review comments from Segher and Michael,
* change incorrect architecture version 2.01 to 2.03 in commit
message.
* ifdef it out the option `i` for PPC_BOOK3S_64 instead to drop it
and change the commit message accordingly.
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index 0ec9640335bb..bfd5a97689cd 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -335,10 +335,12 @@ static inline void cflush(void *p)
asm volatile ("dcbf 0,%0; icbi 0,%0" : : "r" (p));
}
+#ifndef CONFIG_PPC_BOOK3S_64
static inline void cinval(void *p)
{
asm volatile ("dcbi 0,%0; icbi 0,%0" : : "r" (p));
}
+#endif
/**
* write_ciabr() - write the CIABR SPR
@@ -1791,8 +1793,9 @@ static void prregs(struct pt_regs *fp)
static void cacheflush(void)
{
- int cmd;
unsigned long nflush;
+#ifndef CONFIG_PPC_BOOK3S_64
+ int cmd;
cmd = inchar();
if (cmd != 'i')
@@ -1800,13 +1803,14 @@ static void cacheflush(void)
scanhex((void *));
if (termch != '\n')
termch = 0;
+#endif
nflush = 1;
scanhex();
nflush = (nflush + L1_CACHE_BYTES - 1) / L1_CACHE_BYTES;
if (setjmp(bus_error_jmp) == 0) {
catch_memory_errors = 1;
sync();
-
+#ifndef CONFIG_PPC_BOOK3S_64
if (cmd != 'i') {
for (; nflush > 0; --nflush, adrs += L1_CACHE_BYTES)
cflush((void *) adrs);
@@ -1814,6 +1818,10 @@ static void cacheflush(void)
for (; nflush > 0; --nflush, adrs += L1_CACHE_BYTES)
cinval((void *) adrs);
}
+#else
+ for (; nflush > 0; --nflush, adrs += L1_CACHE_BYTES)
+ cflush((void *)adrs);
+#endif
sync();
/* wait a little while to see if we get a machine check */
__delay(200);
base-commit: a87b93bdf800a4d7a42d95683624a4516e516b4f
--
2.24.1
Re: [PATCH v4 08/16] powerpc: Use an accessor for word instructions
On Tue, 2020-03-24 at 14:18 +1100, Jordan Niethe wrote:
> On Mon, Mar 23, 2020 at 10:13 PM Balamuruhan S wrote:
> > On Fri, 2020-03-20 at 16:18 +1100, Jordan Niethe wrote:
> > > In preparation for prefixed instructions where all instructions are no
> > > longer words, use an accessor for getting a word instruction as a u32
> > > from the instruction data type.
> > >
> > > Signed-off-by: Jordan Niethe
> > > ---
> > > v4: New to series
> > > ---
> > > arch/powerpc/kernel/align.c | 2 +-
> > > arch/powerpc/kernel/kprobes.c| 2 +-
> > > arch/powerpc/kernel/trace/ftrace.c | 16 +-
> > > arch/powerpc/lib/code-patching.c | 2 +-
> > > arch/powerpc/lib/feature-fixups.c| 4 +-
> > > arch/powerpc/lib/sstep.c | 270 ++-
> > > arch/powerpc/lib/test_emulate_step.c | 4 +-
> > > arch/powerpc/xmon/xmon.c | 4 +-
> > > 8 files changed, 153 insertions(+), 151 deletions(-)
> > >
> > > diff --git a/arch/powerpc/kernel/align.c b/arch/powerpc/kernel/align.c
> > > index 77c49dfdc1b4..b246ca124931 100644
> > > --- a/arch/powerpc/kernel/align.c
> > > +++ b/arch/powerpc/kernel/align.c
> > > @@ -309,7 +309,7 @@ int fix_alignment(struct pt_regs *regs)
> > > /* We don't handle PPC little-endian any more... */
> > > if (cpu_has_feature(CPU_FTR_PPC_LE))
> > > return -EIO;
> > > - instr = PPC_INST(swab32(instr));
> > > + instr = PPC_INST(swab32(ppc_inst_word(instr)));
> > > }
> > >
> > > #ifdef CONFIG_SPE
> > > diff --git a/arch/powerpc/kernel/kprobes.c
> > > b/arch/powerpc/kernel/kprobes.c
> > > index 4c2b656615a6..0c600b6e4ead 100644
> > > --- a/arch/powerpc/kernel/kprobes.c
> > > +++ b/arch/powerpc/kernel/kprobes.c
> > > @@ -242,7 +242,7 @@ static int try_to_emulate(struct kprobe *p, struct
> > > pt_regs *regs)
> > >* So, we should never get here... but, its still
> > >* good to catch them, just in case...
> > >*/
> > > - printk("Can't step on instruction %x\n", insn);
> > > + printk("Can't step on instruction %x\n",
> > > ppc_inst_word(insn));
> > > BUG();
> > > } else {
> > > /*
> > > diff --git a/arch/powerpc/kernel/trace/ftrace.c
> > > b/arch/powerpc/kernel/trace/ftrace.c
> > > index b3645b664819..7614a9f537fd 100644
> > > --- a/arch/powerpc/kernel/trace/ftrace.c
> > > +++ b/arch/powerpc/kernel/trace/ftrace.c
> > > @@ -74,7 +74,7 @@ ftrace_modify_code(unsigned long ip, ppc_inst old,
> > > ppc_inst
> > > new)
> > > /* Make sure it is what we expect it to be */
> > > if (!ppc_inst_equal(replaced, old)) {
> > > pr_err("%p: replaced (%#x) != old (%#x)",
> > > - (void *)ip, replaced, old);
> > > + (void *)ip, ppc_inst_word(replaced), ppc_inst_word(old));
> > > return -EINVAL;
> > > }
> > >
> > > @@ -136,7 +136,7 @@ __ftrace_make_nop(struct module *mod,
> > >
> > > /* Make sure that that this is still a 24bit jump */
> > > if (!is_bl_op(op)) {
> > > - pr_err("Not expected bl: opcode is %x\n", op);
> > > + pr_err("Not expected bl: opcode is %x\n",
> > > ppc_inst_word(op));
> > > return -EINVAL;
> > > }
> > >
> > > @@ -171,7 +171,7 @@ __ftrace_make_nop(struct module *mod,
> > > /* We expect either a mflr r0, or a std r0, LRSAVE(r1) */
> > > if (!ppc_inst_equal(op, PPC_INST(PPC_INST_MFLR)) &&
> > > !ppc_inst_equal(op, PPC_INST(PPC_INST_STD_LR))) {
> > > - pr_err("Unexpected instruction %08x around bl _mcount\n",
> > > op);
> > > + pr_err("Unexpected instruction %08x around bl _mcount\n",
> > > ppc_inst_word(op));
> > > return -EINVAL;
> > > }
> > > #else
> > > @@ -201,7 +201,7 @@ __ftrace_make_nop(struct module *mod,
> > > }
> > >
> > > if (!ppc_inst_equal(op, PPC_INST(PPC_INST_LD_TOC))) {
> > > - pr_err("Expected %08x found %08x\n", PPC_INST_LD_TOC, op
Re: [PATCH] powerpc xmon: drop the option `i` in cacheflush
On Tue, 2020-03-24 at 14:52 +1100, Michael Ellerman wrote: > "Naveen N. Rao" writes: > > Segher Boessenkool wrote: > > > On Mon, Mar 23, 2020 at 04:55:48PM +0530, Balamuruhan S wrote: > > > > Data Cache Block Invalidate (dcbi) instruction implemented in 32-bit > > > > designs prior to PowerPC architecture version 2.01 and got obsolete > > > > from version 2.01. > > We still support 32-bit ... Okay, got it. > > > > It was added back in 2.03. It also exists in 64-bit designs (using > > > category embedded), in 2.07 still even. > > > > Indeed, it has been part of Book3e. > > > > It isn't clear if this is still useful in this context (xmon) though, > > since 'dcbf' seems to be equivalent in most respects. At the very least, > > we should restrict this to Book3e, if it is of value there. > > Looking at the ISA it looks like dcbf is more or less equivalent and we > could probably drop the explicit invalidate command. > > But the simplest option is probably to just ifdef it out for > PPC_BOOK3S_64. Sure, I will make the changes as suggested. Thank you! -- Bala > > cheers
Re: [PATCH] powerpc xmon: drop the option `i` in cacheflush
On Mon, 2020-03-23 at 07:46 -0500, Segher Boessenkool wrote: > On Mon, Mar 23, 2020 at 04:55:48PM +0530, Balamuruhan S wrote: > > Data Cache Block Invalidate (dcbi) instruction implemented in 32-bit > > designs prior to PowerPC architecture version 2.01 and got obsolete > > from version 2.01. > > It was added back in 2.03. It also exists in 64-bit designs (using > category embedded), in 2.07 still even. I got to know about the version from, https://wiki.alcf.anl.gov/images/f/fb/PowerPC_-_Assembly_-_IBM_Programming_Environment_2.3.pdf please correct me if I was looking into wrong one. -- Bala > > > Segher
[PATCH] powerpc xmon: drop the option `i` in cacheflush
Data Cache Block Invalidate (dcbi) instruction implemented in 32-bit
designs prior to PowerPC architecture version 2.01 and got obsolete
from version 2.01. Attempt to use of this illegal instruction results
in a hypervisor emulation assistance interrupt. So, drop the option
`i` in cacheflush xmon and continue using `dcbf`.
0:mon> fi
cpu 0x0: Vector: 700 (Program Check) at [c3be74a0]
pc: c0102030: cacheflush+0x180/0x1a0
lr: c0101f3c: cacheflush+0x8c/0x1a0
sp: c3be7730
msr: 80081033
current = 0xc35e5c00
paca= 0xc191 irqmask: 0x03 irq_happened: 0x01
pid = 1025, comm = bash
Linux version 5.6.0-rc5-g5aa19adac (root@ltc-wspoon6) (gcc version 7.4.0
(Ubuntu 7.4.0-1ubuntu1~18.04.1)) #1 SMP Tue Mar 10 04:38:41 CDT 2020
cpu 0x0: Exception 700 (Program Check) in xmon, returning to main loop
[c3be7c50] c084abb0 __handle_sysrq+0xf0/0x2a0
[c3be7d00] c084b3c0 write_sysrq_trigger+0xb0/0xe0
[c3be7d30] c04d1edc proc_reg_write+0x8c/0x130
[c3be7d60] c040dc7c __vfs_write+0x3c/0x70
[c3be7d80] c0410e70 vfs_write+0xd0/0x210
[c3be7dd0] c041126c ksys_write+0xdc/0x130
[c3be7e20] c000b9d0 system_call+0x5c/0x68
--- Exception: c01 (System Call) at 7fffa345e420
SP (70b08ab0) is in userspace
Signed-off-by: Balamuruhan S
---
arch/powerpc/xmon/xmon.c | 22 ++
1 file changed, 2 insertions(+), 20 deletions(-)
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index 0ec9640335bb..d287bf2a54be 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -335,11 +335,6 @@ static inline void cflush(void *p)
asm volatile ("dcbf 0,%0; icbi 0,%0" : : "r" (p));
}
-static inline void cinval(void *p)
-{
- asm volatile ("dcbi 0,%0; icbi 0,%0" : : "r" (p));
-}
-
/**
* write_ciabr() - write the CIABR SPR
* @ciabr: The value to write.
@@ -1791,29 +1786,16 @@ static void prregs(struct pt_regs *fp)
static void cacheflush(void)
{
- int cmd;
unsigned long nflush;
- cmd = inchar();
- if (cmd != 'i')
- termch = cmd;
- scanhex((void *));
- if (termch != '\n')
- termch = 0;
nflush = 1;
scanhex();
nflush = (nflush + L1_CACHE_BYTES - 1) / L1_CACHE_BYTES;
if (setjmp(bus_error_jmp) == 0) {
catch_memory_errors = 1;
sync();
-
- if (cmd != 'i') {
- for (; nflush > 0; --nflush, adrs += L1_CACHE_BYTES)
- cflush((void *) adrs);
- } else {
- for (; nflush > 0; --nflush, adrs += L1_CACHE_BYTES)
- cinval((void *) adrs);
- }
+ for (; nflush > 0; --nflush, adrs += L1_CACHE_BYTES)
+ cflush((void *)adrs);
sync();
/* wait a little while to see if we get a machine check */
__delay(200);
base-commit: a87b93bdf800a4d7a42d95683624a4516e516b4f
--
2.24.1
Re: [PATCH v4 08/16] powerpc: Use an accessor for word instructions
On Fri, 2020-03-20 at 16:18 +1100, Jordan Niethe wrote:
> In preparation for prefixed instructions where all instructions are no
> longer words, use an accessor for getting a word instruction as a u32
> from the instruction data type.
>
> Signed-off-by: Jordan Niethe
> ---
> v4: New to series
> ---
> arch/powerpc/kernel/align.c | 2 +-
> arch/powerpc/kernel/kprobes.c| 2 +-
> arch/powerpc/kernel/trace/ftrace.c | 16 +-
> arch/powerpc/lib/code-patching.c | 2 +-
> arch/powerpc/lib/feature-fixups.c| 4 +-
> arch/powerpc/lib/sstep.c | 270 ++-
> arch/powerpc/lib/test_emulate_step.c | 4 +-
> arch/powerpc/xmon/xmon.c | 4 +-
> 8 files changed, 153 insertions(+), 151 deletions(-)
>
> diff --git a/arch/powerpc/kernel/align.c b/arch/powerpc/kernel/align.c
> index 77c49dfdc1b4..b246ca124931 100644
> --- a/arch/powerpc/kernel/align.c
> +++ b/arch/powerpc/kernel/align.c
> @@ -309,7 +309,7 @@ int fix_alignment(struct pt_regs *regs)
> /* We don't handle PPC little-endian any more... */
> if (cpu_has_feature(CPU_FTR_PPC_LE))
> return -EIO;
> - instr = PPC_INST(swab32(instr));
> + instr = PPC_INST(swab32(ppc_inst_word(instr)));
> }
>
> #ifdef CONFIG_SPE
> diff --git a/arch/powerpc/kernel/kprobes.c b/arch/powerpc/kernel/kprobes.c
> index 4c2b656615a6..0c600b6e4ead 100644
> --- a/arch/powerpc/kernel/kprobes.c
> +++ b/arch/powerpc/kernel/kprobes.c
> @@ -242,7 +242,7 @@ static int try_to_emulate(struct kprobe *p, struct
> pt_regs *regs)
>* So, we should never get here... but, its still
>* good to catch them, just in case...
>*/
> - printk("Can't step on instruction %x\n", insn);
> + printk("Can't step on instruction %x\n", ppc_inst_word(insn));
> BUG();
> } else {
> /*
> diff --git a/arch/powerpc/kernel/trace/ftrace.c
> b/arch/powerpc/kernel/trace/ftrace.c
> index b3645b664819..7614a9f537fd 100644
> --- a/arch/powerpc/kernel/trace/ftrace.c
> +++ b/arch/powerpc/kernel/trace/ftrace.c
> @@ -74,7 +74,7 @@ ftrace_modify_code(unsigned long ip, ppc_inst old, ppc_inst
> new)
> /* Make sure it is what we expect it to be */
> if (!ppc_inst_equal(replaced, old)) {
> pr_err("%p: replaced (%#x) != old (%#x)",
> - (void *)ip, replaced, old);
> + (void *)ip, ppc_inst_word(replaced), ppc_inst_word(old));
> return -EINVAL;
> }
>
> @@ -136,7 +136,7 @@ __ftrace_make_nop(struct module *mod,
>
> /* Make sure that that this is still a 24bit jump */
> if (!is_bl_op(op)) {
> - pr_err("Not expected bl: opcode is %x\n", op);
> + pr_err("Not expected bl: opcode is %x\n", ppc_inst_word(op));
> return -EINVAL;
> }
>
> @@ -171,7 +171,7 @@ __ftrace_make_nop(struct module *mod,
> /* We expect either a mflr r0, or a std r0, LRSAVE(r1) */
> if (!ppc_inst_equal(op, PPC_INST(PPC_INST_MFLR)) &&
> !ppc_inst_equal(op, PPC_INST(PPC_INST_STD_LR))) {
> - pr_err("Unexpected instruction %08x around bl _mcount\n", op);
> + pr_err("Unexpected instruction %08x around bl _mcount\n",
> ppc_inst_word(op));
> return -EINVAL;
> }
> #else
> @@ -201,7 +201,7 @@ __ftrace_make_nop(struct module *mod,
> }
>
> if (!ppc_inst_equal(op, PPC_INST(PPC_INST_LD_TOC))) {
> - pr_err("Expected %08x found %08x\n", PPC_INST_LD_TOC, op);
> + pr_err("Expected %08x found %08x\n", PPC_INST_LD_TOC,
> ppc_inst_word(op));
> return -EINVAL;
> }
> #endif /* CONFIG_MPROFILE_KERNEL */
> @@ -401,7 +401,7 @@ static int __ftrace_make_nop_kernel(struct dyn_ftrace
> *rec, unsigned long addr)
>
> /* Make sure that that this is still a 24bit jump */
> if (!is_bl_op(op)) {
> - pr_err("Not expected bl: opcode is %x\n", op);
> + pr_err("Not expected bl: opcode is %x\n", ppc_inst_word(op));
> return -EINVAL;
> }
>
> @@ -525,7 +525,7 @@ __ftrace_make_call(struct dyn_ftrace *rec, unsigned long
> addr)
>
> if (!expected_nop_sequence(ip, op[0], op[1])) {
> pr_err("Unexpected call sequence at %p: %x %x\n",
> - ip, op[0], op[1]);
> + ip, ppc_inst_word(op[0]), ppc_inst_word(op[1]));
> return -EINVAL;
> }
>
> @@ -644,7 +644,7 @@ static int __ftrace_make_call_kernel(struct dyn_ftrace
> *rec, unsigned long addr)
> }
>
> if (!ppc_inst_equal(op, PPC_INST(PPC_INST_NOP))) {
> - pr_err("Unexpected call sequence at %p: %x\n", ip, op);
> + pr_err("Unexpected call sequence at %p: %x\n", ip,
> ppc_inst_word(op));
> return -EINVAL;
> }
>
> @@ -723,7 +723,7 @@ __ftrace_modify_call(struct dyn_ftrace *rec, unsigned
> long
Re: [PATCH v4 16/16] powerpc sstep: Add support for prefixed fixed-point arithmetic
On Fri, 2020-03-20 at 16:18 +1100, Jordan Niethe wrote:
> This adds emulation support for the following prefixed Fixed-Point
> Arithmetic instructions:
> * Prefixed Add Immediate (paddi)
>
> Signed-off-by: Jordan Niethe
Reviewed-by: Balamuruhan S
> ---
> v3: Since we moved the prefixed loads/stores into the load/store switch
> statement it no longer makes sense to have paddi in there, so move it
> out.
> ---
> arch/powerpc/lib/sstep.c | 20
> 1 file changed, 20 insertions(+)
>
> diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
> index daef70eb8e22..6862fc019258 100644
> --- a/arch/powerpc/lib/sstep.c
> +++ b/arch/powerpc/lib/sstep.c
> @@ -1335,6 +1335,26 @@ int analyse_instr(struct instruction_op *op, const
> struct pt_regs *regs,
>
> switch (opcode) {
> #ifdef __powerpc64__
> + case 1:
> + prefix_r = word & (1ul << 20);
> + ra = (suffix >> 16) & 0x1f;
> + rd = (suffix >> 21) & 0x1f;
> + op->reg = rd;
> + op->val = regs->gpr[rd];
> + suffixopcode = suffix >> 26;
> + prefixtype = (word >> 24) & 0x3;
> + switch (prefixtype) {
> + case 2:
> + if (prefix_r && ra)
> + return 0;
> + switch (suffixopcode) {
> + case 14:/* paddi */
> + op->type = COMPUTE | PREFIXED;
> + op->val = mlsd_8lsd_ea(word, suffix, regs);
> + goto compute_done;
> + }
> + }
> + break;
> case 2: /* tdi */
> if (rd & trap_compare(regs->gpr[ra], (short) word))
> goto trap;
Re: [PATCH v4 15/16] powerpc sstep: Add support for prefixed load/stores
On Fri, 2020-03-20 at 16:18 +1100, Jordan Niethe wrote:
> This adds emulation support for the following prefixed integer
> load/stores:
> * Prefixed Load Byte and Zero (plbz)
> * Prefixed Load Halfword and Zero (plhz)
> * Prefixed Load Halfword Algebraic (plha)
> * Prefixed Load Word and Zero (plwz)
> * Prefixed Load Word Algebraic (plwa)
> * Prefixed Load Doubleword (pld)
> * Prefixed Store Byte (pstb)
> * Prefixed Store Halfword (psth)
> * Prefixed Store Word (pstw)
> * Prefixed Store Doubleword (pstd)
> * Prefixed Load Quadword (plq)
> * Prefixed Store Quadword (pstq)
>
> the follow prefixed floating-point load/stores:
> * Prefixed Load Floating-Point Single (plfs)
> * Prefixed Load Floating-Point Double (plfd)
> * Prefixed Store Floating-Point Single (pstfs)
> * Prefixed Store Floating-Point Double (pstfd)
>
> and for the following prefixed VSX load/stores:
> * Prefixed Load VSX Scalar Doubleword (plxsd)
> * Prefixed Load VSX Scalar Single-Precision (plxssp)
> * Prefixed Load VSX Vector [0|1] (plxv, plxv0, plxv1)
> * Prefixed Store VSX Scalar Doubleword (pstxsd)
> * Prefixed Store VSX Scalar Single-Precision (pstxssp)
> * Prefixed Store VSX Vector [0|1] (pstxv, pstxv0, pstxv1)
>
> Signed-off-by: Jordan Niethe
LGTM,
Reviewed-by: Balamuruhan S
> ---
> v2: - Combine all load/store patches
> - Fix the name of Type 01 instructions
> - Remove sign extension flag from pstd/pld
> - Rename sufx -> suffix
> v3: - Move prefixed loads and stores into the switch statement
> ---
> arch/powerpc/lib/sstep.c | 159 +++
> 1 file changed, 159 insertions(+)
>
> diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
> index ab4c71c43c8c..daef70eb8e22 100644
> --- a/arch/powerpc/lib/sstep.c
> +++ b/arch/powerpc/lib/sstep.c
> @@ -187,6 +187,44 @@ static nokprobe_inline unsigned long xform_ea(unsigned
> int instr,
> return ea;
> }
>
> +/*
> + * Calculate effective address for a MLS:D-form / 8LS:D-form
> + * prefixed instruction
> + */
> +static nokprobe_inline unsigned long mlsd_8lsd_ea(unsigned int instr,
> + unsigned int suffix,
> + const struct pt_regs *regs)
> +{
> + int ra, prefix_r;
> + unsigned int dd;
> + unsigned long ea, d0, d1, d;
> +
> + prefix_r = instr & (1ul << 20);
> + ra = (suffix >> 16) & 0x1f;
> +
> + d0 = instr & 0x3;
> + d1 = suffix & 0x;
> + d = (d0 << 16) | d1;
> +
> + /*
> + * sign extend a 34 bit number
> + */
> + dd = (unsigned int)(d >> 2);
> + ea = (signed int)dd;
> + ea = (ea << 2) | (d & 0x3);
> +
> + if (!prefix_r && ra)
> + ea += regs->gpr[ra];
> + else if (!prefix_r && !ra)
> + ; /* Leave ea as is */
> + else if (prefix_r && !ra)
> + ea += regs->nip;
> + else if (prefix_r && ra)
> + ; /* Invalid form. Should already be checked for by caller! */
> +
> + return ea;
> +}
> +
> /*
> * Return the largest power of 2, not greater than sizeof(unsigned long),
> * such that x is a multiple of it.
> @@ -1166,6 +1204,7 @@ int analyse_instr(struct instruction_op *op, const
> struct pt_regs *regs,
> ppc_inst instr)
> {
> unsigned int opcode, ra, rb, rc, rd, spr, u;
> + unsigned int suffixopcode, prefixtype, prefix_r;
> unsigned long int imm;
> unsigned long int val, val2;
> unsigned int mb, me, sh;
> @@ -2652,6 +2691,126 @@ int analyse_instr(struct instruction_op *op, const
> struct pt_regs *regs,
> break;
> }
> break;
> + case 1: /* Prefixed instructions */
> + prefix_r = word & (1ul << 20);
> + ra = (suffix >> 16) & 0x1f;
> + op->update_reg = ra;
> + rd = (suffix >> 21) & 0x1f;
> + op->reg = rd;
> + op->val = regs->gpr[rd];
> +
> + suffixopcode = suffix >> 26;
> + prefixtype = (word >> 24) & 0x3;
> + switch (prefixtype) {
> + case 0: /* Type 00 Eight-Byte Load/Store */
> + if (prefix_r && ra)
> + break;
> + op->ea = mlsd_8lsd_ea(word, suffix, regs);
> + switch (suffixopcode) {
> + case 41:/* plwa */
> +
Re: [PATCH v4 09/16] powerpc: Use a function for reading instructions
On Mon, 2020-03-23 at 18:00 +1000, Nicholas Piggin wrote:
> Jordan Niethe's on March 20, 2020 3:18 pm:
> > Prefixed instructions will mean there are instructions of different
> > length. As a result dereferencing a pointer to an instruction will not
> > necessarily give the desired result. Introduce a function for reading
> > instructions from memory into the instruction data type.
> >
> > Signed-off-by: Jordan Niethe
> > ---
> > v4: New to series
> > ---
> > arch/powerpc/include/asm/uprobes.h | 4 ++--
> > arch/powerpc/kernel/kprobes.c | 8
> > arch/powerpc/kernel/mce_power.c| 2 +-
> > arch/powerpc/kernel/optprobes.c| 6 +++---
> > arch/powerpc/kernel/trace/ftrace.c | 33 +++---
> > arch/powerpc/kernel/uprobes.c | 2 +-
> > arch/powerpc/lib/code-patching.c | 22 ++--
> > arch/powerpc/lib/feature-fixups.c | 6 +++---
> > arch/powerpc/xmon/xmon.c | 6 +++---
> > 9 files changed, 49 insertions(+), 40 deletions(-)
> >
> > diff --git a/arch/powerpc/include/asm/uprobes.h
> > b/arch/powerpc/include/asm/uprobes.h
> > index 2bbdf27d09b5..fff3c5fc90b5 100644
> > --- a/arch/powerpc/include/asm/uprobes.h
> > +++ b/arch/powerpc/include/asm/uprobes.h
> > @@ -23,8 +23,8 @@ typedef ppc_opcode_t uprobe_opcode_t;
> >
> > struct arch_uprobe {
> > union {
> > - u32 insn;
> > - u32 ixol;
> > + u8 insn[MAX_UINSN_BYTES];
> > + u8 ixol[MAX_UINSN_BYTES];
> > };
> > };
>
> Hmm. I wonder if this should be a different patch. Not sure if raw
> bytes is a good idea here. ppc probes also has a ppc_opcode_t, maybe
> could be replaced with ppc_insn_t and used here instead?
>
> Also can't find where you define ppc_inst_read.
Nick, ppc_inst_read and macro PPC_INST you have asked in patch 4 are defined in
asm/inst.h with patch 3 (powerpc: Use a datatype for instructions)
-- Bala
>
> > diff --git a/arch/powerpc/kernel/trace/ftrace.c
> > b/arch/powerpc/kernel/trace/ftrace.c
> > index 7614a9f537fd..ad451205f268 100644
> > --- a/arch/powerpc/kernel/trace/ftrace.c
> > +++ b/arch/powerpc/kernel/trace/ftrace.c
> > @@ -41,6 +41,12 @@
> > #defineNUM_FTRACE_TRAMPS 8
> > static unsigned long ftrace_tramps[NUM_FTRACE_TRAMPS];
> >
> > +static long
> > +read_inst(ppc_inst *inst, const void *src)
> > +{
> > + return probe_kernel_read((void *)inst, src, MCOUNT_INSN_SIZE);
> > +}
>
> Humbly suggest probe_kernel_inst_read.
>
> Thanks,
> Nick
>
Re: [PATCH v4 06/16] powerpc: Use a function for getting the instruction op code
On Fri, 2020-03-20 at 16:17 +1100, Jordan Niethe wrote:
> In preparation for using a data type for instructions that can not be
> directly used with the '>>' operator use a function for getting the op
> code of an instruction.
we need to adopt this in sstep.c and vecemu.c
-- Bala
>
> Signed-off-by: Jordan Niethe
> ---
> v4: New to series
> ---
> arch/powerpc/kernel/align.c | 4 ++--
> arch/powerpc/lib/code-patching.c | 4 ++--
> 2 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/powerpc/kernel/align.c b/arch/powerpc/kernel/align.c
> index 38542fffa179..77c49dfdc1b4 100644
> --- a/arch/powerpc/kernel/align.c
> +++ b/arch/powerpc/kernel/align.c
> @@ -313,8 +313,8 @@ int fix_alignment(struct pt_regs *regs)
> }
>
> #ifdef CONFIG_SPE
> - if ((instr >> 26) == 0x4) {
> - int reg = (instr >> 21) & 0x1f;
> + if (ppc_inst_opcode(instr) == 0x4) {
> + int reg = (ppc_inst_word(instr) >> 21) & 0x1f;
> PPC_WARN_ALIGNMENT(spe, regs);
> return emulate_spe(regs, reg, instr);
> }
> diff --git a/arch/powerpc/lib/code-patching.c b/arch/powerpc/lib/code-
> patching.c
> index e2ba23fd6f4d..04a303c059e2 100644
> --- a/arch/powerpc/lib/code-patching.c
> +++ b/arch/powerpc/lib/code-patching.c
> @@ -228,7 +228,7 @@ bool is_offset_in_branch_range(long offset)
> */
> bool is_conditional_branch(ppc_inst instr)
> {
> - unsigned int opcode = instr >> 26;
> + unsigned int opcode = ppc_inst_opcode(instr);
>
> if (opcode == 16) /* bc, bca, bcl, bcla */
> return true;
> @@ -286,7 +286,7 @@ unsigned int create_cond_branch(const unsigned int *addr,
>
> static unsigned int branch_opcode(ppc_inst instr)
> {
> - return (instr >> 26) & 0x3F;
> + return ppc_inst_opcode(instr) & 0x3F;
> }
>
> static int instr_is_branch_iform(ppc_inst instr)
Re: [PATCH v4 03/16] powerpc: Use a datatype for instructions
On Fri, 2020-03-20 at 16:17 +1100, Jordan Niethe wrote:
> Currently unsigned ints are used to represent instructions on powerpc.
> This has worked well as instructions have always been 4 byte words.
> However, a future ISA version will introduce some changes to
> instructions that mean this scheme will no longer work as well. This
> change is Prefixed Instructions. A prefixed instruction is made up of a
> word prefix followed by a word suffix to make an 8 byte double word
> instruction. No matter the endianess of the system the prefix always
> comes first. Prefixed instructions are only planned for powerpc64.
>
> Introduce a ppc_inst type to represent both prefixed and word
> instructions on powerpc64 while keeping it possible to exclusively have
> word instructions on powerpc32, A latter patch will expand the type to
> include prefixed instructions but for now just typedef it to a u32.
>
> Later patches will introduce helper functions and macros for
> manipulating the instructions so that powerpc64 and powerpc32 might
> maintain separate type definitions.
>
> Signed-off-by: Jordan Niethe
> ---
> arch/powerpc/include/asm/code-patching.h | 31 +--
> arch/powerpc/include/asm/inst.h | 53 +++
> arch/powerpc/include/asm/sstep.h | 5 +-
> arch/powerpc/kernel/align.c | 2 +-
> arch/powerpc/kernel/hw_breakpoint.c | 3 +-
> arch/powerpc/kernel/kprobes.c| 2 +-
> arch/powerpc/kernel/mce_power.c | 5 +-
> arch/powerpc/kernel/optprobes.c | 10 ++--
> arch/powerpc/kernel/trace/ftrace.c | 66
> arch/powerpc/kvm/emulate_loadstore.c | 1 +
> arch/powerpc/lib/code-patching.c | 54 +--
> arch/powerpc/lib/sstep.c | 4 +-
> arch/powerpc/lib/test_emulate_step.c | 9 ++--
> arch/powerpc/xmon/xmon.c | 12 ++---
> 14 files changed, 160 insertions(+), 97 deletions(-)
> create mode 100644 arch/powerpc/include/asm/inst.h
>
> diff --git a/arch/powerpc/include/asm/code-patching.h
> b/arch/powerpc/include/asm/code-patching.h
> index 898b54262881..cb5106f92d67 100644
> --- a/arch/powerpc/include/asm/code-patching.h
> +++ b/arch/powerpc/include/asm/code-patching.h
> @@ -11,6 +11,7 @@
> #include
> #include
> #include
> +#include
>
> /* Flags for create_branch:
> * "b" == create_branch(addr, target, 0);
> @@ -22,27 +23,27 @@
> #define BRANCH_ABSOLUTE 0x2
>
> bool is_offset_in_branch_range(long offset);
> -unsigned int create_branch(const unsigned int *addr,
> +ppc_inst create_branch(const ppc_inst *addr,
> unsigned long target, int flags);
> -unsigned int create_cond_branch(const unsigned int *addr,
> +unsigned int create_cond_branch(const ppc_inst *addr,
> unsigned long target, int flags);
> -int patch_branch(unsigned int *addr, unsigned long target, int flags);
> -int patch_instruction(unsigned int *addr, unsigned int instr);
> -int raw_patch_instruction(unsigned int *addr, unsigned int instr);
> +int patch_branch(ppc_inst *addr, unsigned long target, int flags);
> +int patch_instruction(ppc_inst *addr, ppc_inst instr);
> +int raw_patch_instruction(ppc_inst *addr, ppc_inst instr);
>
> static inline unsigned long patch_site_addr(s32 *site)
> {
> return (unsigned long)site + *site;
> }
>
> -static inline int patch_instruction_site(s32 *site, unsigned int instr)
> +static inline int patch_instruction_site(s32 *site, ppc_inst instr)
> {
> - return patch_instruction((unsigned int *)patch_site_addr(site), instr);
> + return patch_instruction((ppc_inst *)patch_site_addr(site), instr);
> }
>
> static inline int patch_branch_site(s32 *site, unsigned long target, int
> flags)
> {
> - return patch_branch((unsigned int *)patch_site_addr(site), target,
> flags);
> + return patch_branch((ppc_inst *)patch_site_addr(site), target, flags);
> }
>
> static inline int modify_instruction(unsigned int *addr, unsigned int clr,
> @@ -56,13 +57,13 @@ static inline int modify_instruction_site(s32 *site,
> unsigned int clr, unsigned
> return modify_instruction((unsigned int *)patch_site_addr(site), clr,
> set);
> }
>
> -int instr_is_relative_branch(unsigned int instr);
> -int instr_is_relative_link_branch(unsigned int instr);
> -int instr_is_branch_to_addr(const unsigned int *instr, unsigned long addr);
> -unsigned long branch_target(const unsigned int *instr);
> -unsigned int translate_branch(const unsigned int *dest,
> - const unsigned int *src);
> -extern bool is_conditional_branch(unsigned int instr);
> +int instr_is_relative_branch(ppc_inst instr);
> +int instr_is_relative_link_branch(ppc_inst instr);
> +int instr_is_branch_to_addr(const ppc_inst *instr, unsigned long addr);
> +unsigned long branch_target(const ppc_inst *instr);
> +ppc_inst translate_branch(const ppc_inst *dest,
> +
Re: [PATCH v4 02/16] xmon: Move out-of-line instructions to text section
On Fri, 2020-03-20 at 16:17 +1100, Jordan Niethe wrote:
> To execute an instruction out of line after a breakpoint, the NIP is
> set
> to the address of struct bpt::instr. Here a copy of the instruction
> that
> was replaced with a breakpoint is kept, along with a trap so normal
> flow
> can be resumed after XOLing. The struct bpt's are located within the
> data section. This is problematic as the data section may be marked
> as
> no execute.
>
> Instead of each struct bpt holding the instructions to be XOL'd, make
> a
> new array, bpt_table[], with enough space to hold instructions for
> the
> number of supported breakpoints. Place this array in the text
> section.
> Make struct bpt::instr a pointer to the instructions in bpt_table[]
> associated with that breakpoint. This association is a simple
> mapping:
> bpts[n] -> bpt_table[n * words per breakpoint].
Can it separate commits ?
* introduce the array bpt_table[] and make struct bpt::instr a
pointer to the instructions in bpt_table[].
* place the array in text section.
> Currently we only need
> the copied instruction followed by a trap, so 2 words per breakpoint.
>
> Signed-off-by: Jordan Niethe
> ---
> v4: New to series
> ---
> arch/powerpc/kernel/vmlinux.lds.S | 2 +-
> arch/powerpc/xmon/xmon.c | 22 +-
> 2 files changed, 14 insertions(+), 10 deletions(-)
>
> diff --git a/arch/powerpc/kernel/vmlinux.lds.S
> b/arch/powerpc/kernel/vmlinux.lds.S
> index b4c89a1acebb..e90845b8c300 100644
> --- a/arch/powerpc/kernel/vmlinux.lds.S
> +++ b/arch/powerpc/kernel/vmlinux.lds.S
> @@ -86,7 +86,7 @@ SECTIONS
> ALIGN_FUNCTION();
> #endif
> /* careful! __ftr_alt_* sections need to be close to
> .text */
> - *(.text.hot TEXT_MAIN .text.fixup .text.unlikely .fixup
> __ftr_alt_* .ref.text);
> + *(.text.hot TEXT_MAIN .text.fixup .text.unlikely .fixup
> __ftr_alt_* .ref.text .text.xmon_bpts);
> #ifdef CONFIG_PPC64
> *(.tramp.ftrace.text);
> #endif
> diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
> index 02e3bd62cab4..7875d1a37770 100644
> --- a/arch/powerpc/xmon/xmon.c
> +++ b/arch/powerpc/xmon/xmon.c
> @@ -97,7 +97,7 @@ static long *xmon_fault_jmp[NR_CPUS];
> /* Breakpoint stuff */
> struct bpt {
> unsigned long address;
> - unsigned intinstr[2];
> + unsigned int*instr;
> atomic_tref_count;
> int enabled;
> unsigned long pad;
> @@ -109,6 +109,7 @@ struct bpt {
> #define BP_DABR 4
>
> #define NBPTS256
> +#define BPT_WORDS2
> static struct bpt bpts[NBPTS];
> static struct bpt dabr;
> static struct bpt *iabr;
> @@ -116,6 +117,8 @@ static unsigned bpinstr = 0x7fe8; /* trap
> */
>
> #define BP_NUM(bp) ((bp) - bpts + 1)
>
> +static unsigned int __section(.text.xmon_bpts) bpt_table[NBPTS *
> BPT_WORDS];
> +
> /* Prototypes */
> static int cmds(struct pt_regs *);
> static int mread(unsigned long, void *, int);
> @@ -852,16 +855,16 @@ static struct bpt *at_breakpoint(unsigned long
> pc)
> static struct bpt *in_breakpoint_table(unsigned long nip, unsigned
> long *offp)
> {
> unsigned long off;
> + unsigned long bp_off;
>
> - off = nip - (unsigned long) bpts;
> - if (off >= sizeof(bpts))
> + off = nip - (unsigned long) bpt_table;
> + if (off >= sizeof(bpt_table))
> return NULL;
> - off %= sizeof(struct bpt);
> - if (off != offsetof(struct bpt, instr[0])
> - && off != offsetof(struct bpt, instr[1]))
> + bp_off = off % (sizeof(unsigned int) * BPT_WORDS);
> + if (bp_off != 0 && bp_off != 4)
> return NULL;
> - *offp = off - offsetof(struct bpt, instr[0]);
> - return (struct bpt *) (nip - off);
> + *offp = bp_off;
> + return bpts + ((off - bp_off) / (sizeof(unsigned int) *
> BPT_WORDS));
`(off - bp_off) / (sizeof(unsigned int) * BPT_WORDS)` seems to be the
actual breakpoint offset. Can we have something like,
#define NBPTS 256
#define BPT_WORDS 2
#define BPT_WORDS_SIZE (sizeof(unsigned int) * BPT_WORDS)
#define BPT_OFFSET(off, bp_word_off) ((off - bp_word_off) /
BPT_WOR
DS_SIZE);
:::
:::
:::
bp_word_off = off % BPT_WORDS_SIZE;
if (bp_word_off != 0 && bp_word_off != 4)
return NULL;
*offp = bp_word_off;
return bpts + BPT_OFFSET(off, bp_word_off);
-- Bala
> }
static struct bpt *new_breakpoint(unsigned long a)
@@ -876,7
> +879,8 @@ static struct bpt *new_breakpoint(unsigned long a)
for (bp
> = bpts; bp < [NBPTS]; ++bp) {
if (!bp->enabled &&
> atomic_read(>ref_count) == 0) {
bp->address =
> a;
- patch_instruction(>instr[1], bpinstr);
+
> bp->instr = bpt_table + ((bp - bpts) * BPT_WORDS);
+
> patch_instruction(bp->instr + 1, bpinstr);
> return
Re: [PATCH v4 02/16] xmon: Move out-of-line instructions to text section
On Fri, 2020-03-20 at 16:17 +1100, Jordan Niethe wrote:
> To execute an instruction out of line after a breakpoint, the NIP is
> set
> to the address of struct bpt::instr. Here a copy of the instruction
> that
> was replaced with a breakpoint is kept, along with a trap so normal
> flow
> can be resumed after XOLing. The struct bpt's are located within the
> data section. This is problematic as the data section may be marked
> as
> no execute.
>
> Instead of each struct bpt holding the instructions to be XOL'd, make
> a
> new array, bpt_table[], with enough space to hold instructions for
> the
> number of supported breakpoints. Place this array in the text
> section.
> Make struct bpt::instr a pointer to the instructions in bpt_table[]
> associated with that breakpoint. This association is a simple
> mapping:
> bpts[n] -> bpt_table[n * words per breakpoint].
Can we have it in separate commits ?
* introduce the array bpt_table[] and make struct bpt::instr a
pointer to the instructions in bpt_table[].
* place the array in text section.
> Currently we only need
> the copied instruction followed by a trap, so 2 words per breakpoint.
>
> Signed-off-by: Jordan Niethe
> ---
> v4: New to series
> ---
> arch/powerpc/kernel/vmlinux.lds.S | 2 +-
> arch/powerpc/xmon/xmon.c | 22 +-
> 2 files changed, 14 insertions(+), 10 deletions(-)
>
> diff --git a/arch/powerpc/kernel/vmlinux.lds.S
> b/arch/powerpc/kernel/vmlinux.lds.S
> index b4c89a1acebb..e90845b8c300 100644
> --- a/arch/powerpc/kernel/vmlinux.lds.S
> +++ b/arch/powerpc/kernel/vmlinux.lds.S
> @@ -86,7 +86,7 @@ SECTIONS
> ALIGN_FUNCTION();
> #endif
> /* careful! __ftr_alt_* sections need to be close to
> .text */
> - *(.text.hot TEXT_MAIN .text.fixup .text.unlikely .fixup
> __ftr_alt_* .ref.text);
> + *(.text.hot TEXT_MAIN .text.fixup .text.unlikely .fixup
> __ftr_alt_* .ref.text .text.xmon_bpts);
> #ifdef CONFIG_PPC64
> *(.tramp.ftrace.text);
> #endif
> diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
> index 02e3bd62cab4..7875d1a37770 100644
> --- a/arch/powerpc/xmon/xmon.c
> +++ b/arch/powerpc/xmon/xmon.c
> @@ -97,7 +97,7 @@ static long *xmon_fault_jmp[NR_CPUS];
> /* Breakpoint stuff */
> struct bpt {
> unsigned long address;
> - unsigned intinstr[2];
> + unsigned int*instr;
> atomic_tref_count;
> int enabled;
> unsigned long pad;
> @@ -109,6 +109,7 @@ struct bpt {
> #define BP_DABR 4
>
> #define NBPTS256
> +#define BPT_WORDS2
> static struct bpt bpts[NBPTS];
> static struct bpt dabr;
> static struct bpt *iabr;
> @@ -116,6 +117,8 @@ static unsigned bpinstr = 0x7fe8; /* trap
> */
>
> #define BP_NUM(bp) ((bp) - bpts + 1)
>
> +static unsigned int __section(.text.xmon_bpts) bpt_table[NBPTS *
> BPT_WORDS];
> +
> /* Prototypes */
> static int cmds(struct pt_regs *);
> static int mread(unsigned long, void *, int);
> @@ -852,16 +855,16 @@ static struct bpt *at_breakpoint(unsigned long
> pc)
> static struct bpt *in_breakpoint_table(unsigned long nip, unsigned
> long *offp)
> {
> unsigned long off;
> + unsigned long bp_off;
>
> - off = nip - (unsigned long) bpts;
> - if (off >= sizeof(bpts))
> + off = nip - (unsigned long) bpt_table;
> + if (off >= sizeof(bpt_table))
> return NULL;
> - off %= sizeof(struct bpt);
> - if (off != offsetof(struct bpt, instr[0])
> - && off != offsetof(struct bpt, instr[1]))
> + bp_off = off % (sizeof(unsigned int) * BPT_WORDS);
> + if (bp_off != 0 && bp_off != 4)
> return NULL;
> - *offp = off - offsetof(struct bpt, instr[0]);
> - return (struct bpt *) (nip - off);
> + *offp = bp_off;
> + return bpts + ((off - bp_off) / (sizeof(unsigned int) *
> BPT_WORDS));
`(off - bp_off) / (sizeof(unsigned int) * BPT_WORDS)` seems to be the
actual breakpoint offset. Can we have something like,
#define NBPTS 256
#define BPT_WORDS 2
#define BPT_WORDS_SIZE (sizeof(unsigned int) * BPT_WORDS)
#define BPT_OFFSET(off, bp_word_off) ((off - bp_word_off) / \
BPT_WORDS_SIZE)
;
:::
:::
:::
bp_word_off = off % BPT_WORDS_SIZE;
if (bp_word_off != 0 && bp_word_off != 4)
return NULL;
*offp = bp_word_off;
return bpts + BPT_OFFSET(off, bp_word_off);
-- Bala
[RFC PATCH 4/4] powerpc kvm_asm: rename PPC_LD and PPC_STD macros to avoid redefinition
use PPC_KVM_LD and PPC_KVM_STD to fix gcc warnings on redefinition as we consolidate all ppc instruction encoding in ppc-opcode.h Signed-off-by: Balamuruhan S --- arch/powerpc/include/asm/kvm_asm.h| 8 arch/powerpc/kvm/booke_interrupts.S | 8 arch/powerpc/kvm/bookehv_interrupts.S | 28 +-- 3 files changed, 22 insertions(+), 22 deletions(-) diff --git a/arch/powerpc/include/asm/kvm_asm.h b/arch/powerpc/include/asm/kvm_asm.h index 635fb154b33f..d3f607c57856 100644 --- a/arch/powerpc/include/asm/kvm_asm.h +++ b/arch/powerpc/include/asm/kvm_asm.h @@ -11,11 +11,11 @@ #ifdef __ASSEMBLY__ #ifdef CONFIG_64BIT -#define PPC_STD(sreg, offset, areg) std sreg, (offset)(areg) -#define PPC_LD(treg, offset, areg) ld treg, (offset)(areg) +#define PPC_KVM_STD(sreg, offset, areg) (std sreg, (offset)(areg)) +#define PPC_KVM_LD(treg, offset, areg) (ld treg, (offset)(areg)) #else -#define PPC_STD(sreg, offset, areg) stw sreg, (offset+4)(areg) -#define PPC_LD(treg, offset, areg) lwz treg, (offset+4)(areg) +#define PPC_KVM_STD(sreg, offset, areg) (stw sreg, ((offset) + 4)(areg)) +#define PPC_KVM_LD(treg, offset, areg) (lwz treg, ((offset) + 4)(areg)) #endif #endif diff --git a/arch/powerpc/kvm/booke_interrupts.S b/arch/powerpc/kvm/booke_interrupts.S index 2e56ab5a5f55..3a343da95ea5 100644 --- a/arch/powerpc/kvm/booke_interrupts.S +++ b/arch/powerpc/kvm/booke_interrupts.S @@ -443,13 +443,13 @@ lightweight_exit: * written directly to the shared area, so we * need to reload them here with the guest's values. */ - PPC_LD(r3, VCPU_SHARED_SPRG4, r5) + PPC_KVM_LD(r3, VCPU_SHARED_SPRG4, r5) mtspr SPRN_SPRG4W, r3 - PPC_LD(r3, VCPU_SHARED_SPRG5, r5) + PPC_KVM_LD(r3, VCPU_SHARED_SPRG5, r5) mtspr SPRN_SPRG5W, r3 - PPC_LD(r3, VCPU_SHARED_SPRG6, r5) + PPC_KVM_LD(r3, VCPU_SHARED_SPRG6, r5) mtspr SPRN_SPRG6W, r3 - PPC_LD(r3, VCPU_SHARED_SPRG7, r5) + PPC_KVM_LD(r3, VCPU_SHARED_SPRG7, r5) mtspr SPRN_SPRG7W, r3 #ifdef CONFIG_KVM_EXIT_TIMING diff --git a/arch/powerpc/kvm/bookehv_interrupts.S b/arch/powerpc/kvm/bookehv_interrupts.S index c577ba4b3169..97e9b3289c7b 100644 --- a/arch/powerpc/kvm/bookehv_interrupts.S +++ b/arch/powerpc/kvm/bookehv_interrupts.S @@ -89,7 +89,7 @@ END_BTB_FLUSH_SECTION #endif orisr8, r6, MSR_CE@h - PPC_STD(r6, VCPU_SHARED_MSR, r11) + PPC_KVM_STD(r6, VCPU_SHARED_MSR, r11) ori r8, r8, MSR_ME | MSR_RI PPC_STL r5, VCPU_PC(r4) @@ -386,17 +386,17 @@ _GLOBAL(kvmppc_resume_host) PPC_LL r3, PACA_SPRG_VDSO(r13) #endif mfspr r5, SPRN_SPRG9 - PPC_STD(r6, VCPU_SHARED_SPRG4, r11) + PPC_KVM_STD(r6, VCPU_SHARED_SPRG4, r11) mfspr r8, SPRN_SPRG6 - PPC_STD(r7, VCPU_SHARED_SPRG5, r11) + PPC_KVM_STD(r7, VCPU_SHARED_SPRG5, r11) mfspr r9, SPRN_SPRG7 #ifdef CONFIG_64BIT mtspr SPRN_SPRG_VDSO_WRITE, r3 #endif - PPC_STD(r5, VCPU_SPRG9, r4) - PPC_STD(r8, VCPU_SHARED_SPRG6, r11) + PPC_KVM_STD(r5, VCPU_SPRG9, r4) + PPC_KVM_STD(r8, VCPU_SHARED_SPRG6, r11) mfxer r3 - PPC_STD(r9, VCPU_SHARED_SPRG7, r11) + PPC_KVM_STD(r9, VCPU_SHARED_SPRG7, r11) /* save guest MAS registers and restore host mas4 & mas6 */ mfspr r5, SPRN_MAS0 @@ -405,7 +405,7 @@ _GLOBAL(kvmppc_resume_host) stw r5, VCPU_SHARED_MAS0(r11) mfspr r7, SPRN_MAS2 stw r6, VCPU_SHARED_MAS1(r11) - PPC_STD(r7, VCPU_SHARED_MAS2, r11) + PPC_KVM_STD(r7, VCPU_SHARED_MAS2, r11) mfspr r5, SPRN_MAS3 mfspr r6, SPRN_MAS4 stw r5, VCPU_SHARED_MAS7_3+4(r11) @@ -602,7 +602,7 @@ lightweight_exit: stw r3, VCPU_HOST_MAS6(r4) lwz r3, VCPU_SHARED_MAS0(r11) lwz r5, VCPU_SHARED_MAS1(r11) - PPC_LD(r6, VCPU_SHARED_MAS2, r11) + PPC_KVM_LD(r6, VCPU_SHARED_MAS2, r11) lwz r7, VCPU_SHARED_MAS7_3+4(r11) lwz r8, VCPU_SHARED_MAS4(r11) mtspr SPRN_MAS0, r3 @@ -620,15 +620,15 @@ lightweight_exit: * SPRGs, so we need to reload them here with the guest's values. */ lwz r3, VCPU_VRSAVE(r4) - PPC_LD(r5, VCPU_SHARED_SPRG4, r11) + PPC_KVM_LD(r5, VCPU_SHARED_SPRG4, r11) mtspr SPRN_VRSAVE, r3 - PPC_LD(r6, VCPU_SHARED_SPRG5, r11) + PPC_KVM_LD(r6, VCPU_SHARED_SPRG5, r11) mtspr SPRN_SPRG4W, r5 - PPC_LD(r7, VCPU_SHARED_SPRG6, r11) + PPC_KVM_LD(r7, VCPU_SHARED_SPRG6, r11) mtspr SPRN_SPRG5W, r6 - PPC_LD(r8, VCPU_SHARED_SPRG7, r11) + PPC_KVM_LD(r8, VCPU_SHARED_SPRG7, r11) mtspr SPRN_SPRG6W, r7 - PPC_LD(r5, VCPU_SPRG9, r4) + PPC_KVM_LD(r5, VCPU_SPRG9, r4) mtspr SPRN_SPRG7W, r8 mtspr SPRN_SPRG9, r5 @@ -638,7 +638,7 @@ lightweight_exit: PPC_LL r6, VCPU
[RFC PATCH 3/4] powerpc ppc-opcode: move ppc instuction encoding from test_emulate_step
Few ppc instructions are encoded in test_emulate_step.c, consolidate them to ppc-opcode.h, fix redefintion errors in bpf_jit caused due to this consolidation. Reuse the macros from ppc-opcode.h Signed-off-by: Balamuruhan S --- arch/powerpc/include/asm/ppc-opcode.h | 34 ++ arch/powerpc/lib/test_emulate_step.c | 155 ++ arch/powerpc/net/bpf_jit.h| 8 -- arch/powerpc/net/bpf_jit32.h | 10 +- arch/powerpc/net/bpf_jit64.h | 4 +- arch/powerpc/net/bpf_jit_comp.c | 2 +- arch/powerpc/net/bpf_jit_comp64.c | 14 +-- 7 files changed, 105 insertions(+), 122 deletions(-) diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index ea5e0f864b20..2ed8a285f1ec 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -76,6 +76,9 @@ #define__REGA0_R30 30 #define__REGA0_R31 31 +#define IMM_L(i) ((uintptr_t)(i) & 0x) +#define IMM_DS(i) ((uintptr_t)(i) & 0xfffc) + /* opcode and xopcode for instructions */ #define OP_TRAP 3 #define OP_TRAP_64 2 @@ -614,6 +617,37 @@ ___PPC_RA(vra) | \ ___PPC_RB(vrb) | __PPC_RC21) +#define PPC_ENCODE_LD(r, base, i) (PPC_INST_LD | ___PPC_RT(r) | \ + ___PPC_RA(base) | IMM_DS(i)) +#define PPC_ENCODE_LWZ(r, base, i)(PPC_INST_LWZ | ___PPC_RT(r) | \ + ___PPC_RA(base) | IMM_L(i)) +#define PPC_ENCODE_LWZX(t, a, b) (PPC_INST_LWZX | ___PPC_RT(t) | \ + ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_ENCODE_STD(r, base, i)(PPC_INST_STD | ___PPC_RS(r) | \ + ___PPC_RA(base) | IMM_DS(i)) +#define PPC_ENCODE_STDCX(s, a, b) (PPC_INST_STDCX | ___PPC_RS(s) |\ + ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_ENCODE_LFSX(t, a, b) (PPC_INST_LFSX | ___PPC_RT(t) | \ + ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_ENCODE_STFSX(s, a, b) (PPC_INST_STFSX | ___PPC_RS(s) |\ + ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_ENCODE_LFDX(t, a, b) (PPC_INST_LFDX | ___PPC_RT(t) | \ + ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_ENCODE_STFDX(s, a, b) (PPC_INST_STFDX | ___PPC_RS(s) |\ +___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_ENCODE_LVX(t, a, b) (PPC_INST_LVX | ___PPC_RT(t) | \ + ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_ENCODE_STVX(s, a, b) (PPC_INST_STVX | ___PPC_RS(s) | \ + ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_ENCODE_ADD(t, a, b) (PPC_INST_ADD | ___PPC_RT(t) | \ + ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_ENCODE_ADD_DOT(t, a, b) (PPC_INST_ADD | ___PPC_RT(t) | \ + ___PPC_RA(a) | ___PPC_RB(b) | 0x1) +#define PPC_ENCODE_ADDC(t, a, b) (PPC_INST_ADDC | ___PPC_RT(t) | \ + ___PPC_RA(a) | ___PPC_RB(b)) +#define PPC_ENCODE_ADDC_DOT(t, a, b) (PPC_INST_ADDC | ___PPC_RT(t) | \ + ___PPC_RA(a) | ___PPC_RB(b) | 0x1) + #define PPC_CP_ABORTstringify_in_c(.long PPC_ENCODE_CP_ABORT) #define PPC_COPY(a, b) stringify_in_c(.long PPC_ENCODE_COPY(a, b)) #define PPC_DARN(t, l) stringify_in_c(.long PPC_ENCODE_DARN(t, l)) diff --git a/arch/powerpc/lib/test_emulate_step.c b/arch/powerpc/lib/test_emulate_step.c index 53df4146dd32..45b485edfee1 100644 --- a/arch/powerpc/lib/test_emulate_step.c +++ b/arch/powerpc/lib/test_emulate_step.c @@ -12,49 +12,6 @@ #include #include -#define IMM_L(i) ((uintptr_t)(i) & 0x) -#define IMM_DS(i) ((uintptr_t)(i) & 0xfffc) - -/* - * Defined with TEST_ prefix so it does not conflict with other - * definitions. - */ -#define TEST_LD(r, base, i)(PPC_INST_LD | ___PPC_RT(r) | \ - ___PPC_RA(base) | IMM_DS(i)) -#define TEST_LWZ(r, base, i) (PPC_INST_LWZ | ___PPC_RT(r) | \ - ___PPC_RA(base) | IMM_L(i)) -#define TEST_LWZX(t, a, b) (PPC_INST_LWZX | ___PPC_RT(t) | \ - ___PPC_RA(a) | ___PPC_RB(b)) -#define TEST_STD(r, base, i) (PPC_INST_STD | ___PPC_RS(r) | \ - ___PPC_RA(base) | IMM_DS(i)) -#define TEST_LDARX(t, a, b, eh)(PPC_INST_LDARX | ___PPC_RT(t) | \ - ___PPC_RA(a) | ___PPC_RB(b) | \ - __PPC_EH(eh)) -#define TEST_STDCX(s, a, b)
[RFC PATCH 2/4] powerpc selftest: reuse ppc-opcode macros to avoid redundancy
Avoid redefining macros to encode ppc instructions instead reuse it from ppc-opcode.h, Makefile changes are necessary to compile memcmp_64.S with __ASSEMBLY__ defined from selftests. Signed-off-by: Balamuruhan S --- .../selftests/powerpc/stringloops/Makefile| 15 ++-- .../powerpc/stringloops/asm/asm-const.h | 1 + .../powerpc/stringloops/asm/ppc-opcode.h | 36 +-- 3 files changed, 14 insertions(+), 38 deletions(-) create mode 12 tools/testing/selftests/powerpc/stringloops/asm/asm-const.h mode change 100644 => 12 tools/testing/selftests/powerpc/stringloops/asm/ppc-opcode.h diff --git a/tools/testing/selftests/powerpc/stringloops/Makefile b/tools/testing/selftests/powerpc/stringloops/Makefile index 7fc0623d85c3..43eb14bfbe3a 100644 --- a/tools/testing/selftests/powerpc/stringloops/Makefile +++ b/tools/testing/selftests/powerpc/stringloops/Makefile @@ -6,10 +6,19 @@ EXTRA_SOURCES := ../harness.c build_32bit = $(shell if ($(CC) $(CFLAGS) -m32 -o /dev/null memcmp.c >/dev/null 2>&1) then echo "1"; fi) -TEST_GEN_PROGS := memcmp_64 strlen +TEST_GEN_PROGS := memcmp_64 memcmp harness memcmp64 strlen -$(OUTPUT)/memcmp_64: memcmp.c -$(OUTPUT)/memcmp_64: CFLAGS += -m64 -maltivec +$(OUTPUT)/memcmp64: memcmp_64.o memcmp.o ../harness.o + $(CC) $(CFLAGS) -m64 -maltivec memcmp.o memcmp_64.o ../harness.o -o memcmp_64 + +$(OUTPUT)/memcmp_64: memcmp_64.S + $(CC) $(CFLAGS) -m64 -maltivec -D__ASSEMBLY__ -o memcmp_64.o -c memcmp_64.S + +$(OUTPUT)/memcmp: memcmp.c + $(CC) $(CFLAGS) -m64 -maltivec -o memcmp.o -c memcmp.c + +$(OUTPUT)/harness: $(EXTRA_SOURCES) + $(CC) $(CFLAGS) -m64 -maltivec -o ../harness.o -c $(EXTRA_SOURCES) ifeq ($(build_32bit),1) $(OUTPUT)/memcmp_32: memcmp.c diff --git a/tools/testing/selftests/powerpc/stringloops/asm/asm-const.h b/tools/testing/selftests/powerpc/stringloops/asm/asm-const.h new file mode 12 index ..18d8be13e67f --- /dev/null +++ b/tools/testing/selftests/powerpc/stringloops/asm/asm-const.h @@ -0,0 +1 @@ +../../../../../../arch/powerpc/include/asm/asm-const.h \ No newline at end of file diff --git a/tools/testing/selftests/powerpc/stringloops/asm/ppc-opcode.h b/tools/testing/selftests/powerpc/stringloops/asm/ppc-opcode.h deleted file mode 100644 index 3edd1a1d9128.. --- a/tools/testing/selftests/powerpc/stringloops/asm/ppc-opcode.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright 2009 Freescale Semiconductor, Inc. - * - * provides masks and opcode images for use by code generation, emulation - * and for instructions that older assemblers might not know about - */ -#ifndef _ASM_POWERPC_PPC_OPCODE_H -#define _ASM_POWERPC_PPC_OPCODE_H - - -# define stringify_in_c(...) __VA_ARGS__ -# define ASM_CONST(x) x - - -#define PPC_INST_VCMPEQUD_RC 0x10c7 -#define PPC_INST_VCMPEQUB_RC 0x1006 - -#define __PPC_RC21 (0x1 << 10) - -/* macros to insert fields into opcodes */ -#define ___PPC_RA(a) (((a) & 0x1f) << 16) -#define ___PPC_RB(b) (((b) & 0x1f) << 11) -#define ___PPC_RS(s) (((s) & 0x1f) << 21) -#define ___PPC_RT(t) ___PPC_RS(t) - -#define VCMPEQUD_RC(vrt, vra, vrb) stringify_in_c(.long PPC_INST_VCMPEQUD_RC | \ - ___PPC_RT(vrt) | ___PPC_RA(vra) | \ - ___PPC_RB(vrb) | __PPC_RC21) - -#define VCMPEQUB_RC(vrt, vra, vrb) stringify_in_c(.long PPC_INST_VCMPEQUB_RC | \ - ___PPC_RT(vrt) | ___PPC_RA(vra) | \ - ___PPC_RB(vrb) | __PPC_RC21) - -#endif /* _ASM_POWERPC_PPC_OPCODE_H */ diff --git a/tools/testing/selftests/powerpc/stringloops/asm/ppc-opcode.h b/tools/testing/selftests/powerpc/stringloops/asm/ppc-opcode.h new file mode 12 index ..f9b1f27ac335 --- /dev/null +++ b/tools/testing/selftests/powerpc/stringloops/asm/ppc-opcode.h @@ -0,0 +1 @@ +../../../../../../arch/powerpc/include/asm/ppc-opcode.h \ No newline at end of file -- 2.24.1
[RFC PATCH 1/4] powerpc ppc-opcode: introduce PPC_ENCODE_* macros for base instruction encoding
Introduce PPC_ENCODE* macros to have all the bare encoding of ppc instructions and use it wrapped with stringify_in_c() for raw encoding in ppc-opcode.h. Signed-off-by: Balamuruhan S --- arch/powerpc/include/asm/ppc-opcode.h | 330 +- 1 file changed, 220 insertions(+), 110 deletions(-) diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index c1df75edde44..ea5e0f864b20 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -429,105 +429,105 @@ #endif /* Deal with instructions that older assemblers aren't aware of */ -#definePPC_CP_ABORTstringify_in_c(.long PPC_INST_CP_ABORT) -#definePPC_COPY(a, b) stringify_in_c(.long PPC_INST_COPY | \ - ___PPC_RA(a) | ___PPC_RB(b)) -#define PPC_DARN(t, l) stringify_in_c(.long PPC_INST_DARN | \ - ___PPC_RT(t) | \ - (((l) & 0x3) << 16)) -#definePPC_DCBAL(a, b) stringify_in_c(.long PPC_INST_DCBAL | \ - __PPC_RA(a) | __PPC_RB(b)) -#definePPC_DCBZL(a, b) stringify_in_c(.long PPC_INST_DCBZL | \ - __PPC_RA(a) | __PPC_RB(b)) -#define PPC_LQARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LQARX | \ - ___PPC_RT(t) | ___PPC_RA(a) | \ +#definePPC_ENCODE_CP_ABORT (PPC_INST_CP_ABORT) +#definePPC_ENCODE_COPY(a, b) (PPC_INST_COPY | ___PPC_RA(a) | \ + ___PPC_RB(b)) +#define PPC_ENCODE_DARN(t, l) (PPC_INST_DARN | ___PPC_RT(t) | \ + (((l) & 0x3) << 16)) +#definePPC_ENCODE_DCBAL(a, b) (PPC_INST_DCBAL | __PPC_RA(a) | \ + __PPC_RB(b)) +#definePPC_ENCODE_DCBZL(a, b) (PPC_INST_DCBZL | __PPC_RA(a) | \ + __PPC_RB(b)) +#define PPC_ENCODE_LQARX(t, a, b, eh) (PPC_INST_LQARX | ___PPC_RT(t) | \ + ___PPC_RA(a) | \ ___PPC_RB(b) | __PPC_EH(eh)) -#define PPC_LDARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LDARX | \ - ___PPC_RT(t) | ___PPC_RA(a) | \ +#define PPC_ENCODE_LDARX(t, a, b, eh) (PPC_INST_LDARX | ___PPC_RT(t) | \ + ___PPC_RA(a) | \ ___PPC_RB(b) | __PPC_EH(eh)) -#define PPC_LWARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LWARX | \ +#define PPC_ENCODE_LWARX(t, a, b, eh) (PPC_INST_LWARX | \ ___PPC_RT(t) | ___PPC_RA(a) | \ ___PPC_RB(b) | __PPC_EH(eh)) -#define PPC_STQCX(t, a, b) stringify_in_c(.long PPC_INST_STQCX | \ +#define PPC_ENCODE_STQCX(t, a, b) (PPC_INST_STQCX | \ ___PPC_RT(t) | ___PPC_RA(a) | \ ___PPC_RB(b)) -#define PPC_MADDHD(t, a, b, c) stringify_in_c(.long PPC_INST_MADDHD | \ +#define PPC_ENCODE_MADDHD(t, a, b, c) (PPC_INST_MADDHD | \ ___PPC_RT(t) | ___PPC_RA(a) | \ ___PPC_RB(b) | ___PPC_RC(c)) -#define PPC_MADDHDU(t, a, b, c)stringify_in_c(.long PPC_INST_MADDHDU | \ +#define PPC_ENCODE_MADDHDU(t, a, b, c) (PPC_INST_MADDHDU | \ ___PPC_RT(t) | ___PPC_RA(a) | \ ___PPC_RB(b) | ___PPC_RC(c)) -#define PPC_MADDLD(t, a, b, c) stringify_in_c(.long PPC_INST_MADDLD | \ +#define PPC_ENCODE_MADDLD(t, a, b, c) (PPC_INST_MADDLD | \ ___PPC_RT(t) | ___PPC_RA(a) | \ ___PPC_RB(b) | ___PPC_RC(c)) -#define PPC_MSGSND(b) stringify_in_c(.long PPC_INST_MSGSND | \ - ___PPC_RB(b)) -#define PPC_MSGSYNCstringify_in_c(.long PPC_INST_MSGSYNC) -#define PPC_MSGCLR(b) stringify_in_c(.long PPC_INST_MSGCLR | \ - ___PPC_RB(b)) -#define PPC_MSGSNDP(b) stringify_in_c(.long PPC_INST_MSGSNDP | \ - ___PPC_RB(b)) -#define PPC_MSGCLRP(b) stringify_in_c(.long PPC_INST_MSGCLRP | \ +#define PPC_ENCODE_MSGSND(b) (PPC_INST_MSGSND | ___PPC_RB(b)) +#define PPC_ENCODE_MSGSYNC (PPC_INST_MSGSYNC) +#define PPC_ENCODE_MSGCLR(b) (PPC_INST_MSGCLR | ___PPC_RB(b)) +#define PPC_ENCODE_MSGSNDP(b) (PPC_INST_MSGSNDP | ___PPC_RB(b)) +#define PPC_ENCODE_MSGCLRP(b) (PPC_INST_MSGCLRP | ___PPC_RB(b)) +#define PPC_ENCODE_PASTE(a, b) (PPC_IN
[RFC PATCH 0/4] consolidate PowerPC instruction encoding macros
ppc-opcode.h have base instruction encoding wrapped with stringify_in_c() for raw encoding to have compatibility. But there are redundant macros for base instruction encodings in bpf, instruction emulation test infrastructure and powerpc selftests. Currently PPC_INST_* macros are used for encoding instruction opcode and PPC_* for raw instuction encoding, this rfc patchset introduces PPC_ENCODE_* macros for base instruction encoding and reuse it from elsewhere. With this change we can avoid redundant macro definitions in multiple files and start adding new instructions in ppc-opcode.h in future. TODO: We can still improve further by moving all the instruction encoding from bpf_jit.h to ppc-opcode.h and reuse them from bpf source. It can be implemented based on the thoughts and feedback on this RFC. This patchset is based on mpe's merge branch of linuxppc tree with a fix patch on top of it, https://patchwork.ozlabs.org/patch/1252760/ Thanks to Naveen and Sandipan on overall suggestions/improvements. Tested it by compiling vmlinux with and without the changes and the objdump of them remains to be same, # diff vmlinux_objdump vmlinux_rfc_objdump 2c2 < vmlinux: file format elf64-powerpcle --- > vmlinux_rfc: file format elf64-powerpcle I would request for your review and suggestions to make it better. Balamuruhan S (4): powerpc ppc-opcode: consolidate PowerPC instruction macros powerpc selftest: reuse ppc-opcode macros to avoid redundancy powerpc ppc-opcode: move ppc instuction encoding from test_emulate_step powerpc kvm_asm: rename PPC_LD and PPC_STD macros to avoid redefinition arch/powerpc/include/asm/kvm_asm.h| 8 +- arch/powerpc/include/asm/ppc-opcode.h | 364 -- arch/powerpc/kvm/booke_interrupts.S | 8 +- arch/powerpc/kvm/bookehv_interrupts.S | 28 +- arch/powerpc/lib/test_emulate_step.c | 155 +++- arch/powerpc/net/bpf_jit.h| 8 - arch/powerpc/net/bpf_jit32.h | 10 +- arch/powerpc/net/bpf_jit64.h | 4 +- arch/powerpc/net/bpf_jit_comp.c | 2 +- arch/powerpc/net/bpf_jit_comp64.c | 14 +- .../selftests/powerpc/stringloops/Makefile| 15 +- .../powerpc/stringloops/asm/asm-const.h | 1 + .../powerpc/stringloops/asm/ppc-opcode.h | 36 +- 13 files changed, 361 insertions(+), 292 deletions(-) create mode 12 tools/testing/selftests/powerpc/stringloops/asm/asm-const.h mode change 100644 => 12 tools/testing/selftests/powerpc/stringloops/asm/ppc-opcode.h base-commit: 8a445cbcb9f5090cb07ec6cbb89a8a1fc99a0ff7 prerequisite-patch-id: c271d8516dd39526e848dfa95ae38c9205002d2c -- 2.24.1
[PATCH v2] powerpc test_emulate_step: fix DS operand in ld encoding to appropriate value
ld instruction should have 14 bit immediate field (DS) concatenated with
0b00 on the right, encode it accordingly. Introduce macro `IMM_DS()`
to encode DS form instructions with 14 bit immediate field.
Fixes: 4ceae137bdab ("powerpc: emulate_step() tests for load/store
instructions")
Reviewed-by: Sandipan Das
Signed-off-by: Balamuruhan S
---
arch/powerpc/lib/test_emulate_step.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
---
changes in v2:
-
* squash the commits as per Christophe's review comment
diff --git a/arch/powerpc/lib/test_emulate_step.c
b/arch/powerpc/lib/test_emulate_step.c
index 42347067739c..007292a1ad01 100644
--- a/arch/powerpc/lib/test_emulate_step.c
+++ b/arch/powerpc/lib/test_emulate_step.c
@@ -13,19 +13,20 @@
#include
#define IMM_L(i) ((uintptr_t)(i) & 0x)
+#define IMM_DS(i) ((uintptr_t)(i) & 0xfffc)
/*
* Defined with TEST_ prefix so it does not conflict with other
* definitions.
*/
#define TEST_LD(r, base, i)(PPC_INST_LD | ___PPC_RT(r) | \
- ___PPC_RA(base) | IMM_L(i))
+ ___PPC_RA(base) | IMM_DS(i))
#define TEST_LWZ(r, base, i) (PPC_INST_LWZ | ___PPC_RT(r) | \
___PPC_RA(base) | IMM_L(i))
#define TEST_LWZX(t, a, b) (PPC_INST_LWZX | ___PPC_RT(t) | \
___PPC_RA(a) | ___PPC_RB(b))
#define TEST_STD(r, base, i) (PPC_INST_STD | ___PPC_RS(r) | \
- ___PPC_RA(base) | ((i) & 0xfffc))
+ ___PPC_RA(base) | IMM_DS(i))
#define TEST_LDARX(t, a, b, eh)(PPC_INST_LDARX | ___PPC_RT(t) |
\
___PPC_RA(a) | ___PPC_RB(b) | \
__PPC_EH(eh))
base-commit: 5aa19adac1f3152a5fd3b865a1ab46bb845d3696
--
2.24.1
Re: [PATCH 1/2] powerpc test_emulate_step: fix DS operand in ld encoding to appropriate value
On Wed, 2020-03-11 at 08:01 +0100, Christophe Leroy wrote:
>
> Le 11/03/2020 à 07:14, Balamuruhan S a écrit :
> > ld instruction should have 14 bit immediate field (DS) concatenated
> > with
> > 0b00 on the right, encode it accordingly.
> >
> > Fixes: 4ceae137bdab ("powerpc: emulate_step() tests for load/store
> > instructions")
> > Reviewed-by: Sandipan Das
> > Signed-off-by: Balamuruhan S
> > ---
> > arch/powerpc/lib/test_emulate_step.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/powerpc/lib/test_emulate_step.c
> > b/arch/powerpc/lib/test_emulate_step.c
> > index 42347067739c..51c254fd15b5 100644
> > --- a/arch/powerpc/lib/test_emulate_step.c
> > +++ b/arch/powerpc/lib/test_emulate_step.c
> > @@ -19,7 +19,7 @@
> >* definitions.
> >*/
> > #define TEST_LD(r, base, i) (PPC_INST_LD | ___PPC_RT(r) |
> > \
> > - ___PPC_RA(base) | IMM_L(i))
> > + ___PPC_RA(base) | ((i) &
> > 0xfffc))
>
> I think you should squash patch 1 and 2 together. Or at least you
> should
> put the new IMM_DS macro in patch 1 and use it instead of open
> coding.
sure, I will make the changes as suggested.
-- Bala
>
> > #define TEST_LWZ(r, base, i) (PPC_INST_LWZ | ___PPC_RT(r) |
> > \
> > ___PPC_RA(base) | IMM_L(i))
> > #define TEST_LWZX(t, a, b)(PPC_INST_LWZX | ___PPC_RT(t) |
> > \
> >
> > base-commit: 5aa19adac1f3152a5fd3b865a1ab46bb845d3696
> >
>
> Christophe
[PATCH 1/2] powerpc test_emulate_step: fix DS operand in ld encoding to appropriate value
ld instruction should have 14 bit immediate field (DS) concatenated with
0b00 on the right, encode it accordingly.
Fixes: 4ceae137bdab ("powerpc: emulate_step() tests for load/store
instructions")
Reviewed-by: Sandipan Das
Signed-off-by: Balamuruhan S
---
arch/powerpc/lib/test_emulate_step.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/lib/test_emulate_step.c
b/arch/powerpc/lib/test_emulate_step.c
index 42347067739c..51c254fd15b5 100644
--- a/arch/powerpc/lib/test_emulate_step.c
+++ b/arch/powerpc/lib/test_emulate_step.c
@@ -19,7 +19,7 @@
* definitions.
*/
#define TEST_LD(r, base, i)(PPC_INST_LD | ___PPC_RT(r) | \
- ___PPC_RA(base) | IMM_L(i))
+ ___PPC_RA(base) | ((i) & 0xfffc))
#define TEST_LWZ(r, base, i) (PPC_INST_LWZ | ___PPC_RT(r) | \
___PPC_RA(base) | IMM_L(i))
#define TEST_LWZX(t, a, b) (PPC_INST_LWZX | ___PPC_RT(t) | \
base-commit: 5aa19adac1f3152a5fd3b865a1ab46bb845d3696
--
2.24.1
[PATCH 2/2] powerpc test_emulate_step: add macro for 14 bit immediate field
introduce macro `IMM_DS()` to encode DS form instructions with 14 bit immediate field. Signed-off-by: Balamuruhan S --- arch/powerpc/lib/test_emulate_step.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/lib/test_emulate_step.c b/arch/powerpc/lib/test_emulate_step.c index 51c254fd15b5..007292a1ad01 100644 --- a/arch/powerpc/lib/test_emulate_step.c +++ b/arch/powerpc/lib/test_emulate_step.c @@ -13,19 +13,20 @@ #include #define IMM_L(i) ((uintptr_t)(i) & 0x) +#define IMM_DS(i) ((uintptr_t)(i) & 0xfffc) /* * Defined with TEST_ prefix so it does not conflict with other * definitions. */ #define TEST_LD(r, base, i)(PPC_INST_LD | ___PPC_RT(r) | \ - ___PPC_RA(base) | ((i) & 0xfffc)) + ___PPC_RA(base) | IMM_DS(i)) #define TEST_LWZ(r, base, i) (PPC_INST_LWZ | ___PPC_RT(r) | \ ___PPC_RA(base) | IMM_L(i)) #define TEST_LWZX(t, a, b) (PPC_INST_LWZX | ___PPC_RT(t) | \ ___PPC_RA(a) | ___PPC_RB(b)) #define TEST_STD(r, base, i) (PPC_INST_STD | ___PPC_RS(r) | \ - ___PPC_RA(base) | ((i) & 0xfffc)) + ___PPC_RA(base) | IMM_DS(i)) #define TEST_LDARX(t, a, b, eh)(PPC_INST_LDARX | ___PPC_RT(t) | \ ___PPC_RA(a) | ___PPC_RB(b) | \ __PPC_EH(eh)) -- 2.24.1
[PATCH v3 3/3] powerpc test_emulate_step: add testcases for divde[.] and divdeu[.] instructions
add testcases for divde, divde., divdeu, divdeu. emulated
instructions to cover few scenarios,
* with same dividend and divisor to have undefine RT
for divdeu[.]
* with divide by zero to have undefine RT for both
divde[.] and divdeu[.]
* with negative dividend to cover -|divisor| < r <= 0 if
the dividend is negative for divde[.]
* normal case with proper dividend and divisor for both
divde[.] and divdeu[.]
Reviewed-by: Sandipan Das
Signed-off-by: Balamuruhan S
---
arch/powerpc/lib/test_emulate_step.c | 164 +++
1 file changed, 164 insertions(+)
diff --git a/arch/powerpc/lib/test_emulate_step.c
b/arch/powerpc/lib/test_emulate_step.c
index 42347067739c..ffeb9b68a31d 100644
--- a/arch/powerpc/lib/test_emulate_step.c
+++ b/arch/powerpc/lib/test_emulate_step.c
@@ -53,6 +53,14 @@
___PPC_RA(a) | ___PPC_RB(b))
#define TEST_ADDC_DOT(t, a, b) (PPC_INST_ADDC | ___PPC_RT(t) | \
___PPC_RA(a) | ___PPC_RB(b) | 0x1)
+#define TEST_DIVDE(t, a, b)(PPC_INST_DIVDE | ___PPC_RT(t) |\
+ ___PPC_RA(a) | ___PPC_RB(b))
+#define TEST_DIVDE_DOT(t, a, b)(PPC_INST_DIVDE | ___PPC_RT(t) |
\
+ ___PPC_RA(a) | ___PPC_RB(b) | 0x1)
+#define TEST_DIVDEU(t, a, b) (PPC_INST_DIVDEU | ___PPC_RT(t) | \
+ ___PPC_RA(a) | ___PPC_RB(b))
+#define TEST_DIVDEU_DOT(t, a, b)(PPC_INST_DIVDEU | ___PPC_RT(t) | \
+ ___PPC_RA(a) | ___PPC_RB(b) | 0x1)
#define MAX_SUBTESTS 16
@@ -837,6 +845,162 @@ static struct compute_test compute_tests[] = {
}
}
}
+ },
+ {
+ .mnemonic = "divde",
+ .subtests = {
+ {
+ .descr = "RA = LONG_MIN, RB = LONG_MIN",
+ .instr = TEST_DIVDE(20, 21, 22),
+ .regs = {
+ .gpr[21] = LONG_MIN,
+ .gpr[22] = LONG_MIN,
+ }
+ },
+ {
+ .descr = "RA = 1L, RB = 0",
+ .instr = TEST_DIVDE(20, 21, 22),
+ .flags = IGNORE_GPR(20),
+ .regs = {
+ .gpr[21] = 1L,
+ .gpr[22] = 0,
+ }
+ },
+ {
+ .descr = "RA = LONG_MIN, RB = LONG_MAX",
+ .instr = TEST_DIVDE(20, 21, 22),
+ .regs = {
+ .gpr[21] = LONG_MIN,
+ .gpr[22] = LONG_MAX,
+ }
+ }
+ }
+ },
+ {
+ .mnemonic = "divde.",
+ .subtests = {
+ {
+ .descr = "RA = LONG_MIN, RB = LONG_MIN",
+ .instr = TEST_DIVDE_DOT(20, 21, 22),
+ .regs = {
+ .gpr[21] = LONG_MIN,
+ .gpr[22] = LONG_MIN,
+ }
+ },
+ {
+ .descr = "RA = 1L, RB = 0",
+ .instr = TEST_DIVDE_DOT(20, 21, 22),
+ .flags = IGNORE_GPR(20),
+ .regs = {
+ .gpr[21] = 1L,
+ .gpr[22] = 0,
+ }
+ },
+ {
+ .descr = "RA = LONG_MIN, RB = LONG_MAX",
+ .instr = TEST_DIVDE_DOT(20, 21, 22),
+ .regs = {
+ .gpr[21] = LONG_MIN,
+ .gpr[22] = LONG_MAX,
+ }
+ }
+ }
+ },
+ {
+ .mnemonic = "divdeu",
+ .subtests = {
+ {
+ .descr = "RA = LONG_MIN, RB = LONG_MIN",
+ .instr = TEST_DIVDEU(20, 21, 22),
+ .flags = IGNORE_GPR(20),
+ .regs = {
+
[PATCH v3 2/3] powerpc sstep: add support for divde[.] and divdeu[.] instructions
This patch adds emulation support for divde, divdeu instructions, * Divide Doubleword Extended (divde[.]) * Divide Doubleword Extended Unsigned (divdeu[.]) Reviewed-by: Sandipan Das Signed-off-by: Balamuruhan S --- arch/powerpc/lib/sstep.c | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c index c077acb983a1..2cac71a71878 100644 --- a/arch/powerpc/lib/sstep.c +++ b/arch/powerpc/lib/sstep.c @@ -1736,7 +1736,18 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs, op->val = (int) regs->gpr[ra] / (int) regs->gpr[rb]; goto arith_done; - +#ifdef __powerpc64__ + case 425: /* divde[.] */ + asm volatile(PPC_DIVDE(%0, %1, %2) : + "=r" (op->val) : "r" (regs->gpr[ra]), + "r" (regs->gpr[rb])); + goto arith_done; + case 393: /* divdeu[.] */ + asm volatile(PPC_DIVDEU(%0, %1, %2) : + "=r" (op->val) : "r" (regs->gpr[ra]), + "r" (regs->gpr[rb])); + goto arith_done; +#endif case 755: /* darn */ if (!cpu_has_feature(CPU_FTR_ARCH_300)) return -1; -- 2.14.5
