[PATCH v2 stable v4.4 2/2] Documentation: Add nospectre_v1 parameter
commit 26cb1f36c43ee6e89d2a9f48a5a7500d5248f836 upstream. Currently only supported on powerpc. Signed-off-by: Diana Craciun Signed-off-by: Michael Ellerman --- Documentation/kernel-parameters.txt | 4 1 file changed, 4 insertions(+) diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index f0bdf78420a0..3ff87d5d6fea 100644 --- a/Documentation/kernel-parameters.txt +++ b/Documentation/kernel-parameters.txt @@ -2449,6 +2449,10 @@ bytes respectively. Such letter suffixes can also be entirely omitted. legacy floating-point registers on task switch. nohugeiomap [KNL,x86] Disable kernel huge I/O mappings. + + nospectre_v1[PPC] Disable mitigations for Spectre Variant 1 (bounds + check bypass). With this option data leaks are possible + in the system. nospectre_v2[X86,PPC_FSL_BOOK3E] Disable all mitigations for the Spectre variant 2 (indirect branch prediction) vulnerability. System may -- 2.17.1
[PATCH v2 stable v4.4 1/2] powerpc/fsl: Add FSL_PPC_BOOK3E as supported arch for nospectre_v2 boot arg
commit e59f5bd759b7dee57593c5b6c0441609bda5d530 upstream. Signed-off-by: Diana Craciun Signed-off-by: Michael Ellerman --- Documentation/kernel-parameters.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index da515c535e62..f0bdf78420a0 100644 --- a/Documentation/kernel-parameters.txt +++ b/Documentation/kernel-parameters.txt @@ -2450,7 +2450,7 @@ bytes respectively. Such letter suffixes can also be entirely omitted. nohugeiomap [KNL,x86] Disable kernel huge I/O mappings. - nospectre_v2[X86] Disable all mitigations for the Spectre variant 2 + nospectre_v2[X86,PPC_FSL_BOOK3E] Disable all mitigations for the Spectre variant 2 (indirect branch prediction) vulnerability. System may allow data leaks with this option, which is equivalent to spectre_v2=off. -- 2.17.1
[PATCH stable v4.4 6/8] powerpc/fsl: Fixed warning: orphan section `__btb_flush_fixup'
commit 039daac5526932ec731e4499613018d263af8b3e upstream. Fixed the following build warning: powerpc-linux-gnu-ld: warning: orphan section `__btb_flush_fixup' from `arch/powerpc/kernel/head_44x.o' being placed in section `__btb_flush_fixup'. Signed-off-by: Diana Craciun Signed-off-by: Michael Ellerman --- arch/powerpc/kernel/head_booke.h | 18 -- 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h index 384bb4d80520..7b98c7351f6c 100644 --- a/arch/powerpc/kernel/head_booke.h +++ b/arch/powerpc/kernel/head_booke.h @@ -31,6 +31,16 @@ */ #define THREAD_NORMSAVE(offset)(THREAD_NORMSAVES + (offset * 4)) +#ifdef CONFIG_PPC_FSL_BOOK3E +#define BOOKE_CLEAR_BTB(reg) \ +START_BTB_FLUSH_SECTION \ + BTB_FLUSH(reg) \ +END_BTB_FLUSH_SECTION +#else +#define BOOKE_CLEAR_BTB(reg) +#endif + + #define NORMAL_EXCEPTION_PROLOG(intno) \ mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \ mfspr r10, SPRN_SPRG_THREAD; \ @@ -42,9 +52,7 @@ andi. r11, r11, MSR_PR; /* check whether user or kernel*/\ mr r11, r1; \ beq 1f; \ -START_BTB_FLUSH_SECTION\ - BTB_FLUSH(r11) \ -END_BTB_FLUSH_SECTION \ + BOOKE_CLEAR_BTB(r11)\ /* if from user, start at top of this thread's kernel stack */ \ lwz r11, THREAD_INFO-THREAD(r10);\ ALLOC_STACK_FRAME(r11, THREAD_SIZE); \ @@ -130,9 +138,7 @@ END_BTB_FLUSH_SECTION \ stw r9,_CCR(r8);/* save CR on stack*/\ mfspr r11,exc_level_srr1; /* check whether user or kernel*/\ DO_KVM BOOKE_INTERRUPT_##intno exc_level_srr1; \ -START_BTB_FLUSH_SECTION \ - BTB_FLUSH(r10) \ -END_BTB_FLUSH_SECTION \ + BOOKE_CLEAR_BTB(r10)\ andi. r11,r11,MSR_PR; \ mfspr r11,SPRN_SPRG_THREAD; /* if from user, start at top of */\ lwz r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\ -- 2.17.1
[PATCH stable v4.4 3/8] powerpc/fsl: Emulate SPRN_BUCSR register
commit 98518c4d8728656db349f875fcbbc7c126d4c973 upstream. In order to flush the branch predictor the guest kernel performs writes to the BUCSR register which is hypervisor privilleged. However, the branch predictor is flushed at each KVM entry, so the branch predictor has been already flushed, so just return as soon as possible to guest. Signed-off-by: Diana Craciun [mpe: Tweak comment formatting] Signed-off-by: Michael Ellerman --- arch/powerpc/kvm/e500_emulate.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/arch/powerpc/kvm/e500_emulate.c b/arch/powerpc/kvm/e500_emulate.c index 990db69a1d0b..fa88f641ac03 100644 --- a/arch/powerpc/kvm/e500_emulate.c +++ b/arch/powerpc/kvm/e500_emulate.c @@ -277,6 +277,13 @@ int kvmppc_core_emulate_mtspr_e500(struct kvm_vcpu *vcpu, int sprn, ulong spr_va vcpu->arch.pwrmgtcr0 = spr_val; break; + case SPRN_BUCSR: + /* +* If we are here, it means that we have already flushed the +* branch predictor, so just return to guest. +*/ + break; + /* extra exceptions */ #ifdef CONFIG_SPE_POSSIBLE case SPRN_IVOR32: -- 2.17.1
[PATCH stable v4.4 2/8] powerpc/fsl: Flush branch predictor when entering KVM
commit e7aa61f47b23afbec41031bc47ca8d6cb6516abc upstream. Switching from the guest to host is another place where the speculative accesses can be exploited. Flush the branch predictor when entering KVM. Signed-off-by: Diana Craciun Signed-off-by: Michael Ellerman --- arch/powerpc/kvm/bookehv_interrupts.S | 4 1 file changed, 4 insertions(+) diff --git a/arch/powerpc/kvm/bookehv_interrupts.S b/arch/powerpc/kvm/bookehv_interrupts.S index 81bd8a07aa51..612b7f6a887f 100644 --- a/arch/powerpc/kvm/bookehv_interrupts.S +++ b/arch/powerpc/kvm/bookehv_interrupts.S @@ -75,6 +75,10 @@ PPC_LL r1, VCPU_HOST_STACK(r4) PPC_LL r2, HOST_R2(r1) +START_BTB_FLUSH_SECTION + BTB_FLUSH(r10) +END_BTB_FLUSH_SECTION + mfspr r10, SPRN_PID lwz r8, VCPU_HOST_PID(r4) PPC_LL r11, VCPU_SHARED(r4) -- 2.17.1
[PATCH stable v4.4 5/8] powerpc/fsl: Sanitize the syscall table for NXP PowerPC 32 bit platforms
commit c28218d4abbf4f2035495334d8bfcba64bda4787 upstream. Used barrier_nospec to sanitize the syscall table. Signed-off-by: Diana Craciun Signed-off-by: Michael Ellerman --- arch/powerpc/kernel/entry_32.S | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S index 3728e617e17e..609bc7d01f13 100644 --- a/arch/powerpc/kernel/entry_32.S +++ b/arch/powerpc/kernel/entry_32.S @@ -33,6 +33,7 @@ #include #include #include +#include /* * MSR_KERNEL is > 0x1 on 4xx/Book-E since it include MSR_CE. @@ -340,6 +341,15 @@ syscall_dotrace_cont: ori r10,r10,sys_call_table@l slwir0,r0,2 bge-66f + + barrier_nospec_asm + /* +* Prevent the load of the handler below (based on the user-passed +* system call number) being speculatively executed until the test +* against NR_syscalls and branch to .66f above has +* committed. +*/ + lwzxr10,r10,r0 /* Fetch system call handler [ptr] */ mtlrr10 addir9,r1,STACK_FRAME_OVERHEAD -- 2.17.1
[PATCH stable v4.4 8/8] Documentation: Add nospectre_v1 parameter
Currently only supported on powerpc. Signed-off-by: Diana Craciun Signed-off-by: Michael Ellerman --- Documentation/kernel-parameters.txt | 4 1 file changed, 4 insertions(+) diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index f0bdf78420a0..3ff87d5d6fea 100644 --- a/Documentation/kernel-parameters.txt +++ b/Documentation/kernel-parameters.txt @@ -2449,6 +2449,10 @@ bytes respectively. Such letter suffixes can also be entirely omitted. legacy floating-point registers on task switch. nohugeiomap [KNL,x86] Disable kernel huge I/O mappings. + + nospectre_v1[PPC] Disable mitigations for Spectre Variant 1 (bounds + check bypass). With this option data leaks are possible + in the system. nospectre_v2[X86,PPC_FSL_BOOK3E] Disable all mitigations for the Spectre variant 2 (indirect branch prediction) vulnerability. System may -- 2.17.1
[PATCH stable v4.4 4/8] powerpc/fsl: Flush the branch predictor at each kernel entry (32 bit)
commit 7fef436295bf6c05effe682c8797dfcb0deb112a upstream. In order to protect against speculation attacks on indirect branches, the branch predictor is flushed at kernel entry to protect for the following situations: - userspace process attacking another userspace process - userspace process attacking the kernel Basically when the privillege level change (i.e.the kernel is entered), the branch predictor state is flushed. Signed-off-by: Diana Craciun Signed-off-by: Michael Ellerman --- arch/powerpc/kernel/head_booke.h | 6 ++ arch/powerpc/kernel/head_fsl_booke.S | 15 +++ 2 files changed, 21 insertions(+) diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h index a620203f7de3..384bb4d80520 100644 --- a/arch/powerpc/kernel/head_booke.h +++ b/arch/powerpc/kernel/head_booke.h @@ -42,6 +42,9 @@ andi. r11, r11, MSR_PR; /* check whether user or kernel*/\ mr r11, r1; \ beq 1f; \ +START_BTB_FLUSH_SECTION\ + BTB_FLUSH(r11) \ +END_BTB_FLUSH_SECTION \ /* if from user, start at top of this thread's kernel stack */ \ lwz r11, THREAD_INFO-THREAD(r10);\ ALLOC_STACK_FRAME(r11, THREAD_SIZE); \ @@ -127,6 +130,9 @@ stw r9,_CCR(r8);/* save CR on stack*/\ mfspr r11,exc_level_srr1; /* check whether user or kernel*/\ DO_KVM BOOKE_INTERRUPT_##intno exc_level_srr1; \ +START_BTB_FLUSH_SECTION \ + BTB_FLUSH(r10) \ +END_BTB_FLUSH_SECTION \ andi. r11,r11,MSR_PR; \ mfspr r11,SPRN_SPRG_THREAD; /* if from user, start at top of */\ lwz r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\ diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S index fffd1f96bb1d..275769b6fb0d 100644 --- a/arch/powerpc/kernel/head_fsl_booke.S +++ b/arch/powerpc/kernel/head_fsl_booke.S @@ -451,6 +451,13 @@ END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) mfcrr13 stw r13, THREAD_NORMSAVE(3)(r10) DO_KVM BOOKE_INTERRUPT_DTLB_MISS SPRN_SRR1 +START_BTB_FLUSH_SECTION + mfspr r11, SPRN_SRR1 + andi. r10,r11,MSR_PR + beq 1f + BTB_FLUSH(r10) +1: +END_BTB_FLUSH_SECTION mfspr r10, SPRN_DEAR /* Get faulting address */ /* If we are faulting a kernel address, we have to use the @@ -545,6 +552,14 @@ END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) mfcrr13 stw r13, THREAD_NORMSAVE(3)(r10) DO_KVM BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR1 +START_BTB_FLUSH_SECTION + mfspr r11, SPRN_SRR1 + andi. r10,r11,MSR_PR + beq 1f + BTB_FLUSH(r10) +1: +END_BTB_FLUSH_SECTION + mfspr r10, SPRN_SRR0 /* Get faulting address */ /* If we are faulting a kernel address, we have to use the -- 2.17.1
[PATCH stable v4.4 7/8] powerpc/fsl: Add FSL_PPC_BOOK3E as supported arch for nospectre_v2 boot arg
commit f633a8ad636efb5d4bba1a047d4a0f1ef719aa06 upstream. Signed-off-by: Diana Craciun Signed-off-by: Michael Ellerman --- Documentation/kernel-parameters.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index da515c535e62..f0bdf78420a0 100644 --- a/Documentation/kernel-parameters.txt +++ b/Documentation/kernel-parameters.txt @@ -2450,7 +2450,7 @@ bytes respectively. Such letter suffixes can also be entirely omitted. nohugeiomap [KNL,x86] Disable kernel huge I/O mappings. - nospectre_v2[X86] Disable all mitigations for the Spectre variant 2 + nospectre_v2[X86,PPC_FSL_BOOK3E] Disable all mitigations for the Spectre variant 2 (indirect branch prediction) vulnerability. System may allow data leaks with this option, which is equivalent to spectre_v2=off. -- 2.17.1
[PATCH stable v4.4 1/8] powerpc/fsl: Enable runtime patching if nospectre_v2 boot arg is used
commit 3bc8ea8603ae4c1e09aca8de229ad38b8091fcb3 upstream.
If the user choses not to use the mitigations, replace
the code sequence with nops.
Signed-off-by: Diana Craciun
Signed-off-by: Michael Ellerman
---
arch/powerpc/kernel/setup_32.c | 1 +
arch/powerpc/kernel/setup_64.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c
index 5a9f035bcd6b..cb37f27bb928 100644
--- a/arch/powerpc/kernel/setup_32.c
+++ b/arch/powerpc/kernel/setup_32.c
@@ -323,6 +323,7 @@ void __init setup_arch(char **cmdline_p)
if ( ppc_md.progress ) ppc_md.progress("arch: exit", 0x3eab);
setup_barrier_nospec();
+ setup_spectre_v2();
paging_init();
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index 6bb731ababc6..11590f6cb2f9 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -737,6 +737,7 @@ void __init setup_arch(char **cmdline_p)
ppc_md.setup_arch();
setup_barrier_nospec();
+ setup_spectre_v2();
paging_init();
--
2.17.1
[PATCH stable v4.4 0/8] missing powerpc spectre backports for 4.4
Hi Greg, These are missing patches from the initial powerpc spectre backports for 4.4. Please queue them as well if you don't have any objections. Thanks, Diana Craciun (8): powerpc/fsl: Enable runtime patching if nospectre_v2 boot arg is used powerpc/fsl: Flush branch predictor when entering KVM powerpc/fsl: Emulate SPRN_BUCSR register powerpc/fsl: Flush the branch predictor at each kernel entry (32 bit) powerpc/fsl: Sanitize the syscall table for NXP PowerPC 32 bit platforms powerpc/fsl: Fixed warning: orphan section `__btb_flush_fixup' powerpc/fsl: Add FSL_PPC_BOOK3E as supported arch for nospectre_v2 boot arg Documentation: Add nospectre_v1 parameter Documentation/kernel-parameters.txt | 6 +- arch/powerpc/kernel/entry_32.S| 10 ++ arch/powerpc/kernel/head_booke.h | 12 arch/powerpc/kernel/head_fsl_booke.S | 15 +++ arch/powerpc/kernel/setup_32.c| 1 + arch/powerpc/kernel/setup_64.c| 1 + arch/powerpc/kvm/bookehv_interrupts.S | 4 arch/powerpc/kvm/e500_emulate.c | 7 +++ 8 files changed, 55 insertions(+), 1 deletion(-) -- 2.17.1
[PATCH] powerpc/fsl: Fixed warning: orphan section `__btb_flush_fixup'
Fixed the following build warning: powerpc-linux-gnu-ld: warning: orphan section `__btb_flush_fixup' from `arch/powerpc/kernel/head_44x.o' being placed in section `__btb_flush_fixup'. Signed-off-by: Diana Craciun --- arch/powerpc/kernel/head_booke.h | 18 -- 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h index 15ac510..306e26c 100644 --- a/arch/powerpc/kernel/head_booke.h +++ b/arch/powerpc/kernel/head_booke.h @@ -32,6 +32,16 @@ */ #define THREAD_NORMSAVE(offset)(THREAD_NORMSAVES + (offset * 4)) +#ifdef CONFIG_PPC_FSL_BOOK3E +#define BOOKE_CLEAR_BTB(reg) \ +START_BTB_FLUSH_SECTION \ + BTB_FLUSH(reg) \ +END_BTB_FLUSH_SECTION +#else +#define BOOKE_CLEAR_BTB(reg) +#endif + + #define NORMAL_EXCEPTION_PROLOG(intno) \ mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \ mfspr r10, SPRN_SPRG_THREAD; \ @@ -43,9 +53,7 @@ andi. r11, r11, MSR_PR; /* check whether user or kernel*/\ mr r11, r1; \ beq 1f; \ -START_BTB_FLUSH_SECTION\ - BTB_FLUSH(r11) \ -END_BTB_FLUSH_SECTION \ + BOOKE_CLEAR_BTB(r11)\ /* if from user, start at top of this thread's kernel stack */ \ lwz r11, THREAD_INFO-THREAD(r10);\ ALLOC_STACK_FRAME(r11, THREAD_SIZE); \ @@ -131,9 +139,7 @@ END_BTB_FLUSH_SECTION \ stw r9,_CCR(r8);/* save CR on stack*/\ mfspr r11,exc_level_srr1; /* check whether user or kernel*/\ DO_KVM BOOKE_INTERRUPT_##intno exc_level_srr1; \ -START_BTB_FLUSH_SECTION \ - BTB_FLUSH(r10) \ -END_BTB_FLUSH_SECTION \ + BOOKE_CLEAR_BTB(r10)\ andi. r11,r11,MSR_PR; \ mfspr r11,SPRN_SPRG_THREAD; /* if from user, start at top of */\ lwz r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\ -- 2.5.5
[PATCH 11/11 v2] powerpc/fsl: Add FSL_PPC_BOOK3E as supported arch for nospectre_v2 boot arg
Signed-off-by: Diana Craciun --- v1-->v2 - no changes Documentation/admin-guide/kernel-parameters.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index aefd358..cf6b4c5 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -2827,7 +2827,7 @@ check bypass). With this option data leaks are possible in the system. - nospectre_v2[X86] Disable all mitigations for the Spectre variant 2 + nospectre_v2[X86,PPC_FSL_BOOK3E] Disable all mitigations for the Spectre variant 2 (indirect branch prediction) vulnerability. System may allow data leaks with this option, which is equivalent to spectre_v2=off. -- 2.5.5
[PATCH 09/11 v2] powerpc/fsl: Enable runtime patching if nospectre_v2 boot arg is used
If the user choses not to use the mitigations, replace the code sequence with nops. Signed-off-by: Diana Craciun --- v1-->v2 - no changes arch/powerpc/kernel/setup-common.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/powerpc/kernel/setup-common.c b/arch/powerpc/kernel/setup-common.c index 93ee370..f27eeda 100644 --- a/arch/powerpc/kernel/setup-common.c +++ b/arch/powerpc/kernel/setup-common.c @@ -974,6 +974,7 @@ void __init setup_arch(char **cmdline_p) ppc_md.setup_arch(); setup_barrier_nospec(); + setup_spectre_v2(); paging_init(); -- 2.5.5
[PATCH 06/11 v2] powerpc/fsl: Flush the branch predictor at each kernel entry (64bit)
In order to protect against speculation attacks on indirect branches, the branch predictor is flushed at kernel entry to protect for the following situations: - userspace process attacking another userspace process - userspace process attacking the kernel Basically when the privillege level change (i.e. the kernel is entered), the branch predictor state is flushed. Signed-off-by: Diana Craciun --- v1-->v2 - no change arch/powerpc/kernel/entry_64.S | 5 + arch/powerpc/kernel/exceptions-64e.S | 26 +- arch/powerpc/mm/tlb_low_64e.S| 7 +++ 3 files changed, 37 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S index 7b1693a..7c2032e 100644 --- a/arch/powerpc/kernel/entry_64.S +++ b/arch/powerpc/kernel/entry_64.S @@ -80,6 +80,11 @@ END_FTR_SECTION_IFSET(CPU_FTR_TM) std r0,GPR0(r1) std r10,GPR1(r1) beq 2f /* if from kernel mode */ +#ifdef CONFIG_PPC_FSL_BOOK3E +START_BTB_FLUSH_SECTION + BTB_FLUSH(r10) +END_BTB_FLUSH_SECTION +#endif ACCOUNT_CPU_USER_ENTRY(r13, r10, r11) 2: std r2,GPR2(r1) std r3,GPR3(r1) diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S index 6d6e144..afb6387 100644 --- a/arch/powerpc/kernel/exceptions-64e.S +++ b/arch/powerpc/kernel/exceptions-64e.S @@ -296,7 +296,8 @@ ret_from_mc_except: andi. r10,r11,MSR_PR; /* save stack pointer */\ beq 1f; /* branch around if supervisor */ \ ld r1,PACAKSAVE(r13); /* get kernel stack coming from usr */\ -1: cmpdi cr1,r1,0; /* check if SP makes sense */ \ +1: type##_BTB_FLUSH\ + cmpdi cr1,r1,0; /* check if SP makes sense */ \ bge-cr1,exc_##n##_bad_stack;/* bad stack (TODO: out of line) */ \ mfspr r10,SPRN_##type##_SRR0; /* read SRR0 before touching stack */ @@ -328,6 +329,29 @@ ret_from_mc_except: #define SPRN_MC_SRR0 SPRN_MCSRR0 #define SPRN_MC_SRR1 SPRN_MCSRR1 +#ifdef CONFIG_PPC_FSL_BOOK3E +#define GEN_BTB_FLUSH \ + START_BTB_FLUSH_SECTION \ + beq 1f; \ + BTB_FLUSH(r10) \ + 1: \ + END_BTB_FLUSH_SECTION + +#define CRIT_BTB_FLUSH \ + START_BTB_FLUSH_SECTION \ + BTB_FLUSH(r10) \ + END_BTB_FLUSH_SECTION + +#define DBG_BTB_FLUSH CRIT_BTB_FLUSH +#define MC_BTB_FLUSH CRIT_BTB_FLUSH +#define GDBELL_BTB_FLUSH GEN_BTB_FLUSH +#else +#define GEN_BTB_FLUSH +#define CRIT_BTB_FLUSH +#define DBG_BTB_FLUSH +#define GDBELL_BTB_FLUSH +#endif + #define NORMAL_EXCEPTION_PROLOG(n, intnum, addition) \ EXCEPTION_PROLOG(n, intnum, GEN, addition##_GEN(n)) diff --git a/arch/powerpc/mm/tlb_low_64e.S b/arch/powerpc/mm/tlb_low_64e.S index 7fd20c5..9ed9006 100644 --- a/arch/powerpc/mm/tlb_low_64e.S +++ b/arch/powerpc/mm/tlb_low_64e.S @@ -70,6 +70,13 @@ END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) std r15,EX_TLB_R15(r12) std r10,EX_TLB_CR(r12) #ifdef CONFIG_PPC_FSL_BOOK3E +START_BTB_FLUSH_SECTION + mfspr r11, SPRN_SRR1 + andi. r10,r11,MSR_PR + beq 1f + BTB_FLUSH(r10) +1: +END_BTB_FLUSH_SECTION std r7,EX_TLB_R7(r12) #endif TLB_MISS_PROLOG_STATS -- 2.5.5
[PATCH 10/11 v2] powerpc/fsl: Update Spectre v2 reporting
Report branch predictor state flush as a mitigation for
Spectre variant 2.
Signed-off-by: Diana Craciun
---
v1-->v2
- no changes
arch/powerpc/kernel/security.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/security.c b/arch/powerpc/kernel/security.c
index 4393a38..861fab3 100644
--- a/arch/powerpc/kernel/security.c
+++ b/arch/powerpc/kernel/security.c
@@ -212,8 +212,11 @@ ssize_t cpu_show_spectre_v2(struct device *dev, struct
device_attribute *attr, c
if (count_cache_flush_type == COUNT_CACHE_FLUSH_HW)
seq_buf_printf(, "(hardware accelerated)");
- } else
+ } else if (btb_flush_enabled) {
+ seq_buf_printf(, "Mitigation: Branch predictor state flush");
+ } else {
seq_buf_printf(, "Vulnerable");
+ }
seq_buf_printf(, "\n");
--
2.5.5
[PATCH 07/11 v2] powerpc/fsl: Flush the branch predictor at each kernel entry (32 bit)
In order to protect against speculation attacks on indirect branches, the branch predictor is flushed at kernel entry to protect for the following situations: - userspace process attacking another userspace process - userspace process attacking the kernel Basically when the privillege level change (i.e.the kernel is entered), the branch predictor state is flushed. Signed-off-by: Diana Craciun --- v1-->v2 - fixed warnings reported by the automated build system arch/powerpc/kernel/head_booke.h | 11 +++ arch/powerpc/kernel/head_fsl_booke.S | 15 +++ 2 files changed, 26 insertions(+) diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h index d0862a1..27f5249 100644 --- a/arch/powerpc/kernel/head_booke.h +++ b/arch/powerpc/kernel/head_booke.h @@ -32,6 +32,15 @@ */ #define THREAD_NORMSAVE(offset)(THREAD_NORMSAVES + (offset * 4)) +#ifdef CONFIG_PPC_FSL_BOOK3E +#define BOOKE_CLEAR_BTB(reg) \ +START_BTB_FLUSH_SECTION \ + BTB_FLUSH(reg) \ +END_BTB_FLUSH_SECTION +#else +#define BOOKE_CLEAR_BTB(reg) +#endif + #define NORMAL_EXCEPTION_PROLOG(intno) \ mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \ mfspr r10, SPRN_SPRG_THREAD; \ @@ -43,6 +52,7 @@ andi. r11, r11, MSR_PR; /* check whether user or kernel*/\ mr r11, r1; \ beq 1f; \ + BOOKE_CLEAR_BTB(r11)\ /* if from user, start at top of this thread's kernel stack */ \ lwz r11, THREAD_INFO-THREAD(r10);\ ALLOC_STACK_FRAME(r11, THREAD_SIZE); \ @@ -128,6 +138,7 @@ stw r9,_CCR(r8);/* save CR on stack*/\ mfspr r11,exc_level_srr1; /* check whether user or kernel*/\ DO_KVM BOOKE_INTERRUPT_##intno exc_level_srr1; \ + BOOKE_CLEAR_BTB(r10)\ andi. r11,r11,MSR_PR; \ mfspr r11,SPRN_SPRG_THREAD; /* if from user, start at top of */\ lwz r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\ diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S index e2750b8..2386ce2 100644 --- a/arch/powerpc/kernel/head_fsl_booke.S +++ b/arch/powerpc/kernel/head_fsl_booke.S @@ -453,6 +453,13 @@ END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) mfcrr13 stw r13, THREAD_NORMSAVE(3)(r10) DO_KVM BOOKE_INTERRUPT_DTLB_MISS SPRN_SRR1 +START_BTB_FLUSH_SECTION + mfspr r11, SPRN_SRR1 + andi. r10,r11,MSR_PR + beq 1f + BTB_FLUSH(r10) +1: +END_BTB_FLUSH_SECTION mfspr r10, SPRN_DEAR /* Get faulting address */ /* If we are faulting a kernel address, we have to use the @@ -547,6 +554,14 @@ END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) mfcrr13 stw r13, THREAD_NORMSAVE(3)(r10) DO_KVM BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR1 +START_BTB_FLUSH_SECTION + mfspr r11, SPRN_SRR1 + andi. r10,r11,MSR_PR + beq 1f + BTB_FLUSH(r10) +1: +END_BTB_FLUSH_SECTION + mfspr r10, SPRN_SRR0 /* Get faulting address */ /* If we are faulting a kernel address, we have to use the -- 2.5.5
[PATCH 01/11 v2] powerpc/fsl: Add infrastructure to fixup branch predictor flush
In order to protect against speculation attacks (Spectre
variant 2) on NXP PowerPC platforms, the branch predictor
should be flushed when the privillege level is changed.
This patch is adding the infrastructure to fixup at runtime
the code sections that are performing the branch predictor flush
depending on a boot arg parameter which is added later in a
separate patch.
Signed-off-by: Diana Craciun
---
v1-->v2
- no change
arch/powerpc/include/asm/feature-fixups.h | 12
arch/powerpc/include/asm/setup.h | 2 ++
arch/powerpc/kernel/vmlinux.lds.S | 8
arch/powerpc/lib/feature-fixups.c | 21 +
4 files changed, 43 insertions(+)
diff --git a/arch/powerpc/include/asm/feature-fixups.h
b/arch/powerpc/include/asm/feature-fixups.h
index 33b6f9c..40a6c926 100644
--- a/arch/powerpc/include/asm/feature-fixups.h
+++ b/arch/powerpc/include/asm/feature-fixups.h
@@ -221,6 +221,17 @@ label##3: \
FTR_ENTRY_OFFSET 953b-954b; \
.popsection;
+#define START_BTB_FLUSH_SECTION\
+955: \
+
+#define END_BTB_FLUSH_SECTION \
+956: \
+ .pushsection __btb_flush_fixup,"a"; \
+ .align 2; \
+957: \
+ FTR_ENTRY_OFFSET 955b-957b; \
+ FTR_ENTRY_OFFSET 956b-957b; \
+ .popsection;
#ifndef __ASSEMBLY__
#include
@@ -230,6 +241,7 @@ extern long __start___stf_entry_barrier_fixup,
__stop___stf_entry_barrier_fixup;
extern long __start___stf_exit_barrier_fixup, __stop___stf_exit_barrier_fixup;
extern long __start___rfi_flush_fixup, __stop___rfi_flush_fixup;
extern long __start___barrier_nospec_fixup, __stop___barrier_nospec_fixup;
+extern long __start__btb_flush_fixup, __stop__btb_flush_fixup;
void apply_feature_fixups(void);
void setup_feature_keys(void);
diff --git a/arch/powerpc/include/asm/setup.h b/arch/powerpc/include/asm/setup.h
index 1fffbba..c941c8c 100644
--- a/arch/powerpc/include/asm/setup.h
+++ b/arch/powerpc/include/asm/setup.h
@@ -67,6 +67,8 @@ void do_barrier_nospec_fixups_range(bool enable, void *start,
void *end);
static inline void do_barrier_nospec_fixups_range(bool enable, void *start,
void *end) { };
#endif
+void do_btb_flush_fixups(void);
+
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_POWERPC_SETUP_H */
diff --git a/arch/powerpc/kernel/vmlinux.lds.S
b/arch/powerpc/kernel/vmlinux.lds.S
index 434581b..254b757 100644
--- a/arch/powerpc/kernel/vmlinux.lds.S
+++ b/arch/powerpc/kernel/vmlinux.lds.S
@@ -170,6 +170,14 @@ SECTIONS
}
#endif /* CONFIG_PPC_BARRIER_NOSPEC */
+#ifdef CONFIG_PPC_FSL_BOOK3E
+ . = ALIGN(8);
+ __spec_btb_flush_fixup : AT(ADDR(__spec_btb_flush_fixup) - LOAD_OFFSET)
{
+ __start__btb_flush_fixup = .;
+ *(__btb_flush_fixup)
+ __stop__btb_flush_fixup = .;
+ }
+#endif
EXCEPTION_TABLE(0)
NOTES :kernel :notes
diff --git a/arch/powerpc/lib/feature-fixups.c
b/arch/powerpc/lib/feature-fixups.c
index e613b02..02a213c 100644
--- a/arch/powerpc/lib/feature-fixups.c
+++ b/arch/powerpc/lib/feature-fixups.c
@@ -347,6 +347,27 @@ void do_barrier_nospec_fixups_range(bool enable, void
*fixup_start, void *fixup_
printk(KERN_DEBUG "barrier-nospec: patched %d locations\n", i);
}
+static void patch_btb_flush_section(long *curr)
+{
+ unsigned int *start, *end;
+
+ start = (void *)curr + *curr;
+ end = (void *)curr + *(curr + 1);
+ for (; start < end; start++) {
+ pr_devel("patching dest %lx\n", (unsigned long)start);
+ patch_instruction(start, PPC_INST_NOP);
+ }
+}
+void do_btb_flush_fixups(void)
+{
+ long *start, *end;
+
+ start = PTRRELOC(&__start__btb_flush_fixup);
+ end = PTRRELOC(&__stop__btb_flush_fixup);
+
+ for (; start < end; start += 2)
+ patch_btb_flush_section(start);
+}
#endif /* CONFIG_PPC_FSL_BOOK3E */
void do_lwsync_fixups(unsigned long value, void *fixup_start, void *fixup_end)
--
2.5.5
[PATCH 00/11 v2] powerpc/fsl: NXP PowerPC Spectre variant 2 workarounds
Implement Spectre variant 2 workarounds for NXP PowerPC Book3E processors. Diana Craciun (11): Add infrastructure to fixup branch predictor flush Add macro to flush the branch predictor Fix spectre_v2 mitigations reporting Emulate SPRN_BUCSR register Add nospectre_v2 command line argument Flush the branch predictor at each kernel entry (64bit) Flush the branch predictor at each kernel entry (32 bit) Flush branch predictor when entering KVM Enable runtime patching if nospectre_v2 boot arg is used Update Spectre v2 reporting Add FSL_PPC_BOOK3E as supported arch for nospectre_v2 boot arg Documentation/admin-guide/kernel-parameters.txt | 2 +- arch/powerpc/include/asm/feature-fixups.h | 12 +++ arch/powerpc/include/asm/ppc_asm.h | 10 + arch/powerpc/include/asm/setup.h| 7 +++ arch/powerpc/kernel/entry_64.S | 5 + arch/powerpc/kernel/exceptions-64e.S| 26 ++- arch/powerpc/kernel/head_booke.h| 11 ++ arch/powerpc/kernel/head_fsl_booke.S| 15 + arch/powerpc/kernel/security.c | 28 +++-- arch/powerpc/kernel/setup-common.c | 1 + arch/powerpc/kernel/vmlinux.lds.S | 8 +++ arch/powerpc/kvm/bookehv_interrupts.S | 4 arch/powerpc/kvm/e500_emulate.c | 5 + arch/powerpc/lib/feature-fixups.c | 21 +++ arch/powerpc/mm/tlb_low_64e.S | 7 +++ 15 files changed, 158 insertions(+), 4 deletions(-) -- 2.5.5
[PATCH 02/11 v2] powerpc/fsl: Add macro to flush the branch predictor
The BUCSR register can be used to invalidate the entries in the branch prediction mechanisms. Signed-off-by: Diana Craciun --- v1-->v2 - no change arch/powerpc/include/asm/ppc_asm.h | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/powerpc/include/asm/ppc_asm.h b/arch/powerpc/include/asm/ppc_asm.h index b5d0236..5c901bf 100644 --- a/arch/powerpc/include/asm/ppc_asm.h +++ b/arch/powerpc/include/asm/ppc_asm.h @@ -821,4 +821,14 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601) stringify_in_c(.long (_target) - . ;) \ stringify_in_c(.previous) +#ifdef CONFIG_PPC_FSL_BOOK3E +#define BTB_FLUSH(reg) \ + lis reg,BUCSR_INIT@h; \ + ori reg,reg,BUCSR_INIT@l; \ + mtspr SPRN_BUCSR,reg; \ + isync; +#else +#define BTB_FLUSH(reg) +#endif /* CONFIG_PPC_FSL_BOOK3E */ + #endif /* _ASM_POWERPC_PPC_ASM_H */ -- 2.5.5
[PATCH 08/11 v2] powerpc/fsl: Flush branch predictor when entering KVM
Switching from the guest to host is another place where the speculative accesses can be exploited. Flush the branch predictor when entering KVM. Signed-off-by: Diana Craciun --- v1-->v2 - no changes arch/powerpc/kvm/bookehv_interrupts.S | 4 1 file changed, 4 insertions(+) diff --git a/arch/powerpc/kvm/bookehv_interrupts.S b/arch/powerpc/kvm/bookehv_interrupts.S index 051af7d..4e5081e 100644 --- a/arch/powerpc/kvm/bookehv_interrupts.S +++ b/arch/powerpc/kvm/bookehv_interrupts.S @@ -75,6 +75,10 @@ PPC_LL r1, VCPU_HOST_STACK(r4) PPC_LL r2, HOST_R2(r1) +START_BTB_FLUSH_SECTION + BTB_FLUSH(r10) +END_BTB_FLUSH_SECTION + mfspr r10, SPRN_PID lwz r8, VCPU_HOST_PID(r4) PPC_LL r11, VCPU_SHARED(r4) -- 2.5.5
[PATCH 04/11 v2] powerpc/fsl: Emulate SPRN_BUCSR register
In order to flush the branch predictor the guest kernel performs writes to the BUCSR register which is hypervisor privilleged. However, the branch predictor is flushed at each KVM entry, so the branch predictor has been already flushed, so just return as soon as possible to guest. Signed-off-by: Diana Craciun --- v1-->v2 - no change arch/powerpc/kvm/e500_emulate.c | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/powerpc/kvm/e500_emulate.c b/arch/powerpc/kvm/e500_emulate.c index 3f8189e..d0eb670 100644 --- a/arch/powerpc/kvm/e500_emulate.c +++ b/arch/powerpc/kvm/e500_emulate.c @@ -276,6 +276,11 @@ int kvmppc_core_emulate_mtspr_e500(struct kvm_vcpu *vcpu, int sprn, ulong spr_va */ vcpu->arch.pwrmgtcr0 = spr_val; break; + /* if we are here, it means that we have already flushed the +* branch predictor, so just return to guest +*/ + case SPRN_BUCSR: + break; /* extra exceptions */ #ifdef CONFIG_SPE_POSSIBLE -- 2.5.5
[PATCH 03/11 v2] powerpc/fsl: Fix spectre_v2 mitigations reporting
Currently for CONFIG_PPC_FSL_BOOK3E
cat /sys/devices/system/cpu/vulnerabilities/spectre_v2 reports:
"Mitigation: Software count cache flush" which is wrong. Fix it
to report vulnerable for now.
Signed-off-by: Diana Craciun
---
v1->v2
- no change
arch/powerpc/kernel/security.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/security.c b/arch/powerpc/kernel/security.c
index f6f469f..1b395b8 100644
--- a/arch/powerpc/kernel/security.c
+++ b/arch/powerpc/kernel/security.c
@@ -22,7 +22,7 @@ enum count_cache_flush_type {
COUNT_CACHE_FLUSH_SW= 0x2,
COUNT_CACHE_FLUSH_HW= 0x4,
};
-static enum count_cache_flush_type count_cache_flush_type;
+static enum count_cache_flush_type count_cache_flush_type =
COUNT_CACHE_FLUSH_NONE;
bool barrier_nospec_enabled;
static bool no_nospec;
--
2.5.5
[PATCH 05/11 v2] powerpc/fsl: Add nospectre_v2 command line argument
When the command line argument is present, the Spectre variant 2
mitigations are disabled.
Signed-off-by: Diana Craciun
---
v1-->v2
- no changes
arch/powerpc/include/asm/setup.h | 5 +
arch/powerpc/kernel/security.c | 21 +
2 files changed, 26 insertions(+)
diff --git a/arch/powerpc/include/asm/setup.h b/arch/powerpc/include/asm/setup.h
index c941c8c..65676e2 100644
--- a/arch/powerpc/include/asm/setup.h
+++ b/arch/powerpc/include/asm/setup.h
@@ -67,6 +67,11 @@ void do_barrier_nospec_fixups_range(bool enable, void
*start, void *end);
static inline void do_barrier_nospec_fixups_range(bool enable, void *start,
void *end) { };
#endif
+#ifdef CONFIG_PPC_FSL_BOOK3E
+void setup_spectre_v2(void);
+#else
+static inline void setup_spectre_v2(void) {};
+#endif
void do_btb_flush_fixups(void);
#endif /* !__ASSEMBLY__ */
diff --git a/arch/powerpc/kernel/security.c b/arch/powerpc/kernel/security.c
index 1b395b8..4393a38 100644
--- a/arch/powerpc/kernel/security.c
+++ b/arch/powerpc/kernel/security.c
@@ -26,6 +26,10 @@ static enum count_cache_flush_type count_cache_flush_type =
COUNT_CACHE_FLUSH_NO
bool barrier_nospec_enabled;
static bool no_nospec;
+static bool btb_flush_enabled;
+#ifdef CONFIG_PPC_FSL_BOOK3E
+static bool no_spectrev2;
+#endif
static void enable_barrier_nospec(bool enable)
{
@@ -101,6 +105,23 @@ static __init int barrier_nospec_debugfs_init(void)
device_initcall(barrier_nospec_debugfs_init);
#endif /* CONFIG_DEBUG_FS */
+#ifdef CONFIG_PPC_FSL_BOOK3E
+static int __init handle_nospectre_v2(char *p)
+{
+ no_spectrev2 = true;
+
+ return 0;
+}
+early_param("nospectre_v2", handle_nospectre_v2);
+void setup_spectre_v2(void)
+{
+ if (no_spectrev2)
+ do_btb_flush_fixups();
+ else
+ btb_flush_enabled = true;
+}
+#endif /* CONFIG_PPC_FSL_BOOK3E */
+
#ifdef CONFIG_PPC_BOOK3S_64
ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
char *buf)
{
--
2.5.5
[PATCH 07/11] powerpc/fsl: Flush the branch predictor at each kernel entry (32 bit)
In order to protect against speculation attacks on indirect branches, the branch predictor is flushed at kernel entry to protect for the following situations: - userspace process attacking another userspace process - userspace process attacking the kernel Basically when the privillege level change (i.e.the kernel is entered), the branch predictor state is flushed. Signed-off-by: Diana Craciun --- arch/powerpc/kernel/head_booke.h | 6 ++ arch/powerpc/kernel/head_fsl_booke.S | 15 +++ 2 files changed, 21 insertions(+) diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h index d0862a1..15ac510 100644 --- a/arch/powerpc/kernel/head_booke.h +++ b/arch/powerpc/kernel/head_booke.h @@ -43,6 +43,9 @@ andi. r11, r11, MSR_PR; /* check whether user or kernel*/\ mr r11, r1; \ beq 1f; \ +START_BTB_FLUSH_SECTION\ + BTB_FLUSH(r11) \ +END_BTB_FLUSH_SECTION \ /* if from user, start at top of this thread's kernel stack */ \ lwz r11, THREAD_INFO-THREAD(r10);\ ALLOC_STACK_FRAME(r11, THREAD_SIZE); \ @@ -128,6 +131,9 @@ stw r9,_CCR(r8);/* save CR on stack*/\ mfspr r11,exc_level_srr1; /* check whether user or kernel*/\ DO_KVM BOOKE_INTERRUPT_##intno exc_level_srr1; \ +START_BTB_FLUSH_SECTION \ + BTB_FLUSH(r10) \ +END_BTB_FLUSH_SECTION \ andi. r11,r11,MSR_PR; \ mfspr r11,SPRN_SPRG_THREAD; /* if from user, start at top of */\ lwz r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\ diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S index e2750b8..2386ce2 100644 --- a/arch/powerpc/kernel/head_fsl_booke.S +++ b/arch/powerpc/kernel/head_fsl_booke.S @@ -453,6 +453,13 @@ END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) mfcrr13 stw r13, THREAD_NORMSAVE(3)(r10) DO_KVM BOOKE_INTERRUPT_DTLB_MISS SPRN_SRR1 +START_BTB_FLUSH_SECTION + mfspr r11, SPRN_SRR1 + andi. r10,r11,MSR_PR + beq 1f + BTB_FLUSH(r10) +1: +END_BTB_FLUSH_SECTION mfspr r10, SPRN_DEAR /* Get faulting address */ /* If we are faulting a kernel address, we have to use the @@ -547,6 +554,14 @@ END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) mfcrr13 stw r13, THREAD_NORMSAVE(3)(r10) DO_KVM BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR1 +START_BTB_FLUSH_SECTION + mfspr r11, SPRN_SRR1 + andi. r10,r11,MSR_PR + beq 1f + BTB_FLUSH(r10) +1: +END_BTB_FLUSH_SECTION + mfspr r10, SPRN_SRR0 /* Get faulting address */ /* If we are faulting a kernel address, we have to use the -- 2.5.5
[PATCH 04/11] powerpc/fsl: Emulate SPRN_BUCSR register
In order to flush the branch predictor the guest kernel performs writes to the BUCSR register which is hypervisor privilleged. However, the branch predictor is flushed at each KVM entry, so the branch predictor has been already flushed, so just return as soon as possible to guest. Signed-off-by: Diana Craciun --- arch/powerpc/kvm/e500_emulate.c | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/powerpc/kvm/e500_emulate.c b/arch/powerpc/kvm/e500_emulate.c index 3f8189e..d0eb670 100644 --- a/arch/powerpc/kvm/e500_emulate.c +++ b/arch/powerpc/kvm/e500_emulate.c @@ -276,6 +276,11 @@ int kvmppc_core_emulate_mtspr_e500(struct kvm_vcpu *vcpu, int sprn, ulong spr_va */ vcpu->arch.pwrmgtcr0 = spr_val; break; + /* if we are here, it means that we have already flushed the +* branch predictor, so just return to guest +*/ + case SPRN_BUCSR: + break; /* extra exceptions */ #ifdef CONFIG_SPE_POSSIBLE -- 2.5.5
[PATCH 00/11] powerpc/fsl: NXP PowerPC Spectre variant 2 workarounds
Implement Spectre variant 2 workarounds for NXP PowerPC Book3E processors. Diana Craciun (11): Add infrastructure to fixup branch predictor flush Add macro to flush the branch predictor Fix spectre_v2 mitigations reporting Emulate SPRN_BUCSR register Add nospectre_v2 command line argument Flush the branch predictor at each kernel entry (64bit) Flush the branch predictor at each kernel entry (32 bit) Flush branch predictor when entering KVM Enable runtime patching if nospectre_v2 boot arg is used Update Spectre v2 reporting Add FSL_PPC_BOOK3E as supported arch for nospectre_v2 boot arg Documentation/admin-guide/kernel-parameters.txt | 2 +- arch/powerpc/include/asm/feature-fixups.h | 12 +++ arch/powerpc/include/asm/ppc_asm.h | 10 + arch/powerpc/include/asm/setup.h| 7 +++ arch/powerpc/kernel/entry_64.S | 5 + arch/powerpc/kernel/exceptions-64e.S| 26 ++- arch/powerpc/kernel/head_booke.h| 6 ++ arch/powerpc/kernel/head_fsl_booke.S| 15 + arch/powerpc/kernel/security.c | 28 +++-- arch/powerpc/kernel/setup-common.c | 1 + arch/powerpc/kernel/vmlinux.lds.S | 8 +++ arch/powerpc/kvm/bookehv_interrupts.S | 4 arch/powerpc/kvm/e500_emulate.c | 5 + arch/powerpc/lib/feature-fixups.c | 21 +++ arch/powerpc/mm/tlb_low_64e.S | 7 +++ 15 files changed, 153 insertions(+), 4 deletions(-) -- 2.5.5
[PATCH 02/11] powerpc/fsl: Add macro to flush the branch predictor
The BUCSR register can be used to invalidate the entries in the branch prediction mechanisms. Signed-off-by: Diana Craciun --- arch/powerpc/include/asm/ppc_asm.h | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/powerpc/include/asm/ppc_asm.h b/arch/powerpc/include/asm/ppc_asm.h index b5d0236..5c901bf 100644 --- a/arch/powerpc/include/asm/ppc_asm.h +++ b/arch/powerpc/include/asm/ppc_asm.h @@ -821,4 +821,14 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601) stringify_in_c(.long (_target) - . ;) \ stringify_in_c(.previous) +#ifdef CONFIG_PPC_FSL_BOOK3E +#define BTB_FLUSH(reg) \ + lis reg,BUCSR_INIT@h; \ + ori reg,reg,BUCSR_INIT@l; \ + mtspr SPRN_BUCSR,reg; \ + isync; +#else +#define BTB_FLUSH(reg) +#endif /* CONFIG_PPC_FSL_BOOK3E */ + #endif /* _ASM_POWERPC_PPC_ASM_H */ -- 2.5.5
[PATCH 10/11] powerpc/fsl: Update Spectre v2 reporting
Report branch predictor state flush as a mitigation for
Spectre variant 2.
Signed-off-by: Diana Craciun
---
arch/powerpc/kernel/security.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/security.c b/arch/powerpc/kernel/security.c
index 4393a38..861fab3 100644
--- a/arch/powerpc/kernel/security.c
+++ b/arch/powerpc/kernel/security.c
@@ -212,8 +212,11 @@ ssize_t cpu_show_spectre_v2(struct device *dev, struct
device_attribute *attr, c
if (count_cache_flush_type == COUNT_CACHE_FLUSH_HW)
seq_buf_printf(, "(hardware accelerated)");
- } else
+ } else if (btb_flush_enabled) {
+ seq_buf_printf(, "Mitigation: Branch predictor state flush");
+ } else {
seq_buf_printf(, "Vulnerable");
+ }
seq_buf_printf(, "\n");
--
2.5.5
[PATCH 09/11] powerpc/fsl: Enable runtime patching if nospectre_v2 boot arg is used
If the user choses not to use the mitigations, replace the code sequence with nops. Signed-off-by: Diana Craciun --- arch/powerpc/kernel/setup-common.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/powerpc/kernel/setup-common.c b/arch/powerpc/kernel/setup-common.c index 93ee370..f27eeda 100644 --- a/arch/powerpc/kernel/setup-common.c +++ b/arch/powerpc/kernel/setup-common.c @@ -974,6 +974,7 @@ void __init setup_arch(char **cmdline_p) ppc_md.setup_arch(); setup_barrier_nospec(); + setup_spectre_v2(); paging_init(); -- 2.5.5
[PATCH 11/11] powerpc/fsl: Add FSL_PPC_BOOK3E as supported arch for nospectre_v2 boot arg
Signed-off-by: Diana Craciun --- Documentation/admin-guide/kernel-parameters.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index aefd358..cf6b4c5 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -2827,7 +2827,7 @@ check bypass). With this option data leaks are possible in the system. - nospectre_v2[X86] Disable all mitigations for the Spectre variant 2 + nospectre_v2[X86,PPC_FSL_BOOK3E] Disable all mitigations for the Spectre variant 2 (indirect branch prediction) vulnerability. System may allow data leaks with this option, which is equivalent to spectre_v2=off. -- 2.5.5
[PATCH 01/11] powerpc/fsl: Add infrastructure to fixup branch predictor flush
In order to protect against speculation attacks (Spectre
variant 2) on NXP PowerPC platforms, the branch predictor
should be flushed when the privillege level is changed.
This patch is adding the infrastructure to fixup at runtime
the code sections that are performing the branch predictor flush
depending on a boot arg parameter which is added later in a
separate patch.
Signed-off-by: Diana Craciun
---
arch/powerpc/include/asm/feature-fixups.h | 12
arch/powerpc/include/asm/setup.h | 2 ++
arch/powerpc/kernel/vmlinux.lds.S | 8
arch/powerpc/lib/feature-fixups.c | 21 +
4 files changed, 43 insertions(+)
diff --git a/arch/powerpc/include/asm/feature-fixups.h
b/arch/powerpc/include/asm/feature-fixups.h
index 33b6f9c..40a6c926 100644
--- a/arch/powerpc/include/asm/feature-fixups.h
+++ b/arch/powerpc/include/asm/feature-fixups.h
@@ -221,6 +221,17 @@ label##3: \
FTR_ENTRY_OFFSET 953b-954b; \
.popsection;
+#define START_BTB_FLUSH_SECTION\
+955: \
+
+#define END_BTB_FLUSH_SECTION \
+956: \
+ .pushsection __btb_flush_fixup,"a"; \
+ .align 2; \
+957: \
+ FTR_ENTRY_OFFSET 955b-957b; \
+ FTR_ENTRY_OFFSET 956b-957b; \
+ .popsection;
#ifndef __ASSEMBLY__
#include
@@ -230,6 +241,7 @@ extern long __start___stf_entry_barrier_fixup,
__stop___stf_entry_barrier_fixup;
extern long __start___stf_exit_barrier_fixup, __stop___stf_exit_barrier_fixup;
extern long __start___rfi_flush_fixup, __stop___rfi_flush_fixup;
extern long __start___barrier_nospec_fixup, __stop___barrier_nospec_fixup;
+extern long __start__btb_flush_fixup, __stop__btb_flush_fixup;
void apply_feature_fixups(void);
void setup_feature_keys(void);
diff --git a/arch/powerpc/include/asm/setup.h b/arch/powerpc/include/asm/setup.h
index 1fffbba..c941c8c 100644
--- a/arch/powerpc/include/asm/setup.h
+++ b/arch/powerpc/include/asm/setup.h
@@ -67,6 +67,8 @@ void do_barrier_nospec_fixups_range(bool enable, void *start,
void *end);
static inline void do_barrier_nospec_fixups_range(bool enable, void *start,
void *end) { };
#endif
+void do_btb_flush_fixups(void);
+
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_POWERPC_SETUP_H */
diff --git a/arch/powerpc/kernel/vmlinux.lds.S
b/arch/powerpc/kernel/vmlinux.lds.S
index 434581b..254b757 100644
--- a/arch/powerpc/kernel/vmlinux.lds.S
+++ b/arch/powerpc/kernel/vmlinux.lds.S
@@ -170,6 +170,14 @@ SECTIONS
}
#endif /* CONFIG_PPC_BARRIER_NOSPEC */
+#ifdef CONFIG_PPC_FSL_BOOK3E
+ . = ALIGN(8);
+ __spec_btb_flush_fixup : AT(ADDR(__spec_btb_flush_fixup) - LOAD_OFFSET)
{
+ __start__btb_flush_fixup = .;
+ *(__btb_flush_fixup)
+ __stop__btb_flush_fixup = .;
+ }
+#endif
EXCEPTION_TABLE(0)
NOTES :kernel :notes
diff --git a/arch/powerpc/lib/feature-fixups.c
b/arch/powerpc/lib/feature-fixups.c
index e613b02..02a213c 100644
--- a/arch/powerpc/lib/feature-fixups.c
+++ b/arch/powerpc/lib/feature-fixups.c
@@ -347,6 +347,27 @@ void do_barrier_nospec_fixups_range(bool enable, void
*fixup_start, void *fixup_
printk(KERN_DEBUG "barrier-nospec: patched %d locations\n", i);
}
+static void patch_btb_flush_section(long *curr)
+{
+ unsigned int *start, *end;
+
+ start = (void *)curr + *curr;
+ end = (void *)curr + *(curr + 1);
+ for (; start < end; start++) {
+ pr_devel("patching dest %lx\n", (unsigned long)start);
+ patch_instruction(start, PPC_INST_NOP);
+ }
+}
+void do_btb_flush_fixups(void)
+{
+ long *start, *end;
+
+ start = PTRRELOC(&__start__btb_flush_fixup);
+ end = PTRRELOC(&__stop__btb_flush_fixup);
+
+ for (; start < end; start += 2)
+ patch_btb_flush_section(start);
+}
#endif /* CONFIG_PPC_FSL_BOOK3E */
void do_lwsync_fixups(unsigned long value, void *fixup_start, void *fixup_end)
--
2.5.5
[PATCH 03/11] powerpc/fsl: Fix spectre_v2 mitigations reporting
Currently for CONFIG_PPC_FSL_BOOK3E
cat /sys/devices/system/cpu/vulnerabilities/spectre_v2 reports:
"Mitigation: Software count cache flush" which is wrong. Fix it
to report vulnerable for now.
Signed-off-by: Diana Craciun
---
arch/powerpc/kernel/security.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/security.c b/arch/powerpc/kernel/security.c
index f6f469f..1b395b8 100644
--- a/arch/powerpc/kernel/security.c
+++ b/arch/powerpc/kernel/security.c
@@ -22,7 +22,7 @@ enum count_cache_flush_type {
COUNT_CACHE_FLUSH_SW= 0x2,
COUNT_CACHE_FLUSH_HW= 0x4,
};
-static enum count_cache_flush_type count_cache_flush_type;
+static enum count_cache_flush_type count_cache_flush_type =
COUNT_CACHE_FLUSH_NONE;
bool barrier_nospec_enabled;
static bool no_nospec;
--
2.5.5
[PATCH 08/11] powerpc/fsl: Flush branch predictor when entering KVM
Switching from the guest to host is another place where the speculative accesses can be exploited. Flush the branch predictor when entering KVM. Signed-off-by: Diana Craciun --- arch/powerpc/kvm/bookehv_interrupts.S | 4 1 file changed, 4 insertions(+) diff --git a/arch/powerpc/kvm/bookehv_interrupts.S b/arch/powerpc/kvm/bookehv_interrupts.S index 051af7d..4e5081e 100644 --- a/arch/powerpc/kvm/bookehv_interrupts.S +++ b/arch/powerpc/kvm/bookehv_interrupts.S @@ -75,6 +75,10 @@ PPC_LL r1, VCPU_HOST_STACK(r4) PPC_LL r2, HOST_R2(r1) +START_BTB_FLUSH_SECTION + BTB_FLUSH(r10) +END_BTB_FLUSH_SECTION + mfspr r10, SPRN_PID lwz r8, VCPU_HOST_PID(r4) PPC_LL r11, VCPU_SHARED(r4) -- 2.5.5
[PATCH 06/11] powerpc/fsl: Flush the branch predictor at each kernel entry (64bit)
In order to protect against speculation attacks on indirect branches, the branch predictor is flushed at kernel entry to protect for the following situations: - userspace process attacking another userspace process - userspace process attacking the kernel Basically when the privillege level change (i.e. the kernel is entered), the branch predictor state is flushed. Signed-off-by: Diana Craciun --- arch/powerpc/kernel/entry_64.S | 5 + arch/powerpc/kernel/exceptions-64e.S | 26 +- arch/powerpc/mm/tlb_low_64e.S| 7 +++ 3 files changed, 37 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S index 7b1693a..7c2032e 100644 --- a/arch/powerpc/kernel/entry_64.S +++ b/arch/powerpc/kernel/entry_64.S @@ -80,6 +80,11 @@ END_FTR_SECTION_IFSET(CPU_FTR_TM) std r0,GPR0(r1) std r10,GPR1(r1) beq 2f /* if from kernel mode */ +#ifdef CONFIG_PPC_FSL_BOOK3E +START_BTB_FLUSH_SECTION + BTB_FLUSH(r10) +END_BTB_FLUSH_SECTION +#endif ACCOUNT_CPU_USER_ENTRY(r13, r10, r11) 2: std r2,GPR2(r1) std r3,GPR3(r1) diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S index 6d6e144..afb6387 100644 --- a/arch/powerpc/kernel/exceptions-64e.S +++ b/arch/powerpc/kernel/exceptions-64e.S @@ -296,7 +296,8 @@ ret_from_mc_except: andi. r10,r11,MSR_PR; /* save stack pointer */\ beq 1f; /* branch around if supervisor */ \ ld r1,PACAKSAVE(r13); /* get kernel stack coming from usr */\ -1: cmpdi cr1,r1,0; /* check if SP makes sense */ \ +1: type##_BTB_FLUSH\ + cmpdi cr1,r1,0; /* check if SP makes sense */ \ bge-cr1,exc_##n##_bad_stack;/* bad stack (TODO: out of line) */ \ mfspr r10,SPRN_##type##_SRR0; /* read SRR0 before touching stack */ @@ -328,6 +329,29 @@ ret_from_mc_except: #define SPRN_MC_SRR0 SPRN_MCSRR0 #define SPRN_MC_SRR1 SPRN_MCSRR1 +#ifdef CONFIG_PPC_FSL_BOOK3E +#define GEN_BTB_FLUSH \ + START_BTB_FLUSH_SECTION \ + beq 1f; \ + BTB_FLUSH(r10) \ + 1: \ + END_BTB_FLUSH_SECTION + +#define CRIT_BTB_FLUSH \ + START_BTB_FLUSH_SECTION \ + BTB_FLUSH(r10) \ + END_BTB_FLUSH_SECTION + +#define DBG_BTB_FLUSH CRIT_BTB_FLUSH +#define MC_BTB_FLUSH CRIT_BTB_FLUSH +#define GDBELL_BTB_FLUSH GEN_BTB_FLUSH +#else +#define GEN_BTB_FLUSH +#define CRIT_BTB_FLUSH +#define DBG_BTB_FLUSH +#define GDBELL_BTB_FLUSH +#endif + #define NORMAL_EXCEPTION_PROLOG(n, intnum, addition) \ EXCEPTION_PROLOG(n, intnum, GEN, addition##_GEN(n)) diff --git a/arch/powerpc/mm/tlb_low_64e.S b/arch/powerpc/mm/tlb_low_64e.S index 7fd20c5..9ed9006 100644 --- a/arch/powerpc/mm/tlb_low_64e.S +++ b/arch/powerpc/mm/tlb_low_64e.S @@ -70,6 +70,13 @@ END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) std r15,EX_TLB_R15(r12) std r10,EX_TLB_CR(r12) #ifdef CONFIG_PPC_FSL_BOOK3E +START_BTB_FLUSH_SECTION + mfspr r11, SPRN_SRR1 + andi. r10,r11,MSR_PR + beq 1f + BTB_FLUSH(r10) +1: +END_BTB_FLUSH_SECTION std r7,EX_TLB_R7(r12) #endif TLB_MISS_PROLOG_STATS -- 2.5.5
[PATCH 05/11] powerpc/fsl: Add nospectre_v2 command line argument
When the command line argument is present, the Spectre variant 2
mitigations are disabled.
Signed-off-by: Diana Craciun
---
arch/powerpc/include/asm/setup.h | 5 +
arch/powerpc/kernel/security.c | 21 +
2 files changed, 26 insertions(+)
diff --git a/arch/powerpc/include/asm/setup.h b/arch/powerpc/include/asm/setup.h
index c941c8c..65676e2 100644
--- a/arch/powerpc/include/asm/setup.h
+++ b/arch/powerpc/include/asm/setup.h
@@ -67,6 +67,11 @@ void do_barrier_nospec_fixups_range(bool enable, void
*start, void *end);
static inline void do_barrier_nospec_fixups_range(bool enable, void *start,
void *end) { };
#endif
+#ifdef CONFIG_PPC_FSL_BOOK3E
+void setup_spectre_v2(void);
+#else
+static inline void setup_spectre_v2(void) {};
+#endif
void do_btb_flush_fixups(void);
#endif /* !__ASSEMBLY__ */
diff --git a/arch/powerpc/kernel/security.c b/arch/powerpc/kernel/security.c
index 1b395b8..4393a38 100644
--- a/arch/powerpc/kernel/security.c
+++ b/arch/powerpc/kernel/security.c
@@ -26,6 +26,10 @@ static enum count_cache_flush_type count_cache_flush_type =
COUNT_CACHE_FLUSH_NO
bool barrier_nospec_enabled;
static bool no_nospec;
+static bool btb_flush_enabled;
+#ifdef CONFIG_PPC_FSL_BOOK3E
+static bool no_spectrev2;
+#endif
static void enable_barrier_nospec(bool enable)
{
@@ -101,6 +105,23 @@ static __init int barrier_nospec_debugfs_init(void)
device_initcall(barrier_nospec_debugfs_init);
#endif /* CONFIG_DEBUG_FS */
+#ifdef CONFIG_PPC_FSL_BOOK3E
+static int __init handle_nospectre_v2(char *p)
+{
+ no_spectrev2 = true;
+
+ return 0;
+}
+early_param("nospectre_v2", handle_nospectre_v2);
+void setup_spectre_v2(void)
+{
+ if (no_spectrev2)
+ do_btb_flush_fixups();
+ else
+ btb_flush_enabled = true;
+}
+#endif /* CONFIG_PPC_FSL_BOOK3E */
+
#ifdef CONFIG_PPC_BOOK3S_64
ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
char *buf)
{
--
2.5.5
[PATCH v4 6/6] powerpc/fsl: Sanitize the syscall table for NXP PowerPC 32 bit platforms
Used barrier_nospec to sanitize the syscall table. Signed-off-by: Diana Craciun --- History: v2-->v3 - included in the series arch/powerpc/kernel/entry_32.S | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S index 973577f..8f05280 100644 --- a/arch/powerpc/kernel/entry_32.S +++ b/arch/powerpc/kernel/entry_32.S @@ -33,6 +33,7 @@ #include #include #include +#include /* * MSR_KERNEL is > 0x1 on 4xx/Book-E since it include MSR_CE. @@ -358,6 +359,15 @@ syscall_dotrace_cont: ori r10,r10,sys_call_table@l slwir0,r0,2 bge-66f + + barrier_nospec_asm + /* +* Prevent the load of the handler below (based on the user-passed +* system call number) being speculatively executed until the test +* against NR_syscalls and branch to .66f above has +* committed. +*/ + lwzxr10,r10,r0 /* Fetch system call handler [ptr] */ mtlrr10 addir9,r1,STACK_FRAME_OVERHEAD -- 2.5.5
[PATCH v4 5/6] powerpc/fsl: Add barrier_nospec implementation for NXP PowerPC Book3E
Implement the barrier_nospec as a isync;sync instruction sequence.
The implementation uses the infrastructure built for BOOK3S 64.
Signed-off-by: Diana Craciun
---
History:
v3-->v4
- fixed compilation issues
v2-->v3
- added PPC_NOSPEC Kconfig
- addressed the review comments
It was a discussion at the previous review cycle about the place in the code
where to call setup_barrier_nospec. I have chosen to call the function in the
common code in order to be re-used on multiple platforms. However, I am not sure
that changes concerning powernv/pseries are correct, I need some input here.
arch/powerpc/include/asm/barrier.h | 12 +---
arch/powerpc/include/asm/setup.h | 6 +-
arch/powerpc/kernel/Makefile | 3 ++-
arch/powerpc/kernel/module.c | 4 +++-
arch/powerpc/kernel/setup-common.c | 2 ++
arch/powerpc/kernel/vmlinux.lds.S | 4 +++-
arch/powerpc/lib/feature-fixups.c | 35 +-
arch/powerpc/platforms/powernv/setup.c | 1 -
arch/powerpc/platforms/pseries/setup.c | 1 -
9 files changed, 58 insertions(+), 10 deletions(-)
diff --git a/arch/powerpc/include/asm/barrier.h
b/arch/powerpc/include/asm/barrier.h
index f67b3f6..0bdfa81 100644
--- a/arch/powerpc/include/asm/barrier.h
+++ b/arch/powerpc/include/asm/barrier.h
@@ -77,19 +77,25 @@ do {
\
})
#ifdef CONFIG_PPC_BOOK3S_64
+#define NOSPEC_BARRIER_SLOT nop
+#elif defined(CONFIG_PPC_FSL_BOOK3E)
+#define NOSPEC_BARRIER_SLOT nop; nop
+#endif /* CONFIG_PPC_BOOK3S_64 */
+
+#ifdef CONFIG_PPC_NOSPEC
/*
* Prevent execution of subsequent instructions until preceding branches have
* been fully resolved and are no longer executing speculatively.
*/
-#define barrier_nospec_asm NOSPEC_BARRIER_FIXUP_SECTION; nop
+#define barrier_nospec_asm NOSPEC_BARRIER_FIXUP_SECTION; NOSPEC_BARRIER_SLOT
// This also acts as a compiler barrier due to the memory clobber.
#define barrier_nospec() asm (stringify_in_c(barrier_nospec_asm) ::: "memory")
-#else /* !CONFIG_PPC_BOOK3S_64 */
+#else /* !CONFIG_PPC_NOSPEC */
#define barrier_nospec_asm
#define barrier_nospec()
-#endif
+#endif /* CONFIG_PPC_NOSPEC */
#include
diff --git a/arch/powerpc/include/asm/setup.h b/arch/powerpc/include/asm/setup.h
index 8721fd0..a794a40 100644
--- a/arch/powerpc/include/asm/setup.h
+++ b/arch/powerpc/include/asm/setup.h
@@ -52,11 +52,15 @@ enum l1d_flush_type {
void setup_rfi_flush(enum l1d_flush_type, bool enable);
void do_rfi_flush_fixups(enum l1d_flush_type types);
+#ifdef CONFIG_PPC_NOSPEC
void setup_barrier_nospec(void);
+#else
+static inline void setup_barrier_nospec(void) { };
+#endif
void do_barrier_nospec_fixups(bool enable);
extern bool barrier_nospec_enabled;
-#ifdef CONFIG_PPC_BOOK3S_64
+#ifdef CONFIG_PPC_NOSPEC
void do_barrier_nospec_fixups_range(bool enable, void *start, void *end);
#else
static inline void do_barrier_nospec_fixups_range(bool enable, void *start,
void *end) { };
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index 2b4c40b2..cd0eb38 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -42,9 +42,10 @@ obj-$(CONFIG_VDSO32) += vdso32/
obj-$(CONFIG_PPC_WATCHDOG) += watchdog.o
obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o
obj-$(CONFIG_PPC_BOOK3S_64)+= cpu_setup_ppc970.o cpu_setup_pa6t.o
-obj-$(CONFIG_PPC_BOOK3S_64)+= cpu_setup_power.o security.o
+obj-$(CONFIG_PPC_BOOK3S_64)+= cpu_setup_power.o
obj-$(CONFIG_PPC_BOOK3S_64)+= mce.o mce_power.o
obj-$(CONFIG_PPC_BOOK3E_64)+= exceptions-64e.o idle_book3e.o
+obj-$(CONFIG_PPC_NOSPEC) += security.o
obj-$(CONFIG_PPC64)+= vdso64/
obj-$(CONFIG_ALTIVEC) += vecemu.o
obj-$(CONFIG_PPC_970_NAP) += idle_power4.o
diff --git a/arch/powerpc/kernel/module.c b/arch/powerpc/kernel/module.c
index 1b3c683..a0c4967 100644
--- a/arch/powerpc/kernel/module.c
+++ b/arch/powerpc/kernel/module.c
@@ -72,13 +72,15 @@ int module_finalize(const Elf_Ehdr *hdr,
do_feature_fixups(powerpc_firmware_features,
(void *)sect->sh_addr,
(void *)sect->sh_addr + sect->sh_size);
+#endif /* CONFIG_PPC64 */
+#if defined(CONFIG_PPC64) || defined(CONFIG_PPC_FSL_BOOK3E)
sect = find_section(hdr, sechdrs, "__spec_barrier_fixup");
if (sect != NULL)
do_barrier_nospec_fixups_range(barrier_nospec_enabled,
(void *)sect->sh_addr,
(void *)sect->sh_addr + sect->sh_size);
-#endif
+#endif /* CONFIG_PPC64 || CONFIG_PPC_FSL_BOOK3E */
sect = find_section(hdr, sechdrs, "__lwsync_fixup");
if (sect != NULL)
diff --git a/arch/powerpc/kernel/setup-common.c
b/arch/powerpc/kernel/setup-common.c
index 40b44bb..93fa0c9 1006
[PATCH v4 4/6] powerpc/fsl: Enable cpu vulnerabilities reporting for NXP PPC BOOK3E
The NXP PPC Book3E platforms are not vulnerable to meltdown and
Spectre v4, so make them PPC_BOOK3S_64 specific.
Signed-off-by: Diana Craciun
---
History:
v2-->v3
- used the existing functions for spectre v1/v2
arch/powerpc/Kconfig | 7 ++-
arch/powerpc/kernel/security.c | 2 ++
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 9f2b75f..116c953 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -165,7 +165,7 @@ config PPC
select GENERIC_CLOCKEVENTS_BROADCASTif SMP
select GENERIC_CMOS_UPDATE
select GENERIC_CPU_AUTOPROBE
- select GENERIC_CPU_VULNERABILITIES if PPC_BOOK3S_64
+ select GENERIC_CPU_VULNERABILITIES if PPC_NOSPEC
select GENERIC_IRQ_SHOW
select GENERIC_IRQ_SHOW_LEVEL
select GENERIC_SMP_IDLE_THREAD
@@ -240,6 +240,11 @@ config PPC
# Please keep this list sorted alphabetically.
#
+config PPC_NOSPEC
+bool
+default y
+depends on PPC_BOOK3S_64 || PPC_FSL_BOOK3E
+
config GENERIC_CSUM
def_bool n
diff --git a/arch/powerpc/kernel/security.c b/arch/powerpc/kernel/security.c
index 3a4e5c3..539c744 100644
--- a/arch/powerpc/kernel/security.c
+++ b/arch/powerpc/kernel/security.c
@@ -92,6 +92,7 @@ static __init int barrier_nospec_debugfs_init(void)
device_initcall(barrier_nospec_debugfs_init);
#endif /* CONFIG_DEBUG_FS */
+#ifdef CONFIG_PPC_BOOK3S_64
ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
char *buf)
{
bool thread_priv;
@@ -124,6 +125,7 @@ ssize_t cpu_show_meltdown(struct device *dev, struct
device_attribute *attr, cha
return sprintf(buf, "Vulnerable\n");
}
+#endif
ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr,
char *buf)
{
--
2.5.5
[PATCH v4 3/6] powerpc/fsl: Make stf barrier PPC_BOOK3S_64 specific.
NXP Book3E platforms are not vulnerable to speculative store bypass, so make the mitigations PPC_BOOK3S_64 specific. Signed-off-by: Diana Craciun --- History: v2-->v3 - new arch/powerpc/kernel/security.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/powerpc/kernel/security.c b/arch/powerpc/kernel/security.c index 2ebfc5b..3a4e5c3 100644 --- a/arch/powerpc/kernel/security.c +++ b/arch/powerpc/kernel/security.c @@ -169,6 +169,7 @@ ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, c return s.len; } +#ifdef CONFIG_PPC_BOOK3S_64 /* * Store-forwarding barrier support. */ @@ -316,3 +317,5 @@ static __init int stf_barrier_debugfs_init(void) } device_initcall(stf_barrier_debugfs_init); #endif /* CONFIG_DEBUG_FS */ +#endif /* CONFIG_PPC_BOOK3S_64 */ + -- 2.5.5
[PATCH v4 2/6] powerpc/fsl: Document nospectre_v1 kernel parameter.
Signed-off-by: Diana Craciun --- History: v2-->v3 - new Documentation/admin-guide/kernel-parameters.txt | 4 1 file changed, 4 insertions(+) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index efc7aa7..b346cc7 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -2687,6 +2687,10 @@ nosmt [KNL,S390] Disable symmetric multithreading (SMT). Equivalent to smt=1. + nospectre_v1[PPC] Disable mitigations for Spectre Variant 1 + (bounds check bypass). With this option data leaks are + possible in the system. + nospectre_v2[X86] Disable all mitigations for the Spectre variant 2 (indirect branch prediction) vulnerability. System may allow data leaks with this option, which is equivalent -- 2.5.5
[PATCH v4 0/6] powerpc/fsl: Speculation barrier for NXP PowerPC Book3E
Implement barrier_nospec for NXP PowerPC Book3E processors. Diana Craciun (6): Disable the speculation barrier from the command line Document nospectre_v1 kernel parameter. Make stf barrier PPC_BOOK3S_64 specific. Enable cpu vulnerabilities reporting for NXP PPC BOOK3E Add barrier_nospec implementation for NXP PowerPC Book3E powerpc/fsl: Sanitize the syscall table for NXP PowerPC 32 bit platforms Documentation/admin-guide/kernel-parameters.txt | 4 +++ arch/powerpc/Kconfig| 7 - arch/powerpc/include/asm/barrier.h | 12 ++--- arch/powerpc/include/asm/setup.h| 6 - arch/powerpc/kernel/Makefile| 3 ++- arch/powerpc/kernel/entry_32.S | 10 +++ arch/powerpc/kernel/module.c| 4 ++- arch/powerpc/kernel/security.c | 17 +++- arch/powerpc/kernel/setup-common.c | 2 ++ arch/powerpc/kernel/vmlinux.lds.S | 4 ++- arch/powerpc/lib/feature-fixups.c | 35 - arch/powerpc/platforms/powernv/setup.c | 1 - arch/powerpc/platforms/pseries/setup.c | 1 - 13 files changed, 94 insertions(+), 12 deletions(-) -- History: v3 --> v4 - fixed compilation issues v2 --> v3 - addressed review comments - included the 32bit sanitization in the same patch series v1 --> v2 - added implementation for cpu_show_spectre_x functions - the mitigation is no longer enabled through device tree options 2.5.5
[PATCH v4 1/6] powerpc/fsl: Disable the speculation barrier from the command line
The speculation barrier can be disabled from the command line
with the parameter: "nospectre_v1".
Signed-off-by: Diana Craciun
---
History:
v2-->v3
- no changes
arch/powerpc/kernel/security.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/security.c b/arch/powerpc/kernel/security.c
index a8b2773..2ebfc5b 100644
--- a/arch/powerpc/kernel/security.c
+++ b/arch/powerpc/kernel/security.c
@@ -16,6 +16,7 @@
unsigned long powerpc_security_features __read_mostly = SEC_FTR_DEFAULT;
bool barrier_nospec_enabled;
+static bool no_nospec;
static void enable_barrier_nospec(bool enable)
{
@@ -42,9 +43,18 @@ void setup_barrier_nospec(void)
enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) &&
security_ftr_enabled(SEC_FTR_BNDS_CHK_SPEC_BAR);
- enable_barrier_nospec(enable);
+ if (!no_nospec)
+ enable_barrier_nospec(enable);
}
+static int __init handle_nospectre_v1(char *p)
+{
+ no_nospec = true;
+
+ return 0;
+}
+early_param("nospectre_v1", handle_nospectre_v1);
+
#ifdef CONFIG_DEBUG_FS
static int barrier_nospec_set(void *data, u64 val)
{
--
2.5.5
[PATCH v3 6/6] powerpc/fsl: Sanitize the syscall table for NXP PowerPC 32 bit platforms
Used barrier_nospec to sanitize the syscall table. Signed-off-by: Diana Craciun --- History: v2-->v3 - included in the series arch/powerpc/kernel/entry_32.S | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S index 973577f..8f05280 100644 --- a/arch/powerpc/kernel/entry_32.S +++ b/arch/powerpc/kernel/entry_32.S @@ -33,6 +33,7 @@ #include #include #include +#include /* * MSR_KERNEL is > 0x1 on 4xx/Book-E since it include MSR_CE. @@ -358,6 +359,15 @@ syscall_dotrace_cont: ori r10,r10,sys_call_table@l slwir0,r0,2 bge-66f + + barrier_nospec_asm + /* +* Prevent the load of the handler below (based on the user-passed +* system call number) being speculatively executed until the test +* against NR_syscalls and branch to .66f above has +* committed. +*/ + lwzxr10,r10,r0 /* Fetch system call handler [ptr] */ mtlrr10 addir9,r1,STACK_FRAME_OVERHEAD -- 2.5.5
[PATCH v3 5/6] powerpc/fsl: Add barrier_nospec implementation for NXP PowerPC Book3E
Implement the barrier_nospec as a isync;sync instruction sequence.
The implementation uses the infrastructure built for BOOK3S 64.
Signed-off-by: Diana Craciun
---
History:
v2-->v3
- added PPC_NOSPEC Kconfig
- addressed the review comments
It was a discussion at the previous review cycle about the place in the code
where to call setup_barrier_nospec. I have chosen to call the function in the
common code in order to be re-used on multiple platforms. However, I am not sure
that changes concerning powernv/pseries are correct, I need some input here.
arch/powerpc/include/asm/barrier.h | 12 +---
arch/powerpc/include/asm/setup.h | 6 +-
arch/powerpc/kernel/Makefile | 3 ++-
arch/powerpc/kernel/module.c | 4 +++-
arch/powerpc/kernel/setup-common.c | 2 ++
arch/powerpc/kernel/vmlinux.lds.S | 4 +++-
arch/powerpc/lib/feature-fixups.c | 35 +-
arch/powerpc/platforms/powernv/setup.c | 1 -
arch/powerpc/platforms/pseries/setup.c | 1 -
9 files changed, 58 insertions(+), 10 deletions(-)
diff --git a/arch/powerpc/include/asm/barrier.h
b/arch/powerpc/include/asm/barrier.h
index f67b3f6..0bdfa81 100644
--- a/arch/powerpc/include/asm/barrier.h
+++ b/arch/powerpc/include/asm/barrier.h
@@ -77,19 +77,25 @@ do {
\
})
#ifdef CONFIG_PPC_BOOK3S_64
+#define NOSPEC_BARRIER_SLOT nop
+#elif defined(CONFIG_PPC_FSL_BOOK3E)
+#define NOSPEC_BARRIER_SLOT nop; nop
+#endif /* CONFIG_PPC_BOOK3S_64 */
+
+#ifdef CONFIG_PPC_NOSPEC
/*
* Prevent execution of subsequent instructions until preceding branches have
* been fully resolved and are no longer executing speculatively.
*/
-#define barrier_nospec_asm NOSPEC_BARRIER_FIXUP_SECTION; nop
+#define barrier_nospec_asm NOSPEC_BARRIER_FIXUP_SECTION; NOSPEC_BARRIER_SLOT
// This also acts as a compiler barrier due to the memory clobber.
#define barrier_nospec() asm (stringify_in_c(barrier_nospec_asm) ::: "memory")
-#else /* !CONFIG_PPC_BOOK3S_64 */
+#else /* !CONFIG_PPC_NOSPEC */
#define barrier_nospec_asm
#define barrier_nospec()
-#endif
+#endif /* CONFIG_PPC_NOSPEC */
#include
diff --git a/arch/powerpc/include/asm/setup.h b/arch/powerpc/include/asm/setup.h
index 8721fd0..1abe152 100644
--- a/arch/powerpc/include/asm/setup.h
+++ b/arch/powerpc/include/asm/setup.h
@@ -52,11 +52,15 @@ enum l1d_flush_type {
void setup_rfi_flush(enum l1d_flush_type, bool enable);
void do_rfi_flush_fixups(enum l1d_flush_type types);
+#ifdef CONFIG_PPC_NOSPEC
void setup_barrier_nospec(void);
+#else
+void setup_barrier_nospec(void) { };
+#endif
void do_barrier_nospec_fixups(bool enable);
extern bool barrier_nospec_enabled;
-#ifdef CONFIG_PPC_BOOK3S_64
+#ifdef CONFIG_PPC_NOSPEC
void do_barrier_nospec_fixups_range(bool enable, void *start, void *end);
#else
static inline void do_barrier_nospec_fixups_range(bool enable, void *start,
void *end) { };
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index 2b4c40b2..cd0eb38 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -42,9 +42,10 @@ obj-$(CONFIG_VDSO32) += vdso32/
obj-$(CONFIG_PPC_WATCHDOG) += watchdog.o
obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o
obj-$(CONFIG_PPC_BOOK3S_64)+= cpu_setup_ppc970.o cpu_setup_pa6t.o
-obj-$(CONFIG_PPC_BOOK3S_64)+= cpu_setup_power.o security.o
+obj-$(CONFIG_PPC_BOOK3S_64)+= cpu_setup_power.o
obj-$(CONFIG_PPC_BOOK3S_64)+= mce.o mce_power.o
obj-$(CONFIG_PPC_BOOK3E_64)+= exceptions-64e.o idle_book3e.o
+obj-$(CONFIG_PPC_NOSPEC) += security.o
obj-$(CONFIG_PPC64)+= vdso64/
obj-$(CONFIG_ALTIVEC) += vecemu.o
obj-$(CONFIG_PPC_970_NAP) += idle_power4.o
diff --git a/arch/powerpc/kernel/module.c b/arch/powerpc/kernel/module.c
index 1b3c683..a0c4967 100644
--- a/arch/powerpc/kernel/module.c
+++ b/arch/powerpc/kernel/module.c
@@ -72,13 +72,15 @@ int module_finalize(const Elf_Ehdr *hdr,
do_feature_fixups(powerpc_firmware_features,
(void *)sect->sh_addr,
(void *)sect->sh_addr + sect->sh_size);
+#endif /* CONFIG_PPC64 */
+#if defined(CONFIG_PPC64) || defined(CONFIG_PPC_FSL_BOOK3E)
sect = find_section(hdr, sechdrs, "__spec_barrier_fixup");
if (sect != NULL)
do_barrier_nospec_fixups_range(barrier_nospec_enabled,
(void *)sect->sh_addr,
(void *)sect->sh_addr + sect->sh_size);
-#endif
+#endif /* CONFIG_PPC64 || CONFIG_PPC_FSL_BOOK3E */
sect = find_section(hdr, sechdrs, "__lwsync_fixup");
if (sect != NULL)
diff --git a/arch/powerpc/kernel/setup-common.c
b/arch/powerpc/kernel/setup-common.c
index 40b44bb..93fa0c9 100644
--- a/arch/powerpc/kernel/setup-common.c
+++ b/arch/pow
[PATCH v3 4/6] powerpc/fsl: Enable cpu vulnerabilities reporting for NXP PPC BOOK3E
The NXP PPC Book3E platforms are not vulnerable to meltdown, so make it
PPC_BOOK3S_64 specific.
Signed-off-by: Diana Craciun
---
History:
v2-->v3
- used the existing functions for spectre v1/v2
arch/powerpc/Kconfig | 7 ++-
arch/powerpc/kernel/security.c | 2 ++
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 9f2b75f..116c953 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -165,7 +165,7 @@ config PPC
select GENERIC_CLOCKEVENTS_BROADCASTif SMP
select GENERIC_CMOS_UPDATE
select GENERIC_CPU_AUTOPROBE
- select GENERIC_CPU_VULNERABILITIES if PPC_BOOK3S_64
+ select GENERIC_CPU_VULNERABILITIES if PPC_NOSPEC
select GENERIC_IRQ_SHOW
select GENERIC_IRQ_SHOW_LEVEL
select GENERIC_SMP_IDLE_THREAD
@@ -240,6 +240,11 @@ config PPC
# Please keep this list sorted alphabetically.
#
+config PPC_NOSPEC
+bool
+default y
+depends on PPC_BOOK3S_64 || PPC_FSL_BOOK3E
+
config GENERIC_CSUM
def_bool n
diff --git a/arch/powerpc/kernel/security.c b/arch/powerpc/kernel/security.c
index 3a4e5c3..539c744 100644
--- a/arch/powerpc/kernel/security.c
+++ b/arch/powerpc/kernel/security.c
@@ -92,6 +92,7 @@ static __init int barrier_nospec_debugfs_init(void)
device_initcall(barrier_nospec_debugfs_init);
#endif /* CONFIG_DEBUG_FS */
+#ifdef CONFIG_PPC_BOOK3S_64
ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
char *buf)
{
bool thread_priv;
@@ -124,6 +125,7 @@ ssize_t cpu_show_meltdown(struct device *dev, struct
device_attribute *attr, cha
return sprintf(buf, "Vulnerable\n");
}
+#endif
ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr,
char *buf)
{
--
2.5.5
[PATCH v3 3/6] powerpc/fsl: Make stf barrier PPC_BOOK3S_64 specific.
NXP Book3E platforms are not vulnerable to speculative store bypass, so make the mitigations PPC_BOOK3S_64 specific. Signed-off-by: Diana Craciun --- History: v2-->v3 - new arch/powerpc/kernel/security.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/powerpc/kernel/security.c b/arch/powerpc/kernel/security.c index 2ebfc5b..3a4e5c3 100644 --- a/arch/powerpc/kernel/security.c +++ b/arch/powerpc/kernel/security.c @@ -169,6 +169,7 @@ ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, c return s.len; } +#ifdef CONFIG_PPC_BOOK3S_64 /* * Store-forwarding barrier support. */ @@ -316,3 +317,5 @@ static __init int stf_barrier_debugfs_init(void) } device_initcall(stf_barrier_debugfs_init); #endif /* CONFIG_DEBUG_FS */ +#endif /* CONFIG_PPC_BOOK3S_64 */ + -- 2.5.5
[PATCH v3 2/6] powerpc/fsl: Document nospectre_v1 kernel parameter.
Signed-off-by: Diana Craciun --- History: v2-->v3 - new Documentation/admin-guide/kernel-parameters.txt | 4 1 file changed, 4 insertions(+) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index efc7aa7..b346cc7 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -2687,6 +2687,10 @@ nosmt [KNL,S390] Disable symmetric multithreading (SMT). Equivalent to smt=1. + nospectre_v1[PPC] Disable mitigations for Spectre Variant 1 + (bounds check bypass). With this option data leaks are + possible in the system. + nospectre_v2[X86] Disable all mitigations for the Spectre variant 2 (indirect branch prediction) vulnerability. System may allow data leaks with this option, which is equivalent -- 2.5.5
[PATCH v3 0/6] powerpc/fsl: Speculation barrier for NXP PowerPC Book3E
Implement barrier_nospec for NXP PowerPC Book3E processors. Diana Craciun (6): Disable the speculation barrier from the command line Document nospectre_v1 kernel parameter. Make stf barrier PPC_BOOK3S_64 specific. Enable cpu vulnerabilities reporting for NXP PPC BOOK3E Add barrier_nospec implementation for NXP PowerPC Book3E powerpc/fsl: Sanitize the syscall table for NXP PowerPC 32 bit platforms Documentation/admin-guide/kernel-parameters.txt | 4 +++ arch/powerpc/Kconfig| 7 - arch/powerpc/include/asm/barrier.h | 12 ++--- arch/powerpc/include/asm/setup.h| 6 - arch/powerpc/kernel/Makefile| 3 ++- arch/powerpc/kernel/entry_32.S | 10 +++ arch/powerpc/kernel/module.c| 4 ++- arch/powerpc/kernel/security.c | 17 +++- arch/powerpc/kernel/setup-common.c | 2 ++ arch/powerpc/kernel/vmlinux.lds.S | 4 ++- arch/powerpc/lib/feature-fixups.c | 35 - arch/powerpc/platforms/powernv/setup.c | 1 - arch/powerpc/platforms/pseries/setup.c | 1 - 13 files changed, 94 insertions(+), 12 deletions(-) -- History: v2 --> v3 - addressed review comments - included the 32bit sanitization in the same patch series v1 --> v2 - added implementation for cpu_show_spectre_x functions - the mitigation is no longer enabled through device tree options 2.5.5
[PATCH v3 1/6] powerpc/fsl: Disable the speculation barrier from the command line
The speculation barrier can be disabled from the command line
with the parameter: "nospectre_v1".
Signed-off-by: Diana Craciun
---
History:
v2-->v3
- no changes
arch/powerpc/kernel/security.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/security.c b/arch/powerpc/kernel/security.c
index a8b2773..2ebfc5b 100644
--- a/arch/powerpc/kernel/security.c
+++ b/arch/powerpc/kernel/security.c
@@ -16,6 +16,7 @@
unsigned long powerpc_security_features __read_mostly = SEC_FTR_DEFAULT;
bool barrier_nospec_enabled;
+static bool no_nospec;
static void enable_barrier_nospec(bool enable)
{
@@ -42,9 +43,18 @@ void setup_barrier_nospec(void)
enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) &&
security_ftr_enabled(SEC_FTR_BNDS_CHK_SPEC_BAR);
- enable_barrier_nospec(enable);
+ if (!no_nospec)
+ enable_barrier_nospec(enable);
}
+static int __init handle_nospectre_v1(char *p)
+{
+ no_nospec = true;
+
+ return 0;
+}
+early_param("nospectre_v1", handle_nospectre_v1);
+
#ifdef CONFIG_DEBUG_FS
static int barrier_nospec_set(void *data, u64 val)
{
--
2.5.5
[PATCH] powerpc/fsl: Sanitize the syscall table for NXP PowerPC 32 bit platforms
Used barrier_nospec to sanitize the syscall table. Signed-off-by: Diana Craciun --- arch/powerpc/kernel/entry_32.S | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S index eb8d01b..e3ff9ace 100644 --- a/arch/powerpc/kernel/entry_32.S +++ b/arch/powerpc/kernel/entry_32.S @@ -33,6 +33,7 @@ #include #include #include +#include /* * MSR_KERNEL is > 0x1 on 4xx/Book-E since it include MSR_CE. @@ -358,6 +359,15 @@ syscall_dotrace_cont: ori r10,r10,sys_call_table@l slwir0,r0,2 bge-66f + + barrier_nospec_asm + /* +* Prevent the load of the handler below (based on the user-passed +* system call number) being speculatively executed until the test +* against NR_syscalls and branch to .66f above has +* committed. +*/ + lwzxr10,r10,r0 /* Fetch system call handler [ptr] */ mtlrr10 addir9,r1,STACK_FRAME_OVERHEAD -- 2.5.5
[PATCH v2 3/3] powerpc/fsl: Implement cpu_show_spectre_v1/v2 for NXP PowerPC Book3E
Signed-off-by: Diana Craciun
---
arch/powerpc/Kconfig | 2 +-
arch/powerpc/kernel/security.c | 15 +++
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 940c955..a781d60 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -170,7 +170,7 @@ config PPC
select GENERIC_CLOCKEVENTS_BROADCASTif SMP
select GENERIC_CMOS_UPDATE
select GENERIC_CPU_AUTOPROBE
- select GENERIC_CPU_VULNERABILITIES if PPC_BOOK3S_64
+ select GENERIC_CPU_VULNERABILITIES if PPC_BOOK3S_64 ||
PPC_FSL_BOOK3E
select GENERIC_IRQ_SHOW
select GENERIC_IRQ_SHOW_LEVEL
select GENERIC_SMP_IDLE_THREAD
diff --git a/arch/powerpc/kernel/security.c b/arch/powerpc/kernel/security.c
index 797c975..aceaadc 100644
--- a/arch/powerpc/kernel/security.c
+++ b/arch/powerpc/kernel/security.c
@@ -183,3 +183,18 @@ ssize_t cpu_show_spectre_v2(struct device *dev, struct
device_attribute *attr, c
}
#endif /* CONFIG_PPC_BOOK3S_64 */
+#ifdef CONFIG_PPC_FSL_BOOK3E
+ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr,
char *buf)
+{
+ if (barrier_nospec_enabled)
+ return sprintf(buf, "Mitigation: __user pointer
sanitization\n");
+
+ return sprintf(buf, "Vulnerable\n");
+}
+
+ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr,
char *buf)
+{
+ return sprintf(buf, "Vulnerable\n");
+}
+#endif /* CONFIG_PPC_FSL_BOOK3E */
+
--
2.5.5
[PATCH v2 2/3] powerpc/fsl: Add barrier_nospec implementation for NXP PowerPC Book3E
Implement the barrier_nospec as a isync;sync instruction sequence.
The implementation uses the infrastructure built for BOOK3S 64.
Signed-off-by: Diana Craciun
---
arch/powerpc/include/asm/barrier.h | 10 ++
arch/powerpc/include/asm/setup.h | 2 +-
arch/powerpc/kernel/Makefile | 2 +-
arch/powerpc/kernel/module.c | 5 +++--
arch/powerpc/kernel/security.c | 15 +++
arch/powerpc/kernel/setup_32.c | 5 +
arch/powerpc/kernel/setup_64.c | 6 ++
arch/powerpc/kernel/vmlinux.lds.S | 4 +++-
arch/powerpc/lib/feature-fixups.c | 35 ++-
9 files changed, 78 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/include/asm/barrier.h
b/arch/powerpc/include/asm/barrier.h
index f67b3f6..405d572 100644
--- a/arch/powerpc/include/asm/barrier.h
+++ b/arch/powerpc/include/asm/barrier.h
@@ -86,6 +86,16 @@ do {
\
// This also acts as a compiler barrier due to the memory clobber.
#define barrier_nospec() asm (stringify_in_c(barrier_nospec_asm) ::: "memory")
+#elif defined(CONFIG_PPC_FSL_BOOK3E)
+/*
+ * Prevent the execution of subsequent instructions speculatively using a
+ * isync;sync instruction sequence.
+ */
+#define barrier_nospec_asm NOSPEC_BARRIER_FIXUP_SECTION; nop; nop
+
+// This also acts as a compiler barrier due to the memory clobber.
+#define barrier_nospec() asm (stringify_in_c(barrier_nospec_asm) ::: "memory")
+
#else /* !CONFIG_PPC_BOOK3S_64 */
#define barrier_nospec_asm
#define barrier_nospec()
diff --git a/arch/powerpc/include/asm/setup.h b/arch/powerpc/include/asm/setup.h
index 8721fd0..67a2810 100644
--- a/arch/powerpc/include/asm/setup.h
+++ b/arch/powerpc/include/asm/setup.h
@@ -56,7 +56,7 @@ void setup_barrier_nospec(void);
void do_barrier_nospec_fixups(bool enable);
extern bool barrier_nospec_enabled;
-#ifdef CONFIG_PPC_BOOK3S_64
+#if defined(CONFIG_PPC_BOOK3S_64) || defined(CONFIG_PPC_FSL_BOOK3E)
void do_barrier_nospec_fixups_range(bool enable, void *start, void *end);
#else
static inline void do_barrier_nospec_fixups_range(bool enable, void *start,
void *end) { };
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index 2b4c40b2..d9dee43 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -76,7 +76,7 @@ endif
obj64-$(CONFIG_HIBERNATION)+= swsusp_asm64.o
obj-$(CONFIG_MODULES) += module.o module_$(BITS).o
obj-$(CONFIG_44x) += cpu_setup_44x.o
-obj-$(CONFIG_PPC_FSL_BOOK3E) += cpu_setup_fsl_booke.o
+obj-$(CONFIG_PPC_FSL_BOOK3E) += cpu_setup_fsl_booke.o security.o
obj-$(CONFIG_PPC_DOORBELL) += dbell.o
obj-$(CONFIG_JUMP_LABEL) += jump_label.o
diff --git a/arch/powerpc/kernel/module.c b/arch/powerpc/kernel/module.c
index 1b3c683..96a9821 100644
--- a/arch/powerpc/kernel/module.c
+++ b/arch/powerpc/kernel/module.c
@@ -72,13 +72,14 @@ int module_finalize(const Elf_Ehdr *hdr,
do_feature_fixups(powerpc_firmware_features,
(void *)sect->sh_addr,
(void *)sect->sh_addr + sect->sh_size);
-
+#endif /* CONFIG_PPC64 */
+#if defined(CONFIG_PPC64) || defined(CONFIG_PPC_FSL_BOOK3E)
sect = find_section(hdr, sechdrs, "__spec_barrier_fixup");
if (sect != NULL)
do_barrier_nospec_fixups_range(barrier_nospec_enabled,
(void *)sect->sh_addr,
(void *)sect->sh_addr + sect->sh_size);
-#endif
+#endif /* CONFIG_PPC64 || CONFIG_PPC_FSL_BOOK3E */
sect = find_section(hdr, sechdrs, "__lwsync_fixup");
if (sect != NULL)
diff --git a/arch/powerpc/kernel/security.c b/arch/powerpc/kernel/security.c
index c55e102..797c975 100644
--- a/arch/powerpc/kernel/security.c
+++ b/arch/powerpc/kernel/security.c
@@ -13,7 +13,9 @@
#include
+#ifdef CONFIG_PPC_BOOK3S_64
unsigned long powerpc_security_features __read_mostly = SEC_FTR_DEFAULT;
+#endif /* CONFIG_PPC_BOOK3S_64 */
bool barrier_nospec_enabled;
static bool no_nospec;
@@ -24,6 +26,7 @@ static void enable_barrier_nospec(bool enable)
do_barrier_nospec_fixups(enable);
}
+#ifdef CONFIG_PPC_BOOK3S_64
void setup_barrier_nospec(void)
{
bool enable;
@@ -46,6 +49,15 @@ void setup_barrier_nospec(void)
if (!no_nospec)
enable_barrier_nospec(enable);
}
+#endif /* CONFIG_PPC_BOOK3S_64 */
+
+#ifdef CONFIG_PPC_FSL_BOOK3E
+void setup_barrier_nospec(void)
+{
+ if (!no_nospec)
+ enable_barrier_nospec(true);
+}
+#endif /* CONFIG_PPC_FSL_BOOK3E */
static int __init handle_nospectre_v1(char *p)
{
@@ -92,6 +104,7 @@ static __init int barrier_nospec_debugfs_init(void)
device_initcall(barrier_nospec_debugfs_init);
#endif /* CONFIG_DEBUG_FS */
+#ifdef CONFIG_PPC_BOOK3S_64
ssize_t cpu_show_meltdown(str
[PATCH v2 0/3] powerpc/fsl: Speculation barrier for NXP PowerPC Book3E
Implement barrier_nospec for NXP PowerPC Book3E processors. Diana Craciun (3): Disable the speculation barrier from the command line Add barrier_nospec implementation for NXP PowerPC Book3E Implement cpu_show_spectre_v1/v2 for NXP PowerPC Book3E arch/powerpc/Kconfig | 2 +- arch/powerpc/include/asm/barrier.h | 10 + arch/powerpc/include/asm/setup.h | 2 +- arch/powerpc/kernel/Makefile | 2 +- arch/powerpc/kernel/module.c | 5 +++-- arch/powerpc/kernel/security.c | 42 +- arch/powerpc/kernel/setup_32.c | 5 + arch/powerpc/kernel/setup_64.c | 6 ++ arch/powerpc/kernel/vmlinux.lds.S | 4 +++- arch/powerpc/lib/feature-fixups.c | 35 ++- 10 files changed, 105 insertions(+), 8 deletions(-) -- History: v1 --> v2 - added implementation for cpu_show_spectre_x functions - the mitigation is no longer enabled through device tree options 2.5.5
[PATCH v2 1/3] powerpc/fsl: Disable the speculation barrier from the command line
The speculation barrier can be disabled from the command line
with the parameter: "nospectre_v1".
Signed-off-by: Diana Craciun
---
arch/powerpc/kernel/security.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/security.c b/arch/powerpc/kernel/security.c
index 3eb9c45..c55e102 100644
--- a/arch/powerpc/kernel/security.c
+++ b/arch/powerpc/kernel/security.c
@@ -16,6 +16,7 @@
unsigned long powerpc_security_features __read_mostly = SEC_FTR_DEFAULT;
bool barrier_nospec_enabled;
+static bool no_nospec;
static void enable_barrier_nospec(bool enable)
{
@@ -42,9 +43,18 @@ void setup_barrier_nospec(void)
enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) &&
security_ftr_enabled(SEC_FTR_BNDS_CHK_SPEC_BAR);
- enable_barrier_nospec(enable);
+ if (!no_nospec)
+ enable_barrier_nospec(enable);
}
+static int __init handle_nospectre_v1(char *p)
+{
+ no_nospec = true;
+
+ return 0;
+}
+early_param("nospectre_v1", handle_nospectre_v1);
+
#ifdef CONFIG_DEBUG_FS
static int barrier_nospec_set(void *data, u64 val)
{
--
2.5.5
[RESEND RFC PATCH] powerpc/fsl: Add barrier_nospec implementation for NXP PowerPC Book E
Implement the barrier_nospec as a isync;sync instruction sequence.
The implementation uses the infrastructure built for BOOK3S 64
with the difference that for NXP platforms there is no firmware involved
and the need for a speculation barrier is read from the device tree.
I have used the same name for the property:
fsl,needs-spec-barrier-for-bounds-check
Signed-off-by: Diana Craciun <diana.crac...@nxp.com>
---
The patches were created on top of the BOOK3S 64 patches:
https://lists.ozlabs.org/pipermail/linuxppc-dev/2018-April/172137.html
arch/powerpc/include/asm/barrier.h| 12 -
arch/powerpc/include/asm/setup.h | 2 +-
arch/powerpc/kernel/Makefile | 2 +-
arch/powerpc/kernel/module.c | 2 ++
arch/powerpc/kernel/security.c| 12 -
arch/powerpc/kernel/vmlinux.lds.S | 2 ++
arch/powerpc/lib/feature-fixups.c | 38 +--
arch/powerpc/platforms/85xx/corenet_generic.c | 17
8 files changed, 81 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/include/asm/barrier.h
b/arch/powerpc/include/asm/barrier.h
index f67b3f6..1379386 100644
--- a/arch/powerpc/include/asm/barrier.h
+++ b/arch/powerpc/include/asm/barrier.h
@@ -86,7 +86,17 @@ do {
\
// This also acts as a compiler barrier due to the memory clobber.
#define barrier_nospec() asm (stringify_in_c(barrier_nospec_asm) ::: "memory")
-#else /* !CONFIG_PPC_BOOK3S_64 */
+#elif defined(CONFIG_PPC_FSL_BOOK3E)
+/*
+ * Prevent the execution of subsequent instructions speculatively using a
+ * isync;sync instruction sequence.
+ */
+#define barrier_nospec_asm NOSPEC_BARRIER_FIXUP_SECTION; nop; nop
+
+// This also acts as a compiler barrier due to the memory clobber.
+#define barrier_nospec() asm (stringify_in_c(barrier_nospec_asm) ::: "memory")
+
+#else /* !CONFIG_PPC_BOOK3S_64 && !CONFIG_PPC_FSL_BOOK3E */
#define barrier_nospec_asm
#define barrier_nospec()
#endif
diff --git a/arch/powerpc/include/asm/setup.h b/arch/powerpc/include/asm/setup.h
index aeb175e8..fbc3ef7 100644
--- a/arch/powerpc/include/asm/setup.h
+++ b/arch/powerpc/include/asm/setup.h
@@ -55,7 +55,7 @@ void do_rfi_flush_fixups(enum l1d_flush_type types);
void setup_barrier_nospec(void);
void do_barrier_nospec_fixups(bool enable);
-#ifdef CONFIG_PPC_BOOK3S_64
+#if defined(CONFIG_PPC_BOOK3S_64) || defined(CONFIG_PPC_FSL_BOOK3E)
void do_barrier_nospec_fixups_range(bool enable, void *start, void *end);
#else
static inline void do_barrier_nospec_fixups_range(bool enable, void *start,
void *end) { };
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index 2b4c40b2..d9dee43 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -76,7 +76,7 @@ endif
obj64-$(CONFIG_HIBERNATION)+= swsusp_asm64.o
obj-$(CONFIG_MODULES) += module.o module_$(BITS).o
obj-$(CONFIG_44x) += cpu_setup_44x.o
-obj-$(CONFIG_PPC_FSL_BOOK3E) += cpu_setup_fsl_booke.o
+obj-$(CONFIG_PPC_FSL_BOOK3E) += cpu_setup_fsl_booke.o security.o
obj-$(CONFIG_PPC_DOORBELL) += dbell.o
obj-$(CONFIG_JUMP_LABEL) += jump_label.o
diff --git a/arch/powerpc/kernel/module.c b/arch/powerpc/kernel/module.c
index a72698c..ede64a5 100644
--- a/arch/powerpc/kernel/module.c
+++ b/arch/powerpc/kernel/module.c
@@ -72,7 +72,9 @@ int module_finalize(const Elf_Ehdr *hdr,
do_feature_fixups(powerpc_firmware_features,
(void *)sect->sh_addr,
(void *)sect->sh_addr + sect->sh_size);
+#endif
+#if defined(CONFIG_PPC64) || defined(CONFIG_PPC_FSL_BOOK3E)
sect = find_section(hdr, sechdrs, "__spec_barrier_fixup");
if (sect != NULL)
do_barrier_nospec_fixups_range(true,
diff --git a/arch/powerpc/kernel/security.c b/arch/powerpc/kernel/security.c
index d1b9639..01b6c55 100644
--- a/arch/powerpc/kernel/security.c
+++ b/arch/powerpc/kernel/security.c
@@ -12,8 +12,9 @@
#include
#include
-
+#ifdef CONFIG_PPC_BOOK3S_64
unsigned long powerpc_security_features __read_mostly = SEC_FTR_DEFAULT;
+#endif
static bool barrier_nospec_enabled;
@@ -23,6 +24,7 @@ static void enable_barrier_nospec(bool enable)
do_barrier_nospec_fixups(enable);
}
+#ifdef CONFIG_PPC_BOOK3S_64
void setup_barrier_nospec(void)
{
bool enable;
@@ -44,6 +46,12 @@ void setup_barrier_nospec(void)
enable_barrier_nospec(enable);
}
+#elif CONFIG_PPC_FSL_BOOK3E
+void setup_barrier_nospec(void)
+{
+ enable_barrier_nospec(true);
+}
+#endif
#ifdef CONFIG_DEBUG_FS
static int barrier_nospec_set(void *data, u64 val)
@@ -82,6 +90,7 @@ static __init int barrier_nospec_debugfs_init(void)
device_initcall(barrier_nospec_debugfs_init);
#endif /* CONFIG_DEBUG_FS */
+#ifdef CONFIG_PPC_BOOK3S_64
Re: [PATCH 1/3 v3] powerpc/fsl-booke: Add support for T2080/T2081 SoC
On 06/06/2014 10:18 AM, Shengzhou Liu wrote:
The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
Architecture processor cores with high-performance datapath acceleration
logic and network and peripheral bus interfaces required for networking,
telecom/datacom, wireless infrastructure, and mil/aerospace applications.
The T2080 SoC includes the following function and features:
- Four dual-threaded 64-bit Power architecture e6500 cores, up to 1.8GHz
- 2MB L2 cache and 512KB CoreNet platform cache (CPC)
- Hierarchical interconnect fabric
- One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- 16 SerDes lanes up to 10.3125 GHz
- 8 Ethernet interfaces (multiple 1G/2.5G/10G MACs)
- High-speed peripheral interfaces
- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0)
- Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
- Additional peripheral interfaces
- Two serial ATA (SATA 2.0) controllers
- Two high-speed USB 2.0 controllers with integrated PHY
- Enhanced secure digital host controller (SD/SDXC/eMMC)
- Enhanced serial peripheral interface (eSPI)
- Four I2C controllers
- Four 2-pin UARTs or two 4-pin UARTs
- Integrated Flash Controller supporting NAND and NOR flash
- Three eight-channel DMA engines
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0
T2081 is a reduced personality of T2080 with following difference:
Feature T2080 T2081
1G Ethernet numbers: 8 6
10G Ethernet numbers: 4 2
SerDes lanes: 168
Serial RapidIO,RMan: 2 no
SATA Controller: 2 no
Aurora: yes no
SoC Package: 896-pins 780-pins
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
v3: added pamu node and updated clockgen.
v2: updated with some comments.
arch/powerpc/boot/dts/fsl/t2080si-post.dtsi | 69 +
arch/powerpc/boot/dts/fsl/t2081si-post.dtsi | 434
arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi | 91 ++
arch/powerpc/include/asm/mpc85xx.h | 2 +
4 files changed, 596 insertions(+)
create mode 100644 arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
diff --git a/arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
new file mode 100644
index 000..082ec20
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
@@ -0,0 +1,69 @@
+/*
+ * T2080 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ t2081si-post.dtsi
+
+soc {
+/include/ qoriq-sata2-0.dtsi
+ sata@22 {
+ fsl,iommu-parent = pamu1;
+ fsl,liodn-reg = guts 0x550; /* SATA1LIODNR */
+ };
+
+/include/ qoriq-sata2-1.dtsi
+ sata@221000 {
+ fsl,iommu-parent = pamu1;
+ fsl,liodn-reg = guts 0x554; /* SATA2LIODNR */
+ };
+};
+
+rio {
+ compatible = fsl,srio;
+ interrupts = 16
Re: [PATCH] powerpc/fsl: Updated corenet-cf compatible string for corenet1-cf chips
On 05/06/2014 07:57 PM, Scott Wood wrote: On Tue, 2014-05-06 at 17:56 +0300, Diana Craciun wrote: From: Diana Craciun diana.crac...@freescale.com Updated the device trees according to the corenet-cf binding definition. Signed-off-by: Diana Craciun diana.crac...@freescale.com --- arch/powerpc/boot/dts/fsl/p2041si-post.dtsi | 2 +- arch/powerpc/boot/dts/fsl/p3041si-post.dtsi | 2 +- arch/powerpc/boot/dts/fsl/p4080si-post.dtsi | 2 +- arch/powerpc/boot/dts/fsl/p5020si-post.dtsi | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) Oops, I meant to include this in the patch I sent, but forgot to squash the two patches together. :-P Where's p5040? Ups, somehow I failed to commit that file, respinning Diana ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v2] powerpc/fsl: Updated corenet-cf compatible string for corenet1-cf chips
From: Diana Craciun diana.crac...@freescale.com
Updated the device trees according to the corenet-cf
binding definition.
Signed-off-by: Diana Craciun diana.crac...@freescale.com
---
v2:
Added missing p5040
arch/powerpc/boot/dts/fsl/p2041si-post.dtsi | 2 +-
arch/powerpc/boot/dts/fsl/p3041si-post.dtsi | 2 +-
arch/powerpc/boot/dts/fsl/p4080si-post.dtsi | 2 +-
arch/powerpc/boot/dts/fsl/p5020si-post.dtsi | 2 +-
arch/powerpc/boot/dts/fsl/p5040si-post.dtsi | 2 +-
5 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
index e2987a3..b5daa4c 100644
--- a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
@@ -246,7 +246,7 @@
};
corenet-cf@18000 {
- compatible = fsl,corenet-cf;
+ compatible = fsl,corenet1-cf, fsl,corenet-cf;
reg = 0x18000 0x1000;
interrupts = 16 2 1 31;
fsl,ccf-num-csdids = 32;
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
index 7af6d45..5abd1fc 100644
--- a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
@@ -273,7 +273,7 @@
};
corenet-cf@18000 {
- compatible = fsl,corenet-cf;
+ compatible = fsl,corenet1-cf, fsl,corenet-cf;
reg = 0x18000 0x1000;
interrupts = 16 2 1 31;
fsl,ccf-num-csdids = 32;
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
index 2415e1f..bf0e7c9 100644
--- a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
@@ -281,7 +281,7 @@
};
corenet-cf@18000 {
- compatible = fsl,corenet-cf;
+ compatible = fsl,corenet1-cf, fsl,corenet-cf;
reg = 0x18000 0x1000;
interrupts = 16 2 1 31;
fsl,ccf-num-csdids = 32;
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
index 2985de4..f7ca9f4 100644
--- a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
@@ -278,7 +278,7 @@
};
corenet-cf@18000 {
- compatible = fsl,corenet-cf;
+ compatible = fsl,corenet1-cf, fsl,corenet-cf;
reg = 0x18000 0x1000;
interrupts = 16 2 1 31;
fsl,ccf-num-csdids = 32;
diff --git a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
index 546a899..91477b5 100644
--- a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
@@ -233,7 +233,7 @@
};
corenet-cf@18000 {
- compatible = fsl,corenet-cf;
+ compatible = fsl,corenet1-cf, fsl,corenet-cf;
reg = 0x18000 0x1000;
interrupts = 16 2 1 31;
fsl,ccf-num-csdids = 32;
--
1.7.11.7
___
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Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc/fsl: Updated corenet-cf compatible string for corenet1-cf chips
From: Diana Craciun diana.crac...@freescale.com
Updated the device trees according to the corenet-cf
binding definition.
Signed-off-by: Diana Craciun diana.crac...@freescale.com
---
arch/powerpc/boot/dts/fsl/p2041si-post.dtsi | 2 +-
arch/powerpc/boot/dts/fsl/p3041si-post.dtsi | 2 +-
arch/powerpc/boot/dts/fsl/p4080si-post.dtsi | 2 +-
arch/powerpc/boot/dts/fsl/p5020si-post.dtsi | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
index e2987a3..b5daa4c 100644
--- a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
@@ -246,7 +246,7 @@
};
corenet-cf@18000 {
- compatible = fsl,corenet-cf;
+ compatible = fsl,corenet1-cf, fsl,corenet-cf;
reg = 0x18000 0x1000;
interrupts = 16 2 1 31;
fsl,ccf-num-csdids = 32;
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
index 7af6d45..5abd1fc 100644
--- a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
@@ -273,7 +273,7 @@
};
corenet-cf@18000 {
- compatible = fsl,corenet-cf;
+ compatible = fsl,corenet1-cf, fsl,corenet-cf;
reg = 0x18000 0x1000;
interrupts = 16 2 1 31;
fsl,ccf-num-csdids = 32;
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
index 2415e1f..bf0e7c9 100644
--- a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
@@ -281,7 +281,7 @@
};
corenet-cf@18000 {
- compatible = fsl,corenet-cf;
+ compatible = fsl,corenet1-cf, fsl,corenet-cf;
reg = 0x18000 0x1000;
interrupts = 16 2 1 31;
fsl,ccf-num-csdids = 32;
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
index 2985de4..f7ca9f4 100644
--- a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
@@ -278,7 +278,7 @@
};
corenet-cf@18000 {
- compatible = fsl,corenet-cf;
+ compatible = fsl,corenet1-cf, fsl,corenet-cf;
reg = 0x18000 0x1000;
interrupts = 16 2 1 31;
fsl,ccf-num-csdids = 32;
--
1.7.11.7
___
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[PATCH v3] powerpc/fsl: Added binding for Freescale CoreNet coherency fabric (CCF)
From: Diana Craciun diana.crac...@freescale.com
The CoreNet coherency fabric is a fabric-oriented, conectivity
infrastructure that enables the implementation of coherent, multicore
systems. The CCF acts as a central interconnect for cores,
platform-level caches, memory subsystem, peripheral devices and I/O host
bridges in the system.
Signed-off-by: Diana Craciun diana.crac...@freescale.com
---
v3:
- added port ID mapping
- removed fsl,corenetx-cf
.../devicetree/bindings/powerpc/fsl/ccf.txt| 42 ++
.../devicetree/bindings/powerpc/fsl/cpus.txt | 8 +
.../devicetree/bindings/powerpc/fsl/pamu.txt | 8 +
3 files changed, 58 insertions(+)
create mode 100644 Documentation/devicetree/bindings/powerpc/fsl/ccf.txt
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/ccf.txt
b/Documentation/devicetree/bindings/powerpc/fsl/ccf.txt
new file mode 100644
index 000..1263c29
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/ccf.txt
@@ -0,0 +1,42 @@
+Freescale CoreNet Coherency Fabric(CCF) Device Tree Binding
+
+DESCRIPTION
+
+The CoreNet coherency fabric is a fabric-oriented, connectivity infrastructure
+that enables the implementation of coherent, multicore systems.
+
+Required properties:
+
+- compatible : string
+ fsl,corenet1-cf - CoreNet coherency fabric version 1. Example
chips: T4240,
+ B4860
+ fsl,corenet2-cf - CoreNet coherency fabric version 2. Example
chips: P5020,
+ P4080, P3041, P2041
+ fsl,corenet-cf - It is used to represent the common registers
between
+ CCF version 1 and CCF version 2. This compatible is retained for
+ compatibility reasons as it was already used for both CCF
version 1 chips
+ and CCF version 2 chips.
+
+- reg : prop-encoded-array
+ A standard property. Represents the CCF registers.
+
+- interrupts : prop-encoded-array
+ Interrupt mapping for CCF error interrupt.
+
+- fsl,ccf-num-csdids: u32
+ Specifies the number of Coherency Subdomain ID Port Mapping
+ Registers that are supported by the CCF.
+
+- fsl,ccf-num-snoopids: u32
+ Specifies the number of Snoop ID Port Mapping Registers that
+ are supported by CCF.
+
+Example:
+
+ corenet-cf@18000 {
+ compatible = fsl,corenet2-cf, fsl,corenet-cf;
+ reg = 0x18000 0x1000;
+ interrupts = 16 2 1 31;
+ fsl,ccf-num-csdids = 32;
+ fsl,ccf-num-snoopids = 32;
+ };
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpus.txt
b/Documentation/devicetree/bindings/powerpc/fsl/cpus.txt
index 922c30a..09dbc5f 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/cpus.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/cpus.txt
@@ -20,3 +20,11 @@ PROPERTIES
a property named fsl,eref-[CAT], where [CAT] is the abbreviated category
name with all uppercase letters converted to lowercase, indicates that
the category is supported by the implementation.
+
+ - fsl,portid-mapping : u32
+ The Coherency Subdomain ID Port Mapping Registers and Snoop ID Port
Mapping
+ registers which are part of the CoreNet Coherency fabric (CCF) provide a
+ CoreNet Coherency Subdomain ID/CoreNet Snoop ID to cpu mapping
functions.
+ Certain bits from these registers should be set if the coresponding CPU
+ should be snooped. This property defines a bitmask which selects the
bit that
+ should be set if this cpu should be snooped.
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/pamu.txt
b/Documentation/devicetree/bindings/powerpc/fsl/pamu.txt
index 1f5e329..827c637 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/pamu.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/pamu.txt
@@ -26,6 +26,13 @@ Required properties:
A standard property.
- #size-cells : u32
A standard property.
+- fsl,portid-mapping : u32
+ The Coherency Subdomain ID Port Mapping Registers and Snoop ID Port
Mapping
+ registers which are part of the CoreNet Coherency fabric (CCF) provide a
+ CoreNet Coherency Subdomain ID/CoreNet Snoop ID to pamu mapping
functions.
+ Certain bits from these registers should be set if PAMUs should be
snooped.
+ This property defines a bitmask which selects the bits that should be
set
+ if PAMUs should be snooped.
Optional properties:
- reg : prop-encoded-array
@@ -88,6 +95,7 @@ Example:
compatible = fsl,pamu-v1.0, fsl,pamu;
reg = 0x2 0x5000;
ranges = 0 0x2 0x5000;
+ fsl,portid-mapping = 0xf8;
#address-cells = 1;
#size-cells = 1;
interrupts =
--
1.7.11.7
[PATCH v2] powerpc/fsl: Updated device trees for platforms with corenet version 2
From: Diana Craciun diana.crac...@freescale.com
Updated the device trees according to the corenet-cf
binding definition.
Signed-off-by: Diana Craciun diana.crac...@freescale.com
---
arch/powerpc/boot/dts/b4860emu.dts | 7 ++-
arch/powerpc/boot/dts/fsl/b4420si-post.dtsi | 4
arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi | 2 ++
arch/powerpc/boot/dts/fsl/b4860si-post.dtsi | 4
arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi | 4
arch/powerpc/boot/dts/fsl/b4si-post.dtsi| 3 ++-
arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 3 ++-
arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi | 12
arch/powerpc/boot/dts/t4240emu.dts | 15 ++-
9 files changed, 42 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/boot/dts/b4860emu.dts
b/arch/powerpc/boot/dts/b4860emu.dts
index 7290021..85646b4 100644
--- a/arch/powerpc/boot/dts/b4860emu.dts
+++ b/arch/powerpc/boot/dts/b4860emu.dts
@@ -61,21 +61,25 @@
device_type = cpu;
reg = 0 1;
next-level-cache = L2;
+ fsl,portid-mapping = 0x8000;
};
cpu1: PowerPC,e6500@2 {
device_type = cpu;
reg = 2 3;
next-level-cache = L2;
+ fsl,portid-mapping = 0x8000;
};
cpu2: PowerPC,e6500@4 {
device_type = cpu;
reg = 4 5;
next-level-cache = L2;
+ fsl,portid-mapping = 0x8000;
};
cpu3: PowerPC,e6500@6 {
device_type = cpu;
reg = 6 7;
next-level-cache = L2;
+ fsl,portid-mapping = 0x8000;
};
};
};
@@ -157,7 +161,7 @@
};
corenet-cf@18000 {
- compatible = fsl,b4-corenet-cf;
+ compatible = fsl,corenet2-cf, fsl,corenet-cf;
reg = 0x18000 0x1000;
interrupts = 16 2 1 0;
fsl,ccf-num-csdids = 32;
@@ -167,6 +171,7 @@
iommu@2 {
compatible = fsl,pamu-v1.0, fsl,pamu;
reg = 0x2 0x4000;
+ fsl,portid-mapping = 0x8000;
#address-cells = 1;
#size-cells = 1;
interrupts =
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
index 60566f99..d678944 100644
--- a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
@@ -76,10 +76,6 @@
compatible = fsl,b4420-l3-cache-controller, cache;
};
- corenet-cf@18000 {
- compatible = fsl,b4420-corenet-cf;
- };
-
guts: global-utilities@e {
compatible = fsl,b4420-device-config,
fsl,qoriq-device-config-2.0;
};
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
index 2419731..338af7e 100644
--- a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
@@ -66,12 +66,14 @@
reg = 0 1;
clocks = mux0;
next-level-cache = L2;
+ fsl,portid-mapping = 0x8000;
};
cpu1: PowerPC,e6500@2 {
device_type = cpu;
reg = 2 3;
clocks = mux0;
next-level-cache = L2;
+ fsl,portid-mapping = 0x8000;
};
};
};
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
index cbc354b..582381d 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
@@ -120,10 +120,6 @@
compatible = fsl,b4860-l3-cache-controller, cache;
};
- corenet-cf@18000 {
- compatible = fsl,b4860-corenet-cf;
- };
-
guts: global-utilities@e {
compatible = fsl,b4860-device-config,
fsl,qoriq-device-config-2.0;
};
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
index 142ac86..1948f73 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
@@ -66,24 +66,28 @@
reg = 0 1;
clocks = mux0;
next-level-cache = L2;
+ fsl,portid-mapping = 0x8000;
};
cpu1: PowerPC,e6500@2 {
device_type = cpu;
reg = 2 3;
clocks = mux0;
next-level-cache = L2
Re: [PATCH] powerpc/fsl: Updated device trees for platforms with corenet version 2
On 04/19/2014 01:07 AM, Scott Wood wrote: On Fri, 2014-04-18 at 18:21 +0300, Diana Craciun wrote: From: Diana Craciun diana.crac...@freescale.com Updated the device trees according to the corenet-cf binding definition. Signed-off-by: Diana Craciun diana.crac...@freescale.com --- arch/powerpc/boot/dts/b4860emu.dts | 2 +- arch/powerpc/boot/dts/fsl/b4420si-post.dtsi | 4 arch/powerpc/boot/dts/fsl/b4860si-post.dtsi | 4 arch/powerpc/boot/dts/fsl/b4si-post.dtsi| 2 +- arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 2 +- arch/powerpc/boot/dts/t4240emu.dts | 2 +- 6 files changed, 4 insertions(+), 12 deletions(-) Could you update the corenet version 1 trees as well? -Scott Yes, sure, I have this on my to do list. Diana ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v2] powerpc/fsl: Added binding for Freescale CoreNet coherency fabric (CCF)
On 04/19/2014 12:33 AM, Scott Wood wrote: On Fri, 2014-04-18 at 18:11 +0300, Diana Craciun wrote: From: Diana Craciun diana.crac...@freescale.com The CoreNet coherency fabric is a fabric-oriented, conectivity infrastructure that enables the implementation of coherent, multicore systems. The CCF acts as a central interconnect for cores, platform-level caches, memory subsystem, peripheral devices and I/O host bridges in the system. Signed-off-by: Diana Craciun diana.crac...@freescale.com --- .../devicetree/bindings/powerpc/fsl/ccf.txt| 36 ++ 1 file changed, 36 insertions(+) create mode 100644 Documentation/devicetree/bindings/powerpc/fsl/ccf.txt diff --git a/Documentation/devicetree/bindings/powerpc/fsl/ccf.txt b/Documentation/devicetree/bindings/powerpc/fsl/ccf.txt new file mode 100644 index 000..f0b7143 --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/ccf.txt @@ -0,0 +1,36 @@ +Freescale CoreNet Coherency Fabric(CCF) Device Tree Binding + +DESCRIPTION + +The CoreNet coherency fabric is a fabric-oriented, connectivity infrastructure +that enables the implementation of coherent, multicore systems. + +Required properties: + +- compatible : string + Must include fsl,corenetX-cf, fsl,corenet-cf - CoreNet coherency + fabric version X Specify fsl,corenet1-cf and fsl,corenet2-cf rather than fsl,corenetX-cf (given there's nothing in a chip manual that you can correlate with the value of X), and provide example chips for each. OK. Also specify that fsl,corenet-cf represents the registers that are common between the two versions (not arbitrary fsl,corenetX-cf -- if there's ever an fsl,corenet3-cf it may not be compatible with this), and is retained for compatibility reasons. What do you mean by common? There are the csdids and snoop ids registers which are common between the two versions but only by name because the register format is not the same. Diana ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v2] powerpc/fsl: Added binding for Freescale CoreNet coherency fabric (CCF)
From: Diana Craciun diana.crac...@freescale.com
The CoreNet coherency fabric is a fabric-oriented, conectivity
infrastructure that enables the implementation of coherent, multicore
systems. The CCF acts as a central interconnect for cores,
platform-level caches, memory subsystem, peripheral devices and I/O host
bridges in the system.
Signed-off-by: Diana Craciun diana.crac...@freescale.com
---
.../devicetree/bindings/powerpc/fsl/ccf.txt| 36 ++
1 file changed, 36 insertions(+)
create mode 100644 Documentation/devicetree/bindings/powerpc/fsl/ccf.txt
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/ccf.txt
b/Documentation/devicetree/bindings/powerpc/fsl/ccf.txt
new file mode 100644
index 000..f0b7143
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/ccf.txt
@@ -0,0 +1,36 @@
+Freescale CoreNet Coherency Fabric(CCF) Device Tree Binding
+
+DESCRIPTION
+
+The CoreNet coherency fabric is a fabric-oriented, connectivity infrastructure
+that enables the implementation of coherent, multicore systems.
+
+Required properties:
+
+- compatible : string
+ Must include fsl,corenetX-cf, fsl,corenet-cf - CoreNet
coherency
+ fabric version X
+
+- reg : prop-encoded-array
+ A standard property. Represents the CCF registers.
+
+- interrupts : prop-encoded-array
+ Interrupt mapping for CCF error interrupt.
+
+- fsl,ccf-num-csdids: u32
+ Specifies the number of Coherency Subdomain ID Port Mapping
+ Registers that are supported by the CCF.
+
+- fsl,ccf-num-snoopids: u32
+ Specifies the number of Snoop ID Port Mapping Registers that
+ are supported by CCF.
+
+Example:
+
+ corenet-cf@18000 {
+ compatible = fsl,corenet2-cf, fsl,corenet-cf;
+ reg = 0x18000 0x1000;
+ interrupts = 16 2 1 31;
+ fsl,ccf-num-csdids = 32;
+ fsl,ccf-num-snoopids = 32;
+ };
--
1.7.11.7
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[PATCH] powerpc/fsl: Updated device trees for platforms with corenet version 2
From: Diana Craciun diana.crac...@freescale.com
Updated the device trees according to the corenet-cf
binding definition.
Signed-off-by: Diana Craciun diana.crac...@freescale.com
---
arch/powerpc/boot/dts/b4860emu.dts | 2 +-
arch/powerpc/boot/dts/fsl/b4420si-post.dtsi | 4
arch/powerpc/boot/dts/fsl/b4860si-post.dtsi | 4
arch/powerpc/boot/dts/fsl/b4si-post.dtsi| 2 +-
arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 2 +-
arch/powerpc/boot/dts/t4240emu.dts | 2 +-
6 files changed, 4 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/boot/dts/b4860emu.dts
b/arch/powerpc/boot/dts/b4860emu.dts
index 7290021..e41e2a2 100644
--- a/arch/powerpc/boot/dts/b4860emu.dts
+++ b/arch/powerpc/boot/dts/b4860emu.dts
@@ -157,7 +157,7 @@
};
corenet-cf@18000 {
- compatible = fsl,b4-corenet-cf;
+ compatible = fsl,corenet2-cf, fsl,corenet-cf;
reg = 0x18000 0x1000;
interrupts = 16 2 1 0;
fsl,ccf-num-csdids = 32;
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
index 60566f99..d678944 100644
--- a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
@@ -76,10 +76,6 @@
compatible = fsl,b4420-l3-cache-controller, cache;
};
- corenet-cf@18000 {
- compatible = fsl,b4420-corenet-cf;
- };
-
guts: global-utilities@e {
compatible = fsl,b4420-device-config,
fsl,qoriq-device-config-2.0;
};
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
index cbc354b..582381d 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
@@ -120,10 +120,6 @@
compatible = fsl,b4860-l3-cache-controller, cache;
};
- corenet-cf@18000 {
- compatible = fsl,b4860-corenet-cf;
- };
-
guts: global-utilities@e {
compatible = fsl,b4860-device-config,
fsl,qoriq-device-config-2.0;
};
diff --git a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
index 4f6e482..376988c 100644
--- a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
@@ -158,7 +158,7 @@
};
corenet-cf@18000 {
- compatible = fsl,b4-corenet-cf;
+ compatible = fsl,corenet2-cf, fsl,corenet-cf;
reg = 0x18000 0x1000;
interrupts = 16 2 1 0;
fsl,ccf-num-csdids = 32;
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
index f99d74f..c13ce99 100644
--- a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
@@ -343,7 +343,7 @@
};
corenet-cf@18000 {
- compatible = fsl,corenet-cf;
+ compatible = fsl,corenet2-cf, fsl,corenet-cf;
reg = 0x18000 0x1000;
interrupts = 16 2 1 31;
fsl,ccf-num-csdids = 32;
diff --git a/arch/powerpc/boot/dts/t4240emu.dts
b/arch/powerpc/boot/dts/t4240emu.dts
index ee24ab3..c719dcc 100644
--- a/arch/powerpc/boot/dts/t4240emu.dts
+++ b/arch/powerpc/boot/dts/t4240emu.dts
@@ -213,7 +213,7 @@
};
corenet-cf@18000 {
- compatible = fsl,corenet-cf;
+ compatible = fsl,corenet2-cf, fsl, corenet-cf;
reg = 0x18000 0x1000;
interrupts = 16 2 1 31;
fsl,ccf-num-csdids = 32;
--
1.7.11.7
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[PATCH 1/2][powerpc/fsl] Added binding for Freescale CoreNet coherency fabric (CCF)
From: Diana Craciun diana.crac...@freescale.com
The CoreNet coherency fabric is a fabric-oriented, conectivity
infrastructure that enables the implementation of coherent, multicore
systems. The CCF acts as a central interconnect for cores,
platform-level caches, memory subsystem, peripheral devices and I/O host
bridges in the system.
Signed-off-by: Diana Craciun diana.crac...@freescale.com
---
.../devicetree/bindings/powerpc/fsl/ccf.txt| 37 ++
1 file changed, 37 insertions(+)
create mode 100644 Documentation/devicetree/bindings/powerpc/fsl/ccf.txt
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/ccf.txt
b/Documentation/devicetree/bindings/powerpc/fsl/ccf.txt
new file mode 100644
index 000..61f1a33
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/ccf.txt
@@ -0,0 +1,37 @@
+Freescale CoreNet Coherency Fabric(CCF) Device Tree Binding
+
+DESCRIPTION
+
+The CoreNet coherency fabric is a fabric-oriented, connectivity infrastructure
+that enables the implementation of coherent, multicore systems.
+
+Required properties:
+
+- compatible : string
+ fsl,corenet-cf - CoreNet coherency fabric version 1
+ fsl,corenetX-cf - CoreNet coherency fabric version X
+
+- reg : prop-encoded-array
+ A standard property. Specifies the pshysical address and
+ length of the CoreNet coherency fabric memory space.
+
+- interrupts : prop-encoded-array
+ Interrupt mapping for CCF error interrupt.
+
+- fsl,ccf-num-csdids: u32
+ Specifies the number of Coherency Subdomain ID Port Mapping
+ Registers that are supported by the CCF.
+
+- fsl,ccf-num-snoopids: u32
+ Specifies the number of Snoop ID Port Mapping Registers that
+ are supported by CCF.
+
+Example:
+
+ corenet-cf@18000 {
+ compatible = fsl,corenet2-cf;
+ reg = 0x18000 0x1000;
+ interrupts = 16 2 1 31;
+ fsl,ccf-num-csdids = 32;
+ fsl,ccf-num-snoopids = 32;
+ };
--
1.7.11.7
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[PATCH 2/2][powerpc/fsl] Updated T4240 corenet-cf node in device tree
From: Diana Craciun diana.crac...@freescale.com
Updated the compatible to reflect that CCF hardware
is different on T4240
Signed-off-by: Diana Craciun diana.crac...@freescale.com
---
arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
index f99d74f..e1a8734 100644
--- a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
@@ -343,7 +343,7 @@
};
corenet-cf@18000 {
- compatible = fsl,corenet-cf;
+ compatible = fsl,corenet2-cf;
reg = 0x18000 0x1000;
interrupts = 16 2 1 31;
fsl,ccf-num-csdids = 32;
--
1.7.11.7
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Re: big latency while under HV
Hi, Just to be on the same page, are you using the Freescale Embedded Hypervisor provided with the Freescale SDK or other embedded hypervisor? Anyway, the question is not much related with the Linux kernel, so you should probably redirect your question to Freescale support. You can reach Freescale support at supp...@freescale.com. Diana On 09/09/2013 06:19 PM, Ivan Krivonos wrote: Hi, i`m working on the embedded hypervisor targeting QorIQ platforms (p3041/p4080). I have working prototype starting custom RTOS on just single core in the guest space. What I see is the big latency (up to 3 times more) in RTOS running atop of HV comparing to RTOS running bare-metal. I`m using lmbench utility. It shows nteger mul: 3.48 nanoseconds integer div: 30.44 nanoseconds integer mod: 13.92 nanoseconds int64 bit: 1.75 nanoseconds int64 add: 1.42 nanoseconds int64 mul: 6.95 nanoseconds HV:hvpriv_count 6 int64 div: 447.56 nanoseconds int64 mod: 385.42 nanoseconds float add: 7.12 nanoseconds float mul: 6.95 nanoseconds float div: 33.05 nanoseconds double add: 7.11 nanoseconds double mul: 8.70 nanoseconds double div: 57.36 nanoseconds float bogomflops: 46.98 nanoseconds double bogomflops: 73.09 nanoseconds The bare-metal results are 3x better. Does anybody have any ideas on what may be the source of such latency ? I forward all the exceptions to the guest w/o affecting HV. Only hvpriv is processed, it takes not more than 2 bus cycles. Sorry for poor english ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc: Replaced tlbilx with tlbwe in the initialization code
From: Diana Craciun diana.crac...@freescale.com On Freescale e6500 cores EPCR[DGTMI] controls whether guest supervisor state can execute TLB management instructions. If EPCR[DGTMI]=0 tlbwe and tlbilx are allowed to execute normally in the guest state. A hypervisor may choose to virtualize TLB1 and for this purpose it may use IPROT to protect the entries for being invalidated by the guest. However, because tlbwe and tlbilx execution in the guest state are sharing the same bit, it is not possible to have a scenario where tlbwe is allowed to be executed in guest state and tlbilx traps. When guest TLB management instructions are allowed to be executed in guest state the guest cannot use tlbilx to invalidate TLB1 guest entries. Linux is using tlbilx in the boot code to invalidate the temporary entries it creates when initializing the MMU. The patch is replacing the usage of tlbilx in initialization code with tlbwe with VALID bit cleared. Linux is also using tlbilx in other contexts (like huge pages or indirect entries) but removing the tlbilx from the initialization code offers the possibility to have scenarios under hypervisor which are not using huge pages or indirect entries. Signed-off-by: Diana Craciun diana.crac...@freescale.com --- arch/powerpc/kernel/exceptions-64e.S | 10 ++ 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S index 42a756e..a979e9d 100644 --- a/arch/powerpc/kernel/exceptions-64e.S +++ b/arch/powerpc/kernel/exceptions-64e.S @@ -1053,12 +1053,9 @@ skpinv: addir6,r6,1 /* Increment */ mtspr SPRN_MAS0,r3 tlbre mfspr r6,SPRN_MAS1 - rlwinm r6,r6,0,2,0 /* clear IPROT */ + rlwinm r6,r6,0,2,31/* clear IPROT and VALID */ mtspr SPRN_MAS1,r6 tlbwe - - /* Invalidate TLB1 */ - PPC_TLBILX_ALL(0,R0) sync isync @@ -1112,12 +1109,9 @@ skpinv: addir6,r6,1 /* Increment */ mtspr SPRN_MAS0,r4 tlbre mfspr r5,SPRN_MAS1 - rlwinm r5,r5,0,2,0 /* clear IPROT */ + rlwinm r5,r5,0,2,31/* clear IPROT and VALID */ mtspr SPRN_MAS1,r5 tlbwe - - /* Invalidate TLB1 */ - PPC_TLBILX_ALL(0,R0) sync isync -- 1.7.11.7 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH][RFC] Replaced tlbilx with tlbwe in the initialization code
On 02/19/2013 09:47 PM, Scott Wood wrote: On 02/15/2013 09:16:15 AM, Diana Craciun wrote: On 02/15/2013 02:11 AM, Benjamin Herrenschmidt wrote: On Thu, 2013-02-14 at 14:56 +0200, Diana Craciun wrote: From: Diana Craciun diana.crac...@freescale.com On Freescale e6500 cores EPCR[DGTMI] controls whether guest supervisor state can execute TLB management instructions. If EPCR[DGTMI]=0 tlbwe and tlbilx are allowed to execute normally in the guest state. A hypervisor may choose to virtualize TLB1 and for this purpose it may use IPROT to protect the entries for being invalidated by the guest. However, because tlbwe and tlbilx execution in the guest state are sharing the same bit, it is not possible to have a scenario where tlbwe is allowed to be executed in guest state and tlbilx traps. When guest TLB management instructions are allowed to be executed in guest state the guest cannot use tlbilx to invalidate TLB1 guest entries. Sorry, I don't understand the explanation... can you be more detailed ? TLB1 supports huge page sizes. The guest may see the memory as contiguous but it sees the guest physical memory as presented by the hypervisor. In reality the real physical memory may be fragmented. In this case the hypervisor can add more than one TLB1 entry for one guest request and the hypervisor will keep track of all fragments. When the guest performs a tlbilx, the hypervisor will correctly invalidate all the corresponding fragments because both tlbwe and tlbilx trap and has full control of tlb management instructions targeting TLB1. For e6500 a single bit controls if tlbwe and tlbilx trap to the Hypervisor. tlbwe targeting TLB1 always traps. But if we want to use LRAT for TLB0, we have to configure tlbwe (targeting TLB 0) to go directly to the guest. But in this case tlbilx (which is targeting both TLBs) will never trap. If the tlbilx does not trap, the guest can invalidate only one of (possible more) fragments and furthermore the synchronization between what entries the hypervisor thinks there are in the TLB1 and what are the actual entries is lost. This patch addresses boot-time invalidations only. How will you handle hugetlb invalidations (or indirect entry invalidations, once that becomes supported)? -Scott I will not handle them. This patch offers the possibility to run Linux under hypervisor without using hugetlb or indirect entries (of course in case when we configure tlb management instructions to go to the guest because otherwise it works) If indirect entries are supported most likely we will configure tlbilx and tlbwe to trap. In this case LRAT will be still used through the page table walk mechanism. Diana ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH][RFC] Replaced tlbilx with tlbwe in the initialization code
On 02/20/2013 04:22 PM, Stuart Yoder wrote: On Tue, Feb 19, 2013 at 1:47 PM, Scott Wood scottw...@freescale.com wrote: This patch addresses boot-time invalidations only. How will you handle hugetlb invalidations (or indirect entry invalidations, once that becomes supported)? We do envision that direct guest TLB management is an opt-in option that a guest can enable. If LRAT is on, with TLB management directly handled by guests, the only mechanism we have to do TLB1 invalidates is tlbwe. That is our only option as far as I know. So, hugetlb and indirect entries will each need to be addressed separately.The kernel code that handles these either needs to be A) modified to unconditionally do all invalidates by tlbwe or B) conditionally use tlbwe depending on whether this is a guest that has enabled direct TLB management. Stuart In case of indirect entries I think we can configure tlbwe and tlbilx to go to the hypervisor. The guest should not mix tlbwe (for TLB0) and hardware page table walk, so we can support this scenario without modifying the guest. Diana ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 6/6 v8] iommu/fsl: Freescale PAMU driver and IOMMU API implementation.
On 02/18/2013 02:52 PM, Varun Sethi wrote: + +#define PAACE_TCEF_FORMAT0_8B 0x00 +#define PAACE_TCEF_FORMAT1_RSVD 0x01 + +#define PAACE_NUMBER_ENTRIES0x1FF Where is this number coming from? Diana ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 6/6 v8] iommu/fsl: Freescale PAMU driver and IOMMU API implementation.
On 02/18/2013 02:52 PM, Varun Sethi wrote:
+/**
+ * pamu_get_ppaace() - Return the primary PACCE
+ * @liodn: liodn PAACT index for desired PAACE
+ *
+ * Returns the ppace pointer upon success else return
+ * null.
+ */
+static struct paace *pamu_get_ppaace(int liodn)
+{
+ if (!ppaact || liodn PAACE_NUMBER_ENTRIES) {
Shouldn't be liodn = PAACE_NUMBER_ENTRIES ?
+ pr_err(PPAACT doesn't exist\n);
+ return NULL;
+ }
+
+ return ppaact[liodn];
+}
+
Diana
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Re: [PATCH][RFC] Replaced tlbilx with tlbwe in the initialization code
On 02/15/2013 02:11 AM, Benjamin Herrenschmidt wrote: On Thu, 2013-02-14 at 14:56 +0200, Diana Craciun wrote: From: Diana Craciun diana.crac...@freescale.com On Freescale e6500 cores EPCR[DGTMI] controls whether guest supervisor state can execute TLB management instructions. If EPCR[DGTMI]=0 tlbwe and tlbilx are allowed to execute normally in the guest state. A hypervisor may choose to virtualize TLB1 and for this purpose it may use IPROT to protect the entries for being invalidated by the guest. However, because tlbwe and tlbilx execution in the guest state are sharing the same bit, it is not possible to have a scenario where tlbwe is allowed to be executed in guest state and tlbilx traps. When guest TLB management instructions are allowed to be executed in guest state the guest cannot use tlbilx to invalidate TLB1 guest entries. Sorry, I don't understand the explanation... can you be more detailed ? TLB1 supports huge page sizes. The guest may see the memory as contiguous but it sees the guest physical memory as presented by the hypervisor. In reality the real physical memory may be fragmented. In this case the hypervisor can add more than one TLB1 entry for one guest request and the hypervisor will keep track of all fragments. When the guest performs a tlbilx, the hypervisor will correctly invalidate all the corresponding fragments because both tlbwe and tlbilx trap and has full control of tlb management instructions targeting TLB1. For e6500 a single bit controls if tlbwe and tlbilx trap to the Hypervisor. tlbwe targeting TLB1 always traps. But if we want to use LRAT for TLB0, we have to configure tlbwe (targeting TLB 0) to go directly to the guest. But in this case tlbilx (which is targeting both TLBs) will never trap. If the tlbilx does not trap, the guest can invalidate only one of (possible more) fragments and furthermore the synchronization between what entries the hypervisor thinks there are in the TLB1 and what are the actual entries is lost. Diana ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH][RFC] Replaced tlbilx with tlbwe in the initialization code
From: Diana Craciun diana.crac...@freescale.com On Freescale e6500 cores EPCR[DGTMI] controls whether guest supervisor state can execute TLB management instructions. If EPCR[DGTMI]=0 tlbwe and tlbilx are allowed to execute normally in the guest state. A hypervisor may choose to virtualize TLB1 and for this purpose it may use IPROT to protect the entries for being invalidated by the guest. However, because tlbwe and tlbilx execution in the guest state are sharing the same bit, it is not possible to have a scenario where tlbwe is allowed to be executed in guest state and tlbilx traps. When guest TLB management instructions are allowed to be executed in guest state the guest cannot use tlbilx to invalidate TLB1 guest entries. Linux is using tlbilx in the boot code to invalidate the temporary entries it creates when initializing the MMU. The patch is replacing the usage of tlbilx in initialization code with tlbwe with VALID bit cleared. Linux is also using tlbilx in other contexts (like huge pages or indirect entries) but removing the tlbilx from the initialization code offers the possibility to have scenarios under hypervisor which are not using huge pages or indirect entries. Signed-off-by: Diana Craciun diana.crac...@freescale.com --- arch/powerpc/kernel/exceptions-64e.S | 10 ++ 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S index 4684e33..1f0ae33 100644 --- a/arch/powerpc/kernel/exceptions-64e.S +++ b/arch/powerpc/kernel/exceptions-64e.S @@ -1010,12 +1010,9 @@ skpinv: addir6,r6,1 /* Increment */ mtspr SPRN_MAS0,r3 tlbre mfspr r6,SPRN_MAS1 - rlwinm r6,r6,0,2,0 /* clear IPROT */ + rlwinm r6,r6,0,2,31/* clear IPROT and VALID */ mtspr SPRN_MAS1,r6 tlbwe - - /* Invalidate TLB1 */ - PPC_TLBILX_ALL(0,R0) sync isync @@ -1069,12 +1066,9 @@ skpinv: addir6,r6,1 /* Increment */ mtspr SPRN_MAS0,r4 tlbre mfspr r5,SPRN_MAS1 - rlwinm r5,r5,0,2,0 /* clear IPROT */ + rlwinm r5,r5,0,2,31/* clear IPROT and VALID */ mtspr SPRN_MAS1,r5 tlbwe - - /* Invalidate TLB1 */ - PPC_TLBILX_ALL(0,R0) sync isync -- 1.7.11.7 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc/dts: Removed fsl,msi property from dts.
From: Diana CRACIUN diana.crac...@freescale.com
The association in the decice tree between PCI and MSI
using fsl,msi property was an artificial one and it does
not reflect the actual hardware.
Signed-off-by: Diana CRACIUN diana.crac...@freescale.com
---
arch/powerpc/boot/dts/p2041rdb.dts |3 ---
arch/powerpc/boot/dts/p3041ds.dts |4
arch/powerpc/boot/dts/p3060qds.dts |2 --
arch/powerpc/boot/dts/p4080ds.dts |3 ---
arch/powerpc/boot/dts/p5020ds.dts |4
5 files changed, 0 insertions(+), 16 deletions(-)
diff --git a/arch/powerpc/boot/dts/p2041rdb.dts
b/arch/powerpc/boot/dts/p2041rdb.dts
index 4f957db..2852139 100644
--- a/arch/powerpc/boot/dts/p2041rdb.dts
+++ b/arch/powerpc/boot/dts/p2041rdb.dts
@@ -135,7 +135,6 @@
reg = 0xf 0xfe20 0 0x1000;
ranges = 0x0200 0 0xe000 0xc 0x 0x0 0x2000
0x0100 0 0x 0xf 0xf800 0x0
0x0001;
- fsl,msi = msi0;
pcie@0 {
ranges = 0x0200 0 0xe000
0x0200 0 0xe000
@@ -151,7 +150,6 @@
reg = 0xf 0xfe201000 0 0x1000;
ranges = 0x0200 0x0 0xe000 0xc 0x2000 0x0
0x2000
0x0100 0x0 0x 0xf 0xf801 0x0
0x0001;
- fsl,msi = msi1;
pcie@0 {
ranges = 0x0200 0 0xe000
0x0200 0 0xe000
@@ -167,7 +165,6 @@
reg = 0xf 0xfe202000 0 0x1000;
ranges = 0x0200 0 0xe000 0xc 0x4000 0 0x2000
0x0100 0 0x 0xf 0xf802 0 0x0001;
- fsl,msi = msi2;
pcie@0 {
ranges = 0x0200 0 0xe000
0x0200 0 0xe000
diff --git a/arch/powerpc/boot/dts/p3041ds.dts
b/arch/powerpc/boot/dts/p3041ds.dts
index f469145..22a215e 100644
--- a/arch/powerpc/boot/dts/p3041ds.dts
+++ b/arch/powerpc/boot/dts/p3041ds.dts
@@ -173,7 +173,6 @@
reg = 0xf 0xfe20 0 0x1000;
ranges = 0x0200 0 0xe000 0xc 0x 0x0 0x2000
0x0100 0 0x 0xf 0xf800 0x0
0x0001;
- fsl,msi = msi0;
pcie@0 {
ranges = 0x0200 0 0xe000
0x0200 0 0xe000
@@ -189,7 +188,6 @@
reg = 0xf 0xfe201000 0 0x1000;
ranges = 0x0200 0x0 0xe000 0xc 0x2000 0x0
0x2000
0x0100 0x0 0x 0xf 0xf801 0x0
0x0001;
- fsl,msi = msi1;
pcie@0 {
ranges = 0x0200 0 0xe000
0x0200 0 0xe000
@@ -205,7 +203,6 @@
reg = 0xf 0xfe202000 0 0x1000;
ranges = 0x0200 0 0xe000 0xc 0x4000 0 0x2000
0x0100 0 0x 0xf 0xf802 0 0x0001;
- fsl,msi = msi2;
pcie@0 {
ranges = 0x0200 0 0xe000
0x0200 0 0xe000
@@ -221,7 +218,6 @@
reg = 0xf 0xfe203000 0 0x1000;
ranges = 0x0200 0 0xe000 0xc 0x6000 0 0x2000
0x0100 0 0x 0xf 0xf803 0 0x0001;
- fsl,msi = msi2;
pcie@0 {
ranges = 0x0200 0 0xe000
0x0200 0 0xe000
diff --git a/arch/powerpc/boot/dts/p3060qds.dts
b/arch/powerpc/boot/dts/p3060qds.dts
index 529042e..9ae875c 100644
--- a/arch/powerpc/boot/dts/p3060qds.dts
+++ b/arch/powerpc/boot/dts/p3060qds.dts
@@ -212,7 +212,6 @@
reg = 0xf 0xfe20 0 0x1000;
ranges = 0x0200 0 0xe000 0xc 0x 0x0 0x2000
0x0100 0 0x 0xf 0xf800 0x0
0x0001;
- fsl,msi = msi0;
pcie@0 {
ranges = 0x0200 0 0xe000
0x0200 0 0xe000
@@ -228,7 +227,6 @@
reg = 0xf 0xfe201000 0 0x1000;
ranges = 0x0200 0x0 0xe000 0xc 0x2000 0x0
0x2000
0x0100 0x0 0x 0xf 0xf801 0x0
0x0001;
- fsl,msi = msi1;
pcie@0 {
ranges = 0x0200 0 0xe000
0x0200 0 0xe000
diff --git a/arch/powerpc/boot/dts/p4080ds.dts
b/arch/powerpc/boot/dts/p4080ds.dts
index 6d60e54..3e20460 100644
--- a/arch/powerpc/boot/dts/p4080ds.dts
+++ b/arch/powerpc/boot/dts/p4080ds.dts
@@ -141,7 +141,6 @@
reg = 0xf 0xfe20 0 0x1000
[PATCH][upstream] Added aliased MSIIR register address to MSI node in dts
From: Diana CRACIUN diana.crac...@freescale.com
The MSIIR register for each MSI bank is aliased to a different
address. The MSI node reg property was updated to contain this
address:
e.g. reg = 0x41600 0x200 0x44140 4;
The first region contains the address and length of the MSI
register set and the second region contains the address of
the aliased MSIIR register at 0x44140.
Signed-off-by: Diana CRACIUN diana.crac...@freescale.com
---
.../devicetree/bindings/powerpc/fsl/msi-pic.txt|6 --
arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi |6 +++---
2 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
b/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
index 5d586e1..5693877 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
@@ -6,8 +6,10 @@ Required properties:
etc.) and the second is fsl,mpic-msi or fsl,ipic-msi depending on
the parent type.
-- reg : should contain the address and the length of the shared message
- interrupt register set.
+- reg : It may contain one or two regions. The first region should contain
+ the address and the length of the shared message interrupt register set.
+ The second region should contain the address of aliased MSIIR register for
+ platforms that have such an alias.
- msi-available-ranges: use start count style section to define which
msi interrupt can be used in the 256 msi interrupts. This property is
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi
b/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi
index b9bada6..08f4227 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi
@@ -53,7 +53,7 @@ timer@41100 {
msi0: msi@41600 {
compatible = fsl,mpic-msi;
- reg = 0x41600 0x200;
+ reg = 0x41600 0x200 0x44140 4;
msi-available-ranges = 0 0x100;
interrupts =
0xe0 0 0 0
@@ -68,7 +68,7 @@ msi0: msi@41600 {
msi1: msi@41800 {
compatible = fsl,mpic-msi;
- reg = 0x41800 0x200;
+ reg = 0x41800 0x200 0x45140 4;
msi-available-ranges = 0 0x100;
interrupts =
0xe8 0 0 0
@@ -83,7 +83,7 @@ msi1: msi@41800 {
msi2: msi@41a00 {
compatible = fsl,mpic-msi;
- reg = 0x41a00 0x200;
+ reg = 0x41a00 0x200 0x46140 4;
msi-available-ranges = 0 0x100;
interrupts =
0xf0 0 0 0
--
1.7.3.4
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Re: [PATCH][upstream] Added aliased MSIIR register address to MSI node in dts
Please ignore this, I put a wrong subject.
Thanks,
Diana
On 02/01/2012 05:40 PM, Diana Craciun wrote:
From: Diana CRACIUNdiana.crac...@freescale.com
The MSIIR register for each MSI bank is aliased to a different
address. The MSI node reg property was updated to contain this
address:
e.g. reg =0x41600 0x200 0x44140 4;
The first region contains the address and length of the MSI
register set and the second region contains the address of
the aliased MSIIR register at 0x44140.
Signed-off-by: Diana CRACIUNdiana.crac...@freescale.com
---
.../devicetree/bindings/powerpc/fsl/msi-pic.txt|6 --
arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi |6 +++---
2 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
b/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
index 5d586e1..5693877 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
@@ -6,8 +6,10 @@ Required properties:
etc.) and the second is fsl,mpic-msi or fsl,ipic-msi depending on
the parent type.
-- reg : should contain the address and the length of the shared message
- interrupt register set.
+- reg : It may contain one or two regions. The first region should contain
+ the address and the length of the shared message interrupt register set.
+ The second region should contain the address of aliased MSIIR register for
+ platforms that have such an alias.
- msi-available-ranges: usestart count style section to define which
msi interrupt can be used in the 256 msi interrupts. This property is
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi
b/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi
index b9bada6..08f4227 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi
@@ -53,7 +53,7 @@ timer@41100 {
msi0: msi@41600 {
compatible = fsl,mpic-msi;
- reg =0x41600 0x200;
+ reg =0x41600 0x200 0x44140 4;
msi-available-ranges =0 0x100;
interrupts =
0xe0 0 0 0
@@ -68,7 +68,7 @@ msi0: msi@41600 {
msi1: msi@41800 {
compatible = fsl,mpic-msi;
- reg =0x41800 0x200;
+ reg =0x41800 0x200 0x45140 4;
msi-available-ranges =0 0x100;
interrupts =
0xe8 0 0 0
@@ -83,7 +83,7 @@ msi1: msi@41800 {
msi2: msi@41a00 {
compatible = fsl,mpic-msi;
- reg =0x41a00 0x200;
+ reg =0x41a00 0x200 0x46140 4;
msi-available-ranges =0 0x100;
interrupts =
0xf0 0 0 0
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[PATCH] powerpc/dts: Added aliased MSIIR register address to MSI node in dts
From: Diana CRACIUN diana.crac...@freescale.com
The MSIIR register for each MSI bank is aliased to a different
address. The MSI node reg property was updated to contain this
address:
e.g. reg = 0x41600 0x200 0x44140 4;
The first region contains the address and length of the MSI
register set and the second region contains the address of
the aliased MSIIR register at 0x44140.
Signed-off-by: Diana CRACIUN diana.crac...@freescale.com
---
.../devicetree/bindings/powerpc/fsl/msi-pic.txt|6 --
arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi |6 +++---
2 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
b/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
index 5d586e1..5693877 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
@@ -6,8 +6,10 @@ Required properties:
etc.) and the second is fsl,mpic-msi or fsl,ipic-msi depending on
the parent type.
-- reg : should contain the address and the length of the shared message
- interrupt register set.
+- reg : It may contain one or two regions. The first region should contain
+ the address and the length of the shared message interrupt register set.
+ The second region should contain the address of aliased MSIIR register for
+ platforms that have such an alias.
- msi-available-ranges: use start count style section to define which
msi interrupt can be used in the 256 msi interrupts. This property is
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi
b/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi
index b9bada6..08f4227 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi
@@ -53,7 +53,7 @@ timer@41100 {
msi0: msi@41600 {
compatible = fsl,mpic-msi;
- reg = 0x41600 0x200;
+ reg = 0x41600 0x200 0x44140 4;
msi-available-ranges = 0 0x100;
interrupts =
0xe0 0 0 0
@@ -68,7 +68,7 @@ msi0: msi@41600 {
msi1: msi@41800 {
compatible = fsl,mpic-msi;
- reg = 0x41800 0x200;
+ reg = 0x41800 0x200 0x45140 4;
msi-available-ranges = 0 0x100;
interrupts =
0xe8 0 0 0
@@ -83,7 +83,7 @@ msi1: msi@41800 {
msi2: msi@41a00 {
compatible = fsl,mpic-msi;
- reg = 0x41a00 0x200;
+ reg = 0x41a00 0x200 0x46140 4;
msi-available-ranges = 0 0x100;
interrupts =
0xf0 0 0 0
--
1.7.3.4
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