[PATCH] powerpc: p1022: add two functions for reset pci slot

[Dongsheng Wang]

From: Wang Dongsheng 

When the DIU enable, only through the way of indirect access
to read/write pixis register. So add direct and indirect for
pci slot reset.

Signed-off-by: Wang Dongsheng 

diff --git a/arch/powerpc/platforms/85xx/p1022_ds.c 
b/arch/powerpc/platforms/85xx/p1022_ds.c
index 371df82..5c8894c 100644
--- a/arch/powerpc/platforms/85xx/p1022_ds.c
+++ b/arch/powerpc/platforms/85xx/p1022_ds.c
@@ -53,23 +53,6 @@
 #define CLKDVDR_PXCKDLY0x0600
 #define CLKDVDR_PXCLK_MASK 0x00FF
 
-/* Some ngPIXIS register definitions */
-#define PX_CTL 3
-#define PX_BRDCFG0 8
-#define PX_BRDCFG1 9
-
-#define PX_BRDCFG0_ELBC_SPI_MASK   0xc0
-#define PX_BRDCFG0_ELBC_SPI_ELBC   0x00
-#define PX_BRDCFG0_ELBC_SPI_NULL   0xc0
-#define PX_BRDCFG0_ELBC_DIU0x02
-
-#define PX_BRDCFG1_DVIEN   0x80
-#define PX_BRDCFG1_DFPEN   0x40
-#define PX_BRDCFG1_BACKLIGHT   0x20
-#define PX_BRDCFG1_DDCEN   0x10
-
-#define PX_CTL_ALTACC  0x80
-
 /*
  * DIU Area Descriptor
  *
@@ -106,6 +89,28 @@
(c2 << AD_COMP_2_SHIFT) | (c1 << AD_COMP_1_SHIFT) | \
(c0 << AD_COMP_0_SHIFT) | (size << AD_PIXEL_S_SHIFT))
 
+#endif
+
+/* Some ngPIXIS register definitions */
+#define PX_CTL 3
+#define PX_BRDCFG0 8
+#define PX_BRDCFG1 9
+
+#define PX_RST 0x4
+#define PX_RST_PCIE0x8
+
+#define PX_BRDCFG0_ELBC_SPI_MASK   0xc0
+#define PX_BRDCFG0_ELBC_SPI_ELBC   0x00
+#define PX_BRDCFG0_ELBC_SPI_NULL   0xc0
+#define PX_BRDCFG0_ELBC_DIU0x02
+
+#define PX_BRDCFG1_DVIEN   0x80
+#define PX_BRDCFG1_DFPEN   0x40
+#define PX_BRDCFG1_BACKLIGHT   0x20
+#define PX_BRDCFG1_DDCEN   0x10
+
+#define PX_CTL_ALTACC  0x80
+
 struct fsl_law {
u32 lawbar;
u32 reserved1;
@@ -125,6 +130,8 @@ struct fsl_law {
 
 #define BR_BA  0x8000
 
+static int px_ctl_altacc_flag;
+
 /*
  * Map a BRx value to a physical address
  *
@@ -157,48 +164,40 @@ static phys_addr_t lbc_br_to_phys(const void *ecm, 
unsigned int count, u32 br)
 #endif
 }
 
-/**
- * p1022ds_set_monitor_port: switch the output to a different monitor port
- */
-static void p1022ds_set_monitor_port(enum fsl_diu_monitor_port port)
+static u8 __iomem *lbc_lcs0_ba;
+static u8 __iomem *lbc_lcs1_ba;
+
+static inline bool verify_pixis_indirect_access_address(void)
 {
-   struct device_node *guts_node;
-   struct device_node *lbc_node = NULL;
-   struct device_node *law_node = NULL;
-   struct ccsr_guts __iomem *guts;
-   struct fsl_lbc_regs *lbc = NULL;
+   if (lbc_lcs0_ba && lbc_lcs1_ba)
+   return true;
+
+   return false;
+}
+
+static void indirect_access_pixis_probe(void)
+{
+   struct device_node *lbc_node;
+   struct device_node *law_node;
+   struct fsl_lbc_regs *lbc;
void *ecm = NULL;
-   u8 __iomem *lbc_lcs0_ba = NULL;
-   u8 __iomem *lbc_lcs1_ba = NULL;
+
phys_addr_t cs0_addr, cs1_addr;
u32 br0, or0, br1, or1;
const __be32 *iprop;
unsigned int num_laws;
-   u8 b;
-
-   /* Map the global utilities registers. */
-   guts_node = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts");
-   if (!guts_node) {
-   pr_err("p1022ds: missing global utilities device node\n");
-   return;
-   }
-
-   guts = of_iomap(guts_node, 0);
-   if (!guts) {
-   pr_err("p1022ds: could not map global utilities device\n");
-   goto exit;
-   }
 
lbc_node = of_find_compatible_node(NULL, NULL, "fsl,p1022-elbc");
if (!lbc_node) {
pr_err("p1022ds: missing localbus node\n");
-   goto exit;
+   return;
}
 
lbc = of_iomap(lbc_node, 0);
+   of_node_put(lbc_node);
if (!lbc) {
pr_err("p1022ds: could not map localbus node\n");
-   goto exit;
+   return;
}
 
law_node = of_find_compatible_node(NULL, NULL, "fsl,ecm-law");
@@ -282,7 +281,103 @@ static void p1022ds_set_monitor_port(enum 
fsl_diu_monitor_port port)
if (!lbc_lcs1_ba) {
pr_err("p1022ds: could not ioremap CS1 address %llx\n",
   (unsigned long long)cs1_addr);
-   goto exit;
+
+   iounmap(lbc_lcs0_ba);
+   }
+
+exit:
+   if (ecm)
+   iounmap(ecm);
+   if (lbc)
+   iounmap(lbc);
+
+   if (law_node)
+   of_node_put(law_node);
+}
+
+static void indirect_access_pixis_reset_pcie_slot(void)
+{
+   if (!verify_pixis_indirect_access_address()) {
+   WARN_ON(1);
+   return;
+   }
+
+   /* Set FPGA access address */
+   out_8(lbc_lcs0_ba, PX_RST);
+
+   /* power down pcie slot */
+   clrbits8(lbc_lcs1_ba, PX_RST_PCIE);
+
+   /* power up pcie slot */
+   setbits8(lbc_lcs1_ba, 

[PATCH v4] Documentation: dt: binding: fsl: add devicetree binding for describing RCPM

[Dongsheng Wang]

From: Wang Dongsheng 

RCPM is the Run Control and Power Management module performs all
device-level tasks associated with device run control and power
management.

Add this for freescale powerpc platform and layerscape platform.

Signed-off-by: Chenhui Zhao 
Signed-off-by: Tang Yuantian 
Signed-off-by: Wang Dongsheng 
---
*v4*
- Change patch subject.
- A few grammatical mistakes.
- Change "rcpm-wakeup" property to "fsl,rcpm-wakeup" property.
- Remove a few "fsl,-rcpm" examples.
- Now the value of "fsl,#rcpm-wakeup-cells" is not contain rcpm node.
- Add a NOTE to describe IPPDEXPCR register.

*v3*
- Add "fsl,#rcpm-wakeup-cells" for rcpm node. The number of cells
  correspond rcpm-wakeup property.
- Modify rcpm-wakeup property description.

*v2*
- Remove P4080 example.
- Modify rcpm-wakeup property description.

diff --git a/Documentation/devicetree/bindings/soc/fsl/rcpm.txt 
b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
new file mode 100644
index 000..757e0eb
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
@@ -0,0 +1,64 @@
+* Run Control and Power Management
+---
+The RCPM performs all device-level tasks associated with device run control
+and power management.
+
+Required properites:
+  - reg : Offset and length of the register set of the RCPM block.
+  - fsl,#rcpm-wakeup-cells : The number of IPPDEXPCR register cells in the
+   fsl,rcpm-wakeup property.
+  - compatible : Must contain a chip-specific RCPM block compatible string
+   and (if applicable) may contain a chassis-version RCPM compatible
+   string. Chip-specific strings are of the form "fsl,-rcpm",
+   such as:
+   * "fsl,p2041-rcpm"
+   * "fsl,p5020-rcpm"
+   * "fsl,t4240-rcpm"
+
+   Chassis-version strings are of the form "fsl,qoriq-rcpm-",
+   such as:
+   * "fsl,qoriq-rcpm-1.0": for chassis 1.0 rcpm
+   * "fsl,qoriq-rcpm-2.0": for chassis 2.0 rcpm
+   * "fsl,qoriq-rcpm-2.1": for chassis 2.1 rcpm
+
+All references to "1.0" and "2.0" refer to the QorIQ chassis version to
+which the chip complies.
+Chassis VersionExample Chips
+------
+1.0p4080, p5020, p5040, p2041, p3041
+2.0t4240, b4860, b4420
+2.1t1040, ls1021
+
+Example:
+The RCPM node for T4240:
+   rcpm: global-utilities@e2000 {
+   compatible = "fsl,t4240-rcpm", "fsl,qoriq-rcpm-2.0";
+   reg = <0xe2000 0x1000>;
+   fsl,#rcpm-wakeup-cells = <2>;
+   };
+
+* Freescale RCPM Wakeup Source Device Tree Bindings
+---
+Required fsl,rcpm-wakeup property should be added to a device node if the 
device
+can be used as a wakeup source.
+
+  - fsl,rcpm-wakeup: Consists of a pointer to the rcpm node and the IPPDEXPCR
+   register cells. The number of IPPDEXPCR register cells is defined in
+   "fsl,#rcpm-wakeup-cells" in the rcpm node. The first register cell is
+   the bit mask that should be set in IPPDEXPCR0, and the second register
+   cell is for IPPDEXPCR1, and so on.
+
+   Note: IPPDEXPCR(IP Powerdown Exception Control Register) provides a
+   mechanism for keeping certain blocks awake during STANDBY and MEM, in
+   order to use them as wake-up sources.
+
+Example:
+   lpuart0: serial@295 {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x295 0x0 0x1000>;
+   interrupts = ;
+   clocks = <>;
+   clock-names = "ipg";
+   fsl,rcpm-wakeup = < 0x0 0x4000>;
+   status = "disabled";
+   };
-- 
2.1.0.27.g96db324

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[PATCH] powerpc: Quick fix upstream main line build error on PowerPC

[Dongsheng Wang]

From: Wang Dongsheng 

This issue caused on 'commit 990486c8af04 ("strscpy: zero any trailing
garbage bytes in the destination")'.

zero_bytemask is not implemented on PowerPC. So copy the zero_bytemask
of BIG_ENDIAN implementation from include/asm-generic/word-at-a-time.h
to arch/powerpc/include/asm/word-at-a-time.h.

Build message:
lib/string.c: In function 'strscpy':
lib/string.c:209:4: error: implicit declaration of function
'zero_bytemask' [-Werror=implicit-function-declaration]
*(unsigned long *)(dest+res) = c & zero_bytemask(data);
cc1: some warnings being treated as errors
make[1]: *** [lib/string.o] Error 1
make[1]: *** Waiting for unfinished jobs

Signed-off-by: Wang Dongsheng 

diff --git a/arch/powerpc/include/asm/word-at-a-time.h 
b/arch/powerpc/include/asm/word-at-a-time.h
index 5b3a903..d891456 100644
--- a/arch/powerpc/include/asm/word-at-a-time.h
+++ b/arch/powerpc/include/asm/word-at-a-time.h
@@ -40,6 +40,10 @@ static inline bool has_zero(unsigned long val, unsigned long 
*data, const struct
return (val + c->high_bits) & ~rhs;
 }
 
+#ifndef zero_bytemask
+#define zero_bytemask(mask) (~1ul << __fls(mask))
+#endif
+
 #else
 
 #ifdef CONFIG_64BIT
-- 
2.1.0.27.g96db324

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[PATCH v3 2/2] arm/layerscape: add RCPM device tree support for ls1021a.

[Dongsheng Wang]

From: Wang Dongsheng 

Signed-off-by: Wang Dongsheng 
---
*v3*: Add "fsl,#rcpm-wakeup-cells" for rcpm node.
*v2*: No changes.
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 973a496..ac5f9a2 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -139,6 +139,7 @@
sdhci,auto-cmd12;
big-endian;
bus-width = <4>;
+   rcpm-wakeup = < 0x0080 0x0>;
status = "disabled";
};
 
@@ -186,6 +187,12 @@
};
};
 
+   rcpm: rcpm@1ee2000 {
+   compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1";
+   reg = <0x0 0x1ee2000 0x0 0x1>;
+   fsl,#rcpm-wakeup-cells = <3>;
+   };
+
dspi0: dspi@210 {
compatible = "fsl,ls1021a-v1.0-dspi";
#address-cells = <1>;
@@ -287,6 +294,7 @@
interrupts = ;
clocks = <>;
clock-names = "ipg";
+   rcpm-wakeup = < 0x0 0x4000>;
status = "disabled";
};
 
-- 
2.1.0.27.g96db324

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[PATCH v3 1/2] fsl: Add binding for RCPM

[Dongsheng Wang]

From: Wang Dongsheng 

RCPM is the Run Control and Power Management module performs all
device-level tasks associated with device run control and power
management.

Add this for freescale powerpc platform and layerscape platform.

Signed-off-by: Chenhui Zhao 
Signed-off-by: Tang Yuantian 
Signed-off-by: Wang Dongsheng 
---
*v3*
- Add "fsl,#rcpm-wakeup-cells" for rcpm node. The number of cells
  correspond rcpm-wakeup property.
- Modify rcpm-wakeup property description.

*v2*
- Remove P4080 example.
- Modify rcpm-wakeup property description.

diff --git a/Documentation/devicetree/bindings/soc/fsl/rcpm.txt 
b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
new file mode 100644
index 000..52110ec
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
@@ -0,0 +1,63 @@
+* Run Control and Power Management
+---
+The RCPM performs all device-level tasks associated with device run control
+and power management.
+
+Required properites:
+  - reg : Offset and length of the register set of RCPM block.
+  - fsl,#rcpm-wakeup-cells : The number of cells in rcpm-wakeup property.
+  - compatible : Sould contain a chip-specific RCPM block compatible string
+   and (if applicable) may contain a chassis-version RCPM compatible
+   string. Chip-specific strings are of the form "fsl,-rcpm",
+   such as:
+   * "fsl,p2041-rcpm"
+   * "fsl,p3041-rcpm"
+   * "fsl,p4080-rcpm"
+   * "fsl,p5020-rcpm"
+   * "fsl,p5040-rcpm"
+   * "fsl,t4240-rcpm"
+   * "fsl,b4420-rcpm"
+   * "fsl,b4860-rcpm"
+
+   Chassis-version strings are of the form "fsl,qoriq-rcpm-",
+   such as:
+   * "fsl,qoriq-rcpm-1.0": for chassis 1.0 rcpm
+   * "fsl,qoriq-rcpm-2.0": for chassis 2.0 rcpm
+   * "fsl,qoriq-rcpm-2.1": for chassis 2.1 rcpm
+
+All references to "1.0" and "2.0" refer to the QorIQ chassis version to
+which the chip complies.
+Chassis VersionExample Chips
+------
+1.0p4080, p5020, p5040, p2041, p3041
+2.0t4240, b4860, b4420
+2.1t1040, ls1021
+
+Example:
+The RCPM node for T4240:
+   rcpm: global-utilities@e2000 {
+   compatible = "fsl,t4240-rcpm", "fsl,qoriq-rcpm-2.0";
+   reg = <0xe2000 0x1000>;
+   fsl,#rcpm-wakeup-cells = <2>;
+   };
+
+* Freescale RCPM Wakeup Source Device Tree Bindings
+---
+Required rcpm-wakeup property should be added to a device node if the device
+can be used as a wakeup source.
+
+  - rcpm-wakeup: The value of the property consists of cells, the number of
+   cells defined in "fsl,#rcpm-wakeup-cells". The first cell is a pointer
+   to the rcpm node, the second cell is the bit mask that should be set
+   in IPPDEXPCR0, and the third cell is for IPPDEXPCR1, and so on.
+
+Example:
+   lpuart0: serial@295 {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x295 0x0 0x1000>;
+   interrupts = ;
+   clocks = <>;
+   clock-names = "ipg";
+   rcpm-wakeup = < 0x0 0x4000>;
+   status = "disabled";
+   };
-- 
2.1.0.27.g96db324

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[PATCH v2 1/2] fsl: Add binding for RCPM

[Dongsheng Wang]

From: Wang Dongsheng 

RCPM is the Run Control and Power Management module performs all
device-level tasks associated with device run control and power
management.

Add this for freescale powerpc platform and layerscape platform.

Signed-off-by: Chenhui Zhao 
Signed-off-by: Tang Yuantian 
Signed-off-by: Wang Dongsheng 
---
*v2*
- Remove P4080 example.
- Modify rcpm-wakeup property description.
diff --git a/Documentation/devicetree/bindings/soc/fsl/rcpm.txt 
b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
new file mode 100644
index 000..ea24d76
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
@@ -0,0 +1,60 @@
+* Run Control and Power Management
+---
+The RCPM performs all device-level tasks associated with device run control
+and power management.
+
+Required properites:
+  - reg : Offset and length of the register set of RCPM block.
+  - compatible : Sould contain a chip-specific RCPM block compatible string
+   and (if applicable) may contain a chassis-version RCPM compatible 
string.
+   Chip-specific strings are of the form "fsl,-rcpm", such as:
+   * "fsl,p2041-rcpm"
+   * "fsl,p3041-rcpm"
+   * "fsl,p4080-rcpm"
+   * "fsl,p5020-rcpm"
+   * "fsl,p5040-rcpm"
+   * "fsl,t4240-rcpm"
+   * "fsl,b4420-rcpm"
+   * "fsl,b4860-rcpm"
+
+   Chassis-version strings are of the form "fsl,qoriq-rcpm-",
+   such as:
+   * "fsl,qoriq-rcpm-1.0": for chassis 1.0 rcpm
+   * "fsl,qoriq-rcpm-2.0": for chassis 2.0 rcpm
+   * "fsl,qoriq-rcpm-2.1": for chassis 2.1 rcpm
+
+All references to "1.0" and "2.0" refer to the QorIQ chassis version to
+which the chip complies.
+Chassis VersionExample Chips
+------
+1.0p4080, p5020, p5040, p2041, p3041
+2.0t4240, b4860, b4420
+2.1t1040, ls1021
+
+Example:
+The RCPM node for T4240:
+   rcpm: global-utilities@e2000 {
+   compatible = "fsl,t4240-rcpm", "fsl,qoriq-rcpm-2.0";
+   reg = <0xe2000 0x1000>;
+   };
+
+* Freescale RCPM Wakeup Source Device Tree Bindings
+---
+Required rcpm-wakeup property should be added to a device node if the device
+can be used as a wakeup source.
+
+  - rcpm-wakeup: The value of the property consists of 3 cells. The first cell
+   is a pointer to the rcpm node, the second cell is the bit mask that
+   should be set in IPPDEXPCR0, and the last cell is for IPPDEXPCR1.
+   Note: If the platform has no IPPDEXPCR1 register, put a zero here.
+
+Example:
+   lpuart0: serial@295 {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x295 0x0 0x1000>;
+   interrupts = ;
+   clocks = <>;
+   clock-names = "ipg";
+   rcpm-wakeup = < 0x0 0x4000>;
+   status = "disabled";
+   };
-- 
2.1.0.27.g96db324

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[PATCH v2 2/2] arm/layerscape: add RCPM device tree support for ls1021a.

[Dongsheng Wang]

From: Wang Dongsheng 

Signed-off-by: Wang Dongsheng 
---
*v2*: No changes.
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 973a496..deb1271 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -139,6 +139,7 @@
sdhci,auto-cmd12;
big-endian;
bus-width = <4>;
+   rcpm-wakeup = < 0x0080 0x0>;
status = "disabled";
};
 
@@ -186,6 +187,11 @@
};
};
 
+   rcpm: rcpm@1ee2000 {
+   compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1";
+   reg = <0x0 0x1ee2000 0x0 0x1>;
+   };
+
dspi0: dspi@210 {
compatible = "fsl,ls1021a-v1.0-dspi";
#address-cells = <1>;
@@ -287,6 +293,7 @@
interrupts = ;
clocks = <>;
clock-names = "ipg";
+   rcpm-wakeup = < 0x0 0x4000>;
status = "disabled";
};
 
-- 
2.1.0.27.g96db324

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[PATCH 1/2] fsl: Add binding for RCPM

[Dongsheng Wang]

From: Wang Dongsheng 

RCPM is the Run Control and Power Management module performs all
device-level tasks associated with device run control and power
management.

Add this for freescale powerpc platform and layerscape platform.

Signed-off-by: Chenhui Zhao 
Signed-off-by: Tang Yuantian 
Signed-off-by: Wang Dongsheng 

diff --git a/Documentation/devicetree/bindings/soc/fsl/rcpm.txt 
b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
new file mode 100644
index 000..284070c
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
@@ -0,0 +1,64 @@
+* Run Control and Power Management
+---
+The RCPM performs all device-level tasks associated with device run control
+and power management.
+
+Required properites:
+  - reg : Offset and length of the register set of RCPM block.
+  - compatible : Sould contain a chip-specific RCPM block compatible string
+   and (if applicable) may contain a chassis-version RCPM compatible 
string.
+   Chip-specific strings are of the form "fsl,-rcpm", such as:
+   * "fsl,p2041-rcpm"
+   * "fsl,p3041-rcpm"
+   * "fsl,p4080-rcpm"
+   * "fsl,p5020-rcpm"
+   * "fsl,p5040-rcpm"
+   * "fsl,t4240-rcpm"
+   * "fsl,b4420-rcpm"
+   * "fsl,b4860-rcpm"
+
+   Chassis-version strings are of the form "fsl,qoriq-rcpm-",
+   such as:
+   * "fsl,qoriq-rcpm-1.0": for chassis 1.0 rcpm
+   * "fsl,qoriq-rcpm-2.0": for chassis 2.0 rcpm
+   * "fsl,qoriq-rcpm-2.1": for chassis 2.1 rcpm
+
+All references to "1.0" and "2.0" refer to the QorIQ chassis version to
+which the chip complies.
+Chassis VersionExample Chips
+------
+1.0p4080, p5020, p5040, p2041, p3041
+2.0t4240, b4860, b4420
+2.1t1040, ls1021
+
+Example:
+The RCPM node for T4240:
+   rcpm: global-utilities@e2000 {
+   compatible = "fsl,t4240-rcpm", "fsl,qoriq-rcpm-2.0";
+   reg = <0xe2000 0x1000>;
+   };
+
+The RCPM node for P4080:
+   rcpm: global-utilities@e2000 {
+   compatible = "fsl,qoriq-rcpm-1.0";
+   reg = <0xe2000 0x1000>;
+   };
+
+* Freescale RCPM Wakeup Source Device Tree Bindings
+---
+Required rcpm-wakeup property should be added to a device node if the device
+can be used as a wakeup source.
+
+  - rcpm-wakeup: should contain a pointer to the rcpm node and the
+   corresponding bit of device in the register.
+
+Example:
+   lpuart0: serial@295 {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x295 0x0 0x1000>;
+   interrupts = ;
+   clocks = <>;
+   clock-names = "ipg";
+   rcpm-wakeup = < 0x0 0x4000>;
+   status = "disabled";
+   };
-- 
2.1.0.27.g96db324

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[PATCH 2/2] arm/layerscape: add RCPM device tree support for ls1021a.

[Dongsheng Wang]

From: Wang Dongsheng 

Signed-off-by: Wang Dongsheng 

diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 973a496..deb1271 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -139,6 +139,7 @@
sdhci,auto-cmd12;
big-endian;
bus-width = <4>;
+   rcpm-wakeup = < 0x0080 0x0>;
status = "disabled";
};
 
@@ -186,6 +187,11 @@
};
};
 
+   rcpm: rcpm@1ee2000 {
+   compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1";
+   reg = <0x0 0x1ee2000 0x0 0x1>;
+   };
+
dspi0: dspi@210 {
compatible = "fsl,ls1021a-v1.0-dspi";
#address-cells = <1>;
@@ -287,6 +293,7 @@
interrupts = ;
clocks = <>;
clock-names = "ipg";
+   rcpm-wakeup = < 0x0 0x4000>;
status = "disabled";
};
 
-- 
2.1.0.27.g96db324

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[PATCH] powerpc: Add a vga alias node for P1022

[Dongsheng Wang]

From: Jason Jin jason@freescale.com

In u-boot, when set the video as console, the name 'vga' is used
as a general name for the video device, during the fdt_fixup_stdout
process, the 'vga' name is used to search in the dtb to setup the
'linux,stdout-path' node. Though the P1022 DIU is not VGA-compatible
device, to meet the 'vga' name used in u-boot, the vga alias node is
added for P1022 in this patch. At the same time, a display alias is
also added so that no other components grow dependencies on the vga
alias node.

Signed-off-by: Jason Jin jason@freescale.com
Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com

diff --git a/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi 
b/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
index ebf2022..426bf41 100644
--- a/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
@@ -175,7 +175,7 @@
 
 /include/ pq3-gpio-0.dtsi
 
-   display@1 {
+   display: display@1 {
compatible = fsl,diu, fsl,p1022-diu;
reg = 0x1 1000;
interrupts = 64 2 0 0;
diff --git a/arch/powerpc/boot/dts/fsl/p1022si-pre.dtsi 
b/arch/powerpc/boot/dts/fsl/p1022si-pre.dtsi
index 1956dea..de76ae8 100644
--- a/arch/powerpc/boot/dts/fsl/p1022si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1022si-pre.dtsi
@@ -50,6 +50,8 @@
pci0 = pci0;
pci1 = pci1;
pci2 = pci2;
+   vga = display;
+   display = display;
};
 
cpus {
-- 
2.1.0.27.g96db324

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[PATCH v2] video: fbdev: fsl: Fix the sleep function for FSL DIU module

[Dongsheng Wang]

From: Jason Jin jason@freescale.com

For deep sleep, the diu module will power off, when wake up
from the deep sleep, the registers need to be reinitialized.

Signed-off-by: Jason Jin jason@freescale.com
Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
*v2*
Changes:
- int i - unsigned int i.

Rmove:
- struct mfb_info *mfbi;

diff --git a/drivers/video/fbdev/fsl-diu-fb.c b/drivers/video/fbdev/fsl-diu-fb.c
index 7fa2e6f..b335c1a 100644
--- a/drivers/video/fbdev/fsl-diu-fb.c
+++ b/drivers/video/fbdev/fsl-diu-fb.c
@@ -1628,9 +1628,16 @@ static int fsl_diu_suspend(struct platform_device 
*ofdev, pm_message_t state)
 static int fsl_diu_resume(struct platform_device *ofdev)
 {
struct fsl_diu_data *data;
+   unsigned int i;
 
data = dev_get_drvdata(ofdev-dev);
-   enable_lcdc(data-fsl_diu_info);
+
+   fsl_diu_enable_interrupts(data);
+   update_lcdc(data-fsl_diu_info);
+   for (i = 0; i  NUM_AOIS; i++) {
+   if (data-mfb[i].count)
+   fsl_diu_enable_panel(data-fsl_diu_info[i]);
+   }
 
return 0;
 }
-- 
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[PATCH v2 2/2] powerpc/mpc85xx:Add SCFG device tree support of T104x

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
*V2*
No changes.
diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi 
b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
index 9e9f7e2..9770d02 100644
--- a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
@@ -484,6 +484,11 @@
reg= 0xea000 0x4000;
};
 
+   scfg: global-utilities@fc000 {
+   compatible = fsl,t1040-scfg;
+   reg = 0xfc000 0x1000;
+   };
+
 /include/ elo3-dma-0.dtsi
 /include/ elo3-dma-1.dtsi
 /include/ qoriq-espi-0.dtsi
-- 
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[PATCH v2 1/2] powerpc/85xx: Add binding for SCFG

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

SCFG provides SoC specific configuration and status registers for
the chip. Add this for powerpc platform.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
*V2*
- Remove scfg description in board.txt and create scfg.txt for scfg.
- Change fsl,board-scfg to fsl,chip-scfg

diff --git a/Documentation/devicetree/bindings/powerpc/fsl/scfg.txt 
b/Documentation/devicetree/bindings/powerpc/fsl/scfg.txt
new file mode 100644
index 000..0532c46
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/scfg.txt
@@ -0,0 +1,18 @@
+Freescale Supplement configuration unit (SCFG)
+
+SCFG is the supplemental configuration unit, that provides SoC specific
+configuration and status registers for the chip. Such as getting PEX port
+status.
+
+Required properties:
+
+- compatible: should be fsl,chip-scfg
+- reg: should contain base address and length of SCFG memory-mapped
+registers
+
+Example:
+
+   scfg: global-utilities@fc000 {
+   compatible = fsl,t1040-scfg;
+   reg = 0xfc000 0x1000;
+   };
-- 
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[RESEND] powerpc/diu: adjust DIU initialization entry

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

Move fsl_diu_init into diu probe function, because it should be
initialized when system get diu device tree node, not always do
initialization.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
Changes:
Rebase original patch for upstream because fsl-diu-fb.c has moved to fbdev dir.

This patch is a long time ago, there is no feedback, and the Patchwork state
has been modified for the changes requested, I don't know why. So I resend
this patch to upstream.

diff --git a/drivers/video/fbdev/fsl-diu-fb.c b/drivers/video/fbdev/fsl-diu-fb.c
index 7fa2e6f..164e22e 100644
--- a/drivers/video/fbdev/fsl-diu-fb.c
+++ b/drivers/video/fbdev/fsl-diu-fb.c
@@ -1680,6 +1680,105 @@ static ssize_t show_monitor(struct device *device,
return 0;
 }
 
+#ifndef MODULE
+static int __init fsl_diu_setup(char *options)
+{
+   char *opt;
+   unsigned long val;
+
+   if (!options || !*options)
+   return 0;
+
+   while ((opt = strsep(options, ,)) != NULL) {
+   if (!*opt)
+   continue;
+   if (!strncmp(opt, monitor=, 8)) {
+   monitor_port = fsl_diu_name_to_port(opt + 8);
+   } else if (!strncmp(opt, bpp=, 4)) {
+   if (!kstrtoul(opt + 4, 10, val))
+   default_bpp = val;
+   } else {
+   fb_mode = opt;
+   }
+   }
+
+   return 0;
+}
+#endif
+
+static int fsl_diu_perpare(void)
+{
+#ifdef CONFIG_NOT_COHERENT_CACHE
+   struct device_node *np;
+   const u32 *prop;
+#endif
+#ifndef MODULE
+   char *option;
+
+   /*
+* For kernel boot options (in 'video=xxxfb:options' format)
+*/
+   if (fb_get_options(fslfb, option))
+   return -ENODEV;
+   fsl_diu_setup(option);
+#else
+   monitor_port = fsl_diu_name_to_port(monitor_string);
+#endif
+   pr_info(Freescale Display Interface Unit (DIU) framebuffer driver\n);
+
+   if (!diu_ops.set_pixel_clock) {
+   pr_info(%s: Board not support DIU. Can't dispaly video.\n,
+   __func__);
+   return -ENODEV;
+   }
+
+#ifdef CONFIG_NOT_COHERENT_CACHE
+   np = of_find_node_by_type(NULL, cpu);
+   if (!np) {
+   pr_err(fsl-diu-fb: can't find 'cpu' device node\n);
+   return -ENODEV;
+   }
+
+   prop = of_get_property(np, d-cache-size, NULL);
+   if (!prop) {
+   pr_err(fsl-diu-fb: missing 'd-cache-size'\n);
+   of_node_put(np);
+   return -ENODEV;
+   }
+
+   /*
+* Freescale PLRU requires 13/8 times the cache size to do a proper
+* displacement flush
+*/
+   coherence_data_size = be32_to_cpup(prop) * 13;
+   coherence_data_size /= 8;
+
+   pr_debug(fsl-diu-fb: coherence data size is %zu bytes\n,
+coherence_data_size);
+
+   prop = of_get_property(np, d-cache-line-size, NULL);
+   if (!prop) {
+   pr_err(fsl-diu-fb: missing 'd-cache-line-size'\n);
+   of_node_put(np);
+   return -ENODEV;
+   }
+   d_cache_line_size = be32_to_cpup(prop);
+
+   pr_debug(fsl-diu-fb: cache lines size is %u bytes\n,
+d_cache_line_size);
+
+   of_node_put(np);
+   coherence_data = vmalloc(coherence_data_size);
+   if (!coherence_data) {
+   pr_err(fsl-diu-fb: could not allocate coherence data\n);
+   pr_err(coherence_data_size=%zu)\n, coherence_data_size);
+   return -ENOMEM;
+   }
+
+#endif
+   return 0;
+}
+
 static int fsl_diu_probe(struct platform_device *pdev)
 {
struct device_node *np = pdev-dev.of_node;
@@ -1690,10 +1789,16 @@ static int fsl_diu_probe(struct platform_device *pdev)
unsigned int i;
int ret;
 
+   ret = fsl_diu_perpare();
+   if (ret)
+   goto out_perpare;
+
data = dmam_alloc_coherent(pdev-dev, sizeof(struct fsl_diu_data),
   dma_addr, GFP_DMA | __GFP_ZERO);
-   if (!data)
-   return -ENOMEM;
+   if (!data) {
+   ret = -ENOMEM;
+   goto out_perpare;
+   }
data-dma_addr = dma_addr;
 
/*
@@ -1819,6 +1924,11 @@ error:
 
iounmap(data-diu_reg);
 
+out_perpare:
+#if defined(CONFIG_NOT_COHERENT_CACHE)
+   if (coherence_data)
+   vfree(coherence_data);
+#endif
return ret;
 }
 
@@ -1837,34 +1947,12 @@ static int fsl_diu_remove(struct platform_device *pdev)
 
iounmap(data-diu_reg);
 
+#if defined(CONFIG_NOT_COHERENT_CACHE)
+   vfree(coherence_data);
+#endif
return 0;
 }
 
-#ifndef MODULE
-static int __init fsl_diu_setup(char *options)
-{
-   char *opt;
-   unsigned long val;
-
-   if (!options || !*options)
-   return 0;
-
-   while ((opt = 

[PATCH] powerpc/fsl: add power_off support for fsl platform

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

QIXIS System Logic FPGA support to manage system power. So we
through QIXIS to power off freescale SOC.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com

diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c 
b/arch/powerpc/platforms/85xx/corenet_generic.c
index 1f309cc..e1a1eb5 100644
--- a/arch/powerpc/platforms/85xx/corenet_generic.c
+++ b/arch/powerpc/platforms/85xx/corenet_generic.c
@@ -81,6 +81,8 @@ void __init corenet_gen_setup_arch(void)
pr_info(%s board\n, ppc_md.name);
 
mpc85xx_qe_init();
+
+   ppc_md_fixup();
 }
 
 static const struct of_device_id of_device_ids[] = {
diff --git a/arch/powerpc/sysdev/fsl_soc.c b/arch/powerpc/sysdev/fsl_soc.c
index 99269c0..6de9f1b 100644
--- a/arch/powerpc/sysdev/fsl_soc.c
+++ b/arch/powerpc/sysdev/fsl_soc.c
@@ -215,6 +215,54 @@ void fsl_rstcr_restart(char *cmd)
 }
 #endif
 
+#define QIXIS_PWR_CTL2 0x21
+#define QIXIS_PWR_CTL2_PWR 0x80
+static void fsl_power_off(void)
+{
+   struct device_node *pixis_node;
+   void __iomem *pixis;
+   u32 pwroff_offset, value;
+
+   pixis_node = of_find_compatible_node(NULL, NULL, fsl,fpga-qixis);
+   if (!pixis_node) {
+   pr_err(%s: Missing pixis node\n, __func__);
+   return;
+   }
+
+   pwroff_offset = QIXIS_PWR_CTL2;
+   value = QIXIS_PWR_CTL2_PWR;
+
+   pixis = of_iomap(pixis_node, 0);
+   of_node_put(pixis_node);
+   if (!pixis) {
+   pr_err(%s: Could not map pixis registers\n, __func__);
+   return;
+   }
+
+   local_irq_disable();
+
+   setbits8(pixis + pwroff_offset, value);
+
+   iounmap(pixis);
+
+   while (1)
+   ;
+}
+
+void ppc_md_fixup(void)
+{
+   struct device_node *np;
+
+   np = of_find_compatible_node(NULL, NULL, fsl,fpga-qixis);
+   if (!np)
+   return;
+
+   of_node_put(np);
+
+   pm_power_off = fsl_power_off;
+   ppc_md.halt = fsl_power_off;
+}
+
 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
 struct platform_diu_data_ops diu_ops;
 EXPORT_SYMBOL(diu_ops);
diff --git a/arch/powerpc/sysdev/fsl_soc.h b/arch/powerpc/sysdev/fsl_soc.h
index 4c5a19e..ca90e24 100644
--- a/arch/powerpc/sysdev/fsl_soc.h
+++ b/arch/powerpc/sysdev/fsl_soc.h
@@ -21,6 +21,8 @@ struct device_node;
 
 extern void fsl_rstcr_restart(char *cmd);
 
+void ppc_md_fixup(void);
+
 /* The different ports that the DIU can be connected to */
 enum fsl_diu_monitor_port {
FSL_DIU_PORT_DVI,   /* DVI */
-- 
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[PATCH] fsl/smp: add low power boot support to replace spin boot

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

U-boot put non-boot cpus into an low power state(PW10/PW20 or DOZE) when cpu
powered up. To exit low power state kernel will send DOORBELL or MPIC-IPI
signal to all those CPUs.

e500/e500v2 use mpic to send IPI signal.
e500mc and later use doorbell to send IPI signal.

This feature tested on:
POWER UP TEST:
P1022DS(e500v2),96k times.
P4080(e500mc),  110k times.
T1024(e5500),   83k times.
T4240(e6500),   150k times.

CPU HOTPLUG TEST:
P1022DS(e500v2),1.4 million times.
P4080(e500mc),  1.8 million times.
T1024(e5500),   1.3 million times.
T4240(e6500),   1.1 million times.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com

diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index 754f93d..8af6a25 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -474,6 +474,15 @@ extern int mpic_cpu_get_priority(void);
 /* Set the current cpu priority for this cpu */
 extern void mpic_cpu_set_priority(int prio);
 
+/* Set cpu priority */
+void mpic_set_cpu_priority(int nr, int prio);
+
+/* Set cpu EOI */
+void mpic_cpu_eoi_write(int cpu);
+
+/* CPU ACK interrupt */
+void mpic_cpu_ack(int cpu);
+
 /* Request IPIs on primary mpic */
 extern void mpic_request_ipis(void);
 
diff --git a/arch/powerpc/platforms/85xx/smp.c 
b/arch/powerpc/platforms/85xx/smp.c
index d7c1e69..6c54632 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/platforms/85xx/smp.c
@@ -193,6 +193,30 @@ static int smp_85xx_kick_cpu(int nr)
const u64 *cpu_rel_addr;
__iomem struct epapr_spin_table *spin_table;
struct device_node *np;
+
+   /*
+* DOORBELL:
+* When kernel kick one of cpus, all cpus will be wakenup. To make
+* sure that only the target cpu is effected, other cpus (by checking
+* spin_table-addr_l) should go back to low power state.
+*
+* U-boot has renumber the cpu PIR Why we need to set all of PIR to
+* the same value?
+* A: Before kernel kicking cpu, the doorbell message was not configured
+* for target cpu(cpu_messages-data). If we try to send a
+* non-configured message to target cpu, it cannot correctly receive
+* doorbell interrput. So SET ALL OF CPU'S PIR to the same value to
+* let all cpus catch the interrupt.
+*
+* Why set PIR to zero?
+* A: U-boot cannot know how many cpus will be kicked up(Kernel allow us
+* to configure NR_CPUS) and IPI is a per_cpu variable, u-boot cannot
+* set a appropriate PIR for every cpu, but the boot cpu(CPU0) always be
+* there. U-boot set PIR to zero as a default PIR ID for each CPU, so
+* initialize the kick_cpus to 0.
+*/
+   u32 kick_cpus = 0;
+
int hw_cpu = get_hard_smp_processor_id(nr);
int ioremappable;
int ret = 0;
@@ -251,8 +275,7 @@ static int smp_85xx_kick_cpu(int nr)
spin_table = phys_to_virt(*cpu_rel_addr);
 
local_irq_save(flags);
-#ifdef CONFIG_PPC32
-#ifdef CONFIG_HOTPLUG_CPU
+#if defined(CONFIG_PPC32)  defined(CONFIG_HOTPLUG_CPU)
/* Corresponding to generic_set_cpu_dead() */
generic_set_cpu_up(nr);
 
@@ -292,11 +315,58 @@ static int smp_85xx_kick_cpu(int nr)
__secondary_hold_acknowledge = -1;
}
 #endif
+
flush_spin_table(spin_table);
-   out_be32(spin_table-pir, hw_cpu);
+   /*
+* U-boot will wait kernel send eoi to MPIC, after EOI has send
+* kernel will set PIR for uboot, let uboot know EOI has send.
+*/
+   out_be32(spin_table-pir, 0);
+
+#ifdef CONFIG_PPC32
out_be32(spin_table-addr_l, __pa(__early_start));
+#else
+   out_be64((u64 *)(spin_table-addr_h),
+__pa(ppc_function_entry(generic_secondary_smp_init)));
+#endif
flush_spin_table(spin_table);
 
+   /*
+* e500, e500v2 need to use MPIC to send IPI signal, so we need to
+* open IPI firstly.
+*/
+   if (!cpu_has_feature(CPU_FTR_DBELL)) {
+   mpic_set_cpu_priority(nr, 0);
+   kick_cpus = nr;
+   }
+
+   /* Let cpu exit low power state, and from u-boot jump to kernel */
+   arch_send_call_function_single_ipi(kick_cpus);
+
+   /*
+* Let we ACK interrput and Send EOI signal to finish INT server
+* U-boot has read EPR to ACK interrput when MPIC work in external
+* proxy mode. Without the external proxy facility, we need to read
+* MPIC ACK register.
+*
+* There just ACK interrput, we don't need to get the interrupt vector
+* and to handle it. Because there just IPI or DOORBELL interrupt to
+* make u-boot exit low power state and jump to kernel.
+*/
+   mpic_cpu_ack(nr);
+   /* Send EOI to clear ISR bit to remove interrupt from service */
+   mpic_cpu_eoi_write(nr);
+
+   /* After wakeup CPU disable 

[PATCH] powerpc/smp: Fix Non-boot cpus cannot be bring up.

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

Kernel cannot bring up Non-boot cpus always get Processor xx is stuck.
this issue bring by http://patchwork.ozlabs.org/patch/418912/ (powerpc:
Secondary CPUs must set cpu_callin_map after setting active and online)
We need to take timebase after bootup cpu give the timebase firstly.

When start_secondary, non-boot cpus set cpu_callin_map for boot cpu
after that boot cpu will give the timebase for non-boot cpu. Otherwise
non-boot cpus will fall in dead loop to waiting bootup cpu to give
imebase.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com

diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index 8ec017c..9e29836 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -703,10 +703,6 @@ void start_secondary(void *unused)
 
if (smp_ops-setup_cpu)
smp_ops-setup_cpu(cpu);
-   if (smp_ops-take_timebase)
-   smp_ops-take_timebase();
-
-   secondary_cpu_time_init();
 
 #ifdef CONFIG_PPC64
if (system_state == SYSTEM_RUNNING)
@@ -746,6 +742,16 @@ void start_secondary(void *unused)
smp_wmb();
cpu_callin_map[cpu] = 1;
 
+   /*
+* We need to take timebase after bootup cpu give the timebase.
+* Base on cpu_callin_map move to here, so we also need move
+* take_timebase. Because bootup cpu waiting for cpu_callin_map
+* be set after that give_timebase can be executed.
+*/
+   if (smp_ops-take_timebase)
+   smp_ops-take_timebase();
+   secondary_cpu_time_init();
+
local_irq_enable();
 
cpu_startup_entry(CPUHP_ONLINE);
-- 
2.1.0.27.g96db324

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[PATCH v2 1/2] powerpc/pm: add api to get suspend state which is STANDBY or MEM

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

Add set_pm_suspend_state  pm_suspend_state functions to set/get
suspend state. When system going to sleep or deep sleep, devices
can get the system suspend state(STANDBY/MEM) through pm_suspend_state
function and to handle different situations.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
*v2*
Move pm api from fsl platform to powerpc general framework.

diff --git a/arch/powerpc/include/asm/pm.h b/arch/powerpc/include/asm/pm.h
new file mode 100644
index 000..00ddbf1
--- /dev/null
+++ b/arch/powerpc/include/asm/pm.h
@@ -0,0 +1,26 @@
+/*
+ * asm/pm.h
+ *
+ * Definitions for any platform related flags or structures for
+ * Power Management.
+ *
+ * Author: Wang Dongsheng dongsheng.w...@freescale.com
+ *
+ * Copyright 2014 Freescale Semiconductor, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef _POWERPC_PM_H_
+#define _POWERPC_PM_H_
+#ifdef __KERNEL__
+#include linux/suspend.h
+
+extern void set_pm_suspend_state(suspend_state_t state);
+extern suspend_state_t pm_suspend_state(void);
+
+#endif /* __KERNEL__ */
+#endif /* _POWERPC_PM_H_ */
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index fcc9a89..2060145 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -28,7 +28,7 @@ endif
 
 obj-y  := cputable.o ptrace.o syscalls.o \
   irq.o align.o signal_32.o pmc.o vdso.o \
-  process.o systbl.o idle.o \
+  process.o systbl.o idle.o pm.o \
   signal.o sysfs.o cacheinfo.o time.o \
   prom.o traps.o setup-common.o \
   udbg.o misc.o io.o dma.o \
diff --git a/arch/powerpc/kernel/pm.c b/arch/powerpc/kernel/pm.c
new file mode 100644
index 000..23d3c94
--- /dev/null
+++ b/arch/powerpc/kernel/pm.c
@@ -0,0 +1,26 @@
+/*
+ * PowerPC General Power Management Implementation
+ *
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ * Author: Wang Dongsheng dongsheng.w...@freescale.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include linux/suspend.h
+#include asm/pm.h
+
+static suspend_state_t pm_state;
+
+void set_pm_suspend_state(suspend_state_t state)
+{
+   pm_state = state;
+}
+
+suspend_state_t pm_suspend_state(void)
+{
+   return pm_state;
+}
diff --git a/arch/powerpc/sysdev/fsl_pmc.c b/arch/powerpc/sysdev/fsl_pmc.c
index 8cf4aa0..fd777ca 100644
--- a/arch/powerpc/sysdev/fsl_pmc.c
+++ b/arch/powerpc/sysdev/fsl_pmc.c
@@ -21,6 +21,8 @@
 #include linux/of_address.h
 #include linux/of_platform.h
 
+#include asm/pm.h
+
 struct pmc_regs {
__be32 devdisr;
__be32 devdisr2;
@@ -52,12 +54,20 @@ static int pmc_suspend_valid(suspend_state_t state)
 {
if (state != PM_SUSPEND_STANDBY)
return 0;
+
+   set_pm_suspend_state(state);
return 1;
 }
 
+static void pmc_suspend_end(void)
+{
+   set_pm_suspend_state(PM_SUSPEND_ON);
+}
+
 static const struct platform_suspend_ops pmc_suspend_ops = {
.valid = pmc_suspend_valid,
.enter = pmc_suspend_enter,
+   .end= pmc_suspend_end,
 };
 
 static int pmc_probe(struct platform_device *ofdev)
@@ -68,6 +78,7 @@ static int pmc_probe(struct platform_device *ofdev)
 
pmc_dev = ofdev-dev;
suspend_set_ops(pmc_suspend_ops);
+   set_pm_suspend_state(PM_SUSPEND_ON);
return 0;
 }
 
-- 
1.8.5

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[PATCH v2 2/2] fsl/mpic_timer: make mpic_timer to support deep sleep feature

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

At T104x platfrom the timer clock will be changed from platform_clock
to sys_ref_clock when system going to deep sleep.

So before system going to deep sleep, we need to change time to adapt
to the new frequency that is sys_ref_clock. And after resume from deep
sleep, restore the time that based on platform_clock.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
*v2*
Remove some unnecessary warning message.
Remove switch_freq_flag, it's unnecessary.

Modify the description of the patch.

diff --git a/arch/powerpc/sysdev/mpic_timer.c b/arch/powerpc/sysdev/mpic_timer.c
index 9d9b062..71ad368 100644
--- a/arch/powerpc/sysdev/mpic_timer.c
+++ b/arch/powerpc/sysdev/mpic_timer.c
@@ -18,6 +18,7 @@
 #include linux/mm.h
 #include linux/interrupt.h
 #include linux/slab.h
+#include linux/suspend.h
 #include linux/of.h
 #include linux/of_address.h
 #include linux/of_device.h
@@ -26,7 +27,9 @@
 #include sysdev/fsl_soc.h
 #include asm/io.h
 
+#include asm/mpc85xx.h
 #include asm/mpic_timer.h
+#include asm/pm.h
 
 #define FSL_GLOBAL_TIMER   0x1
 
@@ -72,6 +75,8 @@ struct timer_group_priv {
struct mpic_timer   timer[TIMERS_PER_GROUP];
struct list_headnode;
unsigned inttimerfreq;
+   unsigned intsuspended_timerfreq;
+   unsigned intresume_timerfreq;
unsigned intidle;
unsigned intflags;
spinlock_t  lock;
@@ -423,6 +428,33 @@ struct mpic_timer *mpic_request_timer(irq_handler_t fn, 
void *dev,
 }
 EXPORT_SYMBOL(mpic_request_timer);
 
+static void timer_group_get_suspended_freq(struct timer_group_priv *priv)
+{
+   struct device_node *np;
+
+   np = of_find_compatible_node(NULL, NULL, fsl,qoriq-clockgen-2.0);
+   if (!np)
+   return;
+
+   of_property_read_u32(np, clock-frequency, priv-suspended_timerfreq);
+   of_node_put(np);
+
+   if (!priv-suspended_timerfreq)
+   pr_warn(Mpic timer will not be accurate during deep sleep.\n);
+}
+
+static int need_to_switch_freq(void)
+{
+   u32 svr;
+
+   svr = mfspr(SPRN_SVR);
+   if (SVR_SOC_VER(svr) == SVR_T1040 ||
+   SVR_SOC_VER(svr) == SVR_T1042)
+   return 1;
+
+   return 0;
+}
+
 static int timer_group_get_freq(struct device_node *np,
struct timer_group_priv *priv)
 {
@@ -437,6 +469,13 @@ static int timer_group_get_freq(struct device_node *np,
priv-timerfreq);
of_node_put(dn);
}
+
+   /*
+* For deep sleep, if system goes to deep sleep,
+* timer freq will be changed.
+*/
+   if (need_to_switch_freq())
+   timer_group_get_suspended_freq(priv);
}
 
if (priv-timerfreq = 0)
@@ -445,6 +484,7 @@ static int timer_group_get_freq(struct device_node *np,
if (priv-flags  FSL_GLOBAL_TIMER) {
div = (1  (MPIC_TIMER_TCR_CLKDIV  8)) * 8;
priv-timerfreq /= div;
+   priv-suspended_timerfreq /= div;
}
 
return 0;
@@ -564,14 +604,182 @@ out:
kfree(priv);
 }
 
+static void mpic_reset_time(struct mpic_timer *handle, struct timeval 
*bcr_time,
+   struct timeval *ccr_time)
+{
+   struct timer_group_priv *priv = container_of(handle,
+   struct timer_group_priv, timer[handle-num]);
+
+   u64 ccr_ticks = 0;
+   u64 bcr_ticks = 0;
+
+   /* switch bcr time */
+   convert_time_to_ticks(priv, bcr_time, bcr_ticks);
+
+   /* switch ccr time */
+   convert_time_to_ticks(priv, ccr_time, ccr_ticks);
+
+   if (handle-cascade_handle) {
+   u32 tmp_ticks;
+   u32 rem_ticks;
+
+   /* reset ccr ticks to bcr */
+   tmp_ticks = div_u64_rem(ccr_ticks, MAX_TICKS_CASCADE,
+   rem_ticks);
+   out_be32(priv-regs[handle-num].gtbcr,
+   tmp_ticks | TIMER_STOP);
+   out_be32(priv-regs[handle-num - 1].gtbcr, rem_ticks);
+
+   /* start timer */
+   clrbits32(priv-regs[handle-num].gtbcr, TIMER_STOP);
+
+   /* reset bcr */
+   tmp_ticks = div_u64_rem(bcr_ticks, MAX_TICKS_CASCADE,
+   rem_ticks);
+   out_be32(priv-regs[handle-num].gtbcr,
+   tmp_ticks  ~TIMER_STOP);
+   out_be32(priv-regs[handle-num - 1].gtbcr, rem_ticks);
+   } else {
+   /* reset ccr ticks to bcr */
+   out_be32(priv-regs[handle-num].gtbcr,
+   ccr_ticks | TIMER_STOP);
+   /* start timer */
+   

[PATCH] powerpc/diu: adjust DIU initialization entry

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

Move fsl_diu_init into diu probe function, because it should be
initialized when system get diu device tree node, not always do
initialization.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com

diff --git a/drivers/video/fsl-diu-fb.c b/drivers/video/fsl-diu-fb.c
index e8758b9..75ab20e 100644
--- a/drivers/video/fsl-diu-fb.c
+++ b/drivers/video/fsl-diu-fb.c
@@ -1680,6 +1680,99 @@ static ssize_t show_monitor(struct device *device,
return 0;
 }
 
+#ifndef MODULE
+static int __init fsl_diu_setup(char *options)
+{
+   char *opt;
+   unsigned long val;
+
+   if (!options || !*options)
+   return 0;
+
+   while ((opt = strsep(options, ,)) != NULL) {
+   if (!*opt)
+   continue;
+   if (!strncmp(opt, monitor=, 8)) {
+   monitor_port = fsl_diu_name_to_port(opt + 8);
+   } else if (!strncmp(opt, bpp=, 4)) {
+   if (!kstrtoul(opt + 4, 10, val))
+   default_bpp = val;
+   } else
+   fb_mode = opt;
+   }
+
+   return 0;
+}
+#endif
+
+static int fsl_diu_perpare(void)
+{
+#ifdef CONFIG_NOT_COHERENT_CACHE
+   struct device_node *np;
+   const u32 *prop;
+#endif
+   int ret;
+#ifndef MODULE
+   char *option;
+
+   /*
+* For kernel boot options (in 'video=xxxfb:options' format)
+*/
+   if (fb_get_options(fslfb, option))
+   return -ENODEV;
+   fsl_diu_setup(option);
+#else
+   monitor_port = fsl_diu_name_to_port(monitor_string);
+#endif
+   pr_info(Freescale Display Interface Unit (DIU) framebuffer driver\n);
+
+#ifdef CONFIG_NOT_COHERENT_CACHE
+   np = of_find_node_by_type(NULL, cpu);
+   if (!np) {
+   pr_err(fsl-diu-fb: can't find 'cpu' device node\n);
+   return -ENODEV;
+   }
+
+   prop = of_get_property(np, d-cache-size, NULL);
+   if (prop == NULL) {
+   pr_err(fsl-diu-fb: missing 'd-cache-size'\n);
+   of_node_put(np);
+   return -ENODEV;
+   }
+
+   /*
+* Freescale PLRU requires 13/8 times the cache size to do a proper
+* displacement flush
+*/
+   coherence_data_size = be32_to_cpup(prop) * 13;
+   coherence_data_size /= 8;
+
+   pr_debug(fsl-diu-fb: coherence data size is %zu bytes\n,
+coherence_data_size);
+
+   prop = of_get_property(np, d-cache-line-size, NULL);
+   if (prop == NULL) {
+   pr_err(fsl-diu-fb: missing 'd-cache-line-size'\n);
+   of_node_put(np);
+   return -ENODEV;
+   }
+   d_cache_line_size = be32_to_cpup(prop);
+
+   pr_debug(fsl-diu-fb: cache lines size is %u bytes\n,
+d_cache_line_size);
+
+   of_node_put(np);
+   coherence_data = vmalloc(coherence_data_size);
+   if (!coherence_data) {
+   pr_err(fsl-diu-fb: could not allocate coherence data\n);
+   pr_err(coherence_data_size=%zu)\n, coherence_data_size);
+   return -ENOMEM;
+   }
+
+#endif
+   return ret;
+}
+
 static int fsl_diu_probe(struct platform_device *pdev)
 {
struct device_node *np = pdev-dev.of_node;
@@ -1690,10 +1783,14 @@ static int fsl_diu_probe(struct platform_device *pdev)
unsigned int i;
int ret;
 
+   fsl_diu_perpare();
+
data = dmam_alloc_coherent(pdev-dev, sizeof(struct fsl_diu_data),
   dma_addr, GFP_DMA | __GFP_ZERO);
-   if (!data)
-   return -ENOMEM;
+   if (!data) {
+   ret = -ENOMEM;
+   goto out_perpare;
+   }
data-dma_addr = dma_addr;
 
/*
@@ -1819,6 +1916,11 @@ error:
 
iounmap(data-diu_reg);
 
+out_perpare:
+#if defined(CONFIG_NOT_COHERENT_CACHE)
+   if (coherence_data)
+   vfree(coherence_data);
+#endif
return ret;
 }
 
@@ -1837,34 +1939,12 @@ static int fsl_diu_remove(struct platform_device *pdev)
 
iounmap(data-diu_reg);
 
+#if defined(CONFIG_NOT_COHERENT_CACHE)
+   vfree(coherence_data);
+#endif
return 0;
 }
 
-#ifndef MODULE
-static int __init fsl_diu_setup(char *options)
-{
-   char *opt;
-   unsigned long val;
-
-   if (!options || !*options)
-   return 0;
-
-   while ((opt = strsep(options, ,)) != NULL) {
-   if (!*opt)
-   continue;
-   if (!strncmp(opt, monitor=, 8)) {
-   monitor_port = fsl_diu_name_to_port(opt + 8);
-   } else if (!strncmp(opt, bpp=, 4)) {
-   if (!kstrtoul(opt + 4, 10, val))
-   default_bpp = val;
-   } else
-   fb_mode = opt;
-   }
-
-   return 0;
-}
-#endif
-
 static struct of_device_id fsl_diu_match[] = {
 #ifdef 

[PATCH 1/2] fsl/pci: fix RC cannot detect PME message coming

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

PCI controller disable PME message report feature, that shouldn't
have happened. Fix it and enable PME message report feature.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com

diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 3f415e2..4bd091a 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -1150,8 +1150,7 @@ static int fsl_pci_pme_probe(struct pci_controller *hose)
pci = hose-private_data;
 
/* Enable PTOD, ENL23D  EXL23D */
-   out_be32(pci-pex_pme_mes_disr, 0);
-   setbits32(pci-pex_pme_mes_disr,
+   clrbits32(pci-pex_pme_mes_disr,
  PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D);
 
out_be32(pci-pex_pme_mes_ier, 0);
-- 
1.8.5


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[PATCH 2/2] fsl/pci: fix EP device sometimes hangup when system resume from sleep

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

Root cause is pcie power management state transition need a delay.
The delay time define in PCI Bus Power Management Interface Specification.

D0, D1 or D2 -- D3 need to delay 10ms.
D3 -- D0 need to delay 10ms.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com

diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 4bd091a..33950ad 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -1175,15 +1175,24 @@ static void send_pme_turnoff_message(struct 
pci_controller *hose)
setbits32(pci-pex_pmcr, PEX_PMCR_PTOMR);
 
/* Wait trun off done */
-   for (i = 0; i  150; i++) {
+   /* RC will get this detect quickly */
+   for (i = 0; i  50; i++) {
dr = in_be32(pci-pex_pme_mes_dr);
-   if (dr) {
+   if (dr  ENL23_DETECT_BIT) {
out_be32(pci-pex_pme_mes_dr, dr);
break;
}
 
udelay(1000);
}
+
+   /*
+* PCI Bus Power Management Interface Specification define
+* Minimum System Software Guaranteed Delays
+*
+* D0, D1 or D2 -- D3, need delay 10ms.
+*/
+   mdelay(10);
 }
 
 static void fsl_pci_syscore_do_suspend(struct pci_controller *hose)
@@ -1211,9 +1220,10 @@ static void fsl_pci_syscore_do_resume(struct 
pci_controller *hose)
setbits32(pci-pex_pmcr, PEX_PMCR_EXL2S);
 
/* Wait exit done */
-   for (i = 0; i  150; i++) {
+   /* RC will get this detect quickly */
+   for (i = 0; i  50; i++) {
dr = in_be32(pci-pex_pme_mes_dr);
-   if (dr) {
+   if (dr  EXL23_DETECT_BIT) {
out_be32(pci-pex_pme_mes_dr, dr);
break;
}
@@ -1221,6 +1231,14 @@ static void fsl_pci_syscore_do_resume(struct 
pci_controller *hose)
udelay(1000);
}
 
+   /*
+* PCI Bus Power Management Interface Specification define
+* Minimum System Software Guaranteed Delays
+*
+* D3 hot -- D0, need delay 10ms.
+*/
+   mdelay(10);
+
setup_pci_atmu(hose);
 }
 
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
index c1cec77..37fc644 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -39,6 +39,9 @@ struct platform_device;
 #define PME_DISR_EN_ENL23D 0x2000
 #define PME_DISR_EN_EXL23D 0x1000
 
+#define ENL23_DETECT_BIT0x2000
+#define EXL23_DETECT_BIT0x1000
+
 /* PCI/PCI Express outbound window reg */
 struct pci_outbound_window_regs {
__be32  potar;  /* 0x.0 - Outbound translation address register */
-- 
1.8.5


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[PATCH v2 2/2] fsl/corenet_generic: add t104x platform diu special initialization

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

T104x Platforms based on corenet_generic. The platforms DIU-block
that need a special initialization to solve some callback functions,
those functions depend on platform handle.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
This patch is *depends on* Prabhakar Kushwaha support T104x patchset.

v2: No change.
diff --git a/arch/powerpc/platforms/85xx/fix/Makefile 
b/arch/powerpc/platforms/85xx/fix/Makefile
index a8e8154..0530acd 100644
--- a/arch/powerpc/platforms/85xx/fix/Makefile
+++ b/arch/powerpc/platforms/85xx/fix/Makefile
@@ -1 +1,3 @@
 obj-y += fix.o
+
+obj-y += t104x_diu.o
diff --git a/arch/powerpc/platforms/85xx/fix/fix.c 
b/arch/powerpc/platforms/85xx/fix/fix.c
index 7b59a52..c278eb1 100644
--- a/arch/powerpc/platforms/85xx/fix/fix.c
+++ b/arch/powerpc/platforms/85xx/fix/fix.c
@@ -21,6 +21,19 @@
 
 static int fix_platform_init(void)
 {
+   u32 svr;
+
+   svr = SVR_SOC_VER(mfspr(SPRN_SVR));
+
+   switch (svr) {
+   case SVR_T1040:
+   case SVR_T1042:
+   fix_t104x_diu_init();
+   break;
+   default:
+   pr_info(Platform is not need to fix anything\n);
+   }
+
return 0;
 }
 early_initcall(fix_platform_init);
diff --git a/arch/powerpc/platforms/85xx/fix/fix.h 
b/arch/powerpc/platforms/85xx/fix/fix.h
index 5a8c80e3..d27635f 100644
--- a/arch/powerpc/platforms/85xx/fix/fix.h
+++ b/arch/powerpc/platforms/85xx/fix/fix.h
@@ -1,4 +1,6 @@
 #ifndef __CORENET_GENERIC_FIX_H__
 #define __CORENET_GENERIC_FIX_H__
 
+extern void fix_t104x_diu_init(void);
+
 #endif
diff --git a/arch/powerpc/platforms/85xx/fix/t104x_diu.c 
b/arch/powerpc/platforms/85xx/fix/t104x_diu.c
new file mode 100644
index 000..39c7242
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/fix/t104x_diu.c
@@ -0,0 +1,155 @@
+/*
+ * T104x RDB Particular Setup
+ * Should apply for RDB platform of T1040 and it's personalities.
+ * viz T1040/T1042
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include linux/kernel.h
+#include linux/of.h
+#include linux/of_address.h
+
+#include asm/io.h
+#include sysdev/fsl_soc.h
+
+#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
+/*DIU Pixel ClockCR offset in scfg*/
+#define CCSR_SCFG_PIXCLKCR  0x28
+
+/* DIU Pixel Clock bits of the PIXCLKCR */
+#define PIXCLKCR_PXCKEN0x8000
+#define PIXCLKCR_PXCKINV   0x4000
+#define PIXCLKCR_PXCKDLY   0xFF00
+#define PIXCLKCR_PXCLK_MASK0x00FF
+
+/* Some CPLD register definitions */
+#define CPLD_DIUCSR0x16
+#define CPLD_DIUCSR_DVIEN  0x80
+#define CPLD_DIUCSR_BACKLIGHT  0x0f
+
+/**
+ * t104xrdb_set_monitor_port: switch the output to a different monitor port
+ */
+static void t104xrdb_set_monitor_port(enum fsl_diu_monitor_port port)
+{
+   struct device_node *cpld_node;
+   static void __iomem *cpld_base;
+
+   cpld_node = of_find_compatible_node(NULL, NULL, fsl,t104xrdb-cpld);
+   if (!cpld_node) {
+   pr_err(T104xRDB: missing CPLD node\n);
+   return;
+   }
+
+   cpld_base = of_iomap(cpld_node, 0);
+   if (!cpld_base) {
+   pr_err(T104xRDB: could not map cpld registers\n);
+   goto exit;
+   }
+
+   switch (port) {
+   case FSL_DIU_PORT_DVI:
+   /* Enable the DVI(HDMI) port, disable the DFP and
+* the backlight
+*/
+   clrbits8(cpld_base + CPLD_DIUCSR, CPLD_DIUCSR_DVIEN);
+   break;
+   case FSL_DIU_PORT_LVDS:
+   /*
+* LVDS also needs backlight enabled, otherwise the display
+* will be blank.
+*/
+   /* Enable the DFP port, disable the DVI*/
+   setbits8(cpld_base + CPLD_DIUCSR, 0x01  8);
+   setbits8(cpld_base + CPLD_DIUCSR, 0x01  4);
+   setbits8(cpld_base + CPLD_DIUCSR, CPLD_DIUCSR_BACKLIGHT);
+   break;
+   default:
+   pr_err(T104xRDB: unsupported monitor port %i\n, port);
+   }
+
+exit:
+   of_node_put(cpld_node);
+}
+
+/**
+ * t104xrdb_set_pixel_clock: program the DIU's clock
+ *
+ * @pixclock: the wavelength, in picoseconds, of the clock
+ */
+static void t104xrdb_set_pixel_clock(unsigned int pixclock)
+{
+   struct device_node *scfg_np = NULL;
+   void __iomem *scfg;
+   unsigned long freq;
+   u64 temp;
+   u32 pxclk;
+
+   /* Map the global utilities registers. */
+   scfg_np = of_find_compatible_node(NULL, NULL, fsl,t1040-scfg);
+   if (!scfg_np) {
+   freq = temp;
+   pr_err(T104xRDB: missing supplemental configuration unit 

[PATCH v2 1/2] fsl/corenet_generic: add a particular initialization for platform

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

Corenet_generic is a generic platform initialization. Those based on
the corenet_generic board maybe need a particular initialize to
enable/set some IP-Blocks. So add Fix Generic Initialization to solve
this kind of special cases.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
*v2*
 1/ Split DIU code.
 2/ make fix.c as a independent driver.
diff --git a/arch/powerpc/platforms/85xx/Kconfig 
b/arch/powerpc/platforms/85xx/Kconfig
index c17aae8..fce2341 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -269,6 +269,17 @@ config CORENET_GENERIC
  The following boards are supported for both 32bit and 64bit kernel:
P5020 DS and P5040 DS
 
+config FIX_GENERIC_PLATFORM_INIT
+   bool Fix Generic Initialization
+   depends on CORENET_GENERIC
+   default y
+   help
+ This option will create a initialization that is a append 
initialization
+ for a particular platfrom. And this particular platform also based on
+ Freescale CoreNet Generic.
+
+ e.g. DIU need a special initialization at T104x platform.
+
 endif # FSL_SOC_BOOKE
 
 config TQM85xx
diff --git a/arch/powerpc/platforms/85xx/Makefile 
b/arch/powerpc/platforms/85xx/Makefile
index 25cebe7..1162ac7 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_P1022_RDK)   += p1022_rdk.o
 obj-$(CONFIG_P1023_RDS)   += p1023_rds.o
 obj-$(CONFIG_TWR_P102x)   += twr_p102x.o
 obj-$(CONFIG_CORENET_GENERIC)   += corenet_generic.o
+obj-$(CONFIG_FIX_GENERIC_PLATFORM_INIT) += fix/
 obj-$(CONFIG_STX_GP3)+= stx_gp3.o
 obj-$(CONFIG_TQM85xx)+= tqm85xx.o
 obj-$(CONFIG_SBC8548) += sbc8548.o
diff --git a/arch/powerpc/platforms/85xx/fix/Makefile 
b/arch/powerpc/platforms/85xx/fix/Makefile
new file mode 100644
index 000..a8e8154
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/fix/Makefile
@@ -0,0 +1 @@
+obj-y += fix.o
diff --git a/arch/powerpc/platforms/85xx/fix/fix.c 
b/arch/powerpc/platforms/85xx/fix/fix.c
new file mode 100644
index 000..7b59a52
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/fix/fix.c
@@ -0,0 +1,26 @@
+/*
+ * Fix Different Boards Particular Initialization
+ *
+ * Author: Wang Dongsheng dongsheng.w...@freescale.com
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include linux/kernel.h
+
+#include asm/mpc85xx.h
+#include asm/reg.h
+#include asm/reg_booke.h
+
+#include fix.h
+
+static int fix_platform_init(void)
+{
+   return 0;
+}
+early_initcall(fix_platform_init);
diff --git a/arch/powerpc/platforms/85xx/fix/fix.h 
b/arch/powerpc/platforms/85xx/fix/fix.h
new file mode 100644
index 000..5a8c80e3
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/fix/fix.h
@@ -0,0 +1,4 @@
+#ifndef __CORENET_GENERIC_FIX_H__
+#define __CORENET_GENERIC_FIX_H__
+
+#endif
-- 
1.8.5


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[PATCH 1/2] powerpc/mpc85xx: add two functions to get suspend state which is standby or mem

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

Add set_pm_suspend_state  pm_suspend_state functions to set/get suspend state.
When system going to sleep, devices can get the system suspend 
state(STANDBY/MEM)
through pm_suspend_state function and handle different situations.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com

diff --git a/arch/powerpc/platforms/85xx/common.c 
b/arch/powerpc/platforms/85xx/common.c
index b564b5e..3853d43 100644
--- a/arch/powerpc/platforms/85xx/common.c
+++ b/arch/powerpc/platforms/85xx/common.c
@@ -8,6 +8,7 @@
 
 #include linux/of_irq.h
 #include linux/of_platform.h
+#include linux/suspend.h
 
 #include asm/qe.h
 #include sysdev/cpm2_pic.h
@@ -47,6 +48,19 @@ int __init mpc85xx_common_publish_devices(void)
 {
return of_platform_bus_probe(NULL, mpc85xx_common_ids, NULL);
 }
+
+static suspend_state_t pm_state;
+
+void set_pm_suspend_state(suspend_state_t state)
+{
+   pm_state = state;
+}
+
+suspend_state_t pm_suspend_state(void)
+{
+   return pm_state;
+}
+
 #ifdef CONFIG_CPM2
 static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
 {
diff --git a/arch/powerpc/sysdev/fsl_pmc.c b/arch/powerpc/sysdev/fsl_pmc.c
index 8cf4aa0..0b34c00 100644
--- a/arch/powerpc/sysdev/fsl_pmc.c
+++ b/arch/powerpc/sysdev/fsl_pmc.c
@@ -15,6 +15,7 @@
 #include linux/types.h
 #include linux/errno.h
 #include linux/export.h
+#include linux/fsl/fsl_pm.h
 #include linux/suspend.h
 #include linux/delay.h
 #include linux/device.h
@@ -52,12 +53,20 @@ static int pmc_suspend_valid(suspend_state_t state)
 {
if (state != PM_SUSPEND_STANDBY)
return 0;
+
+   set_pm_suspend_state(state);
return 1;
 }
 
+static void pmc_suspend_end(void)
+{
+   set_pm_suspend_state(PM_SUSPEND_ON);
+}
+
 static const struct platform_suspend_ops pmc_suspend_ops = {
.valid = pmc_suspend_valid,
.enter = pmc_suspend_enter,
+   .end= pmc_suspend_end,
 };
 
 static int pmc_probe(struct platform_device *ofdev)
@@ -68,6 +77,7 @@ static int pmc_probe(struct platform_device *ofdev)
 
pmc_dev = ofdev-dev;
suspend_set_ops(pmc_suspend_ops);
+   set_pm_suspend_state(PM_SUSPEND_ON);
return 0;
 }
 
diff --git a/include/linux/fsl/fsl_pm.h b/include/linux/fsl/fsl_pm.h
new file mode 100644
index 000..705ea52
--- /dev/null
+++ b/include/linux/fsl/fsl_pm.h
@@ -0,0 +1,25 @@
+/*
+ * include/linux/fsl/fsl_pm.h
+ *
+ * Definitions for any platform related flags or structures for Freescale
+ * Power Management.
+ *
+ * Author: Wang Dongsheng dongsheng.w...@freescale.com
+ *
+ * Copyright 2014 Freescale Semiconductor, Inc
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include linux/suspend.h
+
+#ifdef CONFIG_FSL_SOC_BOOKE
+extern void set_pm_suspend_state(suspend_state_t state);
+extern suspend_state_t pm_suspend_state(void);
+#else
+static inline void set_pm_suspend_state(suspend_state_t state) { }
+static inline suspend_state_t pm_suspend_state(void) { }
+#endif
-- 
1.8.5


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[PATCH 2/2] fsl/mpic_timer: make mpic_timer to support deep sleep feature

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

At T104x platfrom the timer clock will be changed when system going to
deep sleep. Add suspend function to switch timer time before system
going to deep sleep, and recovery the time after resume from deep sleep.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com

diff --git a/arch/powerpc/sysdev/mpic_timer.c b/arch/powerpc/sysdev/mpic_timer.c
index 9d9b062..737a53d 100644
--- a/arch/powerpc/sysdev/mpic_timer.c
+++ b/arch/powerpc/sysdev/mpic_timer.c
@@ -11,6 +11,7 @@
  * option) any later version.
  */
 
+#include linux/fsl/fsl_pm.h
 #include linux/kernel.h
 #include linux/init.h
 #include linux/module.h
@@ -18,6 +19,7 @@
 #include linux/mm.h
 #include linux/interrupt.h
 #include linux/slab.h
+#include linux/suspend.h
 #include linux/of.h
 #include linux/of_address.h
 #include linux/of_device.h
@@ -26,6 +28,7 @@
 #include sysdev/fsl_soc.h
 #include asm/io.h
 
+#include asm/mpc85xx.h
 #include asm/mpic_timer.h
 
 #define FSL_GLOBAL_TIMER   0x1
@@ -71,8 +74,10 @@ struct timer_group_priv {
struct timer_regs __iomem   *regs;
struct mpic_timer   timer[TIMERS_PER_GROUP];
struct list_headnode;
+   unsigned long   idle;
unsigned inttimerfreq;
-   unsigned intidle;
+   unsigned intsuspended_timerfreq;
+   unsigned intresume_timerfreq;
unsigned intflags;
spinlock_t  lock;
void __iomem*group_tcr;
@@ -88,6 +93,7 @@ static struct cascade_priv cascade_timer[] = {
 };
 
 static LIST_HEAD(timer_group_list);
+static int switch_freq_flag;
 
 static void convert_ticks_to_time(struct timer_group_priv *priv,
const u64 ticks, struct timeval *time)
@@ -423,6 +429,33 @@ struct mpic_timer *mpic_request_timer(irq_handler_t fn, 
void *dev,
 }
 EXPORT_SYMBOL(mpic_request_timer);
 
+static void timer_group_get_suspended_freq(struct timer_group_priv *priv)
+{
+   struct device_node *np;
+
+   np = of_find_compatible_node(NULL, NULL, fsl,qoriq-clockgen-2.0);
+   if (!np) {
+   pr_err(mpic timer: Missing clockgen device node.\n);
+
+   return;
+   }
+
+   of_property_read_u32(np, clock-frequency, priv-suspended_timerfreq);
+   of_node_put(np);
+}
+
+static int need_to_switch_freq(void)
+{
+   u32 svr;
+
+   svr = mfspr(SPRN_SVR);
+   if (SVR_SOC_VER(svr) == SVR_T1040 ||
+   SVR_SOC_VER(svr) == SVR_T1042)
+   return 1;
+
+   return 0;
+}
+
 static int timer_group_get_freq(struct device_node *np,
struct timer_group_priv *priv)
 {
@@ -437,6 +470,15 @@ static int timer_group_get_freq(struct device_node *np,
priv-timerfreq);
of_node_put(dn);
}
+
+   /*
+* For deep sleep, if system going to deep sleep,
+* timer freq will be changed.
+*/
+   if (need_to_switch_freq()) {
+   timer_group_get_suspended_freq(priv);
+   switch_freq_flag = 1;
+   }
}
 
if (priv-timerfreq = 0)
@@ -445,6 +487,7 @@ static int timer_group_get_freq(struct device_node *np,
if (priv-flags  FSL_GLOBAL_TIMER) {
div = (1  (MPIC_TIMER_TCR_CLKDIV  8)) * 8;
priv-timerfreq /= div;
+   priv-suspended_timerfreq /= div;
}
 
return 0;
@@ -564,14 +607,190 @@ out:
kfree(priv);
 }
 
+static void mpic_reset_time(struct mpic_timer *handle, struct timeval 
*bcr_time,
+   struct timeval *ccr_time)
+{
+   struct timer_group_priv *priv = container_of(handle,
+   struct timer_group_priv, timer[handle-num]);
+
+   u64 ccr_ticks = 0;
+   u64 bcr_ticks = 0;
+
+   /* switch bcr time */
+   convert_time_to_ticks(priv, bcr_time, bcr_ticks);
+
+   /* switch ccr time */
+   convert_time_to_ticks(priv, ccr_time, ccr_ticks);
+
+   if (handle-cascade_handle) {
+   u32 tmp_ticks;
+   u32 rem_ticks;
+
+   /* reset ccr ticks to bcr */
+   tmp_ticks = div_u64_rem(ccr_ticks, MAX_TICKS_CASCADE,
+   rem_ticks);
+   out_be32(priv-regs[handle-num].gtbcr,
+   tmp_ticks | TIMER_STOP);
+   out_be32(priv-regs[handle-num - 1].gtbcr, rem_ticks);
+
+   /* start timer */
+   clrbits32(priv-regs[handle-num].gtbcr, TIMER_STOP);
+
+   /* reset bcr */
+   tmp_ticks = div_u64_rem(bcr_ticks, MAX_TICKS_CASCADE,
+   rem_ticks);
+   out_be32(priv-regs[handle-num].gtbcr,
+ 

[PATCH] cpuidle: add freescale e500 family porcessors idle support

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

Add cpuidle support for e500 family, using cpuidle framework to
manage various low power modes. The new implementation will remain
compatible with original idle method.

I have done test about power consumption and latency. Cpuidle framework
will make CPU response time faster than original method, but power
consumption is higher than original method.

Power consumption:
The original method, power consumption is 10.51202 (W).
The cpuidle framework, power consumption is 10.5311 (W).

Latency:
The original method, avg latency is 6782 (us).
The cpuidle framework, avg latency is 6482 (us).

Initially, this supports PW10, PW20 and subsequent patches will support
DOZE/NAP and PH10, PH20.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com

diff --git a/arch/powerpc/include/asm/machdep.h 
b/arch/powerpc/include/asm/machdep.h
index 5b6c03f..9301420 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -294,6 +294,15 @@ extern void power7_idle(void);
 extern void ppc6xx_idle(void);
 extern void book3e_idle(void);
 
+static inline void cpuidle_wait(void)
+{
+#ifdef CONFIG_PPC64
+   book3e_idle();
+#else
+   e500_idle();
+#endif
+}
+
 /*
  * ppc_md contains a copy of the machine description structure for the
  * current platform. machine_id contains the initial address where the
diff --git a/arch/powerpc/kernel/sysfs.c b/arch/powerpc/kernel/sysfs.c
index 97e1dc9..edd193f 100644
--- a/arch/powerpc/kernel/sysfs.c
+++ b/arch/powerpc/kernel/sysfs.c
@@ -190,6 +190,9 @@ static ssize_t show_pw20_wait_time(struct device *dev,
return sprintf(buf, %llu\n, time  0 ? time : 0);
 }
 
+#ifdef CONFIG_CPU_IDLE_E500
+u32 cpuidle_entry_bit;
+#endif
 static void set_pw20_wait_entry_bit(void *val)
 {
u32 *value = val;
@@ -204,7 +207,11 @@ static void set_pw20_wait_entry_bit(void *val)
/* set count */
pw20_idle |= ((MAX_BIT - *value)  PWRMGTCR0_PW20_ENT_SHIFT);
 
+#ifdef CONFIG_CPU_IDLE_E500
+   cpuidle_entry_bit = *value;
+#else
mtspr(SPRN_PWRMGTCR0, pw20_idle);
+#endif
 }
 
 static ssize_t store_pw20_wait_time(struct device *dev,
diff --git a/drivers/cpuidle/Kconfig.powerpc b/drivers/cpuidle/Kconfig.powerpc
index 66c3a09..0949dbf 100644
--- a/drivers/cpuidle/Kconfig.powerpc
+++ b/drivers/cpuidle/Kconfig.powerpc
@@ -18,3 +18,10 @@ config POWERNV_CPUIDLE
help
  Select this option to enable processor idle state management
  through cpuidle subsystem.
+
+config CPU_IDLE_E500
+   bool CPU Idle Driver for E500 family processors
+   depends on CPU_IDLE
+   depends on FSL_SOC_BOOKE
+   help
+ Select this to enable cpuidle on e500 family processors.
diff --git a/drivers/cpuidle/Makefile b/drivers/cpuidle/Makefile
index f71ae1b..7e6adea 100644
--- a/drivers/cpuidle/Makefile
+++ b/drivers/cpuidle/Makefile
@@ -18,3 +18,4 @@ obj-$(CONFIG_ARM_AT91_CPUIDLE)  += cpuidle-at91.o
 # POWERPC drivers
 obj-$(CONFIG_PSERIES_CPUIDLE)  += cpuidle-pseries.o
 obj-$(CONFIG_POWERNV_CPUIDLE)  += cpuidle-powernv.o
+obj-$(CONFIG_CPU_IDLE_E500)+= cpuidle-e500.o
diff --git a/drivers/cpuidle/cpuidle-e500.c b/drivers/cpuidle/cpuidle-e500.c
new file mode 100644
index 000..ddc0def
--- /dev/null
+++ b/drivers/cpuidle/cpuidle-e500.c
@@ -0,0 +1,194 @@
+/*
+ * CPU Idle driver for Freescale PowerPC e500 family processors.
+ *
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * Author: Dongsheng Wang dongsheng.w...@freescale.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/cpu.h
+#include linux/cpuidle.h
+#include linux/init.h
+#include linux/kernel.h
+#include linux/notifier.h
+
+#include asm/cputable.h
+#include asm/machdep.h
+#include asm/mpc85xx.h
+
+static unsigned int max_idle_state;
+static struct cpuidle_state *cpuidle_state_table;
+
+struct cpuidle_driver e500_idle_driver = {
+   .name = e500_idle,
+   .owner = THIS_MODULE,
+};
+
+static void e500_cpuidle(void)
+{
+   if (cpuidle_idle_call())
+   cpuidle_wait();
+}
+
+static int pw10_enter(struct cpuidle_device *dev,
+   struct cpuidle_driver *drv, int index)
+{
+   cpuidle_wait();
+   return index;
+}
+
+#define MAX_BIT63
+#define MIN_BIT1
+extern u32 cpuidle_entry_bit;
+static int pw20_enter(struct cpuidle_device *dev,
+   struct cpuidle_driver *drv, int index)
+{
+   u32 pw20_idle;
+   u32 entry_bit;
+   pw20_idle = mfspr(SPRN_PWRMGTCR0);
+   if ((pw20_idle  PWRMGTCR0_PW20_ENT) != PWRMGTCR0_PW20_ENT) {
+   pw20_idle = ~PWRMGTCR0_PW20_ENT;
+   entry_bit = MAX_BIT - cpuidle_entry_bit;
+   pw20_idle |= (entry_bit  PWRMGTCR0_PW20_ENT_SHIFT);
+   mtspr(SPRN_PWRMGTCR0

[PATCH] powerpc/irq: Remove HAVE_IRQ_EXIT_ON_IRQ_STACK feature at powerpc platform

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

If softirq use hardirq stack, we will get kernel painc when a hard irq coming 
again
during __do_softirq enable local irq to deal with softirq action. So we need to 
switch
satck into softirq stack when invoke soft irq.

 Task---
| Task stack
|
Interrput-EXCEPTION-do_IRQ-
^| Hard irq stack
||
|irq_exit-__do_softirq-local_irq_enable-- 
  --local_irq_disable
|   
| Hard irq stack
|   
|
|   
Interrupt coming again
|   There will get a Interrupt nesting  
|


Trace 1: Trap 900

Kernel stack overflow in process e8152f40, r1=e8e05ec0
CPU: 0 PID: 2399 Comm: image_compress/ Not tainted 3.13.0-rc3-03475-g2e3f85b 
#432
task: e8152f40 ti: c080a000 task.ti: ef176000
NIP: c05bec04 LR: c0305590 CTR: 0010
REGS: e8e05e10 TRAP: 0901   Not tainted  (3.13.0-rc3-03475-g2e3f85b)
MSR: 00029000 CE,EE,ME  CR: 22f22722  XER: 2000

GPR00: c0305590 e8e05ec0 e8152f40 c07e1e2c 00029000 00ec fffc 0010
GPR08: 007f   b02539f3 a00ae278
NIP [c05bec04] _raw_spin_unlock_irqrestore+0x10/0x14
LR [c0305590] add_timer_randomness+0x60/0xfc
Call Trace:
[e8e05ec0] [c0305590] add_timer_randomness+0x60/0xfc (unreliable)
[e8e05ee0] [c026c9a8] blk_update_bidi_request+0x64/0x94
[e8e05f00] [c026cd00] blk_end_bidi_request+0x20/0x7c
[e8e05f20] [c032f21c] scsi_io_completion+0xe0/0x5e8
[e8e05f70] [c0272b84] blk_done_softirq+0x98/0xb8
[e8e05f90] [c004893c] __do_softirq+0xf8/0x1f8
[e8e05fe0] [c0048dbc] irq_exit+0xa4/0xc8
[e8e05ff0] [c000d5f4] call_do_irq+0x24/0x3c
[ef177d50] [c00046ec] do_IRQ+0x8c/0xf8
[ef177d70] [c000f6dc] ret_from_except+0x0/0x18
--- Exception: 501 at lzo1x_1_do_compress+0x248/0x40c
LR = lzo1x_1_compress+0x98/0x268
[ef177e30] [c07c7440] runqueues+0x0/0x540 (unreliable)
[ef177e60] []   (null)
[ef177ea0] [c0085a9c] lzo_compress_threadfn+0x6c/0x138
[ef177ef0] [c0062a00] kthread+0xc4/0xd8
[ef177f40] [c000f158] ret_from_kernel_thread+0x5c/0x64
Instruction dump:
40a2fff0 4c00012c 2f89 419e000c 3860 4e800020 3861 4e800020
7c0004ac 3920 9123 7c800106 4e800020 7d201828 35290001 40810010
Kernel panic - not syncing: kernel stack overflow
CPU: 0 PID: 2399 Comm: image_compress/ Not tainted 3.13.0-rc3-03475-g2e3f85b 
#432
Call Trace:
Rebooting in 180 seconds..

Trace 2: Trap 500

VFS: Mounted root (ext2 filesystem) on device 1:0.
devtmpfs: mounted
Freeing unused kernel memory: 268K (c079a000 - c07dd000)
INIT: version 2.88 booting
Starting udev
udevd[1423]: starting version 182
random: nonblocking pool is initialized
Kernel stack overflow in process e829ca80, r1=e8badf90
CPU: 0 PID: 1553 Comm: mount.sh Not tainted 3.13.0-rc1-148228-gea7ca7c #21
task: e829ca80 ti: c081c000 task.ti: e9d28000
NIP: c00434bc LR: c0043444 CTR: c0018cec
REGS: e8badee0 TRAP: 0501   Not tainted  (3.13.0-rc1-148228-gea7ca7c)
MSR: 00029000 CE,EE,ME  CR: 48222422  XER: 2000

GPR00: c00439a0 e8badf90 e829ca80 0001 e80cc780 0001 b92f44af 
GPR08: 0001 010ba000 010ba000 ddd3e6d1 48222422
NIP [c00434bc] __do_softirq+0x94/0x1f8
LR [c0043444] __do_softirq+0x1c/0x1f8
Call Trace:
[e8badf90] [100f] 0x100f (unreliable)
[e8badfe0] [c00439a0] irq_exit+0xa4/0xc8
[e8badff0] [c000ccd8] call_do_irq+0x24/0x3c
[e9d29f20] [c000479c] do_IRQ+0x8c/0xf8
[e9d29f40] [c000eb54] ret_from_except+0x0/0x18
--- Exception: 501 at 0x1003d540
LR = 0x10041974
Instruction dump:
3e80c082 3f40c07e 3b6a 3a941040 3aa0 3b5a9388 7f16c378 812f0008
5529103a 7d3c482e 7eb8492e 7c008146 3ba0 7e9ea378 4814 57fff87f
Kernel panic - not syncing: kernel stack overflow
CPU: 0 PID: 1553 Comm: mount.sh Not tainted 3.13.0-rc1-148228-gea7ca7c #21
Call Trace:
Rebooting in 180 seconds..

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
Cc: Frederic Weisbecker fweis...@gmail.com
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: Linus Torvalds torva...@linux-foundation.org
Cc: Thomas Gleixner t...@linutronix.de
Cc: Ingo Molnar mi...@kernel.org
Cc: Peter Zijlstra pet...@infradead.org
Cc: H. Peter Anvin h...@zytor.com
Cc: Paul Mackerras pau...@au1.ibm.com
Cc: James Hogan james.ho...@imgtec.com
Cc: James E.J. Bottomley j...@parisc-linux.org
Cc: Helge Deller del...@gmx.de
Cc: Martin Schwidefsky schwidef...@de.ibm.com
Cc: Heiko Carstens heiko.carst...@de.ibm.com
Cc: David S. Miller da...@davemloft.net
Cc: Andrew Morton a...@linux-foundation.org

diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 957bf34..ffde3fb 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ 

[PATCH] video/fsl: Fix the sleep function for FSL DIU module

[Dongsheng Wang]

From: Jason Jin jason@freescale.com

For deep sleep, the diu module will power off, when wake up
from the deep sleep, the registers need to be reinitialized.

Signed-off-by: Jason Jin jason@freescale.com
Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com

diff --git a/drivers/video/fsl-diu-fb.c b/drivers/video/fsl-diu-fb.c
index e8758b9..7ec780c 100644
--- a/drivers/video/fsl-diu-fb.c
+++ b/drivers/video/fsl-diu-fb.c
@@ -1628,9 +1628,18 @@ static int fsl_diu_suspend(struct platform_device 
*ofdev, pm_message_t state)
 static int fsl_diu_resume(struct platform_device *ofdev)
 {
struct fsl_diu_data *data;
+   struct mfb_info *mfbi;
+   int i;
 
data = dev_get_drvdata(ofdev-dev);
-   enable_lcdc(data-fsl_diu_info);
+   fsl_diu_enable_interrupts(data);
+   update_lcdc(data-fsl_diu_info);
+
+   for (i = 0; i  NUM_AOIS; i++) {
+   mfbi = data-mfb[i];
+   if (mfbi-count)
+   fsl_diu_enable_panel(data-fsl_diu_info[i]);
+   }
 
return 0;
 }
-- 
1.8.5


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[PATCH v2] fsl/pci: The new pci suspend/resume implementation

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

If we do nothing in suspend/resume, some platform PCIe ip-block
can't guarantee the link back to L0 state from sleep, then, when
we read the EP device will hang. Only we send pme turnoff message
in pci controller suspend, and send pme exit message in resume, the
link state will be normal.

When we send pme turnoff message in pci controller suspend, the
links will into l2/l3 ready, then, host cannot communicate with
ep device, but pci-driver will call back EP device to save them
state. So we need to change platform_driver-suspend/resume to
syscore-suspend/resume.

So the new suspend/resume implementation, send pme turnoff message
in suspend, and send pme exit message in resume. And add a PME handler,
to response PME  message interrupt.

Change platform_driver-suspend/resume to syscore-suspend/resume.
pci-driver will call back EP device, to save EP state in
pci_pm_suspend_noirq, so we need to keep the link, until
pci_pm_suspend_noirq finish.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
*V2*
- Abandon patch 1/2. And send this as a independent patch.
  The original patch links:
  patch 1/2, http://patchwork.ozlabs.org/patch/307553/ (Abandon)
  patch 2/2, http://patchwork.ozlabs.org/patch/307554/
- Change pr_warn to dev_err().
- Fix code style that to deal with if statement.

diff --git a/arch/powerpc/platforms/85xx/c293pcie.c 
b/arch/powerpc/platforms/85xx/c293pcie.c
index 213d5b8..84476b6 100644
--- a/arch/powerpc/platforms/85xx/c293pcie.c
+++ b/arch/powerpc/platforms/85xx/c293pcie.c
@@ -68,6 +68,7 @@ define_machine(c293_pcie) {
.init_IRQ   = c293_pcie_pic_init,
 #ifdef CONFIG_PCI
.pcibios_fixup_bus  = fsl_pcibios_fixup_bus,
+   .pcibios_fixup_phb  = fsl_pcibios_fixup_phb,
 #endif
.get_irq= mpic_get_irq,
.restart= fsl_rstcr_restart,
diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c 
b/arch/powerpc/platforms/85xx/corenet_generic.c
index fbd871e..aa8b9a3 100644
--- a/arch/powerpc/platforms/85xx/corenet_generic.c
+++ b/arch/powerpc/platforms/85xx/corenet_generic.c
@@ -163,6 +163,7 @@ define_machine(corenet_generic) {
.init_IRQ   = corenet_gen_pic_init,
 #ifdef CONFIG_PCI
.pcibios_fixup_bus  = fsl_pcibios_fixup_bus,
+   .pcibios_fixup_phb  = fsl_pcibios_fixup_phb,
 #endif
.get_irq= mpic_get_coreint_irq,
.restart= fsl_rstcr_restart,
diff --git a/arch/powerpc/platforms/85xx/ge_imp3a.c 
b/arch/powerpc/platforms/85xx/ge_imp3a.c
index e6285ae..11790e0 100644
--- a/arch/powerpc/platforms/85xx/ge_imp3a.c
+++ b/arch/powerpc/platforms/85xx/ge_imp3a.c
@@ -215,6 +215,7 @@ define_machine(ge_imp3a) {
.show_cpuinfo   = ge_imp3a_show_cpuinfo,
 #ifdef CONFIG_PCI
.pcibios_fixup_bus  = fsl_pcibios_fixup_bus,
+   .pcibios_fixup_phb  = fsl_pcibios_fixup_phb,
 #endif
.get_irq= mpic_get_irq,
.restart= fsl_rstcr_restart,
diff --git a/arch/powerpc/platforms/85xx/mpc8536_ds.c 
b/arch/powerpc/platforms/85xx/mpc8536_ds.c
index 15ce4b5..a378ba3 100644
--- a/arch/powerpc/platforms/85xx/mpc8536_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc8536_ds.c
@@ -76,6 +76,7 @@ define_machine(mpc8536_ds) {
.init_IRQ   = mpc8536_ds_pic_init,
 #ifdef CONFIG_PCI
.pcibios_fixup_bus  = fsl_pcibios_fixup_bus,
+   .pcibios_fixup_phb  = fsl_pcibios_fixup_phb,
 #endif
.get_irq= mpic_get_irq,
.restart= fsl_rstcr_restart,
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c 
b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
index 7a31a0e..b0753e2 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
@@ -385,6 +385,7 @@ define_machine(mpc85xx_cds) {
 #ifdef CONFIG_PCI
.restart= mpc85xx_cds_restart,
.pcibios_fixup_bus  = mpc85xx_cds_fixup_bus,
+   .pcibios_fixup_phb  = fsl_pcibios_fixup_phb,
 #else
.restart= fsl_rstcr_restart,
 #endif
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ds.c 
b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
index 9ebb91e..ffdf021 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
@@ -209,6 +209,7 @@ define_machine(mpc8544_ds) {
.init_IRQ   = mpc85xx_ds_pic_init,
 #ifdef CONFIG_PCI
.pcibios_fixup_bus  = fsl_pcibios_fixup_bus,
+   .pcibios_fixup_phb  = fsl_pcibios_fixup_phb,
 #endif
.get_irq= mpic_get_irq,
.restart= fsl_rstcr_restart,
@@ -223,6 +224,7 @@ define_machine(mpc8572_ds) {
.init_IRQ   = mpc85xx_ds_pic_init,
 #ifdef CONFIG_PCI
.pcibios_fixup_bus  = fsl_pcibios_fixup_bus,
+   .pcibios_fixup_phb  = fsl_pcibios_fixup_phb,
 #endif
.get_irq

[PATCH] rtc/ds3232: Enable ds3232 to work as wakeup source

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

Add suspend/resume and device_init_wakeup to enable ds3232 as
wakeup source, /sys/class/rtc/rtcX/wakealarm for set wakeup alarm.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com

diff --git a/drivers/rtc/rtc-ds3232.c b/drivers/rtc/rtc-ds3232.c
index b83bb5a5..a3c40d5 100644
--- a/drivers/rtc/rtc-ds3232.c
+++ b/drivers/rtc/rtc-ds3232.c
@@ -57,6 +57,7 @@ struct ds3232 {
 * in the remove function.
 */
struct mutex mutex;
+   bool suspended;
int exiting;
 };
 
@@ -345,7 +346,15 @@ static irqreturn_t ds3232_irq(int irq, void *dev_id)
struct ds3232 *ds3232 = i2c_get_clientdata(client);
 
disable_irq_nosync(irq);
-   schedule_work(ds3232-work);
+
+   /*
+* If rtc as a wakeup source, can't schedule the work
+* at system resume flow, because at this time the i2c bus
+* has not been resumed.
+*/
+   if (!ds3232-suspended)
+   schedule_work(ds3232-work);
+
return IRQ_HANDLED;
 }
 
@@ -363,22 +372,26 @@ static void ds3232_work(struct work_struct *work)
 
if (stat  DS3232_REG_SR_A1F) {
control = i2c_smbus_read_byte_data(client, DS3232_REG_CR);
-   if (control  0)
-   goto out;
-   /* disable alarm1 interrupt */
-   control = ~(DS3232_REG_CR_A1IE);
-   i2c_smbus_write_byte_data(client, DS3232_REG_CR, control);
-
-   /* clear the alarm pend flag */
-   stat = ~DS3232_REG_SR_A1F;
-   i2c_smbus_write_byte_data(client, DS3232_REG_SR, stat);
-
-   rtc_update_irq(ds3232-rtc, 1, RTC_AF | RTC_IRQF);
+   if (control  0) {
+   pr_warn(Read DS3232 Control Register error.
+   Disable IRQ%d.\n, client-irq);
+   } else {
+   /* disable alarm1 interrupt */
+   control = ~(DS3232_REG_CR_A1IE);
+   i2c_smbus_write_byte_data(client, DS3232_REG_CR,
+   control);
+
+   /* clear the alarm pend flag */
+   stat = ~DS3232_REG_SR_A1F;
+   i2c_smbus_write_byte_data(client, DS3232_REG_SR, stat);
+
+   rtc_update_irq(ds3232-rtc, 1, RTC_AF | RTC_IRQF);
+
+   if (!ds3232-exiting)
+   enable_irq(client-irq);
+   }
}
 
-out:
-   if (!ds3232-exiting)
-   enable_irq(client-irq);
 unlock:
mutex_unlock(ds3232-mutex);
 }
@@ -411,23 +424,21 @@ static int ds3232_probe(struct i2c_client *client,
if (ret)
return ret;
 
-   ds3232-rtc = devm_rtc_device_register(client-dev, client-name,
- ds3232_rtc_ops, THIS_MODULE);
-   if (IS_ERR(ds3232-rtc)) {
-   dev_err(client-dev, unable to register the class device\n);
-   return PTR_ERR(ds3232-rtc);
-   }
-
-   if (client-irq = 0) {
+   if (client-irq != NO_IRQ) {
ret = devm_request_irq(client-dev, client-irq, ds3232_irq, 0,
 ds3232, client);
if (ret) {
dev_err(client-dev, unable to request IRQ\n);
return ret;
}
+
+   device_init_wakeup(client-dev, 1);
+
}
 
-   return 0;
+   ds3232-rtc = devm_rtc_device_register(client-dev, client-name,
+ ds3232_rtc_ops, THIS_MODULE);
+   return PTR_ERR_OR_ZERO(ds3232-rtc);
 }
 
 static int ds3232_remove(struct i2c_client *client)
@@ -446,6 +457,42 @@ static int ds3232_remove(struct i2c_client *client)
return 0;
 }
 
+#ifdef CONFIG_PM_SLEEP
+static int ds3232_suspend(struct device *dev)
+{
+   struct ds3232 *ds3232 = dev_get_drvdata(dev);
+   struct i2c_client *client = to_i2c_client(dev);
+
+   if (device_can_wakeup(dev)) {
+   ds3232-suspended = true;
+   irq_set_irq_wake(client-irq, 1);
+   }
+
+   return 0;
+}
+
+static int ds3232_resume(struct device *dev)
+{
+   struct ds3232 *ds3232 = dev_get_drvdata(dev);
+   struct i2c_client *client = to_i2c_client(dev);
+
+   if (ds3232-suspended) {
+   ds3232-suspended = false;
+
+   /* Clear the hardware alarm pend flag */
+   schedule_work(ds3232-work);
+
+   irq_set_irq_wake(client-irq, 0);
+   }
+
+   return 0;
+}
+#endif
+
+static const struct dev_pm_ops ds3232_pm_ops = {
+   SET_SYSTEM_SLEEP_PM_OPS(ds3232_suspend, ds3232_resume)
+};
+
 static const struct i2c_device_id ds3232_id[] = {
{ ds3232, 0 },
{ }
@@ -456,6 +503,7 @@ static struct i2c_driver ds3232_driver = {
.driver = {
.name = rtc-ds3232,

[PATCH 1/3] powerpc/fsl: add E500MC and E5500 PVR define

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

E500MC and E5500 PVR will be used in subsequent save/restore core
state patches.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 62b114e..cd7b630 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -1075,6 +1075,8 @@
 #define PVR_8560   0x8020
 #define PVR_VER_E500V1 0x8020
 #define PVR_VER_E500V2 0x8021
+#define PVR_VER_E500MC 0x8023
+#define PVR_VER_E5500  0x8024
 #define PVR_VER_E6500  0x8040
 
 /*
-- 
1.8.5


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[PATCH 3/3] powerpc/fsl: Use the new interface to save or restore registers

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

Use fsl_cpu_state_save/fsl_cpu_state_restore to save/restore registers.
Use the functions to save/restore registers, so we don't need to
maintain the code.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com

diff --git a/arch/powerpc/kernel/swsusp_booke.S 
b/arch/powerpc/kernel/swsusp_booke.S
index 553c140..b5992db 100644
--- a/arch/powerpc/kernel/swsusp_booke.S
+++ b/arch/powerpc/kernel/swsusp_booke.S
@@ -4,92 +4,28 @@
  * Copyright (c) 2009-2010 MontaVista Software, LLC.
  */
 
-#include linux/threads.h
-#include asm/processor.h
 #include asm/page.h
-#include asm/cputable.h
-#include asm/thread_info.h
 #include asm/ppc_asm.h
 #include asm/asm-offsets.h
 #include asm/mmu.h
-
-/*
- * Structure for storing CPU registers on the save area.
- */
-#define SL_SP  0
-#define SL_PC  4
-#define SL_MSR 8
-#define SL_TCR 0xc
-#define SL_SPRG0   0x10
-#define SL_SPRG1   0x14
-#define SL_SPRG2   0x18
-#define SL_SPRG3   0x1c
-#define SL_SPRG4   0x20
-#define SL_SPRG5   0x24
-#define SL_SPRG6   0x28
-#define SL_SPRG7   0x2c
-#define SL_TBU 0x30
-#define SL_TBL 0x34
-#define SL_R2  0x38
-#define SL_CR  0x3c
-#define SL_LR  0x40
-#define SL_R12 0x44/* r12 to r31 */
-#define SL_SIZE(SL_R12 + 80)
-
-   .section .data
-   .align  5
-
-_GLOBAL(swsusp_save_area)
-   .space  SL_SIZE
-
+#include asm/fsl_sleep.h
 
.section .text
.align  5
 
 _GLOBAL(swsusp_arch_suspend)
-   lis r11,swsusp_save_area@h
-   ori r11,r11,swsusp_save_area@l
-
-   mflrr0
-   stw r0,SL_LR(r11)
-   mfcrr0
-   stw r0,SL_CR(r11)
-   stw r1,SL_SP(r11)
-   stw r2,SL_R2(r11)
-   stmwr12,SL_R12(r11)
-
-   /* Save MSR  TCR */
-   mfmsr   r4
-   stw r4,SL_MSR(r11)
-   mfspr   r4,SPRN_TCR
-   stw r4,SL_TCR(r11)
-
-   /* Get a stable timebase and save it */
-1: mfspr   r4,SPRN_TBRU
-   stw r4,SL_TBU(r11)
-   mfspr   r5,SPRN_TBRL
-   stw r5,SL_TBL(r11)
-   mfspr   r3,SPRN_TBRU
-   cmpwr3,r4
-   bne 1b
+   mflrr15
+   lis r3, core_registers_save_area@h
+   ori r3, r3, core_registers_save_area@l
+
+   /* Save base register */
+   li  r4, 0
+   bl  fsl_cpu_state_save
 
-   /* Save SPRGs */
-   mfspr   r4,SPRN_SPRG0
-   stw r4,SL_SPRG0(r11)
-   mfspr   r4,SPRN_SPRG1
-   stw r4,SL_SPRG1(r11)
-   mfspr   r4,SPRN_SPRG2
-   stw r4,SL_SPRG2(r11)
-   mfspr   r4,SPRN_SPRG3
-   stw r4,SL_SPRG3(r11)
-   mfspr   r4,SPRN_SPRG4
-   stw r4,SL_SPRG4(r11)
-   mfspr   r4,SPRN_SPRG5
-   stw r4,SL_SPRG5(r11)
-   mfspr   r4,SPRN_SPRG6
-   stw r4,SL_SPRG6(r11)
-   mfspr   r4,SPRN_SPRG7
-   stw r4,SL_SPRG7(r11)
+   /* Save LR */
+   lis r3, core_registers_save_area@h
+   ori r3, r3, core_registers_save_area@l
+   stw r15, SR_LR(r3)
 
/* Call the low level suspend stuff (we should probably have made
 * a stackframe...
@@ -97,11 +33,12 @@ _GLOBAL(swsusp_arch_suspend)
bl  swsusp_save
 
/* Restore LR from the save area */
-   lis r11,swsusp_save_area@h
-   ori r11,r11,swsusp_save_area@l
-   lwz r0,SL_LR(r11)
-   mtlrr0
+   lis r3, core_registers_save_area@h
+   ori r3, r3, core_registers_save_area@l
+   lwz r15, SR_LR(r3)
+   mtlrr15
 
+   li  r3, 0
blr
 
 _GLOBAL(swsusp_arch_resume)
@@ -138,9 +75,6 @@ _GLOBAL(swsusp_arch_resume)
bl flush_dcache_L1
bl flush_instruction_cache
 
-   lis r11,swsusp_save_area@h
-   ori r11,r11,swsusp_save_area@l
-
/*
 * Mappings from virtual addresses to physical addresses may be
 * different than they were prior to restoring hibernation state. 
@@ -149,53 +83,12 @@ _GLOBAL(swsusp_arch_resume)
 */
bl  _tlbil_all
 
-   lwz r4,SL_SPRG0(r11)
-   mtspr   SPRN_SPRG0,r4
-   lwz r4,SL_SPRG1(r11)
-   mtspr   SPRN_SPRG1,r4
-   lwz r4,SL_SPRG2(r11)
-   mtspr   SPRN_SPRG2,r4
-   lwz r4,SL_SPRG3(r11)
-   mtspr   SPRN_SPRG3,r4
-   lwz r4,SL_SPRG4(r11)
-   mtspr   SPRN_SPRG4,r4
-   lwz r4,SL_SPRG5(r11)
-   mtspr   SPRN_SPRG5,r4
-   lwz r4,SL_SPRG6(r11)
-   mtspr   SPRN_SPRG6,r4
-   lwz r4,SL_SPRG7(r11)
-   mtspr   SPRN_SPRG7,r4
-
-   /* restore the MSR */
-   lwz r3,SL_MSR(r11)
-   mtmsr   r3
-
-   /* Restore TB */
-   li  r3,0
-   mtspr   SPRN_TBWL,r3
-   lwz r3,SL_TBU(r11)
-   lwz r4,SL_TBL(r11)
-   mtspr   SPRN_TBWU,r3
-   mtspr   SPRN_TBWL,r4
-
-   /* Restore TCR and clear any pending bits in TSR. */
-  

[PATCH 2/3] powerpc/85xx: Provide two functions to save/restore the core registers

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

Add fsl_cpu_state_save/fsl_cpu_state_restore functions, used for deep
sleep and hibernation to save/restore core registers. We abstract out
save/restore code for use in various modules, to make them don't need
to maintain.

Currently supported processors type are E6500, E5500, E500MC, E500v2 and
E500v1.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com

diff --git a/arch/powerpc/include/asm/fsl_sleep.h 
b/arch/powerpc/include/asm/fsl_sleep.h
new file mode 100644
index 000..31c8a9b
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_sleep.h
@@ -0,0 +1,98 @@
+/*
+ * Freescale 85xx Power management set
+ *
+ * Author: Wang Dongsheng dongsheng.w...@freescale.com
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_FSL_SLEEP_H
+#define __ASM_FSL_SLEEP_H
+
+/*
+ * Freescale 85xx Core registers set, core register map definition
+ * Address base on r3, we need to compatible with both 32-bit and 64-bit, so
+ * the data width is 64-bit(double word).
+ *
+ * Acronyms:
+ * dw(data width)  0x08
+ *
+ * Map:
+ * General-Purpose Registers
+ * GPR1(sp)0
+ * GPR20x8 (dw * 1)
+ * GPR13 - GPR31   0x10 ~ 0xa0 (dw * 2 ~ dw * 20)
+ * Foating-point registers
+ * FPR14 - FPR31   0xa8 ~ 0x130(dw * 21 ~ dw * 38)
+ * Registers for Branch Operations
+ * CR  0x138   (dw * 39)
+ * LR  0x140   (dw * 40)
+ * Processor Control Registers
+ * MSR 0x148   (dw * 41)
+ * EPCR0x150   (dw * 42)
+ *
+ * Only e500, e500v2 need to save HID0 - HID1
+ * HID0 - HID1 0x158 ~ 0x160 (dw * 43 ~ dw * 44)
+ * Timer Registers
+ * TCR 0x168   (dw * 45)
+ * TB(64bit)   0x170   (dw * 46)
+ * TBU(32bit)  0x178   (dw * 47)
+ * TBL(32bit)  0x180   (dw * 48)
+ * Interrupt Registers
+ * IVPR0x188   (dw * 49)
+ * IVOR0 - IVOR15  0x190 ~ 0x208   (dw * 50 ~ dw * 65)
+ * IVOR32 - IVOR41 0x210 ~ 0x258   (dw * 66 ~ dw * 75)
+ * Software-Use Registers
+ * SPRG1   0x260   (dw * 76), 64-bit need to save.
+ * SPRG3   0x268   (dw * 77), 32-bit need to save.
+ * MMU Registers
+ * PID0 - PID2 0x270 ~ 0x280   (dw * 78 ~ dw * 80)
+ * Debug Registers
+ * DBCR0 - DBCR2   0x288 ~ 0x298   (dw * 81 ~ dw * 83)
+ * IAC1 - IAC4 0x2a0 ~ 0x2b8   (dw * 84 ~ dw * 87)
+ * DAC1 - DAC2 0x2c0 ~ 0x2c8   (dw * 88 ~ dw * 89)
+ *
+ */
+
+#define SR_GPR10x000
+#define SR_GPR20x008
+#define SR_GPR13   0x010
+#define SR_FPR14   0x0a8
+#define SR_CR  0x138
+#define SR_LR  0x140
+#define SR_MSR 0x148
+#define SR_EPCR0x150
+#define SR_HID00x158
+#define SR_TCR 0x168
+#define SR_TB  0x170
+#define SR_TBU 0x178
+#define SR_TBL 0x180
+#define SR_IVPR0x188
+#define SR_IVOR0   0x190
+#define SR_IVOR32  0x210
+#define SR_SPRG1   0x260
+#define SR_SPRG3   0x268
+#define SR_PID00x270
+#define SR_DBCR0   0x288
+#define SR_IAC10x2a0
+#define SR_DAC10x2c0
+#define FSL_CPU_SR_SIZE(SR_DAC1 + 0x10)
+
+#ifndef __ASSEMBLY__
+
+enum core_save_type {
+   BASE_SAVE = 0,
+   ALL_SAVE = 1,
+};
+
+extern int fsl_cpu_state_save(void *save_page, enum core_save_type type);
+extern int fsl_cpu_state_restore(void *restore_page, enum core_save_type type);
+
+#endif
+
+#endif
+
diff --git a/arch/powerpc/platforms/85xx/Makefile 
b/arch/powerpc/platforms/85xx/Makefile
index 25cebe7..650a01c 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -4,6 +4,7 @@
 obj-$(CONFIG_SMP) += smp.o
 
 obj-y += common.o
+obj-y += save-core.o
 
 obj-$(CONFIG_BSC9131_RDB) += bsc913x_rdb.o
 obj-$(CONFIG_C293_PCIE)   += c293pcie.o
diff --git a/arch/powerpc/platforms/85xx/save-core.S 
b/arch/powerpc/platforms/85xx/save-core.S
new file mode 100644
index 000..a6b93b8
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/save-core.S
@@ -0,0 +1,497 @@
+/*
+ * Freescale Power Management, Save/Restore core state
+ *
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ * Author: Wang Dongsheng dongsheng.w...@freescale.com
+ *
+ * This program 

[PATCH 1/2] pci: Fix root port bus-self is NULL

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

the root port bus-self always NULL, so put root port pci device
into root port bus-self.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com

diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 38e403d..7f2d1ab 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -1472,6 +1472,9 @@ int pci_scan_slot(struct pci_bus *bus, int devfn)
if (!dev-is_added)
nr++;
 
+   if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
+   bus-self = dev;
+
for (fn = next_fn(bus, dev, 0); fn  0; fn = next_fn(bus, dev, fn)) {
dev = pci_scan_single_device(bus, devfn + fn);
if (dev) {
-- 
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[PATCH 2/2] fsl/pci: The new pci suspend/resume implementation

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

The new suspend/resume implementation, send pme turnoff message
in suspend, and send pme exit message in resume.

Add a PME handler, to response PME  message interrupt.

Change platform_driver-suspend/resume to syscore-suspend/resume.
pci-driver will call back EP device, to save EP state in
pci_pm_suspend_noirq, so we need to keep the link, until
pci_pm_suspend_noirq finish.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com

diff --git a/arch/powerpc/platforms/85xx/c293pcie.c 
b/arch/powerpc/platforms/85xx/c293pcie.c
index 213d5b8..84476b6 100644
--- a/arch/powerpc/platforms/85xx/c293pcie.c
+++ b/arch/powerpc/platforms/85xx/c293pcie.c
@@ -68,6 +68,7 @@ define_machine(c293_pcie) {
.init_IRQ   = c293_pcie_pic_init,
 #ifdef CONFIG_PCI
.pcibios_fixup_bus  = fsl_pcibios_fixup_bus,
+   .pcibios_fixup_phb  = fsl_pcibios_fixup_phb,
 #endif
.get_irq= mpic_get_irq,
.restart= fsl_rstcr_restart,
diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c 
b/arch/powerpc/platforms/85xx/corenet_generic.c
index fbd871e..aa8b9a3 100644
--- a/arch/powerpc/platforms/85xx/corenet_generic.c
+++ b/arch/powerpc/platforms/85xx/corenet_generic.c
@@ -163,6 +163,7 @@ define_machine(corenet_generic) {
.init_IRQ   = corenet_gen_pic_init,
 #ifdef CONFIG_PCI
.pcibios_fixup_bus  = fsl_pcibios_fixup_bus,
+   .pcibios_fixup_phb  = fsl_pcibios_fixup_phb,
 #endif
.get_irq= mpic_get_coreint_irq,
.restart= fsl_rstcr_restart,
diff --git a/arch/powerpc/platforms/85xx/ge_imp3a.c 
b/arch/powerpc/platforms/85xx/ge_imp3a.c
index e6285ae..11790e0 100644
--- a/arch/powerpc/platforms/85xx/ge_imp3a.c
+++ b/arch/powerpc/platforms/85xx/ge_imp3a.c
@@ -215,6 +215,7 @@ define_machine(ge_imp3a) {
.show_cpuinfo   = ge_imp3a_show_cpuinfo,
 #ifdef CONFIG_PCI
.pcibios_fixup_bus  = fsl_pcibios_fixup_bus,
+   .pcibios_fixup_phb  = fsl_pcibios_fixup_phb,
 #endif
.get_irq= mpic_get_irq,
.restart= fsl_rstcr_restart,
diff --git a/arch/powerpc/platforms/85xx/mpc8536_ds.c 
b/arch/powerpc/platforms/85xx/mpc8536_ds.c
index 15ce4b5..a378ba3 100644
--- a/arch/powerpc/platforms/85xx/mpc8536_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc8536_ds.c
@@ -76,6 +76,7 @@ define_machine(mpc8536_ds) {
.init_IRQ   = mpc8536_ds_pic_init,
 #ifdef CONFIG_PCI
.pcibios_fixup_bus  = fsl_pcibios_fixup_bus,
+   .pcibios_fixup_phb  = fsl_pcibios_fixup_phb,
 #endif
.get_irq= mpic_get_irq,
.restart= fsl_rstcr_restart,
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c 
b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
index 7a31a0e..b0753e2 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
@@ -385,6 +385,7 @@ define_machine(mpc85xx_cds) {
 #ifdef CONFIG_PCI
.restart= mpc85xx_cds_restart,
.pcibios_fixup_bus  = mpc85xx_cds_fixup_bus,
+   .pcibios_fixup_phb  = fsl_pcibios_fixup_phb,
 #else
.restart= fsl_rstcr_restart,
 #endif
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ds.c 
b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
index 9ebb91e..ffdf021 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
@@ -209,6 +209,7 @@ define_machine(mpc8544_ds) {
.init_IRQ   = mpc85xx_ds_pic_init,
 #ifdef CONFIG_PCI
.pcibios_fixup_bus  = fsl_pcibios_fixup_bus,
+   .pcibios_fixup_phb  = fsl_pcibios_fixup_phb,
 #endif
.get_irq= mpic_get_irq,
.restart= fsl_rstcr_restart,
@@ -223,6 +224,7 @@ define_machine(mpc8572_ds) {
.init_IRQ   = mpc85xx_ds_pic_init,
 #ifdef CONFIG_PCI
.pcibios_fixup_bus  = fsl_pcibios_fixup_bus,
+   .pcibios_fixup_phb  = fsl_pcibios_fixup_phb,
 #endif
.get_irq= mpic_get_irq,
.restart= fsl_rstcr_restart,
@@ -237,6 +239,7 @@ define_machine(p2020_ds) {
.init_IRQ   = mpc85xx_ds_pic_init,
 #ifdef CONFIG_PCI
.pcibios_fixup_bus  = fsl_pcibios_fixup_bus,
+   .pcibios_fixup_phb  = fsl_pcibios_fixup_phb,
 #endif
.get_irq= mpic_get_irq,
.restart= fsl_rstcr_restart,
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c 
b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index a7b3621..6cd3b8a 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -416,6 +416,7 @@ define_machine(mpc8568_mds) {
.progress   = udbg_progress,
 #ifdef CONFIG_PCI
.pcibios_fixup_bus  = fsl_pcibios_fixup_bus,
+   .pcibios_fixup_phb  = fsl_pcibios_fixup_phb,
 

[PATCH] powerpc/mpic: supply a .disable callback

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

Currently MPIC provides .mask, but not .disable.  This means that
effectively disable_irq() soft-disables the interrupt, and you get
a .mask call if an interrupt actually occurs.

I'm not sure if this was intended as a performance benefit (it seems common
to omit .disable on powerpc interrupt controllers, but nowhere else), but it
interacts badly with threaded/workqueue interrupts (including KVM
reflection).  In such cases, where the real interrupt handler does a
disable_irq_nosync(), schedules defered handling, and returns, we get two
interrupts for every real interrupt.  The second interrupt does nothing
but see that IRQ_DISABLED is set, and decide that it would be a good
idea to actually call .mask.

Signed-off-by: Scott Wood scottw...@freescale.com
Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com

diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 0e166ed..dd7564b 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -975,6 +975,7 @@ void mpic_set_destination(unsigned int virq, unsigned int 
cpuid)
 }
 
 static struct irq_chip mpic_irq_chip = {
+   .irq_disable= mpic_mask_irq,
.irq_mask   = mpic_mask_irq,
.irq_unmask = mpic_unmask_irq,
.irq_eoi= mpic_end_irq,
@@ -984,6 +985,7 @@ static struct irq_chip mpic_irq_chip = {
 
 #ifdef CONFIG_SMP
 static struct irq_chip mpic_ipi_chip = {
+   .irq_disable= mpic_mask_ipi,
.irq_mask   = mpic_mask_ipi,
.irq_unmask = mpic_unmask_ipi,
.irq_eoi= mpic_end_ipi,
@@ -991,6 +993,7 @@ static struct irq_chip mpic_ipi_chip = {
 #endif /* CONFIG_SMP */
 
 static struct irq_chip mpic_tm_chip = {
+   .irq_disable= mpic_mask_tm,
.irq_mask   = mpic_mask_tm,
.irq_unmask = mpic_unmask_tm,
.irq_eoi= mpic_end_irq,
@@ -1001,6 +1004,7 @@ static struct irq_chip mpic_tm_chip = {
 static struct irq_chip mpic_irq_ht_chip = {
.irq_startup= mpic_startup_ht_irq,
.irq_shutdown   = mpic_shutdown_ht_irq,
+   .irq_disable= mpic_mask_irq,
.irq_mask   = mpic_mask_irq,
.irq_unmask = mpic_unmask_ht_irq,
.irq_eoi= mpic_end_ht_irq,
-- 
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[PATCH 1/2] powerpc/dts: fix lbc lack of error interrupt

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

P1020, P1021, P1022, P1023 when the lbc get error, the error
interrupt will be triggered. The corresponding interrupt is
internal IRQ0. So system have to process the lbc IRQ0 interrupt.

The corresponding lbc general interrupt is internal IRQ3.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com

diff --git a/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi 
b/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
index 68cc5e7..13f209f 100644
--- a/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
@@ -36,7 +36,8 @@
#address-cells = 2;
#size-cells = 1;
compatible = fsl,p1020-elbc, fsl,elbc, simple-bus;
-   interrupts = 19 2 0 0;
+   interrupts = 19 2 0 0
+ 16 2 0 0;
 };
 
 /* controller at 0x9000 */
diff --git a/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi 
b/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
index adb82fd..cffc93e 100644
--- a/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
@@ -36,7 +36,8 @@
#address-cells = 2;
#size-cells = 1;
compatible = fsl,p1021-elbc, fsl,elbc, simple-bus;
-   interrupts = 19 2 0 0;
+   interrupts = 19 2 0 0
+ 16 2 0 0;
 };
 
 /* controller at 0x9000 */
diff --git a/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi 
b/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
index e179803..979670d 100644
--- a/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
@@ -40,7 +40,8 @@
 * pin muxing when the DIU is enabled.
 */
compatible = fsl,p1022-elbc, fsl,elbc;
-   interrupts = 19 2 0 0;
+   interrupts = 19 2 0 0
+ 16 2 0 0;
 };
 
 /* controller at 0x9000 */
diff --git a/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi 
b/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi
index f1105bf..f5f5043 100644
--- a/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi
@@ -36,7 +36,8 @@
#address-cells = 2;
#size-cells = 1;
compatible = fsl,p1023-elbc, fsl,elbc, simple-bus;
-   interrupts = 19 2 0 0;
+   interrupts = 19 2 0 0
+ 16 2 0 0;
 };
 
 /* controller at 0xa000 */
-- 
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[PATCH 2/2] powerpc/85xx: handle the eLBC error interrupt if it exist in dts

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

On P3041, P1020, P1021, P1022, P1023 eLBC event interrupts are routed
to Int9(P3041)  Int3(P102x) while ELBC error interrupts are routed to
Int0, we need to call request_irq for each.

Signed-off-by: Shaohui Xie shaohui@freescale.com
Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
Signed-off-by: Kumar Gala ga...@kernel.crashing.org

diff --git a/arch/powerpc/include/asm/fsl_lbc.h 
b/arch/powerpc/include/asm/fsl_lbc.h
index 420b453..067fb0d 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -285,7 +285,7 @@ struct fsl_lbc_ctrl {
/* device info */
struct device   *dev;
struct fsl_lbc_regs __iomem *regs;
-   int irq;
+   int irq[2];
wait_queue_head_t   irq_wait;
spinlock_t  lock;
void*nand;
diff --git a/arch/powerpc/sysdev/fsl_lbc.c b/arch/powerpc/sysdev/fsl_lbc.c
index 6bc5a54..d631022 100644
--- a/arch/powerpc/sysdev/fsl_lbc.c
+++ b/arch/powerpc/sysdev/fsl_lbc.c
@@ -214,10 +214,14 @@ static irqreturn_t fsl_lbc_ctrl_irq(int irqno, void *data)
struct fsl_lbc_ctrl *ctrl = data;
struct fsl_lbc_regs __iomem *lbc = ctrl-regs;
u32 status;
+   unsigned long flags;
 
+   spin_lock_irqsave(fsl_lbc_lock, flags);
status = in_be32(lbc-ltesr);
-   if (!status)
+   if (!status) {
+   spin_unlock_irqrestore(fsl_lbc_lock, flags);
return IRQ_NONE;
+   }
 
out_be32(lbc-ltesr, LTESR_CLEAR);
out_be32(lbc-lteatr, 0);
@@ -260,6 +264,7 @@ static irqreturn_t fsl_lbc_ctrl_irq(int irqno, void *data)
if (status  ~LTESR_MASK)
dev_err(ctrl-dev, Unknown error: 
LTESR 0x%08X\n, status);
+   spin_unlock_irqrestore(fsl_lbc_lock, flags);
return IRQ_HANDLED;
 }
 
@@ -298,8 +303,8 @@ static int fsl_lbc_ctrl_probe(struct platform_device *dev)
goto err;
}
 
-   fsl_lbc_ctrl_dev-irq = irq_of_parse_and_map(dev-dev.of_node, 0);
-   if (fsl_lbc_ctrl_dev-irq == NO_IRQ) {
+   fsl_lbc_ctrl_dev-irq[0] = irq_of_parse_and_map(dev-dev.of_node, 0);
+   if (!fsl_lbc_ctrl_dev-irq[0]) {
dev_err(dev-dev, failed to get irq resource\n);
ret = -ENODEV;
goto err;
@@ -311,20 +316,34 @@ static int fsl_lbc_ctrl_probe(struct platform_device *dev)
if (ret  0)
goto err;
 
-   ret = request_irq(fsl_lbc_ctrl_dev-irq, fsl_lbc_ctrl_irq, 0,
+   ret = request_irq(fsl_lbc_ctrl_dev-irq[0], fsl_lbc_ctrl_irq, 0,
fsl-lbc, fsl_lbc_ctrl_dev);
if (ret != 0) {
dev_err(dev-dev, failed to install irq (%d)\n,
-   fsl_lbc_ctrl_dev-irq);
-   ret = fsl_lbc_ctrl_dev-irq;
+   fsl_lbc_ctrl_dev-irq[0]);
+   ret = fsl_lbc_ctrl_dev-irq[0];
goto err;
}
 
+   fsl_lbc_ctrl_dev-irq[1] = irq_of_parse_and_map(dev-dev.of_node, 1);
+   if (fsl_lbc_ctrl_dev-irq[1]) {
+   ret = request_irq(fsl_lbc_ctrl_dev-irq[1], fsl_lbc_ctrl_irq,
+   IRQF_SHARED, fsl-lbc-err, fsl_lbc_ctrl_dev);
+   if (ret) {
+   dev_err(dev-dev, failed to install irq (%d)\n,
+   fsl_lbc_ctrl_dev-irq[1]);
+   ret = fsl_lbc_ctrl_dev-irq[1];
+   goto err1;
+   }
+   }
+
/* Enable interrupts for any detected events */
out_be32(fsl_lbc_ctrl_dev-regs-lteir, LTEIR_ENABLE);
 
return 0;
 
+err1:
+   free_irq(fsl_lbc_ctrl_dev-irq[0], fsl_lbc_ctrl_dev);
 err:
iounmap(fsl_lbc_ctrl_dev-regs);
kfree(fsl_lbc_ctrl_dev);
-- 
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[PATCH v2 2/2] powerpc/mpic_timer: fix convert ticks to time subtraction overflow

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

In some cases tmp_sec may be greater than ticks, because in the process
of calculation ticks and tmp_sec will be rounded.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
v2:
Add the new patch in v2.

diff --git a/arch/powerpc/sysdev/mpic_timer.c b/arch/powerpc/sysdev/mpic_timer.c
index 70dcf9c..9d9b062 100644
--- a/arch/powerpc/sysdev/mpic_timer.c
+++ b/arch/powerpc/sysdev/mpic_timer.c
@@ -97,8 +97,11 @@ static void convert_ticks_to_time(struct timer_group_priv 
*priv,
time-tv_sec = (__kernel_time_t)div_u64(ticks, priv-timerfreq);
tmp_sec = (u64)time-tv_sec * (u64)priv-timerfreq;
 
-   time-tv_usec = (__kernel_suseconds_t)
-   div_u64((ticks - tmp_sec) * 100, priv-timerfreq);
+   time-tv_usec = 0;
+
+   if (tmp_sec = ticks)
+   time-tv_usec = (__kernel_suseconds_t)
+   div_u64((ticks - tmp_sec) * 100, priv-timerfreq);
 
return;
 }
-- 
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[PATCH] powerpc/mpic_timer: fix the time calculation is not accurate

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

When the timer GTCCR toggle bit is inverted, we calculated the rest
of the time is not accurate. So we need to ignore this bit.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com

diff --git a/arch/powerpc/sysdev/mpic_timer.c b/arch/powerpc/sysdev/mpic_timer.c
index 22d7d57..0fb70c9 100644
--- a/arch/powerpc/sysdev/mpic_timer.c
+++ b/arch/powerpc/sysdev/mpic_timer.c
@@ -41,6 +41,7 @@
 #define MPIC_TIMER_TCR_ROVR_OFFSET 24
 
 #define TIMER_STOP 0x8000
+#define GTCCR_TOG  0x8000
 #define TIMERS_PER_GROUP   4
 #define MAX_TICKS  (~0U  1)
 #define MAX_TICKS_CASCADE  (~0U)
@@ -96,8 +97,15 @@ static void convert_ticks_to_time(struct timer_group_priv 
*priv,
time-tv_sec = (__kernel_time_t)div_u64(ticks, priv-timerfreq);
tmp_sec = (u64)time-tv_sec * (u64)priv-timerfreq;
 
-   time-tv_usec = (__kernel_suseconds_t)
-   div_u64((ticks - tmp_sec) * 100, priv-timerfreq);
+   time-tv_usec = 0;
+
+   /*
+* In some cases tmp_sec may be greater than ticks, because in the
+* process of calculation ticks and tmp_sec will be rounded.
+*/
+   if (tmp_sec = ticks)
+   time-tv_usec = (__kernel_suseconds_t)
+   div_u64((ticks - tmp_sec) * 100, priv-timerfreq);
 
return;
 }
@@ -327,11 +335,13 @@ void mpic_get_remain_time(struct mpic_timer *handle, 
struct timeval *time)
casc_priv = priv-timer[handle-num].cascade_handle;
if (casc_priv) {
tmp_ticks = in_be32(priv-regs[handle-num].gtccr);
+   tmp_ticks = ~GTCCR_TOG;
ticks = ((u64)tmp_ticks  UINT_MAX) * (u64)MAX_TICKS_CASCADE;
tmp_ticks = in_be32(priv-regs[handle-num - 1].gtccr);
ticks += tmp_ticks;
} else {
ticks = in_be32(priv-regs[handle-num].gtccr);
+   ticks = ~GTCCR_TOG;
}
 
convert_ticks_to_time(priv, ticks, time);
-- 
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[RFC] linux/pci: move pci_platform_pm_ops to linux/pci.h

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

make Freescale platform use pci_platform_pm_ops struct.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---

If device's not set power state, we will use this interface to put the
device's into the correct state.

diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 9c91ecc..48f8b1a 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -33,36 +33,6 @@ int pci_mmap_fits(struct pci_dev *pdev, int resno, struct 
vm_area_struct *vmai,
 #endif
 int pci_probe_reset_function(struct pci_dev *dev);
 
-/**
- * struct pci_platform_pm_ops - Firmware PM callbacks
- *
- * @is_manageable: returns 'true' if given device is power manageable by the
- * platform firmware
- *
- * @set_state: invokes the platform firmware to set the device's power state
- *
- * @choose_state: returns PCI power state of given device preferred by the
- *platform; to be used during system-wide transitions from a
- *sleeping state to the working state and vice versa
- *
- * @sleep_wake: enables/disables the system wake up capability of given device
- *
- * @run_wake: enables/disables the platform to generate run-time wake-up events
- * for given device (the device's wake-up capability has to be
- * enabled by @sleep_wake for this feature to work)
- *
- * If given platform is generally capable of power managing PCI devices, all of
- * these callbacks are mandatory.
- */
-struct pci_platform_pm_ops {
-   bool (*is_manageable)(struct pci_dev *dev);
-   int (*set_state)(struct pci_dev *dev, pci_power_t state);
-   pci_power_t (*choose_state)(struct pci_dev *dev);
-   int (*sleep_wake)(struct pci_dev *dev, bool enable);
-   int (*run_wake)(struct pci_dev *dev, bool enable);
-};
-
-int pci_set_platform_pm(struct pci_platform_pm_ops *ops);
 void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
 void pci_power_up(struct pci_dev *dev);
 void pci_disable_enabled_device(struct pci_dev *dev);
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 1084a15..20e07b8 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -365,6 +365,37 @@ struct pci_dev {
size_t romlen; /* Length of ROM if it's not from the BAR */
 };
 
+/**
+ * struct pci_platform_pm_ops - Firmware PM callbacks
+ *
+ * @is_manageable: returns 'true' if given device is power manageable by the
+ * platform firmware
+ *
+ * @set_state: invokes the platform firmware to set the device's power state
+ *
+ * @choose_state: returns PCI power state of given device preferred by the
+ *platform; to be used during system-wide transitions from a
+ *sleeping state to the working state and vice versa
+ *
+ * @sleep_wake: enables/disables the system wake up capability of given device
+ *
+ * @run_wake: enables/disables the platform to generate run-time wake-up events
+ * for given device (the device's wake-up capability has to be
+ * enabled by @sleep_wake for this feature to work)
+ *
+ * If given platform is generally capable of power managing PCI devices, all of
+ * these callbacks are mandatory.
+ */
+struct pci_platform_pm_ops {
+   bool (*is_manageable)(struct pci_dev *dev);
+   int (*set_state)(struct pci_dev *dev, pci_power_t state);
+   pci_power_t (*choose_state)(struct pci_dev *dev);
+   int (*sleep_wake)(struct pci_dev *dev, bool enable);
+   int (*run_wake)(struct pci_dev *dev, bool enable);
+};
+
+int pci_set_platform_pm(struct pci_platform_pm_ops *ops);
+
 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
 {
 #ifdef CONFIG_PCI_IOV
-- 
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[PATCH 1/2] powerpc/p1022ds: fix rtc compatible string

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

RTC Hardware(ds3232) and rtc compatible string does not match.
Change dallas,ds1339 to dallas,ds3232.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com

diff --git a/arch/powerpc/boot/dts/p1022ds.dtsi 
b/arch/powerpc/boot/dts/p1022ds.dtsi
index 873da35..5725058 100644
--- a/arch/powerpc/boot/dts/p1022ds.dtsi
+++ b/arch/powerpc/boot/dts/p1022ds.dtsi
@@ -146,7 +146,7 @@
 */
};
rtc@68 {
-   compatible = dallas,ds1339;
+   compatible = dallas,ds3232;
reg = 0x68;
};
adt7461@4c {
-- 
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[PATCH 2/2] powerpc/p1022ds: add a interrupt for rtc node

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

Add an external interrupt for rtc node.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com

diff --git a/arch/powerpc/boot/dts/p1022ds.dtsi 
b/arch/powerpc/boot/dts/p1022ds.dtsi
index 5725058..957e0dc 100644
--- a/arch/powerpc/boot/dts/p1022ds.dtsi
+++ b/arch/powerpc/boot/dts/p1022ds.dtsi
@@ -148,6 +148,7 @@
rtc@68 {
compatible = dallas,ds3232;
reg = 0x68;
+   interrupts = 0x1 0x1 0 0;
};
adt7461@4c {
compatible = adi,adt7461;
-- 
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[PATCH v6 2/4] powerpc/85xx: add hardware automatically enter altivec idle state

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

Each core's AltiVec unit may be placed into a power savings mode
by turning off power to the unit. Core hardware will automatically
power down the AltiVec unit after no AltiVec instructions have
executed in N cycles. The AltiVec power-control is triggered by hardware.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
*v3:
Assembly code instead of C code.

*v2:
Remove:
delete setup_idle_hw_governor function.
delete Fix erratum for rev1.

Move:
move setup_* into __setup/restore_cpu_e6500.

 arch/powerpc/kernel/cpu_setup_fsl_booke.S | 21 +
 1 file changed, 21 insertions(+)

diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S 
b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index bfb18c7..4789056 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -53,11 +53,31 @@ _GLOBAL(__e500_dcache_setup)
isync
blr
 
+/*
+ * FIXME - we haven't yet done testing to determine a reasonable default
+ * value for AV_WAIT_IDLE_BIT.
+ */
+#define AV_WAIT_IDLE_BIT   50 /* 1ms, TB frequency is 41.66MHZ */
+_GLOBAL(setup_altivec_idle)
+   mfspr   r3, SPRN_PWRMGTCR0
+
+   /* Enable Altivec Idle */
+   orisr3, r3, PWRMGTCR0_AV_IDLE_PD_EN@h
+   li  r11, AV_WAIT_IDLE_BIT
+
+   /* Set Automatic AltiVec Idle Count */
+   rlwimi  r3, r11, PWRMGTCR0_AV_IDLE_CNT_SHIFT, PWRMGTCR0_AV_IDLE_CNT
+
+   mtspr   SPRN_PWRMGTCR0, r3
+
+   blr
+
 _GLOBAL(__setup_cpu_e6500)
mflrr6
 #ifdef CONFIG_PPC64
bl  .setup_altivec_ivors
 #endif
+   bl  setup_altivec_idle
bl  __setup_cpu_e5500
mtlrr6
blr
@@ -119,6 +139,7 @@ _GLOBAL(__setup_cpu_e5500)
 _GLOBAL(__restore_cpu_e6500)
mflrr5
bl  .setup_altivec_ivors
+   bl  .setup_altivec_idle
bl  __restore_cpu_e5500
mtlrr5
blr
-- 
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[PATCH v6 3/4] powerpc/85xx: add hardware automatically enter pw20 state

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

Using hardware features make core automatically enter PW20 state.
Set a TB count to hardware, the effective count begins when PW10
is entered. When the effective period has expired, the core will
proceed from PW10 to PW20 if no exit conditions have occurred during
the period.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
*v3:
Assembly code instead of C code.

*v2:
Remove:
delete setup_idle_hw_governor function.
delete Fix erratum for rev1.

Move:
move setup_* into __setup/restore_cpu_e6500.

 arch/powerpc/kernel/cpu_setup_fsl_booke.S | 21 +
 1 file changed, 21 insertions(+)

diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S 
b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index 4789056..49e738e 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -55,6 +55,25 @@ _GLOBAL(__e500_dcache_setup)
 
 /*
  * FIXME - we haven't yet done testing to determine a reasonable default
+ * value for PW20_WAIT_IDLE_BIT.
+ */
+#define PW20_WAIT_IDLE_BIT 50 /* 1ms, TB frequency is 41.66MHZ */
+_GLOBAL(setup_pw20_idle)
+   mfspr   r3, SPRN_PWRMGTCR0
+
+   /* Set PW20_WAIT bit, enable pw20 state*/
+   ori r3, r3, PWRMGTCR0_PW20_WAIT
+   li  r11, PW20_WAIT_IDLE_BIT
+
+   /* Set Automatic PW20 Core Idle Count */
+   rlwimi  r3, r11, PWRMGTCR0_PW20_ENT_SHIFT, PWRMGTCR0_PW20_ENT
+
+   mtspr   SPRN_PWRMGTCR0, r3
+
+   blr
+
+/*
+ * FIXME - we haven't yet done testing to determine a reasonable default
  * value for AV_WAIT_IDLE_BIT.
  */
 #define AV_WAIT_IDLE_BIT   50 /* 1ms, TB frequency is 41.66MHZ */
@@ -77,6 +96,7 @@ _GLOBAL(__setup_cpu_e6500)
 #ifdef CONFIG_PPC64
bl  .setup_altivec_ivors
 #endif
+   bl  setup_pw20_idle
bl  setup_altivec_idle
bl  __setup_cpu_e5500
mtlrr6
@@ -139,6 +159,7 @@ _GLOBAL(__setup_cpu_e5500)
 _GLOBAL(__restore_cpu_e6500)
mflrr5
bl  .setup_altivec_ivors
+   bl  .setup_pw20_idle
bl  .setup_altivec_idle
bl  __restore_cpu_e5500
mtlrr5
-- 
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[PATCH v6 4/4] powerpc/85xx: add sysfs for pw20 state and altivec idle

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

Add a sys interface to enable/diable pw20 state or altivec idle, and
control the wait entry time.

Enable/Disable interface:
0, disable. 1, enable.
/sys/devices/system/cpu/cpuX/pw20_state
/sys/devices/system/cpu/cpuX/altivec_idle

Set wait time interface:(Nanosecond)
/sys/devices/system/cpu/cpuX/pw20_wait_time
/sys/devices/system/cpu/cpuX/altivec_idle_wait_time
Example: Base on TBfreq is 41MHZ.
1~48(ns): TB[63]
49~97(ns): TB[62]
98~195(ns): TB[61]
196~390(ns): TB[60]
391~780(ns): TB[59]
781~1560(ns): TB[58]
...

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
*v6:
Change show_pw20_wait_time/show_altivec_idle_wait_time functions implementation.

*v5:
Change get_idle_ticks_bit function implementation.

*v4:
Move code from 85xx/common.c to kernel/sysfs.c.

Remove has_pw20_altivec_idle function.

Change wait entry_bit to wait time.

diff --git a/arch/powerpc/kernel/sysfs.c b/arch/powerpc/kernel/sysfs.c
index b4e6676..6c92e23 100644
--- a/arch/powerpc/kernel/sysfs.c
+++ b/arch/powerpc/kernel/sysfs.c
@@ -86,6 +86,304 @@ __setup(smt-snooze-delay=, setup_smt_snooze_delay);
 
 #endif /* CONFIG_PPC64 */
 
+#ifdef CONFIG_FSL_SOC
+#define MAX_BIT63
+
+static u64 pw20_wt;
+static u64 altivec_idle_wt;
+
+static unsigned int get_idle_ticks_bit(u64 ns)
+{
+   u64 cycle;
+
+   if (ns = 1)
+   cycle = div_u64(ns + 500, 1000) * tb_ticks_per_usec;
+   else
+   cycle = div_u64(ns * tb_ticks_per_usec, 1000);
+
+   if (!cycle)
+   return 0;
+
+   return ilog2(cycle);
+}
+
+static void do_show_pwrmgtcr0(void *val)
+{
+   u32 *value = val;
+
+   *value = mfspr(SPRN_PWRMGTCR0);
+}
+
+static ssize_t show_pw20_state(struct device *dev,
+   struct device_attribute *attr, char *buf)
+{
+   u32 value;
+   unsigned int cpu = dev-id;
+
+   smp_call_function_single(cpu, do_show_pwrmgtcr0, value, 1);
+
+   value = PWRMGTCR0_PW20_WAIT;
+
+   return sprintf(buf, %u\n, value ? 1 : 0);
+}
+
+static void do_store_pw20_state(void *val)
+{
+   u32 *value = val;
+   u32 pw20_state;
+
+   pw20_state = mfspr(SPRN_PWRMGTCR0);
+
+   if (*value)
+   pw20_state |= PWRMGTCR0_PW20_WAIT;
+   else
+   pw20_state = ~PWRMGTCR0_PW20_WAIT;
+
+   mtspr(SPRN_PWRMGTCR0, pw20_state);
+}
+
+static ssize_t store_pw20_state(struct device *dev,
+   struct device_attribute *attr,
+   const char *buf, size_t count)
+{
+   u32 value;
+   unsigned int cpu = dev-id;
+
+   if (kstrtou32(buf, 0, value))
+   return -EINVAL;
+
+   if (value  1)
+   return -EINVAL;
+
+   smp_call_function_single(cpu, do_store_pw20_state, value, 1);
+
+   return count;
+}
+
+static ssize_t show_pw20_wait_time(struct device *dev,
+   struct device_attribute *attr, char *buf)
+{
+   u32 value;
+   u64 tb_cycle = 1;
+   u64 time;
+
+   unsigned int cpu = dev-id;
+
+   if (!pw20_wt) {
+   smp_call_function_single(cpu, do_show_pwrmgtcr0, value, 1);
+   value = (value  PWRMGTCR0_PW20_ENT) 
+   PWRMGTCR0_PW20_ENT_SHIFT;
+
+   tb_cycle = (tb_cycle  (MAX_BIT - value + 1));
+   /* convert ms to ns */
+   if (tb_ticks_per_usec  1000) {
+   time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
+   } else {
+   u32 rem_us;
+
+   time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
+   rem_us);
+   time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
+   }
+   } else {
+   time = pw20_wt;
+   }
+
+   return sprintf(buf, %llu\n, time  0 ? time : 0);
+}
+
+static void set_pw20_wait_entry_bit(void *val)
+{
+   u32 *value = val;
+   u32 pw20_idle;
+
+   pw20_idle = mfspr(SPRN_PWRMGTCR0);
+
+   /* Set Automatic PW20 Core Idle Count */
+   /* clear count */
+   pw20_idle = ~PWRMGTCR0_PW20_ENT;
+
+   /* set count */
+   pw20_idle |= ((MAX_BIT - *value)  PWRMGTCR0_PW20_ENT_SHIFT);
+
+   mtspr(SPRN_PWRMGTCR0, pw20_idle);
+}
+
+static ssize_t store_pw20_wait_time(struct device *dev,
+   struct device_attribute *attr,
+   const char *buf, size_t count)
+{
+   u32 entry_bit;
+   u64 value;
+
+   unsigned int cpu = dev-id;
+
+   if (kstrtou64(buf, 0, value))
+   return -EINVAL;
+
+   if (!value)
+   return -EINVAL;
+
+   entry_bit = get_idle_ticks_bit(value);
+   if (entry_bit  MAX_BIT)
+   return -EINVAL;
+
+   pw20_wt = value;
+
+   

RE: [PATCH v5 4/4] powerpc/85xx: add sysfs for pw20 state and altivec idle

[Dongsheng Wang]

 -Original Message-
 From: Wang Dongsheng-B40534
 Sent: Thursday, November 07, 2013 10:13 AM
 To: Wood Scott-B07421
 Cc: Bhushan Bharat-R65777; linuxppc-dev@lists.ozlabs.org
 Subject: RE: [PATCH v5 4/4] powerpc/85xx: add sysfs for pw20 state and
 altivec idle
 
 
 
  -Original Message-
  From: Wood Scott-B07421
  Sent: Thursday, November 07, 2013 9:20 AM
  To: Wang Dongsheng-B40534
  Cc: Bhushan Bharat-R65777; Wood Scott-B07421; linuxppc-
  d...@lists.ozlabs.org
  Subject: Re: [PATCH v5 4/4] powerpc/85xx: add sysfs for pw20 state and
  altivec idle
 
  On Wed, 2013-11-06 at 01:50 -0600, Wang Dongsheng-B40534 wrote:
  
-Original Message-
From: Bhushan Bharat-R65777
Sent: Wednesday, November 06, 2013 1:25 PM
To: Wang Dongsheng-B40534; Wood Scott-B07421
Cc: linuxppc-dev@lists.ozlabs.org
Subject: RE: [PATCH v5 4/4] powerpc/85xx: add sysfs for pw20 state
and altivec idle
   
   
   
 -Original Message-
 From: Wang Dongsheng-B40534
 Sent: Tuesday, November 05, 2013 8:40 AM
 To: Wood Scott-B07421
 Cc: Bhushan Bharat-R65777; linuxppc-dev@lists.ozlabs.org
 Subject: RE: [PATCH v5 4/4] powerpc/85xx: add sysfs for pw20
 state
 and altivec idle



  -Original Message-
  From: Wood Scott-B07421
  Sent: Tuesday, November 05, 2013 5:52 AM
  To: Wang Dongsheng-B40534
  Cc: Wood Scott-B07421; Bhushan Bharat-R65777; linuxppc-
  d...@lists.ozlabs.org
  Subject: Re: [PATCH v5 4/4] powerpc/85xx: add sysfs for pw20
  state and altivec idle
 
  On Sun, 2013-11-03 at 22:04 -0600, Wang Dongsheng-B40534 wrote:
-Original Message-
From: Wang Dongsheng-B40534
Sent: Monday, October 21, 2013 11:11 AM
To: Wood Scott-B07421
Cc: Bhushan Bharat-R65777; linuxppc-dev@lists.ozlabs.org
Subject: RE: [PATCH v5 4/4] powerpc/85xx: add sysfs for
 pw20
state and altivec idle
   
   
   
 -Original Message-
 From: Wood Scott-B07421
 Sent: Saturday, October 19, 2013 3:22 AM
 To: Wang Dongsheng-B40534
 Cc: Bhushan Bharat-R65777; Wood Scott-B07421; linuxppc-
 d...@lists.ozlabs.org
 Subject: Re: [PATCH v5 4/4] powerpc/85xx: add sysfs for
 pw20 state and altivec idle

 On Thu, 2013-10-17 at 22:02 -0500, Wang Dongsheng-B40534
  wrote:
 
   -Original Message-
   From: Bhushan Bharat-R65777
   Sent: Thursday, October 17, 2013 2:46 PM
   To: Wang Dongsheng-B40534; Wood Scott-B07421
   Cc: linuxppc-dev@lists.ozlabs.org
   Subject: RE: [PATCH v5 4/4] powerpc/85xx: add sysfs
   for
   pw20 state and altivec idle
  
  
  
  -Original Message-
  From: Wang Dongsheng-B40534
  Sent: Thursday, October 17, 2013 11:22 AM
  To: Bhushan Bharat-R65777; Wood Scott-B07421
  Cc: linuxppc-dev@lists.ozlabs.org
  Subject: RE: [PATCH v5 4/4] powerpc/85xx: add
  sysfs for
  pw20 state and altivec idle
 
 
 
   -Original Message-
   From: Bhushan Bharat-R65777
   Sent: Thursday, October 17, 2013 11:20 AM
   To: Wang Dongsheng-B40534; Wood Scott-B07421
   Cc: linuxppc-dev@lists.ozlabs.org
   Subject: RE: [PATCH v5 4/4] powerpc/85xx: add
   sysfs for
   pw20 state and altivec idle
  
  
  
-Original Message-
From: Wang Dongsheng-B40534
Sent: Thursday, October 17, 2013 8:16 AM
To: Bhushan Bharat-R65777; Wood Scott-
 B07421
Cc: linuxppc-dev@lists.ozlabs.org
Subject: RE: [PATCH v5 4/4] powerpc/85xx:
add sysfs for
pw20 state and altivec idle
   
   
   
 -Original Message-
 From: Bhushan Bharat-R65777
 Sent: Thursday, October 17, 2013 1:01 AM
 To: Wang Dongsheng-B40534; Wood
 Scott-B07421
 Cc: linuxppc-dev@lists.ozlabs.org
 Subject: RE: [PATCH v5 4/4] powerpc/85xx:
 add sysfs for
 pw20 state and altivec idle



  -Original Message-
  From: Wang Dongsheng-B40534
  Sent: Tuesday, October 15, 2013 2:51 PM
  To: Wood Scott-B07421
  Cc: Bhushan Bharat-R65777;
  linuxppc-dev@lists.ozlabs.org; Wang
 Dongsheng-B40534
  Subject: [PATCH v5 4/4] powerpc/85xx:
  add sysfs for
  pw20 

RE: [PATCH v5 4/4] powerpc/85xx: add sysfs for pw20 state and altivec idle

[Dongsheng Wang]

 -Original Message-
 From: Wood Scott-B07421
 Sent: Thursday, November 07, 2013 9:20 AM
 To: Wang Dongsheng-B40534
 Cc: Bhushan Bharat-R65777; Wood Scott-B07421; linuxppc-
 d...@lists.ozlabs.org
 Subject: Re: [PATCH v5 4/4] powerpc/85xx: add sysfs for pw20 state and
 altivec idle
 
 On Wed, 2013-11-06 at 01:50 -0600, Wang Dongsheng-B40534 wrote:
 
   -Original Message-
   From: Bhushan Bharat-R65777
   Sent: Wednesday, November 06, 2013 1:25 PM
   To: Wang Dongsheng-B40534; Wood Scott-B07421
   Cc: linuxppc-dev@lists.ozlabs.org
   Subject: RE: [PATCH v5 4/4] powerpc/85xx: add sysfs for pw20 state
   and altivec idle
  
  
  
-Original Message-
From: Wang Dongsheng-B40534
Sent: Tuesday, November 05, 2013 8:40 AM
To: Wood Scott-B07421
Cc: Bhushan Bharat-R65777; linuxppc-dev@lists.ozlabs.org
Subject: RE: [PATCH v5 4/4] powerpc/85xx: add sysfs for pw20 state
and altivec idle
   
   
   
 -Original Message-
 From: Wood Scott-B07421
 Sent: Tuesday, November 05, 2013 5:52 AM
 To: Wang Dongsheng-B40534
 Cc: Wood Scott-B07421; Bhushan Bharat-R65777; linuxppc-
 d...@lists.ozlabs.org
 Subject: Re: [PATCH v5 4/4] powerpc/85xx: add sysfs for pw20
 state and altivec idle

 On Sun, 2013-11-03 at 22:04 -0600, Wang Dongsheng-B40534 wrote:
   -Original Message-
   From: Wang Dongsheng-B40534
   Sent: Monday, October 21, 2013 11:11 AM
   To: Wood Scott-B07421
   Cc: Bhushan Bharat-R65777; linuxppc-dev@lists.ozlabs.org
   Subject: RE: [PATCH v5 4/4] powerpc/85xx: add sysfs for pw20
   state and altivec idle
  
  
  
-Original Message-
From: Wood Scott-B07421
Sent: Saturday, October 19, 2013 3:22 AM
To: Wang Dongsheng-B40534
Cc: Bhushan Bharat-R65777; Wood Scott-B07421; linuxppc-
d...@lists.ozlabs.org
Subject: Re: [PATCH v5 4/4] powerpc/85xx: add sysfs for
pw20 state and altivec idle
   
On Thu, 2013-10-17 at 22:02 -0500, Wang Dongsheng-B40534
 wrote:

  -Original Message-
  From: Bhushan Bharat-R65777
  Sent: Thursday, October 17, 2013 2:46 PM
  To: Wang Dongsheng-B40534; Wood Scott-B07421
  Cc: linuxppc-dev@lists.ozlabs.org
  Subject: RE: [PATCH v5 4/4] powerpc/85xx: add sysfs
  for
  pw20 state and altivec idle
 
 
 
 -Original Message-
 From: Wang Dongsheng-B40534
 Sent: Thursday, October 17, 2013 11:22 AM
 To: Bhushan Bharat-R65777; Wood Scott-B07421
 Cc: linuxppc-dev@lists.ozlabs.org
 Subject: RE: [PATCH v5 4/4] powerpc/85xx: add
 sysfs for
 pw20 state and altivec idle



  -Original Message-
  From: Bhushan Bharat-R65777
  Sent: Thursday, October 17, 2013 11:20 AM
  To: Wang Dongsheng-B40534; Wood Scott-B07421
  Cc: linuxppc-dev@lists.ozlabs.org
  Subject: RE: [PATCH v5 4/4] powerpc/85xx: add
  sysfs for
  pw20 state and altivec idle
 
 
 
   -Original Message-
   From: Wang Dongsheng-B40534
   Sent: Thursday, October 17, 2013 8:16 AM
   To: Bhushan Bharat-R65777; Wood Scott-B07421
   Cc: linuxppc-dev@lists.ozlabs.org
   Subject: RE: [PATCH v5 4/4] powerpc/85xx:
   add sysfs for
   pw20 state and altivec idle
  
  
  
-Original Message-
From: Bhushan Bharat-R65777
Sent: Thursday, October 17, 2013 1:01 AM
To: Wang Dongsheng-B40534; Wood
Scott-B07421
Cc: linuxppc-dev@lists.ozlabs.org
Subject: RE: [PATCH v5 4/4] powerpc/85xx:
add sysfs for
pw20 state and altivec idle
   
   
   
 -Original Message-
 From: Wang Dongsheng-B40534
 Sent: Tuesday, October 15, 2013 2:51 PM
 To: Wood Scott-B07421
 Cc: Bhushan Bharat-R65777;
 linuxppc-dev@lists.ozlabs.org; Wang
Dongsheng-B40534
 Subject: [PATCH v5 4/4] powerpc/85xx:
 add sysfs for
 pw20 state and
altivec idle

 From: Wang Dongsheng
 dongsheng.w...@freescale.com

 Add a sys interface to enable/diable
 pw20 state or altivec idle, and
control the
 wait entry time.

 Enable/Disable interface:
 0, 

RE: [PATCH v5 4/4] powerpc/85xx: add sysfs for pw20 state and altivec idle

[Dongsheng Wang]

 -Original Message-
 From: Bhushan Bharat-R65777
 Sent: Wednesday, November 06, 2013 1:25 PM
 To: Wang Dongsheng-B40534; Wood Scott-B07421
 Cc: linuxppc-dev@lists.ozlabs.org
 Subject: RE: [PATCH v5 4/4] powerpc/85xx: add sysfs for pw20 state and
 altivec idle
 
 
 
  -Original Message-
  From: Wang Dongsheng-B40534
  Sent: Tuesday, November 05, 2013 8:40 AM
  To: Wood Scott-B07421
  Cc: Bhushan Bharat-R65777; linuxppc-dev@lists.ozlabs.org
  Subject: RE: [PATCH v5 4/4] powerpc/85xx: add sysfs for pw20 state and
  altivec idle
 
 
 
   -Original Message-
   From: Wood Scott-B07421
   Sent: Tuesday, November 05, 2013 5:52 AM
   To: Wang Dongsheng-B40534
   Cc: Wood Scott-B07421; Bhushan Bharat-R65777; linuxppc-
   d...@lists.ozlabs.org
   Subject: Re: [PATCH v5 4/4] powerpc/85xx: add sysfs for pw20 state
   and altivec idle
  
   On Sun, 2013-11-03 at 22:04 -0600, Wang Dongsheng-B40534 wrote:
 -Original Message-
 From: Wang Dongsheng-B40534
 Sent: Monday, October 21, 2013 11:11 AM
 To: Wood Scott-B07421
 Cc: Bhushan Bharat-R65777; linuxppc-dev@lists.ozlabs.org
 Subject: RE: [PATCH v5 4/4] powerpc/85xx: add sysfs for pw20
 state and altivec idle



  -Original Message-
  From: Wood Scott-B07421
  Sent: Saturday, October 19, 2013 3:22 AM
  To: Wang Dongsheng-B40534
  Cc: Bhushan Bharat-R65777; Wood Scott-B07421; linuxppc-
  d...@lists.ozlabs.org
  Subject: Re: [PATCH v5 4/4] powerpc/85xx: add sysfs for pw20
  state and altivec idle
 
  On Thu, 2013-10-17 at 22:02 -0500, Wang Dongsheng-B40534 wrote:
  
-Original Message-
From: Bhushan Bharat-R65777
Sent: Thursday, October 17, 2013 2:46 PM
To: Wang Dongsheng-B40534; Wood Scott-B07421
Cc: linuxppc-dev@lists.ozlabs.org
Subject: RE: [PATCH v5 4/4] powerpc/85xx: add sysfs for
pw20 state and altivec idle
   
   
   
   -Original Message-
   From: Wang Dongsheng-B40534
   Sent: Thursday, October 17, 2013 11:22 AM
   To: Bhushan Bharat-R65777; Wood Scott-B07421
   Cc: linuxppc-dev@lists.ozlabs.org
   Subject: RE: [PATCH v5 4/4] powerpc/85xx: add sysfs
   for
   pw20 state and altivec idle
  
  
  
-Original Message-
From: Bhushan Bharat-R65777
Sent: Thursday, October 17, 2013 11:20 AM
To: Wang Dongsheng-B40534; Wood Scott-B07421
Cc: linuxppc-dev@lists.ozlabs.org
Subject: RE: [PATCH v5 4/4] powerpc/85xx: add
sysfs for
pw20 state and altivec idle
   
   
   
 -Original Message-
 From: Wang Dongsheng-B40534
 Sent: Thursday, October 17, 2013 8:16 AM
 To: Bhushan Bharat-R65777; Wood Scott-B07421
 Cc: linuxppc-dev@lists.ozlabs.org
 Subject: RE: [PATCH v5 4/4] powerpc/85xx: add
 sysfs for
 pw20 state and altivec idle



  -Original Message-
  From: Bhushan Bharat-R65777
  Sent: Thursday, October 17, 2013 1:01 AM
  To: Wang Dongsheng-B40534; Wood Scott-B07421
  Cc: linuxppc-dev@lists.ozlabs.org
  Subject: RE: [PATCH v5 4/4] powerpc/85xx: add
  sysfs for
  pw20 state and altivec idle
 
 
 
   -Original Message-
   From: Wang Dongsheng-B40534
   Sent: Tuesday, October 15, 2013 2:51 PM
   To: Wood Scott-B07421
   Cc: Bhushan Bharat-R65777;
   linuxppc-dev@lists.ozlabs.org; Wang
  Dongsheng-B40534
   Subject: [PATCH v5 4/4] powerpc/85xx: add
   sysfs for
   pw20 state and
  altivec idle
  
   From: Wang Dongsheng
   dongsheng.w...@freescale.com
  
   Add a sys interface to enable/diable pw20
   state or altivec idle, and
  control the
   wait entry time.
  
   Enable/Disable interface:
   0, disable. 1, enable.
   /sys/devices/system/cpu/cpuX/pw20_state
   /sys/devices/system/cpu/cpuX/altivec_idle
  
   Set wait time interface:(Nanosecond)
   /sys/devices/system/cpu/cpuX/pw20_wait_time
   /sys/devices/system/cpu/cpuX/altivec_idle_wa
   it
   _t
   ime
   Example: Base on TBfreq is 41MHZ.
   1~48(ns): TB[63]
   49~97(ns): TB[62]
   98~195(ns): TB[61]
   196~390(ns): TB[60]
   391~780(ns): TB[59]
   781~1560(ns): TB[58] ...

RE: [PATCH v5 4/4] powerpc/85xx: add sysfs for pw20 state and altivec idle

[Dongsheng Wang]

 -Original Message-
 From: Wood Scott-B07421
 Sent: Tuesday, November 05, 2013 7:48 AM
 To: Wang Dongsheng-B40534
 Cc: Wood Scott-B07421; Bhushan Bharat-R65777; linuxppc-
 d...@lists.ozlabs.org
 Subject: Re: [PATCH v5 4/4] powerpc/85xx: add sysfs for pw20 state and
 altivec idle
 
 On Sun, 2013-10-20 at 22:27 -0500, Wang Dongsheng-B40534 wrote:
 
   -Original Message-
   From: Wood Scott-B07421
   Sent: Saturday, October 19, 2013 3:23 AM
   To: Wang Dongsheng-B40534
   Cc: Wood Scott-B07421; Bhushan Bharat-R65777; linuxppc-
   d...@lists.ozlabs.org
   Subject: Re: [PATCH v5 4/4] powerpc/85xx: add sysfs for pw20 state
   and altivec idle
  
   On Thu, 2013-10-17 at 21:36 -0500, Wang Dongsheng-B40534 wrote:
   
 -Original Message-
 From: Wood Scott-B07421
 Sent: Friday, October 18, 2013 12:52 AM
 To: Wang Dongsheng-B40534
 Cc: Bhushan Bharat-R65777; Wood Scott-B07421; linuxppc-
 d...@lists.ozlabs.org
 Subject: Re: [PATCH v5 4/4] powerpc/85xx: add sysfs for pw20
 state and altivec idle

 On Thu, 2013-10-17 at 00:51 -0500, Wang Dongsheng-B40534 wrote:
 
   -Original Message-
   From: Bhushan Bharat-R65777
   Sent: Thursday, October 17, 2013 11:20 AM
   To: Wang Dongsheng-B40534; Wood Scott-B07421
   Cc: linuxppc-dev@lists.ozlabs.org
   Subject: RE: [PATCH v5 4/4] powerpc/85xx: add sysfs for pw20
   state and altivec idle
  
  
  
-Original Message-
From: Wang Dongsheng-B40534
Sent: Thursday, October 17, 2013 8:16 AM
To: Bhushan Bharat-R65777; Wood Scott-B07421
Cc: linuxppc-dev@lists.ozlabs.org
Subject: RE: [PATCH v5 4/4] powerpc/85xx: add sysfs for
pw20 state and altivec idle
   
   
   
 -Original Message-
 From: Bhushan Bharat-R65777
 Sent: Thursday, October 17, 2013 1:01 AM
 To: Wang Dongsheng-B40534; Wood Scott-B07421
 Cc: linuxppc-dev@lists.ozlabs.org
 Subject: RE: [PATCH v5 4/4] powerpc/85xx: add sysfs for
 pw20 state and altivec idle



  -Original Message-
  From: Wang Dongsheng-B40534
  Sent: Tuesday, October 15, 2013 2:51 PM
  To: Wood Scott-B07421
  Cc: Bhushan Bharat-R65777;
  linuxppc-dev@lists.ozlabs.org; Wang
 Dongsheng-B40534
  Subject: [PATCH v5 4/4] powerpc/85xx: add sysfs for
  pw20 state and
 altivec idle
 
  +static ssize_t show_pw20_wait_time(struct device *dev,
  +   struct device_attribute *attr,
 char
   *buf) {
  +   u32 value;
  +   u64 tb_cycle;
  +   s64 time;
  +
  +   unsigned int cpu = dev-id;
  +
  +   if (!pw20_wt) {
  +   smp_call_function_single(cpu,
 do_show_pwrmgtcr0,
  +value,
   1);
  +   value = (value  PWRMGTCR0_PW20_ENT) 
  +   
  PWRMGTCR0_PW20_ENT_SHIFT;
  +
  +   tb_cycle = (1  (MAX_BIT - value)) * 2;

 Is value = 0 and value = 1 legal? These will make
 tb_cycle = 0,

  +   time = div_u64(tb_cycle * 1000,
 tb_ticks_per_usec)
   - 1;

 And time = -1;

Please look at the end of the function, :)
   
return sprintf(buf, %llu\n, time  0 ? time : 0);
  
   I know you return 0 if value = 0/1, my question was that, is
   this correct as per specification?
  
   Ahh, also for value upto 7 you will return 0, no?
  
  If value = 0, MAX_BIT - value = 63 tb_cycle =
  0x_,

 Actually, tb_cycle will be undefined because you shifted a
 32-bit value
 (1) by more than 31 bits.  s/1/1ULL/

Actually, we have been discussing this situation that could not
have
   happened.
See !pw20_wt branch, this branch is read default wait bit.
The default wait bit is 50, the time is about 1ms.
The default wait bit cannot less than 50, means the wait entry
time
   cannot greater than 1ms.
We have already begun benchmark test, and we got a preliminary
 results.
55, 56, 57bit looks good, but we need more benchmark to get the
default
   bit.
  
   What does the default have to do with it?  The user could have set a
   different value, and then read it back.
  
   Plus, how much time corresponds to bit 50 depends on the actual
   timebase frequency which could vary.
  
  if (!pw20_wt) {
  smp_call_function_single(cpu, do_show_pwrmgtcr0, value, 1);
  value = (value  PWRMGTCR0_PW20_ENT) 
  PWRMGTCR0_PW20_ENT_SHIFT;
 
  tb_cycle = (1  (MAX_BIT - value)) * 2;
  time = tb_cycle * (1000 / tb_ticks_per_usec) - 1;
  } else {
  time = 

RE: [PATCH v5 4/4] powerpc/85xx: add sysfs for pw20 state and altivec idle

[Dongsheng Wang]

 -Original Message-
 From: Wood Scott-B07421
 Sent: Tuesday, November 05, 2013 5:52 AM
 To: Wang Dongsheng-B40534
 Cc: Wood Scott-B07421; Bhushan Bharat-R65777; linuxppc-
 d...@lists.ozlabs.org
 Subject: Re: [PATCH v5 4/4] powerpc/85xx: add sysfs for pw20 state and
 altivec idle
 
 On Sun, 2013-11-03 at 22:04 -0600, Wang Dongsheng-B40534 wrote:
   -Original Message-
   From: Wang Dongsheng-B40534
   Sent: Monday, October 21, 2013 11:11 AM
   To: Wood Scott-B07421
   Cc: Bhushan Bharat-R65777; linuxppc-dev@lists.ozlabs.org
   Subject: RE: [PATCH v5 4/4] powerpc/85xx: add sysfs for pw20 state
   and altivec idle
  
  
  
-Original Message-
From: Wood Scott-B07421
Sent: Saturday, October 19, 2013 3:22 AM
To: Wang Dongsheng-B40534
Cc: Bhushan Bharat-R65777; Wood Scott-B07421; linuxppc-
d...@lists.ozlabs.org
Subject: Re: [PATCH v5 4/4] powerpc/85xx: add sysfs for pw20 state
and altivec idle
   
On Thu, 2013-10-17 at 22:02 -0500, Wang Dongsheng-B40534 wrote:

  -Original Message-
  From: Bhushan Bharat-R65777
  Sent: Thursday, October 17, 2013 2:46 PM
  To: Wang Dongsheng-B40534; Wood Scott-B07421
  Cc: linuxppc-dev@lists.ozlabs.org
  Subject: RE: [PATCH v5 4/4] powerpc/85xx: add sysfs for pw20
  state and altivec idle
 
 
 
 -Original Message-
 From: Wang Dongsheng-B40534
 Sent: Thursday, October 17, 2013 11:22 AM
 To: Bhushan Bharat-R65777; Wood Scott-B07421
 Cc: linuxppc-dev@lists.ozlabs.org
 Subject: RE: [PATCH v5 4/4] powerpc/85xx: add sysfs for
 pw20 state and altivec idle



  -Original Message-
  From: Bhushan Bharat-R65777
  Sent: Thursday, October 17, 2013 11:20 AM
  To: Wang Dongsheng-B40534; Wood Scott-B07421
  Cc: linuxppc-dev@lists.ozlabs.org
  Subject: RE: [PATCH v5 4/4] powerpc/85xx: add sysfs
  for
  pw20 state and altivec idle
 
 
 
   -Original Message-
   From: Wang Dongsheng-B40534
   Sent: Thursday, October 17, 2013 8:16 AM
   To: Bhushan Bharat-R65777; Wood Scott-B07421
   Cc: linuxppc-dev@lists.ozlabs.org
   Subject: RE: [PATCH v5 4/4] powerpc/85xx: add sysfs
   for
   pw20 state and altivec idle
  
  
  
-Original Message-
From: Bhushan Bharat-R65777
Sent: Thursday, October 17, 2013 1:01 AM
To: Wang Dongsheng-B40534; Wood Scott-B07421
Cc: linuxppc-dev@lists.ozlabs.org
Subject: RE: [PATCH v5 4/4] powerpc/85xx: add
sysfs for
pw20 state and altivec idle
   
   
   
 -Original Message-
 From: Wang Dongsheng-B40534
 Sent: Tuesday, October 15, 2013 2:51 PM
 To: Wood Scott-B07421
 Cc: Bhushan Bharat-R65777;
 linuxppc-dev@lists.ozlabs.org; Wang
Dongsheng-B40534
 Subject: [PATCH v5 4/4] powerpc/85xx: add sysfs
 for
 pw20 state and
altivec idle

 From: Wang Dongsheng
 dongsheng.w...@freescale.com

 Add a sys interface to enable/diable pw20 state
 or altivec idle, and
control the
 wait entry time.

 Enable/Disable interface:
 0, disable. 1, enable.
 /sys/devices/system/cpu/cpuX/pw20_state
 /sys/devices/system/cpu/cpuX/altivec_idle

 Set wait time interface:(Nanosecond)
 /sys/devices/system/cpu/cpuX/pw20_wait_time
 /sys/devices/system/cpu/cpuX/altivec_idle_wait_t
 ime
 Example: Base on TBfreq is 41MHZ.
 1~48(ns): TB[63]
 49~97(ns): TB[62]
 98~195(ns): TB[61]
 196~390(ns): TB[60]
 391~780(ns): TB[59]
 781~1560(ns): TB[58] ...

 Signed-off-by: Wang Dongsheng
 dongsheng.w...@freescale.com
 ---
 *v5:
 Change get_idle_ticks_bit function implementation.

 *v4:
 Move code from 85xx/common.c to kernel/sysfs.c.

 Remove has_pw20_altivec_idle function.

 Change wait entry_bit to wait time.

 diff --git a/arch/powerpc/kernel/sysfs.c
 b/arch/powerpc/kernel/sysfs.c
index
 27a90b9..10d1128 100644
 --- a/arch/powerpc/kernel/sysfs.c
 +++ b/arch/powerpc/kernel/sysfs.c
 @@ -85,6 +85,284 @@ __setup(smt-snooze-delay=,
setup_smt_snooze_delay);

  #endif /* CONFIG_PPC64 */

 

RE: [PATCH v5 4/4] powerpc/85xx: add sysfs for pw20 state and altivec idle

[Dongsheng Wang]

 -Original Message-
 From: Wang Dongsheng-B40534
 Sent: Monday, October 21, 2013 11:11 AM
 To: Wood Scott-B07421
 Cc: Bhushan Bharat-R65777; linuxppc-dev@lists.ozlabs.org
 Subject: RE: [PATCH v5 4/4] powerpc/85xx: add sysfs for pw20 state and
 altivec idle
 
 
 
  -Original Message-
  From: Wood Scott-B07421
  Sent: Saturday, October 19, 2013 3:22 AM
  To: Wang Dongsheng-B40534
  Cc: Bhushan Bharat-R65777; Wood Scott-B07421; linuxppc-
  d...@lists.ozlabs.org
  Subject: Re: [PATCH v5 4/4] powerpc/85xx: add sysfs for pw20 state and
  altivec idle
 
  On Thu, 2013-10-17 at 22:02 -0500, Wang Dongsheng-B40534 wrote:
  
-Original Message-
From: Bhushan Bharat-R65777
Sent: Thursday, October 17, 2013 2:46 PM
To: Wang Dongsheng-B40534; Wood Scott-B07421
Cc: linuxppc-dev@lists.ozlabs.org
Subject: RE: [PATCH v5 4/4] powerpc/85xx: add sysfs for pw20 state
and altivec idle
   
   
   
   -Original Message-
   From: Wang Dongsheng-B40534
   Sent: Thursday, October 17, 2013 11:22 AM
   To: Bhushan Bharat-R65777; Wood Scott-B07421
   Cc: linuxppc-dev@lists.ozlabs.org
   Subject: RE: [PATCH v5 4/4] powerpc/85xx: add sysfs for pw20
   state and altivec idle
  
  
  
-Original Message-
From: Bhushan Bharat-R65777
Sent: Thursday, October 17, 2013 11:20 AM
To: Wang Dongsheng-B40534; Wood Scott-B07421
Cc: linuxppc-dev@lists.ozlabs.org
Subject: RE: [PATCH v5 4/4] powerpc/85xx: add sysfs for
pw20 state and altivec idle
   
   
   
 -Original Message-
 From: Wang Dongsheng-B40534
 Sent: Thursday, October 17, 2013 8:16 AM
 To: Bhushan Bharat-R65777; Wood Scott-B07421
 Cc: linuxppc-dev@lists.ozlabs.org
 Subject: RE: [PATCH v5 4/4] powerpc/85xx: add sysfs for
 pw20 state and altivec idle



  -Original Message-
  From: Bhushan Bharat-R65777
  Sent: Thursday, October 17, 2013 1:01 AM
  To: Wang Dongsheng-B40534; Wood Scott-B07421
  Cc: linuxppc-dev@lists.ozlabs.org
  Subject: RE: [PATCH v5 4/4] powerpc/85xx: add sysfs
  for
  pw20 state and altivec idle
 
 
 
   -Original Message-
   From: Wang Dongsheng-B40534
   Sent: Tuesday, October 15, 2013 2:51 PM
   To: Wood Scott-B07421
   Cc: Bhushan Bharat-R65777;
   linuxppc-dev@lists.ozlabs.org; Wang
  Dongsheng-B40534
   Subject: [PATCH v5 4/4] powerpc/85xx: add sysfs for
   pw20 state and
  altivec idle
  
   From: Wang Dongsheng dongsheng.w...@freescale.com
  
   Add a sys interface to enable/diable pw20 state or
   altivec idle, and
  control the
   wait entry time.
  
   Enable/Disable interface:
   0, disable. 1, enable.
   /sys/devices/system/cpu/cpuX/pw20_state
   /sys/devices/system/cpu/cpuX/altivec_idle
  
   Set wait time interface:(Nanosecond)
   /sys/devices/system/cpu/cpuX/pw20_wait_time
   /sys/devices/system/cpu/cpuX/altivec_idle_wait_time
   Example: Base on TBfreq is 41MHZ.
   1~48(ns): TB[63]
   49~97(ns): TB[62]
   98~195(ns): TB[61]
   196~390(ns): TB[60]
   391~780(ns): TB[59]
   781~1560(ns): TB[58] ...
  
   Signed-off-by: Wang Dongsheng
   dongsheng.w...@freescale.com
   ---
   *v5:
   Change get_idle_ticks_bit function implementation.
  
   *v4:
   Move code from 85xx/common.c to kernel/sysfs.c.
  
   Remove has_pw20_altivec_idle function.
  
   Change wait entry_bit to wait time.
  
   diff --git a/arch/powerpc/kernel/sysfs.c
   b/arch/powerpc/kernel/sysfs.c
  index
   27a90b9..10d1128 100644
   --- a/arch/powerpc/kernel/sysfs.c
   +++ b/arch/powerpc/kernel/sysfs.c
   @@ -85,6 +85,284 @@ __setup(smt-snooze-delay=,
  setup_smt_snooze_delay);
  
#endif /* CONFIG_PPC64 */
  
   +#ifdef CONFIG_FSL_SOC
   +#define MAX_BIT  63
   +
   +static u64 pw20_wt; static u64 altivec_idle_wt;
   +
   +static unsigned int get_idle_ticks_bit(u64 ns) {
   + u64 cycle;
   +
   + if (ns = 1)
   + cycle = div_u64(ns + 500, 1000) *
tb_ticks_per_usec;
   + else
   + cycle = div_u64(ns * tb_ticks_per_usec,
  1000);
   +
   + if (!cycle)
   + return 0;
   +
   + return ilog2(cycle); }
   +
   +static void do_show_pwrmgtcr0(void *val) {
   + u32 *value = 

[PATCH v5 1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 define

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

E6500 PVR and SPRN_PWRMGTCR0 will be used in subsequent pw20/altivec
idle patches.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
*v3:
Add bit definitions for PWRMGTCR0.

 arch/powerpc/include/asm/reg.h   | 2 ++
 arch/powerpc/include/asm/reg_booke.h | 9 +
 2 files changed, 11 insertions(+)

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 64264bf..d4160ca 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -1053,6 +1053,8 @@
 #define PVR_8560   0x8020
 #define PVR_VER_E500V1 0x8020
 #define PVR_VER_E500V2 0x8021
+#define PVR_VER_E6500  0x8040
+
 /*
  * For the 8xx processors, all of them report the same PVR family for
  * the PowerPC core. The various versions of these processors must be
diff --git a/arch/powerpc/include/asm/reg_booke.h 
b/arch/powerpc/include/asm/reg_booke.h
index ed8f836..4a6457e 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -170,6 +170,7 @@
 #define SPRN_L2CSR10x3FA   /* L2 Data Cache Control and Status Register 1 
*/
 #define SPRN_DCCR  0x3FA   /* Data Cache Cacheability Register */
 #define SPRN_ICCR  0x3FB   /* Instruction Cache Cacheability Register */
+#define SPRN_PWRMGTCR0 0x3FB   /* Power management control register 0 */
 #define SPRN_SVR   0x3FF   /* System Version Register */
 
 /*
@@ -216,6 +217,14 @@
 #defineCCR1_DPC0x0100 /* Disable L1 I-Cache/D-Cache parity 
checking */
 #defineCCR1_TCS0x0080 /* Timer Clock Select */
 
+/* Bit definitions for PWRMGTCR0. */
+#define PWRMGTCR0_PW20_WAIT(1  14) /* PW20 state enable bit */
+#define PWRMGTCR0_PW20_ENT_SHIFT   8
+#define PWRMGTCR0_PW20_ENT 0x3F00
+#define PWRMGTCR0_AV_IDLE_PD_EN(1  22) /* Altivec idle 
enable */
+#define PWRMGTCR0_AV_IDLE_CNT_SHIFT16
+#define PWRMGTCR0_AV_IDLE_CNT  0x3F
+
 /* Bit definitions for the MCSR. */
 #define MCSR_MCS   0x8000 /* Machine Check Summary */
 #define MCSR_IB0x4000 /* Instruction PLB Error */
-- 
1.8.0


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[PATCH v5 2/4] powerpc/85xx: add hardware automatically enter altivec idle state

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

Each core's AltiVec unit may be placed into a power savings mode
by turning off power to the unit. Core hardware will automatically
power down the AltiVec unit after no AltiVec instructions have
executed in N cycles. The AltiVec power-control is triggered by hardware.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
*v3:
Assembly code instead of C code.

*v2:
Remove:
delete setup_idle_hw_governor function.
delete Fix erratum for rev1.

Move:
move setup_* into __setup/restore_cpu_e6500.

 arch/powerpc/kernel/cpu_setup_fsl_booke.S | 21 +
 1 file changed, 21 insertions(+)

diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S 
b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index bfb18c7..4789056 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -53,11 +53,31 @@ _GLOBAL(__e500_dcache_setup)
isync
blr
 
+/*
+ * FIXME - we haven't yet done testing to determine a reasonable default
+ * value for AV_WAIT_IDLE_BIT.
+ */
+#define AV_WAIT_IDLE_BIT   50 /* 1ms, TB frequency is 41.66MHZ */
+_GLOBAL(setup_altivec_idle)
+   mfspr   r3, SPRN_PWRMGTCR0
+
+   /* Enable Altivec Idle */
+   orisr3, r3, PWRMGTCR0_AV_IDLE_PD_EN@h
+   li  r11, AV_WAIT_IDLE_BIT
+
+   /* Set Automatic AltiVec Idle Count */
+   rlwimi  r3, r11, PWRMGTCR0_AV_IDLE_CNT_SHIFT, PWRMGTCR0_AV_IDLE_CNT
+
+   mtspr   SPRN_PWRMGTCR0, r3
+
+   blr
+
 _GLOBAL(__setup_cpu_e6500)
mflrr6
 #ifdef CONFIG_PPC64
bl  .setup_altivec_ivors
 #endif
+   bl  setup_altivec_idle
bl  __setup_cpu_e5500
mtlrr6
blr
@@ -119,6 +139,7 @@ _GLOBAL(__setup_cpu_e5500)
 _GLOBAL(__restore_cpu_e6500)
mflrr5
bl  .setup_altivec_ivors
+   bl  .setup_altivec_idle
bl  __restore_cpu_e5500
mtlrr5
blr
-- 
1.8.0


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[PATCH v5 3/4] powerpc/85xx: add hardware automatically enter pw20 state

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

Using hardware features make core automatically enter PW20 state.
Set a TB count to hardware, the effective count begins when PW10
is entered. When the effective period has expired, the core will
proceed from PW10 to PW20 if no exit conditions have occurred during
the period.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
*v3:
Assembly code instead of C code.

*v2:
Remove:
delete setup_idle_hw_governor function.
delete Fix erratum for rev1.

Move:
move setup_* into __setup/restore_cpu_e6500.

 arch/powerpc/kernel/cpu_setup_fsl_booke.S | 21 +
 1 file changed, 21 insertions(+)

diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S 
b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index 4789056..49e738e 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -55,6 +55,25 @@ _GLOBAL(__e500_dcache_setup)
 
 /*
  * FIXME - we haven't yet done testing to determine a reasonable default
+ * value for PW20_WAIT_IDLE_BIT.
+ */
+#define PW20_WAIT_IDLE_BIT 50 /* 1ms, TB frequency is 41.66MHZ */
+_GLOBAL(setup_pw20_idle)
+   mfspr   r3, SPRN_PWRMGTCR0
+
+   /* Set PW20_WAIT bit, enable pw20 state*/
+   ori r3, r3, PWRMGTCR0_PW20_WAIT
+   li  r11, PW20_WAIT_IDLE_BIT
+
+   /* Set Automatic PW20 Core Idle Count */
+   rlwimi  r3, r11, PWRMGTCR0_PW20_ENT_SHIFT, PWRMGTCR0_PW20_ENT
+
+   mtspr   SPRN_PWRMGTCR0, r3
+
+   blr
+
+/*
+ * FIXME - we haven't yet done testing to determine a reasonable default
  * value for AV_WAIT_IDLE_BIT.
  */
 #define AV_WAIT_IDLE_BIT   50 /* 1ms, TB frequency is 41.66MHZ */
@@ -77,6 +96,7 @@ _GLOBAL(__setup_cpu_e6500)
 #ifdef CONFIG_PPC64
bl  .setup_altivec_ivors
 #endif
+   bl  setup_pw20_idle
bl  setup_altivec_idle
bl  __setup_cpu_e5500
mtlrr6
@@ -139,6 +159,7 @@ _GLOBAL(__setup_cpu_e5500)
 _GLOBAL(__restore_cpu_e6500)
mflrr5
bl  .setup_altivec_ivors
+   bl  .setup_pw20_idle
bl  .setup_altivec_idle
bl  __restore_cpu_e5500
mtlrr5
-- 
1.8.0


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[PATCH v5 4/4] powerpc/85xx: add sysfs for pw20 state and altivec idle

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

Add a sys interface to enable/diable pw20 state or altivec idle, and
control the wait entry time.

Enable/Disable interface:
0, disable. 1, enable.
/sys/devices/system/cpu/cpuX/pw20_state
/sys/devices/system/cpu/cpuX/altivec_idle

Set wait time interface:(Nanosecond)
/sys/devices/system/cpu/cpuX/pw20_wait_time
/sys/devices/system/cpu/cpuX/altivec_idle_wait_time
Example: Base on TBfreq is 41MHZ.
1~48(ns): TB[63]
49~97(ns): TB[62]
98~195(ns): TB[61]
196~390(ns): TB[60]
391~780(ns): TB[59]
781~1560(ns): TB[58]
...

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
*v5:
Change get_idle_ticks_bit function implementation.

*v4:
Move code from 85xx/common.c to kernel/sysfs.c.

Remove has_pw20_altivec_idle function.

Change wait entry_bit to wait time.

diff --git a/arch/powerpc/kernel/sysfs.c b/arch/powerpc/kernel/sysfs.c
index 27a90b9..10d1128 100644
--- a/arch/powerpc/kernel/sysfs.c
+++ b/arch/powerpc/kernel/sysfs.c
@@ -85,6 +85,284 @@ __setup(smt-snooze-delay=, setup_smt_snooze_delay);
 
 #endif /* CONFIG_PPC64 */
 
+#ifdef CONFIG_FSL_SOC
+#define MAX_BIT63
+
+static u64 pw20_wt;
+static u64 altivec_idle_wt;
+
+static unsigned int get_idle_ticks_bit(u64 ns)
+{
+   u64 cycle;
+
+   if (ns = 1)
+   cycle = div_u64(ns + 500, 1000) * tb_ticks_per_usec;
+   else
+   cycle = div_u64(ns * tb_ticks_per_usec, 1000);
+
+   if (!cycle)
+   return 0;
+
+   return ilog2(cycle);
+}
+
+static void do_show_pwrmgtcr0(void *val)
+{
+   u32 *value = val;
+
+   *value = mfspr(SPRN_PWRMGTCR0);
+}
+
+static ssize_t show_pw20_state(struct device *dev,
+   struct device_attribute *attr, char *buf)
+{
+   u32 value;
+   unsigned int cpu = dev-id;
+
+   smp_call_function_single(cpu, do_show_pwrmgtcr0, value, 1);
+
+   value = PWRMGTCR0_PW20_WAIT;
+
+   return sprintf(buf, %u\n, value ? 1 : 0);
+}
+
+static void do_store_pw20_state(void *val)
+{
+   u32 *value = val;
+   u32 pw20_state;
+
+   pw20_state = mfspr(SPRN_PWRMGTCR0);
+
+   if (*value)
+   pw20_state |= PWRMGTCR0_PW20_WAIT;
+   else
+   pw20_state = ~PWRMGTCR0_PW20_WAIT;
+
+   mtspr(SPRN_PWRMGTCR0, pw20_state);
+}
+
+static ssize_t store_pw20_state(struct device *dev,
+   struct device_attribute *attr,
+   const char *buf, size_t count)
+{
+   u32 value;
+   unsigned int cpu = dev-id;
+
+   if (kstrtou32(buf, 0, value))
+   return -EINVAL;
+
+   if (value  1)
+   return -EINVAL;
+
+   smp_call_function_single(cpu, do_store_pw20_state, value, 1);
+
+   return count;
+}
+
+static ssize_t show_pw20_wait_time(struct device *dev,
+   struct device_attribute *attr, char *buf)
+{
+   u32 value;
+   u64 tb_cycle;
+   s64 time;
+
+   unsigned int cpu = dev-id;
+
+   if (!pw20_wt) {
+   smp_call_function_single(cpu, do_show_pwrmgtcr0, value, 1);
+   value = (value  PWRMGTCR0_PW20_ENT) 
+   PWRMGTCR0_PW20_ENT_SHIFT;
+
+   tb_cycle = (1  (MAX_BIT - value)) * 2;
+   time = div_u64(tb_cycle * 1000, tb_ticks_per_usec) - 1;
+   } else {
+   time = pw20_wt;
+   }
+
+   return sprintf(buf, %llu\n, time  0 ? time : 0);
+}
+
+static void set_pw20_wait_entry_bit(void *val)
+{
+   u32 *value = val;
+   u32 pw20_idle;
+
+   pw20_idle = mfspr(SPRN_PWRMGTCR0);
+
+   /* Set Automatic PW20 Core Idle Count */
+   /* clear count */
+   pw20_idle = ~PWRMGTCR0_PW20_ENT;
+
+   /* set count */
+   pw20_idle |= ((MAX_BIT - *value)  PWRMGTCR0_PW20_ENT_SHIFT);
+
+   mtspr(SPRN_PWRMGTCR0, pw20_idle);
+}
+
+static ssize_t store_pw20_wait_time(struct device *dev,
+   struct device_attribute *attr,
+   const char *buf, size_t count)
+{
+   u32 entry_bit;
+   u64 value;
+
+   unsigned int cpu = dev-id;
+
+   if (kstrtou64(buf, 0, value))
+   return -EINVAL;
+
+   if (!value)
+   return -EINVAL;
+
+   entry_bit = get_idle_ticks_bit(value);
+   if (entry_bit  MAX_BIT)
+   return -EINVAL;
+
+   pw20_wt = value;
+   smp_call_function_single(cpu, set_pw20_wait_entry_bit,
+   entry_bit, 1);
+
+   return count;
+}
+
+static ssize_t show_altivec_idle(struct device *dev,
+   struct device_attribute *attr, char *buf)
+{
+   u32 value;
+   unsigned int cpu = dev-id;
+
+   smp_call_function_single(cpu, do_show_pwrmgtcr0, value, 1);
+
+   value = PWRMGTCR0_AV_IDLE_PD_EN;
+
+   return sprintf(buf, %u\n, value ? 1 : 0);
+}
+
+static void do_store_altivec_idle(void *val)
+{
+   

[PATCH v4 1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 define

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

E6500 PVR and SPRN_PWRMGTCR0 will be used in subsequent pw20/altivec
idle patches.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
*v3:
Add bit definitions for PWRMGTCR0.

 arch/powerpc/include/asm/reg.h   | 2 ++
 arch/powerpc/include/asm/reg_booke.h | 9 +
 2 files changed, 11 insertions(+)

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 64264bf..d4160ca 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -1053,6 +1053,8 @@
 #define PVR_8560   0x8020
 #define PVR_VER_E500V1 0x8020
 #define PVR_VER_E500V2 0x8021
+#define PVR_VER_E6500  0x8040
+
 /*
  * For the 8xx processors, all of them report the same PVR family for
  * the PowerPC core. The various versions of these processors must be
diff --git a/arch/powerpc/include/asm/reg_booke.h 
b/arch/powerpc/include/asm/reg_booke.h
index ed8f836..4a6457e 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -170,6 +170,7 @@
 #define SPRN_L2CSR10x3FA   /* L2 Data Cache Control and Status Register 1 
*/
 #define SPRN_DCCR  0x3FA   /* Data Cache Cacheability Register */
 #define SPRN_ICCR  0x3FB   /* Instruction Cache Cacheability Register */
+#define SPRN_PWRMGTCR0 0x3FB   /* Power management control register 0 */
 #define SPRN_SVR   0x3FF   /* System Version Register */
 
 /*
@@ -216,6 +217,14 @@
 #defineCCR1_DPC0x0100 /* Disable L1 I-Cache/D-Cache parity 
checking */
 #defineCCR1_TCS0x0080 /* Timer Clock Select */
 
+/* Bit definitions for PWRMGTCR0. */
+#define PWRMGTCR0_PW20_WAIT(1  14) /* PW20 state enable bit */
+#define PWRMGTCR0_PW20_ENT_SHIFT   8
+#define PWRMGTCR0_PW20_ENT 0x3F00
+#define PWRMGTCR0_AV_IDLE_PD_EN(1  22) /* Altivec idle 
enable */
+#define PWRMGTCR0_AV_IDLE_CNT_SHIFT16
+#define PWRMGTCR0_AV_IDLE_CNT  0x3F
+
 /* Bit definitions for the MCSR. */
 #define MCSR_MCS   0x8000 /* Machine Check Summary */
 #define MCSR_IB0x4000 /* Instruction PLB Error */
-- 
1.8.0


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[PATCH v4 2/4] powerpc/85xx: add hardware automatically enter altivec idle state

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

Each core's AltiVec unit may be placed into a power savings mode
by turning off power to the unit. Core hardware will automatically
power down the AltiVec unit after no AltiVec instructions have
executed in N cycles. The AltiVec power-control is triggered by hardware.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
*v3:
Assembly code instead of C code.

*v2:
Remove:
delete setup_idle_hw_governor function.
delete Fix erratum for rev1.

Move:
move setup_* into __setup/restore_cpu_e6500.

 arch/powerpc/kernel/cpu_setup_fsl_booke.S | 21 +
 1 file changed, 21 insertions(+)

diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S 
b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index bfb18c7..4789056 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -53,11 +53,31 @@ _GLOBAL(__e500_dcache_setup)
isync
blr
 
+/*
+ * FIXME - we haven't yet done testing to determine a reasonable default
+ * value for AV_WAIT_IDLE_BIT.
+ */
+#define AV_WAIT_IDLE_BIT   50 /* 1ms, TB frequency is 41.66MHZ */
+_GLOBAL(setup_altivec_idle)
+   mfspr   r3, SPRN_PWRMGTCR0
+
+   /* Enable Altivec Idle */
+   orisr3, r3, PWRMGTCR0_AV_IDLE_PD_EN@h
+   li  r11, AV_WAIT_IDLE_BIT
+
+   /* Set Automatic AltiVec Idle Count */
+   rlwimi  r3, r11, PWRMGTCR0_AV_IDLE_CNT_SHIFT, PWRMGTCR0_AV_IDLE_CNT
+
+   mtspr   SPRN_PWRMGTCR0, r3
+
+   blr
+
 _GLOBAL(__setup_cpu_e6500)
mflrr6
 #ifdef CONFIG_PPC64
bl  .setup_altivec_ivors
 #endif
+   bl  setup_altivec_idle
bl  __setup_cpu_e5500
mtlrr6
blr
@@ -119,6 +139,7 @@ _GLOBAL(__setup_cpu_e5500)
 _GLOBAL(__restore_cpu_e6500)
mflrr5
bl  .setup_altivec_ivors
+   bl  .setup_altivec_idle
bl  __restore_cpu_e5500
mtlrr5
blr
-- 
1.8.0


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[PATCH v4 3/4] powerpc/85xx: add hardware automatically enter pw20 state

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

Using hardware features make core automatically enter PW20 state.
Set a TB count to hardware, the effective count begins when PW10
is entered. When the effective period has expired, the core will
proceed from PW10 to PW20 if no exit conditions have occurred during
the period.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
*v3:
Assembly code instead of C code.

*v2:
Remove:
delete setup_idle_hw_governor function.
delete Fix erratum for rev1.

Move:
move setup_* into __setup/restore_cpu_e6500.

 arch/powerpc/kernel/cpu_setup_fsl_booke.S | 21 +
 1 file changed, 21 insertions(+)

diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S 
b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index 4789056..49e738e 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -55,6 +55,25 @@ _GLOBAL(__e500_dcache_setup)
 
 /*
  * FIXME - we haven't yet done testing to determine a reasonable default
+ * value for PW20_WAIT_IDLE_BIT.
+ */
+#define PW20_WAIT_IDLE_BIT 50 /* 1ms, TB frequency is 41.66MHZ */
+_GLOBAL(setup_pw20_idle)
+   mfspr   r3, SPRN_PWRMGTCR0
+
+   /* Set PW20_WAIT bit, enable pw20 state*/
+   ori r3, r3, PWRMGTCR0_PW20_WAIT
+   li  r11, PW20_WAIT_IDLE_BIT
+
+   /* Set Automatic PW20 Core Idle Count */
+   rlwimi  r3, r11, PWRMGTCR0_PW20_ENT_SHIFT, PWRMGTCR0_PW20_ENT
+
+   mtspr   SPRN_PWRMGTCR0, r3
+
+   blr
+
+/*
+ * FIXME - we haven't yet done testing to determine a reasonable default
  * value for AV_WAIT_IDLE_BIT.
  */
 #define AV_WAIT_IDLE_BIT   50 /* 1ms, TB frequency is 41.66MHZ */
@@ -77,6 +96,7 @@ _GLOBAL(__setup_cpu_e6500)
 #ifdef CONFIG_PPC64
bl  .setup_altivec_ivors
 #endif
+   bl  setup_pw20_idle
bl  setup_altivec_idle
bl  __setup_cpu_e5500
mtlrr6
@@ -139,6 +159,7 @@ _GLOBAL(__setup_cpu_e5500)
 _GLOBAL(__restore_cpu_e6500)
mflrr5
bl  .setup_altivec_ivors
+   bl  .setup_pw20_idle
bl  .setup_altivec_idle
bl  __restore_cpu_e5500
mtlrr5
-- 
1.8.0


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[PATCH v4 4/4] powerpc/85xx: add sysfs for pw20 state and altivec idle

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

Add a sys interface to enable/diable pw20 state or altivec idle, and
control the wait entry time.

Enable/Disable interface:
0, disable. 1, enable.
/sys/devices/system/cpu/cpuX/pw20_state
/sys/devices/system/cpu/cpuX/altivec_idle

Set wait time interface:(Nanosecond)
/sys/devices/system/cpu/cpuX/pw20_wait_time
/sys/devices/system/cpu/cpuX/altivec_idle_wait_time
Example: Base on TBfreq is 41MHZ.
1~47(ns): TB[63]
48~95(ns): TB[62]
96~191(ns): TB[61]
192~383(ns): TB[62]
384~767(ns): TB[60]
...

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
*v4:
Move code from 85xx/common.c to kernel/sysfs.c.

Remove has_pw20_altivec_idle function.

Change wait entry_bit to wait time.

 arch/powerpc/kernel/sysfs.c | 291 
 1 file changed, 291 insertions(+)

diff --git a/arch/powerpc/kernel/sysfs.c b/arch/powerpc/kernel/sysfs.c
index 27a90b9..23fece6 100644
--- a/arch/powerpc/kernel/sysfs.c
+++ b/arch/powerpc/kernel/sysfs.c
@@ -85,6 +85,279 @@ __setup(smt-snooze-delay=, setup_smt_snooze_delay);
 
 #endif /* CONFIG_PPC64 */
 
+#ifdef CONFIG_FSL_SOC
+#define MAX_BIT63
+
+static u64 pw20_wt;
+static u64 altivec_idle_wt;
+
+static unsigned int get_idle_ticks_bit(u64 ns)
+{
+   u64 cycle;
+
+   cycle = div_u64(ns, 1000 / tb_ticks_per_usec);
+   if (!cycle)
+   return 0;
+
+   return ilog2(cycle);
+}
+
+static void do_show_pwrmgtcr0(void *val)
+{
+   u32 *value = val;
+
+   *value = mfspr(SPRN_PWRMGTCR0);
+}
+
+static ssize_t show_pw20_state(struct device *dev,
+   struct device_attribute *attr, char *buf)
+{
+   u32 value;
+   unsigned int cpu = dev-id;
+
+   smp_call_function_single(cpu, do_show_pwrmgtcr0, value, 1);
+
+   value = PWRMGTCR0_PW20_WAIT;
+
+   return sprintf(buf, %u\n, value ? 1 : 0);
+}
+
+static void do_store_pw20_state(void *val)
+{
+   u32 *value = val;
+   u32 pw20_state;
+
+   pw20_state = mfspr(SPRN_PWRMGTCR0);
+
+   if (*value)
+   pw20_state |= PWRMGTCR0_PW20_WAIT;
+   else
+   pw20_state = ~PWRMGTCR0_PW20_WAIT;
+
+   mtspr(SPRN_PWRMGTCR0, pw20_state);
+}
+
+static ssize_t store_pw20_state(struct device *dev,
+   struct device_attribute *attr,
+   const char *buf, size_t count)
+{
+   u32 value;
+   unsigned int cpu = dev-id;
+
+   if (kstrtou32(buf, 0, value))
+   return -EINVAL;
+
+   if (value  1)
+   return -EINVAL;
+
+   smp_call_function_single(cpu, do_store_pw20_state, value, 1);
+
+   return count;
+}
+
+static ssize_t show_pw20_wait_time(struct device *dev,
+   struct device_attribute *attr, char *buf)
+{
+   u32 value;
+   u64 tb_cycle;
+   u64 time;
+
+   unsigned int cpu = dev-id;
+
+   if (!pw20_wt) {
+   smp_call_function_single(cpu, do_show_pwrmgtcr0, value, 1);
+   value = (value  PWRMGTCR0_PW20_ENT) 
+   PWRMGTCR0_PW20_ENT_SHIFT;
+
+   tb_cycle = (1  (MAX_BIT - value)) * 2;
+   time = tb_cycle * (1000 / tb_ticks_per_usec) - 1;
+   } else {
+   time = pw20_wt;
+   }
+
+   return sprintf(buf, %llu\n, time);
+}
+
+static void set_pw20_wait_entry_bit(void *val)
+{
+   u32 *value = val;
+   u32 pw20_idle;
+
+   pw20_idle = mfspr(SPRN_PWRMGTCR0);
+
+   /* Set Automatic PW20 Core Idle Count */
+   /* clear count */
+   pw20_idle = ~PWRMGTCR0_PW20_ENT;
+
+   /* set count */
+   pw20_idle |= ((MAX_BIT - *value)  PWRMGTCR0_PW20_ENT_SHIFT);
+
+   mtspr(SPRN_PWRMGTCR0, pw20_idle);
+}
+
+static ssize_t store_pw20_wait_time(struct device *dev,
+   struct device_attribute *attr,
+   const char *buf, size_t count)
+{
+   u32 entry_bit;
+   u64 value;
+
+   unsigned int cpu = dev-id;
+
+   if (kstrtou64(buf, 0, value))
+   return -EINVAL;
+
+   if (!value)
+   return -EINVAL;
+
+   entry_bit = get_idle_ticks_bit(value);
+   if (entry_bit  MAX_BIT)
+   return -EINVAL;
+
+   pw20_wt = value;
+   smp_call_function_single(cpu, set_pw20_wait_entry_bit,
+   entry_bit, 1);
+
+   return count;
+}
+
+static ssize_t show_altivec_idle(struct device *dev,
+   struct device_attribute *attr, char *buf)
+{
+   u32 value;
+   unsigned int cpu = dev-id;
+
+   smp_call_function_single(cpu, do_show_pwrmgtcr0, value, 1);
+
+   value = PWRMGTCR0_AV_IDLE_PD_EN;
+
+   return sprintf(buf, %u\n, value ? 1 : 0);
+}
+
+static void do_store_altivec_idle(void *val)
+{
+   u32 *value = val;
+   u32 altivec_idle;
+
+   altivec_idle = mfspr(SPRN_PWRMGTCR0);
+
+   if (*value)

[PATCH v3 2/4] powerpc/85xx: add hardware automatically enter altivec idle state

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

Each core's AltiVec unit may be placed into a power savings mode
by turning off power to the unit. Core hardware will automatically
power down the AltiVec unit after no AltiVec instructions have
executed in N cycles. The AltiVec power-control is triggered by hardware.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
*v3:
Assembly code instead of C code.

*v2:
Remove:
delete setup_idle_hw_governor function.
delete Fix erratum for rev1.

Move:
move setup_* into __setup/restore_cpu_e6500.

 arch/powerpc/kernel/cpu_setup_fsl_booke.S | 20 
 1 file changed, 20 insertions(+)

diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S 
b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index bfb18c7..3c03c109 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -53,11 +53,30 @@ _GLOBAL(__e500_dcache_setup)
isync
blr

+/*
+ * FIXME - We don't know the AltiVec application scenarios.
+ */
+#define AV_WAIT_IDLE_BIT   50 /* 1ms, TB frequency is 41.66MHZ */
+_GLOBAL(setup_altivec_idle)
+   mfspr   r3, SPRN_PWRMGTCR0
+
+   /* Enable Altivec Idle */
+   orisr3, r3, PWRMGTCR0_AV_IDLE_PD_EN@h
+   li  r4, AV_WAIT_IDLE_BIT
+
+   /* Set Automatic AltiVec Idle Count */
+   rlwimi  r3, r4, PWRMGTCR0_AV_IDLE_CNT_SHIFT, PWRMGTCR0_AV_IDLE_CNT
+
+   mtspr   SPRN_PWRMGTCR0, r3
+
+   blr
+
 _GLOBAL(__setup_cpu_e6500)
mflrr6
 #ifdef CONFIG_PPC64
bl  .setup_altivec_ivors
 #endif
+   bl  .setup_altivec_idle
bl  __setup_cpu_e5500
mtlrr6
blr
@@ -119,6 +138,7 @@ _GLOBAL(__setup_cpu_e5500)
 _GLOBAL(__restore_cpu_e6500)
mflrr5
bl  .setup_altivec_ivors
+   bl  .setup_altivec_idle
bl  __restore_cpu_e5500
mtlrr5
blr
--
1.8.0


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[PATCH v3 1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 define

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

E6500 PVR and SPRN_PWRMGTCR0 will be used in subsequent pw20/altivec
idle patches.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
*v3:
Add bit definitions for PWRMGTCR0.

 arch/powerpc/include/asm/reg.h   | 2 ++
 arch/powerpc/include/asm/reg_booke.h | 9 +
 2 files changed, 11 insertions(+)

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 64264bf..d4160ca 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -1053,6 +1053,8 @@
 #define PVR_8560   0x8020
 #define PVR_VER_E500V1 0x8020
 #define PVR_VER_E500V2 0x8021
+#define PVR_VER_E6500  0x8040
+
 /*
  * For the 8xx processors, all of them report the same PVR family for
  * the PowerPC core. The various versions of these processors must be
diff --git a/arch/powerpc/include/asm/reg_booke.h 
b/arch/powerpc/include/asm/reg_booke.h
index ed8f836..4a6457e 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -170,6 +170,7 @@
 #define SPRN_L2CSR10x3FA   /* L2 Data Cache Control and Status Register 1 
*/
 #define SPRN_DCCR  0x3FA   /* Data Cache Cacheability Register */
 #define SPRN_ICCR  0x3FB   /* Instruction Cache Cacheability Register */
+#define SPRN_PWRMGTCR0 0x3FB   /* Power management control register 0 */
 #define SPRN_SVR   0x3FF   /* System Version Register */

 /*
@@ -216,6 +217,14 @@
 #defineCCR1_DPC0x0100 /* Disable L1 I-Cache/D-Cache parity 
checking */
 #defineCCR1_TCS0x0080 /* Timer Clock Select */

+/* Bit definitions for PWRMGTCR0. */
+#define PWRMGTCR0_PW20_WAIT(1  14) /* PW20 state enable bit */
+#define PWRMGTCR0_PW20_ENT_SHIFT   8
+#define PWRMGTCR0_PW20_ENT 0x3F00
+#define PWRMGTCR0_AV_IDLE_PD_EN(1  22) /* Altivec idle 
enable */
+#define PWRMGTCR0_AV_IDLE_CNT_SHIFT16
+#define PWRMGTCR0_AV_IDLE_CNT  0x3F
+
 /* Bit definitions for the MCSR. */
 #define MCSR_MCS   0x8000 /* Machine Check Summary */
 #define MCSR_IB0x4000 /* Instruction PLB Error */
--
1.8.0


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[PATCH v3 4/4] powerpc/85xx: add sysfs for pw20 state and altivec idle

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

Add a sys interface to enable/diable pw20 state or altivec idle, and
control the wait entry time.

Enable/Disable interface:
0, disable. 1, enable.
/sys/devices/system/cpu/cpuX/pw20_state
/sys/devices/system/cpu/cpuX/altivec_idle

Set wait entry bit interface:
bit value range 0~63, 0 bit is Mintime, 63 bit is Maxtime.
/sys/devices/system/cpu/cpuX/pw20_wait_entry_bit
/sys/devices/system/cpu/cpuX/altivec_idle_wait_entry_bit

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S 
b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index 7389d49..7395d79 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -53,6 +53,21 @@ _GLOBAL(__e500_dcache_setup)
isync
blr

+_GLOBAL(has_pw20_altivec_idle)
+   /* 0 false, 1 true */
+   li  r3, 0
+
+   /* PW20  AltiVec idle feature only exists for E6500 */
+   mfspr   r0, SPRN_PVR
+   rlwinm  r4, r0, 16, 16, 31
+   lis r12, 0
+   ori r12, r12, PVR_VER_E6500@l
+   cmpwr4, r12
+   bne 2f
+   li  r3, 1
+2:
+   blr
+
 /*
  * FIXME - We don't know, what time should we let the core into PW20 state.
  * because we don't know the current state of the cpu load. And threads are
diff --git a/arch/powerpc/platforms/85xx/common.c 
b/arch/powerpc/platforms/85xx/common.c
index d0861a0..fe4d3a7 100644
--- a/arch/powerpc/platforms/85xx/common.c
+++ b/arch/powerpc/platforms/85xx/common.c
@@ -5,12 +5,16 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+
+#include linux/cpu.h
 #include linux/of_platform.h

 #include sysdev/cpm2_pic.h

 #include mpc85xx.h

+#define MAX_BIT63
+
 static struct of_device_id __initdata mpc85xx_common_ids[] = {
{ .type = soc, },
{ .compatible = soc, },
@@ -80,3 +84,234 @@ void __init mpc85xx_cpm2_pic_init(void)
irq_set_chained_handler(irq, cpm2_cascade);
 }
 #endif
+
+static void query_pwrmgtcr0(void *val)
+{
+   u32 *value = val;
+
+   *value = mfspr(SPRN_PWRMGTCR0);
+}
+
+static ssize_t show_pw20_state(struct device *dev,
+   struct device_attribute *attr, char *buf)
+{
+   u32 value;
+   unsigned int cpu = dev-id;
+
+   smp_call_function_single(cpu, query_pwrmgtcr0, value, 1);
+
+   value = PWRMGTCR0_PW20_WAIT;
+
+   return sprintf(buf, %u\n, value ? 1 : 0);
+}
+
+static void control_pw20_state(void *val)
+{
+   u32 *value = val;
+   u32 pw20_state;
+
+   pw20_state = mfspr(SPRN_PWRMGTCR0);
+
+   if (*value)
+   pw20_state |= PWRMGTCR0_PW20_WAIT;
+   else
+   pw20_state = ~PWRMGTCR0_PW20_WAIT;
+
+   mtspr(SPRN_PWRMGTCR0, pw20_state);
+}
+
+static ssize_t store_pw20_state(struct device *dev,
+   struct device_attribute *attr,
+   const char *buf, size_t count)
+{
+   u32 value;
+   unsigned int cpu = dev-id;
+
+   if (kstrtou32(buf, 0, value))
+   return -EINVAL;
+
+   if (value  1)
+   return -EINVAL;
+
+   smp_call_function_single(cpu, control_pw20_state, value, 1);
+
+   return count;
+}
+
+static ssize_t show_pw20_wait_entry_bit(struct device *dev,
+   struct device_attribute *attr, char *buf)
+{
+   u32 value;
+   unsigned int cpu = dev-id;
+
+   smp_call_function_single(cpu, query_pwrmgtcr0, value, 1);
+
+   value = MAX_BIT - ((value  PWRMGTCR0_PW20_ENT) 
+   PWRMGTCR0_PW20_ENT_SHIFT);
+
+   return sprintf(buf, wait entry bit is %u\n, value);
+}
+
+static void set_pw20_wait_entry_bit(void *val)
+{
+   u32 *value = val;
+   u32 pw20_idle;
+
+   pw20_idle = mfspr(SPRN_PWRMGTCR0);
+
+   /* Set Automatic PW20 Core Idle Count */
+   /* clear count */
+   pw20_idle = ~PWRMGTCR0_PW20_ENT;
+
+   /* set count */
+   pw20_idle |= ((MAX_BIT - *value)  PWRMGTCR0_PW20_ENT_SHIFT);
+
+   mtspr(SPRN_PWRMGTCR0, pw20_idle);
+}
+
+static ssize_t store_pw20_wait_entry_bit(struct device *dev,
+   struct device_attribute *attr,
+   const char *buf, size_t count)
+{
+   u32 value;
+   unsigned int cpu = dev-id;
+
+   if (kstrtou32(buf, 0, value))
+   return -EINVAL;
+
+   if (value  MAX_BIT)
+   return -EINVAL;
+
+   smp_call_function_single(cpu, set_pw20_wait_entry_bit,
+   value, 1);
+
+   return count;
+}
+
+static ssize_t show_altivec_idle(struct device *dev,
+   struct device_attribute *attr, char *buf)
+{
+   u32 value;
+   unsigned int cpu = dev-id;
+
+   smp_call_function_single(cpu, query_pwrmgtcr0, value, 1);
+
+   value = 

[PATCH v3 3/4] powerpc/85xx: add hardware automatically enter pw20 state

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

Using hardware features make core automatically enter PW20 state.
Set a TB count to hardware, the effective count begins when PW10
is entered. When the effective period has expired, the core will
proceed from PW10 to PW20 if no exit conditions have occurred during
the period.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
*v3:
Assembly code instead of C code.

*v2:
Remove:
delete setup_idle_hw_governor function.
delete Fix erratum for rev1.

Move:
move setup_* into __setup/restore_cpu_e6500.

 arch/powerpc/kernel/cpu_setup_fsl_booke.S | 23 +++
 1 file changed, 23 insertions(+)

diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S 
b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index 3c03c109..7389d49 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -54,6 +54,27 @@ _GLOBAL(__e500_dcache_setup)
blr

 /*
+ * FIXME - We don't know, what time should we let the core into PW20 state.
+ * because we don't know the current state of the cpu load. And threads are
+ * independent, so we can not know the state of different thread has been
+ * idle.
+ */
+#define PW20_WAIT_IDLE_BIT 50 /* 1ms, TB frequency is 41.66MHZ */
+_GLOBAL(setup_pw20_idle)
+   mfspr   r3, SPRN_PWRMGTCR0
+
+   /* Set PW20_WAIT bit, enable pw20 state*/
+   ori r3, r3, PWRMGTCR0_PW20_WAIT
+   li  r4, PW20_WAIT_IDLE_BIT
+
+   /* Set Automatic PW20 Core Idle Count */
+   rlwimi  r3, r4, PWRMGTCR0_PW20_ENT_SHIFT, PWRMGTCR0_PW20_ENT
+
+   mtspr   SPRN_PWRMGTCR0, r3
+
+   blr
+
+/*
  * FIXME - We don't know the AltiVec application scenarios.
  */
 #define AV_WAIT_IDLE_BIT   50 /* 1ms, TB frequency is 41.66MHZ */
@@ -76,6 +97,7 @@ _GLOBAL(__setup_cpu_e6500)
 #ifdef CONFIG_PPC64
bl  .setup_altivec_ivors
 #endif
+   bl  .setup_pw20_idle
bl  .setup_altivec_idle
bl  __setup_cpu_e5500
mtlrr6
@@ -138,6 +160,7 @@ _GLOBAL(__setup_cpu_e5500)
 _GLOBAL(__restore_cpu_e6500)
mflrr5
bl  .setup_altivec_ivors
+   bl  .setup_pw20_idle
bl  .setup_altivec_idle
bl  __restore_cpu_e5500
mtlrr5
--
1.8.0


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[PATCH v2 1/3] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 define

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

E6500 PVR and SPRN_PWRMGTCR0 will be used in subsequent pw20/altivec idle 
patches.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 64264bf..d4160ca 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -1053,6 +1053,8 @@
 #define PVR_8560   0x8020
 #define PVR_VER_E500V1 0x8020
 #define PVR_VER_E500V2 0x8021
+#define PVR_VER_E6500  0x8040
+
 /*
  * For the 8xx processors, all of them report the same PVR family for
  * the PowerPC core. The various versions of these processors must be
diff --git a/arch/powerpc/include/asm/reg_booke.h 
b/arch/powerpc/include/asm/reg_booke.h
index ed8f836..86ede76 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -170,6 +170,7 @@
 #define SPRN_L2CSR10x3FA   /* L2 Data Cache Control and Status Register 1 
*/
 #define SPRN_DCCR  0x3FA   /* Data Cache Cacheability Register */
 #define SPRN_ICCR  0x3FB   /* Instruction Cache Cacheability Register */
+#define SPRN_PWRMGTCR0 0x3FB   /* Power management control register 0 */
 #define SPRN_SVR   0x3FF   /* System Version Register */
 
 /*
-- 
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[PATCH v2 2/3] powerpc/85xx: add hardware automatically enter altivec idle state

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

Each core's AltiVec unit may be placed into a power savings mode
by turning off power to the unit. Core hardware will automatically
power down the AltiVec unit after no AltiVec instructions have
executed in N cycles. The AltiVec power-control is triggered by hardware.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
*v2:
Remove:
delete setup_idle_hw_governor function.
delete Fix erratum for rev1.

Move:
move setup_* into __setup/restore_cpu_e6500.

diff --git a/arch/powerpc/include/asm/reg_booke.h 
b/arch/powerpc/include/asm/reg_booke.h
index 86ede76..8364bbe 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -217,6 +217,9 @@
 #defineCCR1_DPC0x0100 /* Disable L1 I-Cache/D-Cache parity 
checking */
 #defineCCR1_TCS0x0080 /* Timer Clock Select */
 
+/* Bit definitions for PWRMGTCR0. */
+#define PWRMGTCR0_ALTIVEC_IDLE (1  22) /* Altivec idle enable */
+
 /* Bit definitions for the MCSR. */
 #define MCSR_MCS   0x8000 /* Machine Check Summary */
 #define MCSR_IB0x4000 /* Instruction PLB Error */
diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S 
b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index bfb18c7..90bbb46 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -58,6 +58,7 @@ _GLOBAL(__setup_cpu_e6500)
 #ifdef CONFIG_PPC64
bl  .setup_altivec_ivors
 #endif
+   bl  setup_altivec_idle
bl  __setup_cpu_e5500
mtlrr6
blr
@@ -119,6 +120,7 @@ _GLOBAL(__setup_cpu_e5500)
 _GLOBAL(__restore_cpu_e6500)
mflrr5
bl  .setup_altivec_ivors
+   bl  setup_altivec_idle
bl  __restore_cpu_e5500
mtlrr5
blr
diff --git a/arch/powerpc/platforms/85xx/common.c 
b/arch/powerpc/platforms/85xx/common.c
index d0861a0..93b563b 100644
--- a/arch/powerpc/platforms/85xx/common.c
+++ b/arch/powerpc/platforms/85xx/common.c
@@ -11,6 +11,16 @@
 
 #include mpc85xx.h
 
+#define MAX_BIT64
+
+#define ALTIVEC_COUNT_OFFSET   16
+#define ALTIVEC_IDLE_COUNT_MASK0x003f
+
+/*
+ * FIXME - We don't know the AltiVec application scenarios.
+ */
+#define ALTIVEC_IDLE_TIME_BIT  14 /* 1ms */
+
 static struct of_device_id __initdata mpc85xx_common_ids[] = {
{ .type = soc, },
{ .compatible = soc, },
@@ -80,3 +90,38 @@ void __init mpc85xx_cpm2_pic_init(void)
irq_set_chained_handler(irq, cpm2_cascade);
 }
 #endif
+
+static bool has_pw20_altivec_idle(void)
+{
+   u32 pvr;
+
+   pvr = mfspr(SPRN_PVR);
+
+   /* PW20  AltiVec idle feature only exists for E6500 */
+   if (PVR_VER(pvr) != PVR_VER_E6500)
+   return false;
+
+   return true;
+}
+
+void setup_altivec_idle(void)
+{
+   u32 altivec_idle;
+
+   if (!has_pw20_altivec_idle())
+   return;
+
+   /* Enable Altivec Idle */
+   altivec_idle = mfspr(SPRN_PWRMGTCR0);
+   altivec_idle |= PWRMGTCR0_ALTIVEC_IDLE;
+
+   /* Set Automatic AltiVec Idle Count */
+   /* clear count */
+   altivec_idle = ~ALTIVEC_IDLE_COUNT_MASK;
+
+   /* set count */
+   altivec_idle |=
+   ((MAX_BIT - ALTIVEC_IDLE_TIME_BIT)  ALTIVEC_COUNT_OFFSET);
+
+   mtspr(SPRN_PWRMGTCR0, altivec_idle);
+}
-- 
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[PATCH v2 3/3] powerpc/85xx: add hardware automatically enter pw20 state

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

Using hardware features make core automatically enter PW20 state.
Set a TB count to hardware, the effective count begins when PW10
is entered. When the effective period has expired, the core will
proceed from PW10 to PW20 if no exit conditions have occurred during
the period.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
Remove:
delete setup_idle_hw_governor function.
delete Fix erratum for rev1.

Move:
move setup_* into __setup/restore_cpu_e6500.

diff --git a/arch/powerpc/include/asm/reg_booke.h 
b/arch/powerpc/include/asm/reg_booke.h
index 8364bbe..e846495 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -219,6 +219,7 @@
 
 /* Bit definitions for PWRMGTCR0. */
 #define PWRMGTCR0_ALTIVEC_IDLE (1  22) /* Altivec idle enable */
+#define PWRMGTCR0_PW20_WAIT(1  14) /* PW20 state enable bit */
 
 /* Bit definitions for the MCSR. */
 #define MCSR_MCS   0x8000 /* Machine Check Summary */
diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S 
b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index 90bbb46..295ccb5 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -59,6 +59,7 @@ _GLOBAL(__setup_cpu_e6500)
bl  .setup_altivec_ivors
 #endif
bl  setup_altivec_idle
+   bl  setup_pw20_idle
bl  __setup_cpu_e5500
mtlrr6
blr
@@ -121,6 +122,7 @@ _GLOBAL(__restore_cpu_e6500)
mflrr5
bl  .setup_altivec_ivors
bl  setup_altivec_idle
+   bl  setup_pw20_idle
bl  __restore_cpu_e5500
mtlrr5
blr
diff --git a/arch/powerpc/platforms/85xx/common.c 
b/arch/powerpc/platforms/85xx/common.c
index 93b563b..cdd526e 100644
--- a/arch/powerpc/platforms/85xx/common.c
+++ b/arch/powerpc/platforms/85xx/common.c
@@ -15,12 +15,22 @@
 
 #define ALTIVEC_COUNT_OFFSET   16
 #define ALTIVEC_IDLE_COUNT_MASK0x003f
+#define PW20_COUNT_OFFSET  8
+#define PW20_IDLE_COUNT_MASK   0x3f00
 
 /*
  * FIXME - We don't know the AltiVec application scenarios.
  */
 #define ALTIVEC_IDLE_TIME_BIT  14 /* 1ms */
 
+/*
+ * FIXME - We don't know, what time should we let the core into PW20 state.
+ * because we don't know the current state of the cpu load. And threads are
+ * independent, so we can not know the state of different thread has been
+ * idle.
+ */
+#define PW20_IDLE_TIME_BIT 14 /* 1ms */
+
 static struct of_device_id __initdata mpc85xx_common_ids[] = {
{ .type = soc, },
{ .compatible = soc, },
@@ -125,3 +135,25 @@ void setup_altivec_idle(void)
 
mtspr(SPRN_PWRMGTCR0, altivec_idle);
 }
+
+void setup_pw20_idle(void)
+{
+   u32 pw20_idle;
+
+   if (!has_pw20_altivec_idle())
+   return;
+
+   pw20_idle = mfspr(SPRN_PWRMGTCR0);
+
+   /* Set PW20_WAIT bit, Enable PW20 State */
+   pw20_idle |= PWRMGTCR0_PW20_WAIT;
+
+   /* Set Automatic PW20 Core Idle Count */
+   /* clear count */
+   pw20_idle = ~PW20_IDLE_COUNT_MASK;
+
+   /* set count */
+   pw20_idle |= ((MAX_BIT - PW20_IDLE_TIME_BIT)  PW20_COUNT_OFFSET);
+
+   mtspr(SPRN_PWRMGTCR0, pw20_idle);
+}
-- 
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[PATCH 1/2] powerpc/85xx: add hardware automatically enter altivec idle state

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

Each core's AltiVec unit may be placed into a power savings mode
by turning off power to the unit. Core hardware will automatically
power down the AltiVec unit after no AltiVec instructions have
executed in N cycles. The AltiVec power-control is triggered by hardware.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 5d7d9c2..5c7a7ba 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -1053,6 +1053,8 @@
 #define PVR_8560   0x8020
 #define PVR_VER_E500V1 0x8020
 #define PVR_VER_E500V2 0x8021
+#define PVR_VER_E6500  0x8040
+
 /*
  * For the 8xx processors, all of them report the same PVR family for
  * the PowerPC core. The various versions of these processors must be
diff --git a/arch/powerpc/include/asm/reg_booke.h 
b/arch/powerpc/include/asm/reg_booke.h
index b417de3..c047e08 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -170,6 +170,7 @@
 #define SPRN_L2CSR10x3FA   /* L2 Data Cache Control and Status Register 1 
*/
 #define SPRN_DCCR  0x3FA   /* Data Cache Cacheability Register */
 #define SPRN_ICCR  0x3FB   /* Instruction Cache Cacheability Register */
+#define SPRN_PWRMGTCR0 0x3FB   /* Power management control register 0 */
 #define SPRN_SVR   0x3FF   /* System Version Register */
 
 /*
@@ -216,6 +217,9 @@
 #defineCCR1_DPC0x0100 /* Disable L1 I-Cache/D-Cache parity 
checking */
 #defineCCR1_TCS0x0080 /* Timer Clock Select */
 
+/* Bit definitions for PWRMGTCR0. */
+#define PWRMGTCR0_ALTIVEC_IDLE (1  22) /* Altivec idle enable */
+
 /* Bit definitions for the MCSR. */
 #define MCSR_MCS   0x8000 /* Machine Check Summary */
 #define MCSR_IB0x4000 /* Instruction PLB Error */
diff --git a/arch/powerpc/platforms/85xx/common.c 
b/arch/powerpc/platforms/85xx/common.c
index d0861a0..dbbbc24 100644
--- a/arch/powerpc/platforms/85xx/common.c
+++ b/arch/powerpc/platforms/85xx/common.c
@@ -7,10 +7,22 @@
  */
 #include linux/of_platform.h
 
+#include asm/time.h
+
 #include sysdev/cpm2_pic.h
 
 #include mpc85xx.h
 
+#define MAX_BIT64
+
+#define ALTIVEC_COUNT_OFFSET   16
+#define ALTIVEC_IDLE_COUNT_MASK0x003f
+
+/*
+ * FIXME - We don't know the AltiVec application scenarios.
+ */
+#define ALTIVEC_IDLE_TIME  1000 /* 1ms */
+
 static struct of_device_id __initdata mpc85xx_common_ids[] = {
{ .type = soc, },
{ .compatible = soc, },
@@ -80,3 +92,63 @@ void __init mpc85xx_cpm2_pic_init(void)
irq_set_chained_handler(irq, cpm2_cascade);
 }
 #endif
+
+static bool has_pw20_altivec_idle(void)
+{
+   u32 pvr;
+
+   pvr = mfspr(SPRN_PVR);
+
+   /* PW20  AltiVec idle feature only exists for E6500 */
+   if (PVR_VER(pvr) != PVR_VER_E6500)
+   return false;
+
+   /* Fix erratum, e6500 rev1 does not support PW20  AltiVec idle */
+   if (PVR_REV(pvr)  0x20)
+   return false;
+
+   return true;
+}
+
+static unsigned int get_idle_ticks_bit(unsigned int us)
+{
+   unsigned int cycle;
+
+   /*
+* The time control by TB turn over bit, so we need
+* to be divided by 2.
+*/
+   cycle = (us / 2) * tb_ticks_per_usec;
+
+   return ilog2(cycle) + 1;
+}
+
+static void setup_altivec_idle(void *unused)
+{
+   u32 altivec_idle, bit;
+
+   if (!has_pw20_altivec_idle())
+   return;
+
+   /* Enable Altivec Idle */
+   altivec_idle = mfspr(SPRN_PWRMGTCR0);
+   altivec_idle |= PWRMGTCR0_ALTIVEC_IDLE;
+
+   /* Set Automatic AltiVec Idle Count */
+   /* clear count */
+   altivec_idle = ~ALTIVEC_IDLE_COUNT_MASK;
+
+   /* set count */
+   bit = get_idle_ticks_bit(ALTIVEC_IDLE_TIME);
+   altivec_idle |= ((MAX_BIT - bit)  ALTIVEC_COUNT_OFFSET);
+
+   mtspr(SPRN_PWRMGTCR0, altivec_idle);
+}
+
+static int __init setup_idle_hw_governor(void)
+{
+   on_each_cpu(setup_altivec_idle, NULL, 1);
+
+   return 0;
+}
+late_initcall(setup_idle_hw_governor);
-- 
1.8.0


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[PATCH 2/2] powerpc/85xx: add hardware automatically enter pw20 state

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

Using hardware features make core automatically enter PW20 state.
Set a TB count to hardware, the effective count begins when PW10
is entered. When the effective period has expired, the core will
proceed from PW10 to PW20 if no exit conditions have occurred during
the period.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com

diff --git a/arch/powerpc/include/asm/reg_booke.h 
b/arch/powerpc/include/asm/reg_booke.h
index c047e08..3c81a88 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -219,6 +219,7 @@
 
 /* Bit definitions for PWRMGTCR0. */
 #define PWRMGTCR0_ALTIVEC_IDLE (1  22) /* Altivec idle enable */
+#define PWRMGTCR0_PW20_WAIT(1  14) /* PW20 state enable bit */
 
 /* Bit definitions for the MCSR. */
 #define MCSR_MCS   0x8000 /* Machine Check Summary */
diff --git a/arch/powerpc/platforms/85xx/common.c 
b/arch/powerpc/platforms/85xx/common.c
index dbbbc24..a208d52 100644
--- a/arch/powerpc/platforms/85xx/common.c
+++ b/arch/powerpc/platforms/85xx/common.c
@@ -17,12 +17,22 @@
 
 #define ALTIVEC_COUNT_OFFSET   16
 #define ALTIVEC_IDLE_COUNT_MASK0x003f
+#define PW20_COUNT_OFFSET  8
+#define PW20_IDLE_COUNT_MASK   0x3f00
 
 /*
  * FIXME - We don't know the AltiVec application scenarios.
  */
 #define ALTIVEC_IDLE_TIME  1000 /* 1ms */
 
+/*
+ * FIXME - We don't know, what time should we let the core into PW20 state.
+ * because we don't know the current state of the cpu load. And threads are
+ * independent, so we can not know the state of different thread has been
+ * idle.
+ */
+#definePW20_IDLE_TIME  1000 /* 1ms */
+
 static struct of_device_id __initdata mpc85xx_common_ids[] = {
{ .type = soc, },
{ .compatible = soc, },
@@ -145,9 +155,33 @@ static void setup_altivec_idle(void *unused)
mtspr(SPRN_PWRMGTCR0, altivec_idle);
 }
 
+static void setup_pw20_idle(void *unused)
+{
+   u32 pw20_idle, bit;
+
+   if (!has_pw20_altivec_idle())
+   return;
+
+   pw20_idle = mfspr(SPRN_PWRMGTCR0);
+
+   /* set PW20_WAIT bit, enable pw20 */
+   pw20_idle |= PWRMGTCR0_PW20_WAIT;
+
+   /* Set Automatic PW20 Core Idle Count */
+   /* clear count */
+   pw20_idle = ~PW20_IDLE_COUNT_MASK;
+
+   /* set count */
+   bit = get_idle_ticks_bit(PW20_IDLE_TIME);
+   pw20_idle |= ((MAX_BIT - bit)  PW20_COUNT_OFFSET);
+
+   mtspr(SPRN_PWRMGTCR0, pw20_idle);
+}
+
 static int __init setup_idle_hw_governor(void)
 {
on_each_cpu(setup_altivec_idle, NULL, 1);
+   on_each_cpu(setup_pw20_idle, NULL, 1);
 
return 0;
 }
-- 
1.8.0


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[PATCH v3 1/2] powerpc: add Book E support to 64-bit hibernation

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

Update the 64-bit hibernation code to support Book E CPUs.
Some registers and instructions are not defined for Book3e
(SDR reg, tlbia instruction).

SDR: Storage Description Register. Book3S and Book3E have different
address translation mode, we do not need HTABORG  HTABSIZE to
translate virtual address to real address.

More registers are saved in BookE-64bit.(TCR, SPRG1)

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
v3:
* Move invaild tlb code to FSL code path.
  Book3S has already invaild tlb.

v2:
* Remove: Save SPRG0, SPRG2-SPRG7.
SPRG1 should be saved, the paca will be saved here.

* Add: Invaild tlbs.

* Modify: Code style, add whitespace after commas.

diff --git a/arch/powerpc/kernel/swsusp_asm64.S 
b/arch/powerpc/kernel/swsusp_asm64.S
index 86ac1d9..2204598 100644
--- a/arch/powerpc/kernel/swsusp_asm64.S
+++ b/arch/powerpc/kernel/swsusp_asm64.S
@@ -46,10 +46,19 @@
 #define SL_r29 0xe8
 #define SL_r30 0xf0
 #define SL_r31 0xf8
-#define SL_SIZESL_r31+8
+#define SL_SPRG1   0x100
+#define SL_TCR 0x108
+#define SL_SIZESL_TCR+8
 
 /* these macros rely on the save area being
  * pointed to by r11 */
+
+#define SAVE_SPR(register) \
+   mfspr   r0, SPRN_##register ;\
+   std r0, SL_##register(r11)
+#define RESTORE_SPR(register)  \
+   ld  r0, SL_##register(r11)  ;\
+   mtspr   SPRN_##register, r0
 #define SAVE_SPECIAL(special)  \
mf##special r0  ;\
std r0, SL_##special(r11)
@@ -103,8 +112,15 @@ _GLOBAL(swsusp_arch_suspend)
SAVE_REGISTER(r30)
SAVE_REGISTER(r31)
SAVE_SPECIAL(MSR)
-   SAVE_SPECIAL(SDR1)
SAVE_SPECIAL(XER)
+#ifdef CONFIG_PPC_BOOK3S_64
+   SAVE_SPECIAL(SDR1)
+#else
+   SAVE_SPR(TCR)
+
+   /* Save SPRG1, SPRG1 be used save paca */
+   SAVE_SPR(SPRG1)
+#endif
 
/* we push the stack up 128 bytes but don't store the
 * stack pointer on the stack like a real stackframe */
@@ -151,6 +167,7 @@ copy_page_loop:
bne+copyloop
 nothing_to_copy:
 
+#ifdef CONFIG_PPC_BOOK3S_64
/* flush caches */
lis r3, 0x10
mtctr   r3
@@ -167,6 +184,7 @@ nothing_to_copy:
sync
 
tlbia
+#endif
 
ld  r11,swsusp_save_area_ptr@toc(r2)
 
@@ -208,16 +226,39 @@ nothing_to_copy:
RESTORE_REGISTER(r29)
RESTORE_REGISTER(r30)
RESTORE_REGISTER(r31)
+
+#ifdef CONFIG_PPC_BOOK3S_64
/* can't use RESTORE_SPECIAL(MSR) */
ld  r0, SL_MSR(r11)
mtmsrd  r0, 0
RESTORE_SPECIAL(SDR1)
+#else
+   /* Restore SPRG1, be used to save paca */
+   ld  r0, SL_SPRG1(r11)
+   mtsprg  1, r0
+
+   RESTORE_SPECIAL(MSR)
+
+   /* Restore TCR and clear any pending bits in TSR. */
+   RESTORE_SPR(TCR)
+   lis r0, (TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS)@h
+   mtspr   SPRN_TSR, r0
+
+   /* Kick decrementer */
+   li  r0, 1
+   mtdec   r0
+
+   /* Invalidate all tlbs */
+   bl  _tlbil_all
+#endif
RESTORE_SPECIAL(XER)
 
sync
 
addir1,r1,-128
+#ifdef CONFIG_PPC_BOOK3S_64
bl  slb_flush_and_rebolt
+#endif
bl  do_after_copyback
addir1,r1,128
 
-- 
1.8.0


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[PATCH] cpuidle: fix unremovable issue for module driver

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

After __cpuidle_register_device, the cpu incs are added up, but decs
are not, thus the module refcount is not match. So the module exit
function can not be executed when we do remove operation. Move
module_put into __cpuidle_register_device to fix it.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com

diff --git a/drivers/cpuidle/cpuidle.c b/drivers/cpuidle/cpuidle.c
index d75040d..e964ada 100644
--- a/drivers/cpuidle/cpuidle.c
+++ b/drivers/cpuidle/cpuidle.c
@@ -351,11 +351,8 @@ EXPORT_SYMBOL_GPL(cpuidle_disable_device);
 
 static void __cpuidle_unregister_device(struct cpuidle_device *dev)
 {
-   struct cpuidle_driver *drv = cpuidle_get_cpu_driver(dev);
-
list_del(dev-device_list);
per_cpu(cpuidle_devices, dev-cpu) = NULL;
-   module_put(drv-owner);
 }
 
 static int __cpuidle_device_init(struct cpuidle_device *dev)
@@ -384,6 +381,8 @@ static int __cpuidle_register_device(struct cpuidle_device 
*dev)
per_cpu(cpuidle_devices, dev-cpu) = dev;
list_add(dev-device_list, cpuidle_detected_devices);
 
+   module_put(drv-owner);
+
ret = cpuidle_coupled_register_device(dev);
if (ret) {
__cpuidle_unregister_device(dev);
-- 
1.8.0


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[PATCH] cpuidle: add freescale e500 family porcessors idle support

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

Add cpuidle support for e500 family, using cpuidle framework to
manage various low power modes. The new implementation will remain
compatible with original idle method.

Initially, this supports PW10, and subsequent patches will support
PW20/DOZE/NAP.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
This patch keep using cpuidle_register_device(), because we need to support cpu
hotplug. I will fix device issue in this driver, after
Deepthi Dharwar deep...@linux.vnet.ibm.com add a hotplug handler into cpuidle
freamwork.

diff --git a/arch/powerpc/include/asm/machdep.h 
b/arch/powerpc/include/asm/machdep.h
index 8b48090..cbdbe25 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -271,6 +271,16 @@ extern void power7_idle(void);
 extern void ppc6xx_idle(void);
 extern void book3e_idle(void);
 
+/* Wait for Interrupt */
+static inline void fsl_cpuidle_wait(void)
+{
+#ifdef CONFIG_PPC64
+   book3e_idle();
+#else
+   e500_idle();
+#endif
+}
+
 /*
  * ppc_md contains a copy of the machine description structure for the
  * current platform. machine_id contains the initial address where the
diff --git a/drivers/cpuidle/Kconfig b/drivers/cpuidle/Kconfig
index b3fb81d..7ed114b 100644
--- a/drivers/cpuidle/Kconfig
+++ b/drivers/cpuidle/Kconfig
@@ -35,6 +35,11 @@ depends on ARM
 source drivers/cpuidle/Kconfig.arm
 endmenu
 
+menu PowerPC CPU Idle Drivers
+depends on PPC32 || PPC64
+source drivers/cpuidle/Kconfig.powerpc
+endmenu
+
 endif
 
 config ARCH_NEEDS_CPU_IDLE_COUPLED
diff --git a/drivers/cpuidle/Kconfig.powerpc b/drivers/cpuidle/Kconfig.powerpc
new file mode 100644
index 000..9f3f5ef
--- /dev/null
+++ b/drivers/cpuidle/Kconfig.powerpc
@@ -0,0 +1,9 @@
+#
+# PowerPC CPU Idle drivers
+#
+
+config PPC_E500_CPUIDLE
+   bool CPU Idle Driver for E500 family processors
+   depends on FSL_SOC_BOOKE
+   help
+ Select this to enable cpuidle on e500 family processors.
diff --git a/drivers/cpuidle/Makefile b/drivers/cpuidle/Makefile
index 0b9d200..0dde3db 100644
--- a/drivers/cpuidle/Makefile
+++ b/drivers/cpuidle/Makefile
@@ -11,3 +11,7 @@ obj-$(CONFIG_ARM_HIGHBANK_CPUIDLE)+= cpuidle-calxeda.o
 obj-$(CONFIG_ARM_KIRKWOOD_CPUIDLE) += cpuidle-kirkwood.o
 obj-$(CONFIG_ARM_ZYNQ_CPUIDLE) += cpuidle-zynq.o
 obj-$(CONFIG_ARM_U8500_CPUIDLE) += cpuidle-ux500.o
+
+##
+# PowerPC platform drivers
+obj-$(CONFIG_PPC_E500_CPUIDLE) += cpuidle-e500.o
diff --git a/drivers/cpuidle/cpuidle-e500.c b/drivers/cpuidle/cpuidle-e500.c
new file mode 100644
index 000..1919cea
--- /dev/null
+++ b/drivers/cpuidle/cpuidle-e500.c
@@ -0,0 +1,222 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * CPU Idle driver for Freescale PowerPC e500 family processors.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Author: Wang Dongsheng dongsheng.w...@freescale.com
+ */
+
+#include linux/cpu.h
+#include linux/cpuidle.h
+#include linux/init.h
+#include linux/kernel.h
+#include linux/module.h
+#include linux/notifier.h
+
+#include asm/machdep.h
+
+static struct cpuidle_driver e500_idle_driver = {
+   .name = e500_idle,
+   .owner = THIS_MODULE,
+};
+
+static struct cpuidle_device __percpu *e500_cpuidle_devices;
+
+static void e500_cpuidle(void)
+{
+   /*
+* This would call on the cpuidle framework, and the back-end
+* driver to go to idle states.
+*/
+   if (cpuidle_idle_call()) {
+   /*
+* On error, execute default handler
+* to go into low thread priority and possibly
+* low power mode.
+*/
+   HMT_low();
+   HMT_very_low();
+   }
+}
+
+static int pw10_enter(struct cpuidle_device *dev,
+   struct cpuidle_driver *drv, int index)
+{
+   fsl_cpuidle_wait();
+   return index;
+}
+
+static struct cpuidle_state fsl_pw_idle_states[] = {
+   {
+   .name = pw10,
+   .desc = pw10,
+   .flags = CPUIDLE_FLAG_TIME_VALID,
+   .exit_latency = 0,
+   .target_residency = 0,
+   .enter = pw10_enter
+   },
+};
+
+static int cpu_hotplug_notify(struct notifier_block *n,
+   unsigned long action, void *hcpu)
+{
+   unsigned long hotcpu = (unsigned long)hcpu;
+   struct cpuidle_device *dev =
+   per_cpu_ptr(e500_cpuidle_devices, hotcpu);
+
+   if (dev  cpuidle_get_driver()) {
+   switch (action) {
+   case CPU_ONLINE:
+   case CPU_ONLINE_FROZEN:
+   cpuidle_pause_and_lock();
+   

[PATCH 1/2] cpuidle: fix cpu idle driver as a module can not remove

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

The module can not be removed when execute rmmod. rmmod not use
--force.

Log:
root:~# rmmod cpuidle-e500
incs[9], decs[1]
rmmod: can't unload 'cpuidle_e500': Resource temporarily unavailable

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
Branch: pm-cpuidle

 drivers/cpuidle/cpuidle.c | 7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/cpuidle/cpuidle.c b/drivers/cpuidle/cpuidle.c
index fdc432f..534320a 100644
--- a/drivers/cpuidle/cpuidle.c
+++ b/drivers/cpuidle/cpuidle.c
@@ -386,6 +386,9 @@ static int __cpuidle_register_device(struct cpuidle_device 
*dev)
goto err_coupled;
 
dev-registered = 1;
+
+   module_put(drv-owner);
+
return 0;
 
 err_coupled:
@@ -432,8 +435,6 @@ EXPORT_SYMBOL_GPL(cpuidle_register_device);
  */
 void cpuidle_unregister_device(struct cpuidle_device *dev)
 {
-   struct cpuidle_driver *drv = cpuidle_get_cpu_driver(dev);
-
if (dev-registered == 0)
return;
 
@@ -448,8 +449,6 @@ void cpuidle_unregister_device(struct cpuidle_device *dev)
cpuidle_coupled_unregister_device(dev);
 
cpuidle_resume_and_unlock();
-
-   module_put(drv-owner);
 }
 
 EXPORT_SYMBOL_GPL(cpuidle_unregister_device);
-- 
1.8.0


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[PATCH 2/2] cpuidle: export cpuidle_idle_call symbol

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

Export cpuidle_idle_call symbol, make this function can be invoked
in the module.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
Branch: pm-cpuidle

 drivers/cpuidle/cpuidle.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/cpuidle/cpuidle.c b/drivers/cpuidle/cpuidle.c
index 534320a..d0a61d6 100644
--- a/drivers/cpuidle/cpuidle.c
+++ b/drivers/cpuidle/cpuidle.c
@@ -168,6 +168,7 @@ int cpuidle_idle_call(void)
 
return 0;
 }
+EXPORT_SYMBOL_GPL(cpuidle_idle_call);
 
 /**
  * cpuidle_install_idle_handler - installs the cpuidle idle loop handler
-- 
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[PATCH v2 1/2] powerpc: add Book E support to 64-bit hibernation

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

Update the 64-bit hibernation code to support Book E CPUs.
Some registers and instructions are not defined for Book3e
(SDR reg, tlbia instruction).

SDR: Storage Description Register. Book3S and Book3E have different
address translation mode, we do not need HTABORG  HTABSIZE to
translate virtual address to real address.

More registers are saved in BookE-64bit.(TCR, SPRG1)

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
v2:
* Remove: Save SPRG0, SPRG2-SPRG7.
  SPRG1 should be saved, the paca will be saved here.

* Add: Invaild tlbs.

* Modify: Code style, add whitespace after commas.

diff --git a/arch/powerpc/kernel/swsusp_asm64.S 
b/arch/powerpc/kernel/swsusp_asm64.S
index 86ac1d9..f530350 100644
--- a/arch/powerpc/kernel/swsusp_asm64.S
+++ b/arch/powerpc/kernel/swsusp_asm64.S
@@ -46,10 +46,19 @@
 #define SL_r29 0xe8
 #define SL_r30 0xf0
 #define SL_r31 0xf8
-#define SL_SIZESL_r31+8
+#define SL_SPRG1   0x100
+#define SL_TCR 0x108
+#define SL_SIZESL_TCR+8
 
 /* these macros rely on the save area being
  * pointed to by r11 */
+
+#define SAVE_SPR(register) \
+   mfspr   r0, SPRN_##register ;\
+   std r0, SL_##register(r11)
+#define RESTORE_SPR(register)  \
+   ld  r0, SL_##register(r11)  ;\
+   mtspr   SPRN_##register, r0
 #define SAVE_SPECIAL(special)  \
mf##special r0  ;\
std r0, SL_##special(r11)
@@ -103,8 +112,15 @@ _GLOBAL(swsusp_arch_suspend)
SAVE_REGISTER(r30)
SAVE_REGISTER(r31)
SAVE_SPECIAL(MSR)
-   SAVE_SPECIAL(SDR1)
SAVE_SPECIAL(XER)
+#ifdef CONFIG_PPC_BOOK3S_64
+   SAVE_SPECIAL(SDR1)
+#else
+   SAVE_SPR(TCR)
+
+   /* Save SPRG1, SPRG1 be used save paca */
+   SAVE_SPR(SPRG1)
+#endif
 
/* we push the stack up 128 bytes but don't store the
 * stack pointer on the stack like a real stackframe */
@@ -151,6 +167,7 @@ copy_page_loop:
bne+copyloop
 nothing_to_copy:
 
+#ifdef CONFIG_PPC_BOOK3S_64
/* flush caches */
lis r3, 0x10
mtctr   r3
@@ -167,6 +184,7 @@ nothing_to_copy:
sync
 
tlbia
+#endif
 
ld  r11,swsusp_save_area_ptr@toc(r2)
 
@@ -208,16 +226,39 @@ nothing_to_copy:
RESTORE_REGISTER(r29)
RESTORE_REGISTER(r30)
RESTORE_REGISTER(r31)
+
+#ifdef CONFIG_PPC_BOOK3S_64
/* can't use RESTORE_SPECIAL(MSR) */
ld  r0, SL_MSR(r11)
mtmsrd  r0, 0
RESTORE_SPECIAL(SDR1)
+#else
+   /* Restore SPRG1, be used to save paca */
+   ld  r0, SL_SPRG1(r11)
+   mtsprg  1, r0
+
+   RESTORE_SPECIAL(MSR)
+
+   /* Restore TCR and clear any pending bits in TSR. */
+   RESTORE_SPR(TCR)
+   lis r0, (TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS)@h
+   mtspr   SPRN_TSR, r0
+
+   /* Kick decrementer */
+   li  r0, 1
+   mtdec   r0
+#endif
RESTORE_SPECIAL(XER)
 
sync
 
+   /* Invalidate all tlbs */
+   bl  _tlbil_all
+
addir1,r1,-128
+#ifdef CONFIG_PPC_BOOK3S_64
bl  slb_flush_and_rebolt
+#endif
bl  do_after_copyback
addir1,r1,128
 
-- 
1.8.0


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[RFC 1/2] fsl/pm: combined the idle(PHPW) state

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

move wait instructions from idle_e500.S to idle_book3e.S

idle_e500.S: rename e500_idle to e500_idle_ph.
idle_book3e.S: rename BOOK3E to E500, this file not only use 64bit
mode.

Next we will modify the current cpu idle running way, and will use
cpuidle framework. Distinguish between PH mode and WAIT mode is to
prepare for subsequent development.

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com

diff --git a/arch/powerpc/include/asm/machdep.h 
b/arch/powerpc/include/asm/machdep.h
index 92386fc..5688c39 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -262,11 +262,11 @@ struct machdep_calls {
 #endif
 };
 
-extern void e500_idle(void);
+extern void e500_idle_ph(void);
 extern void power4_idle(void);
 extern void power7_idle(void);
 extern void ppc6xx_idle(void);
-extern void book3e_idle(void);
+extern void e500_idle_wait(void);
 
 /*
  * ppc_md contains a copy of the machine description structure for the
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index f960a79..047c7e3 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -28,7 +28,7 @@ endif
 
 obj-y  := cputable.o ptrace.o syscalls.o \
   irq.o align.o signal_32.o pmc.o vdso.o \
-  process.o systbl.o idle.o \
+  process.o systbl.o idle.o idle_book3e.o \
   signal.o sysfs.o cacheinfo.o time.o \
   prom.o traps.o setup-common.o \
   udbg.o misc.o io.o dma.o \
@@ -40,7 +40,7 @@ obj-$(CONFIG_HAVE_HW_BREAKPOINT)  += hw_breakpoint.o
 obj-$(CONFIG_PPC_BOOK3S_64)+= cpu_setup_ppc970.o cpu_setup_pa6t.o
 obj-$(CONFIG_PPC_BOOK3S_64)+= cpu_setup_power.o
 obj64-$(CONFIG_RELOCATABLE)+= reloc_64.o
-obj-$(CONFIG_PPC_BOOK3E_64)+= exceptions-64e.o idle_book3e.o
+obj-$(CONFIG_PPC_BOOK3E_64)+= exceptions-64e.o
 obj-$(CONFIG_PPC_A2)   += cpu_setup_a2.o
 obj-$(CONFIG_PPC64)+= vdso64/
 obj-$(CONFIG_ALTIVEC)  += vecemu.o
diff --git a/arch/powerpc/kernel/idle_book3e.S 
b/arch/powerpc/kernel/idle_book3e.S
index bfb73cc..229f86b 100644
--- a/arch/powerpc/kernel/idle_book3e.S
+++ b/arch/powerpc/kernel/idle_book3e.S
@@ -1,7 +1,7 @@
 /*
  * Copyright 2010 IBM Corp, Benjamin Herrenschmidt b...@kernel.crashing.org
  *
- * Generic idle routine for Book3E processors
+ * Generic idle(wait) routine for e500mc, e5500, e6500 processors
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -18,11 +18,9 @@
 #include asm/thread_info.h
 #include asm/epapr_hcalls.h
 
-/* 64-bit version only for now */
-#ifdef CONFIG_PPC64
-
-.macro BOOK3E_IDLE name loop
+.macro E500_IDLE_WAIT name loop
 _GLOBAL(\name)
+#ifdef CONFIG_PPC64
/* Save LR for later */
mflrr0
std r0,16(r1)
@@ -66,6 +64,12 @@ _GLOBAL(\name)
ld  r10,TI_LOCAL_FLAGS(r11)
ori r10,r10,_TLF_NAPPING
std r10,TI_LOCAL_FLAGS(r11)
+#else
+   CURRENT_THREAD_INFO(r11, r1)
+   lwz r4,TI_LOCAL_FLAGS(r11)  /* set napping bit */
+   ori r4,r4,_TLF_NAPPING  /* so when we take an exception */
+   stw r4,TI_LOCAL_FLAGS(r11)  /* it will return to our caller */
+#endif
 
/* We can now re-enable hard interrupts and go to sleep */
wrteei  1
@@ -73,7 +77,7 @@ _GLOBAL(\name)
 
 .endm
 
-.macro BOOK3E_IDLE_LOOP
+.macro E500_IDLE_LOOP
 1:
PPC_WAIT(0)
b   1b
@@ -94,8 +98,8 @@ epapr_ev_idle_start:
b   idle_loop
 .endm
 
-BOOK3E_IDLE epapr_ev_idle EPAPR_EV_IDLE_LOOP
-
-BOOK3E_IDLE book3e_idle BOOK3E_IDLE_LOOP
+#ifdef CONFIG_PPC64
+E500_IDLE_WAIT epapr_ev_idle EPAPR_EV_IDLE_LOOP
+#endif
 
-#endif /* CONFIG_PPC64 */
+E500_IDLE_WAIT e500_idle_wait E500_IDLE_LOOP
diff --git a/arch/powerpc/kernel/idle_e500.S b/arch/powerpc/kernel/idle_e500.S
index 1544866..8b9ccaa 100644
--- a/arch/powerpc/kernel/idle_e500.S
+++ b/arch/powerpc/kernel/idle_e500.S
@@ -20,23 +20,12 @@
 
.text
 
-_GLOBAL(e500_idle)
+_GLOBAL(e500_idle_ph)
CURRENT_THREAD_INFO(r3, r1)
lwz r4,TI_LOCAL_FLAGS(r3)   /* set napping bit */
ori r4,r4,_TLF_NAPPING  /* so when we take an exception */
stw r4,TI_LOCAL_FLAGS(r3)   /* it will return to our caller */
 
-#ifdef CONFIG_PPC_E500MC
-   wrteei  1
-1: wait
-
-   /*
-* Guard against spurious wakeups (e.g. from a hypervisor) --
-* any real interrupt will cause us to return to LR due to
-* _TLF_NAPPING.
-*/
-   b   1b
-#else
/* Check if we can nap or doze, put HID0 mask in r3 */
lis r3,0
 BEGIN_FTR_SECTION
@@ -83,7 +72,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_L2CSR|CPU_FTR_CAN_NAP)
mtmsr   r7
   

[RFC 2/2] powerpc/cputable: add wait feature for CPU kernel features

[Dongsheng Wang]

From: Wang Dongsheng dongsheng.w...@freescale.com

Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com

diff --git a/arch/powerpc/include/asm/cputable.h 
b/arch/powerpc/include/asm/cputable.h
index 6f3887d..0a8d0cb 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -138,6 +138,7 @@ extern const char *powerpc_base_platform;
 #define CPU_FTR_NOEXECUTE  ASM_CONST(0x1000)
 #define CPU_FTR_INDEXED_DCRASM_CONST(0x2000)
 #define CPU_FTR_EMB_HV ASM_CONST(0x4000)
+#define CPU_FTR_CAN_WAIT   ASM_CONST(0x8000)
 
 /*
  * Add the 64-bit processor unique features in the top half of the word;
@@ -250,9 +251,11 @@ extern const char *powerpc_base_platform;
 #ifndef CONFIG_BDI_SWITCH
 #define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
 #define CPU_FTR_MAYBE_CAN_NAP  CPU_FTR_CAN_NAP
+#define CPU_FTR_MAYBE_CAN_WAIT CPU_FTR_CAN_WAIT
 #else
 #define CPU_FTR_MAYBE_CAN_DOZE 0
 #define CPU_FTR_MAYBE_CAN_NAP  0
+#define CPU_FTR_MAYBE_CAN_WAIT 0
 #endif
 
 #define CLASSIC_PPC (!defined(CONFIG_8xx)  !defined(CONFIG_4xx)  \
@@ -370,15 +373,17 @@ extern const char *powerpc_base_platform;
CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
 #define CPU_FTRS_E500MC(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
-   CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
+   CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | \
+   CPU_FTR_MAYBE_CAN_WAIT)
 #define CPU_FTRS_E5500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
-   CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
+   CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_MAYBE_CAN_WAIT)
 #define CPU_FTRS_E6500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
-   CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP)
+   CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \
+   CPU_FTR_MAYBE_CAN_WAIT)
 #define CPU_FTRS_GENERIC_32(CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
 
 /* 64-bit CPUs */
-- 
1.8.0


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