Re: [PATCH] MAINTAINERS: cxl: update maintainership

Acked-by: Ian Munsie <imun...@au1.ibm.com> Excerpts from andrew.donnellan's message of 2017-06-28 17:22:30 +1000: > As Ian's stepping down from his maintainer role now that he's leaving IBM, > Frederic has asked me to add myself to the cxl maintainer list. Updating > accor

[PATCH] MAINTAINERS: Remove myself as cxl maintainer

From: Ian Munsie <imun...@au1.ibm.com> I am no longer employed by IBM and will no longer have access to cxl hardware, so remove myself as a cxl maintainer. If anyone needs to contact me in the future, please use my personal email address darkstarsw...@gmail.com Signed-off-by: Ian Munsie

Re: [PATCH v2] cxl: fix build when CONFIG_DEBUG_FS=n

Acked-by: Ian Munsie <imun...@au1.ibm.com>

Re: [PATCH] cxl: prevent read/write to AFU config space while AFU not configured

Acked-by: Ian Munsie <imun...@au1.ibm.com> Looks like a reasonable solution > Pradipta found this while doing testing for cxlflash. I've tested this > patch and I'm satisfied that it solves the issue, but I've asked Pradipta > to test it a bit further. :)

Re: [PATCH] cxl: drop duplicate header sched.h

Acked-by: Ian Munsie <imun...@au1.ibm.com>

Re: [PATCH] cxl: fix coccinelle warnings

Excerpts from andrew.donnellan's message of 2016-11-23 18:06:59 +1100: > On 23/11/16 17:49, Ian Munsie wrote: > > Most of these look fine > > > >> -return debugfs_create_file(name, mode, parent, (void __force *)value, > >> _io_x64); > >> +re

Re: [PATCH] cxl: fix coccinelle warnings

Most of these look fine > -return debugfs_create_file(name, mode, parent, (void __force *)value, > _io_x64); > +return debugfs_create_file_unsafe(name, mode, parent, > + (void __force *)value, _io_x64); Just wondering what this one is about? Cheers, -Ian

Re: [PATCH] cxl: Fix memory allocation failure test

Acked-by: Ian Munsie <imun...@au1.ibm.com>

Re: [PATCH] cxl: Fix error handling

Acked-by: Ian Munsie <imun...@au1.ibm.com>

Re: [PATCH] cxl: Fix error handling

Acked-by: Ian Munsie <imun...@au1.ibm.com>

Re: [PATCH] powerpc/mm/coproc: Handle bad address on coproc slb fault

Reviewed-by: Ian Munsie <imun...@au1.ibm.com>

Re: [PATCH v2] cxl: Flush PSL cache before resetting the adapter

Acked-by: Ian Munsie <imun...@au1.ibm.com>

Re: [PATCH] cxl: Flush PSL cache before resetting the adapter

Acked-by: Ian Munsie <imun...@au1.ibm.com>

Re: [PATCH] cxl: use pcibios_free_controller_deferred() when removing vPHBs

Acked-by: Ian Munsie <imun...@au1.ibm.com>

Re: [PATCH] cxl: fix NULL dereference in cxl_context_init() on PowerVM guests

Whoops! Acked-by: Ian Munsie <imun...@au1.ibm.com> ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev

Re: [PATCH] cxl: add device ID for Mellanox ConnectX-4

Acked-by: Ian Munsie <imun...@au1.ibm.com> ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev

Re: [PATCH] cxl: fix sparse warnings

Acked-by: Ian Munsie <imun...@au1.ibm.com> ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev

[PATCH v2] powerpc/powernv: fix pci-cxl.c build when CONFIG_MODULES=n

From: Ian Munsie <imun...@au1.ibm.com> pnv_cxl_enable_phb_kernel_api() grabs a reference to the cxl module to prevent it from being unloaded after the PHB has been switched to CX4 mode. This breaks the build when CONFIG_MODULES=n as module_mutex doesn't exist. However, if we don't have m

Re: [PATCH] cxl: add option to enable -DDEBUG

Acked-by: Ian Munsie <imun...@au1.ibm.com> ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev

Re: [PATCH -next] cxl: Use for_each_compatible_node() macro

Acked-by: Ian Munsie <imun...@au1.ibm.com> ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev

[PATCH 15/15] cxl: Add cxl_check_and_switch_mode() API to switch bi-modal cards

roduce a new option, CONFIG_CXL_BIMODAL, with a dependency on the pnv_php driver. Refactor existing code that touches the mode control register in the regular single mode case into a new function, setup_cxl_protocol_area(). Co-authored-by: Ian Munsie <imun...@au1.ibm.com> Cc: Gav

[PATCH 14/15] PCI/hotplug: pnv_php: handle OPAL_PCI_SLOT_OFFLINE power state

ernel.org Cc: Bjorn Helgaas <bhelg...@google.com> Signed-off-by: Andrew Donnellan <andrew.donnel...@au1.ibm.com> Signed-off-by: Ian Munsie <imun...@au1.ibm.com> Acked-by: Gavin Shan <gws...@linux.vnet.ibm.com> --- drivers/pci/hotplug/pnv_php.c | 2 +- 1 file changed, 1 ins

[PATCH 13/15] PCI/hotplug: pnv_php: export symbols and move struct types needed by cxl

onding declarations, as well as the definition of struct pnv_php_slot, to asm/pnv-pci.h. Cc: Gavin Shan <gws...@linux.vnet.ibm.com> Cc: linux-...@vger.kernel.org Cc: Bjorn Helgaas <bhelg...@google.com> Signed-off-by: Andrew Donnellan <andrew.donnel...@au1.ibm.com> Signed-off-by: Ian Mun

[PATCH 11/15] cxl: Add support for interrupts on the Mellanox CX4

From: Ian Munsie <imun...@au1.ibm.com> The Mellanox CX4 in cxl mode uses a hybrid interrupt model, where interrupts are routed from the networking hardware to the XSL using the MSIX table, and from there will be transformed back into an MSIX interrupt using the cxl style interrupts (i.e.

[PATCH 12/15] cxl: Workaround PE=0 hardware limitation in Mellanox CX4

From: Ian Munsie <imun...@au1.ibm.com> The CX4 card cannot cope with a context with PE=0 due to a hardware limitation, resulting in: [ 34.166577] command failed, status limits exceeded(0x8), syndrome 0x5a7939 [ 34.166580] mlx5_core :01:00.1: Failed allocating uar, aborting

[PATCH 10/15] cxl: Add preliminary workaround for CX4 interrupt limitation

From: Ian Munsie <imun...@au1.ibm.com> The Mellanox CX4 has a hardware limitation where only 4 bits of the AFU interrupt number can be passed to the XSL when sending an interrupt, limiting it to only 15 interrupts per context (AFU interrupt number 0 is invalid). In order to overcome th

[PATCH 09/15] cxl: Add kernel APIs to get & set the max irqs per context

From: Ian Munsie <imun...@au1.ibm.com> These APIs will be used by the Mellanox CX4 support. While they function standalone to configure existing behaviour, their primary purpose is to allow the Mellanox driver to inform the cxl driver of a hardware limitation, which will be used in a future

[PATCH 08/15] cxl: Add support for using the kernel API with a real PHB

From: Ian Munsie <imun...@au1.ibm.com> This hooks up support for using the kernel API with a real PHB. After the AFU initialisation has completed it calls into the PHB code to pass it the AFU that will be used by other peer physical functions on the adapter. The cxl_pci_to_afu API is ex

[PATCH 07/15] powerpc/powernv: Add support for the cxl kernel api on the real phb

From: Ian Munsie <imun...@au1.ibm.com> This adds support for the peer model of the cxl kernel api to the PowerNV PHB, in which physical function 0 represents the cxl function on the card (an XSL in the case of the CX4), which other physical functions will use for memory access and int

[PATCH 06/15] cxl: Do not create vPHB if there are no AFU configuration records

From: Ian Munsie <imun...@au1.ibm.com> The vPHB model of the cxl kernel API is a hierarchy where the AFU is represented by the vPHB, and it's AFU configuration records are exposed as functions under that vPHB. If there are no AFU configuration records we will create a vPHB with nothing

[PATCH 05/15] cxl: Allow a default context to be associated with an external pci_dev

From: Ian Munsie <imun...@au1.ibm.com> The cxl kernel API has a concept of a default context associated with each PCI device under the virtual PHB. The Mellanox CX4 will also use the cxl kernel API, but it does not use a virtual PHB - rather, the AFU appears as a physical function as

[PATCH 03/15] cxl: Enable bus mastering for devices using CAPP DMA mode

From: Ian Munsie <imun...@au1.ibm.com> Devices that use CAPP DMA mode (such as the Mellanox CX4) require bus master to be enabled in order for the CAPI traffic to flow. This should be harmless to enable for other cxl devices, so unconditionally enable it in the adapter init flow. Sign

[PATCH 04/15] cxl: Move cxl_afu_get / cxl_afu_put to base

From: Ian Munsie <imun...@au1.ibm.com> The Mellanox CX4 uses a model where the AFU is one physical function of the device, and is used by other peer physical functions of the same device. This will require those other devices to grab a reference on the AFU when they are initialised to mak

[PATCH 02/15] cxl: Add cxl_slot_is_supported API

From: Ian Munsie <imun...@au1.ibm.com> This extends the check that the adapter is in a CAPI capable slot so that it may be called by external users in the kernel API. This will be used by the upcoming Mellanox CX4 support, which needs to know ahead of time if the card can be switched to cx

[PATCH 01/15] powerpc/powernv: Split cxl code out into a separate file

From: Ian Munsie <imun...@au1.ibm.com> The support for using the Mellanox CX4 in cxl mode will require additions to the PHB code. In preparation for this, move the existing cxl code out of pci-ioda.c into a separate pci-cxl.c file to keep things more organised. Signed-off-by: Ian Munsie

[PATCH v3] powerpc / cxl: Add support for the Mellanox CX4 in cxl mode

r pointing it out (Patch 13) - Added new error label for error paths calling pci_dev_put() - suggested by Ian Munsie (Patch 15) - Added newline at end of Kconfig (Patch 15) ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs

Re: [PATCH 05/15] cxl: Allow a default context to be associated with an external pci_dev

Excerpts from andrew.donnellan's message of 2016-07-13 15:52:45 +1000: > > +bool _cxl_pci_associate_default_context(struct pci_dev *dev, struct > > cxl_afu *afu) > > If we're sharing these functions between the vPHB and peer models, do we > have a better place than vphb.c for them? Sure, I

Re: [PATCH 07/15] powerpc/powernv: Add support for the cxl kernel api on the real phb

Excerpts from andrew.donnellan's message of 2016-07-12 20:39:13 +1000: > Some comments below - with those addressed: > > Reviewed-by: Andrew Donnellan Thanks for the review :) > > V1->V2: > > - Add an explanation of the peer model to the commit message, > >

[PATCH 15/15] cxl: Add cxl_check_and_switch_mode() API to switch bi-modal cards

roduce a new option, CONFIG_CXL_BIMODAL, with a dependency on the pnv_php driver. Refactor existing code that touches the mode control register in the regular single mode case into a new function, setup_cxl_protocol_area(). Co-authored-by: Ian Munsie <imun...@au1.ibm.com> Cc: Gav

[PATCH 14/15] PCI/hotplug: pnv_php: handle OPAL_PCI_SLOT_OFFLINE power state

ernel.org Cc: Bjorn Helgaas <bhelg...@google.com> Signed-off-by: Andrew Donnellan <andrew.donnel...@au1.ibm.com> Signed-off-by: Ian Munsie <imun...@au1.ibm.com> Acked-by: Gavin Shan <gws...@linux.vnet.ibm.com> --- drivers/pci/hotplug/pnv_php.c | 2 +- 1 file changed, 1 ins

[PATCH 10/15] cxl: Add preliminary workaround for CX4 interrupt limitation

From: Ian Munsie <imun...@au1.ibm.com> The Mellanox CX4 has a hardware limitation where only 4 bits of the AFU interrupt number can be passed to the XSL when sending an interrupt, limiting it to only 15 interrupts per context (AFU interrupt number 0 is invalid). In order to overcome th

[PATCH 08/15] cxl: Add support for using the kernel API with a real PHB

From: Ian Munsie <imun...@au1.ibm.com> This hooks up support for using the kernel API with a real PHB. After the AFU initialisation has completed it calls into the PHB code to pass it the AFU that will be used by other peer physical functions on the adapter. The cxl_pci_to_afu API is ex

[PATCH 13/15] PCI/hotplug: pnv_php: export symbols and move struct types needed by cxl

onding declarations, as well as the definition of struct pnv_php_slot, to asm/pnv-pci.h. Cc: Gavin Shan <gws...@linux.vnet.ibm.com> Cc: linux-...@vger.kernel.org Cc: Bjorn Helgaas <bhelg...@google.com> Signed-off-by: Andrew Donnellan <andrew.donnel...@au1.ibm.com> Signed-off-by: Ian Mun

[PATCH 12/15] cxl: Workaround PE=0 hardware limitation in Mellanox CX4

From: Ian Munsie <imun...@au1.ibm.com> The CX4 card cannot cope with a context with PE=0 due to a hardware limitation, resulting in: [ 34.166577] command failed, status limits exceeded(0x8), syndrome 0x5a7939 [ 34.166580] mlx5_core :01:00.1: Failed allocating uar, aborting

[PATCH 05/15] cxl: Allow a default context to be associated with an external pci_dev

From: Ian Munsie <imun...@au1.ibm.com> The cxl kernel API has a concept of a default context associated with each PCI device under the virtual PHB. The Mellanox CX4 will also use the cxl kernel API, but it does not use a virtual PHB - rather, the AFU appears as a physical function as

[PATCH 11/15] cxl: Add support for interrupts on the Mellanox CX4

From: Ian Munsie <imun...@au1.ibm.com> The Mellanox CX4 in cxl mode uses a hybrid interrupt model, where interrupts are routed from the networking hardware to the XSL using the MSIX table, and from there will be transformed back into an MSIX interrupt using the cxl style interrupts (i.e.

[PATCH 09/15] cxl: Add kernel APIs to get & set the max irqs per context

From: Ian Munsie <imun...@au1.ibm.com> These APIs will be used by the Mellanox CX4 support. While they function standalone to configure existing behaviour, their primary purpose is to allow the Mellanox driver to inform the cxl driver of a hardware limitation, which will be used in a future

[PATCH 07/15] powerpc/powernv: Add support for the cxl kernel api on the real phb

From: Ian Munsie <imun...@au1.ibm.com> This adds support for the peer model of the cxl kernel api to the PowerNV PHB, in which physical function 0 represents the cxl function on the card (an XSL in the case of the CX4), which other physical functions will use for memory access and int

[PATCH 06/15] cxl: Do not create vPHB if there are no AFU configuration records

From: Ian Munsie <imun...@au1.ibm.com> The vPHB model of the cxl kernel API is a hierarchy where the AFU is represented by the vPHB, and it's AFU configuration records are exposed as functions under that vPHB. If there are no AFU configuration records we will create a vPHB with nothing

[PATCH v2] powerpc / cxl: Add support for the Mellanox CX4 in cxl mode

on. Thanks to Gavin Shan for pointing it out (Patch 13) - Added new error label for error paths calling pci_dev_put() - suggested by Ian Munsie (Patch 15) - Added newline at end of Kconfig (Patch 15) ___ Linuxppc-dev mailing list Li

[PATCH 04/15] cxl: Move cxl_afu_get / cxl_afu_put to base

From: Ian Munsie <imun...@au1.ibm.com> The Mellanox CX4 uses a model where the AFU is one physical function of the device, and is used by other peer physical functions of the same device. This will require those other devices to grab a reference on the AFU when they are initialised to mak

[PATCH 03/15] cxl: Enable bus mastering for devices using CAPP DMA mode

From: Ian Munsie <imun...@au1.ibm.com> Devices that use CAPP DMA mode (such as the Mellanox CX4) require bus master to be enabled in order for the CAPI traffic to flow. This should be harmless to enable for other cxl devices, so unconditionally enable it in the adapter init flow. Sign

[PATCH 02/15] cxl: Add cxl_slot_is_supported API

From: Ian Munsie <imun...@au1.ibm.com> This extends the check that the adapter is in a CAPI capable slot so that it may be called by external users in the kernel API. This will be used by the upcoming Mellanox CX4 support, which needs to know ahead of time if the card can be switched to cx

[PATCH 01/15] powerpc/powernv: Split cxl code out into a separate file

From: Ian Munsie <imun...@au1.ibm.com> The support for using the Mellanox CX4 in cxl mode will require additions to the PHB code. In preparation for this, move the existing cxl code out of pci-ioda.c into a separate pci-cxl.c file to keep things more organised. Signed-off-by: Ian Munsie

Re: [PATCH 14/14] cxl: Add cxl_check_and_switch_mode() API to switch bi-modal cards

Excerpts from andrew.donnellan's message of 2016-07-07 18:15:06 +1000: > On 07/07/16 16:44, Andrew Donnellan wrote: > > We can match the vendor, device ID *and* class code - unfortunately > > there isn't a macro for this, which makes it a little bit less > > aesthetically pleasing, but I'm pretty

Re: [PATCH 07/14] cxl: Add support for using the kernel API with a real PHB

Excerpts from Frederic Barrat's message of 2016-07-06 20:30:41 +0200: > > > @@ -1572,6 +1575,9 @@ static pci_ers_result_t cxl_pci_error_detected(struct > > pci_dev *pdev, > >*/ > > for (i = 0; i < adapter->slices; i++) { > > afu = adapter->afu[i]; > > +

Re: [PATCH 06/14] powerpc/powernv: Add support for the cxl kernel api on the real phb

Excerpts from Frederic Barrat's message of 2016-07-06 19:38:18 +0200: > > > +/* No special handling for cxl function: */ > > +if (PCI_FUNC(dev->devfn) == 0) > > +return true; > > I believe that is the first time we're getting a hint of the black magic > which is going to occur

Re: [PATCH 14/14] cxl: Add cxl_check_and_switch_mode() API to switch bi-modal cards

Excerpts from andrew.donnellan's message of 2016-07-07 11:18:37 +1000: > > This is to balance the 'get' done in cxl_check_and_switch_mode(), right? > > A comment wouldn't hurt. I think we're missing the 'put' on the first > > error path above (!bridge). > > Yep, it's to balance the pci_dev_get()

Re: [PATCH 10/14] cxl: Add support for interrupts on the Mellanox CX4

Excerpts from Frederic Barrat's message of 2016-07-06 20:41:42 +0200: > I think we want: > if (WARN_ON(hwirq <= 0)) > cxl_find_afu_irq() returns 0 if doesn't find the irq, which is not > supposed to happen here. Good catch - will fix in v2. Cheers, -Ian

Re: [PATCH 08/14] cxl: Add kernel APIs to get & set the max irqs per context

Excerpts from Frederic Barrat's message of 2016-07-06 20:11:48 +0200: > > Le 04/07/2016 15:22, Ian Munsie a écrit : > > From: Ian Munsie <imun...@au1.ibm.com> > > > > These APIs will be used by the Mellanox CX4 support. While they function > > standa

Re: [PATCH v3] cxl: Refine slice error debug messages

Acked-by: Ian Munsie <imun...@au1.ibm.com> ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev

Re: [PATCH v2] cxl: Refine slice error debug messages

I agree with Mikey - this needs a description. But otherwise it looks good to me, and I'll be happy if it stops any more AFU developers from reporting their bugs to us, so happy to add this now: Acked-by: Ian Munsie <imun...@au1.ibm.com> Excerpts from Philippe Bergheaud's message of 2016

[PATCH 10/14] cxl: Add support for interrupts on the Mellanox CX4

From: Ian Munsie <imun...@au1.ibm.com> The Mellanox CX4 in cxl mode uses a hybrid interrupt model, where interrupts are routed from the networking hardware to the XSL using the MSIX table, and from there will be transformed back into an MSIX interrupt using the cxl style interrupts (i.e.

[PATCH 04/14] cxl: Move cxl_afu_get / cxl_afu_put to base

From: Ian Munsie <imun...@au1.ibm.com> The Mellanox CX4 uses a model where the AFU is one physical function of the device, and is used by other peer physical functions of the same device. This will require those other devices to grab a reference on the AFU when they are initialised to mak

[PATCH 02/14] cxl: Add cxl_slot_is_supported API

From: Ian Munsie <imun...@au1.ibm.com> This extends the check that the adapter is in a CAPI capable slot so that it may be called by external users in the kernel API. This will be used by the upcoming Mellanox CX4 support, which needs to know ahead of time if the card can be switched to cx

[PATCH 14/14] cxl: Add cxl_check_and_switch_mode() API to switch bi-modal cards

roduce a new option, CONFIG_CXL_BIMODAL, with a dependency on the pnv_php driver. Refactor existing code that touches the mode control register in the regular single mode case into a new function, setup_cxl_protocol_area(). Co-authored-by: Ian Munsie <imun...@au1.ibm.com> Cc: Gav

[PATCH 13/14] PCI/hotplug: pnv_php: handle OPAL_PCI_SLOT_OFFLINE power state

From: Andrew Donnellan When calling pnv_php_set_slot_power_state() with state == OPAL_PCI_SLOT_OFFLINE, remove devices from the device tree as if we're dealing with OPAL_PCI_SLOT_POWER_OFF. Cc: Gavin Shan Cc: linux-...@vger.kernel.org

[PATCH 12/14] PCI/hotplug: pnv_php: export symbols and move struct types needed by cxl

From: Andrew Donnellan The cxl driver will use infrastructure from pnv_php to handle device tree updates when switching bi-modal CAPI cards into CAPI mode. To enable this, export pnv_php_find_slot() and pnv_php_set_slot_power_state(), and add corresponding

[PATCH 11/14] cxl: Workaround PE=0 hardware limitation in Mellanox CX4

From: Ian Munsie <imun...@au1.ibm.com> The CX4 card cannot cope with a context with PE=0 due to a hardware limitation, resulting in: [ 34.166577] command failed, status limits exceeded(0x8), syndrome 0x5a7939 [ 34.166580] mlx5_core :01:00.1: Failed allocating uar, aborting

[PATCH 09/14] cxl: Add preliminary workaround for CX4 interrupt limitation

From: Ian Munsie <imun...@au1.ibm.com> The Mellanox CX4 has a hardware limitation where only 4 bits of the AFU interrupt number can be passed to the XSL when sending an interrupt, limiting it to only 15 interrupts per context (AFU interrupt number 0 is invalid). In order to overcome th

[PATCH 08/14] cxl: Add kernel APIs to get & set the max irqs per context

From: Ian Munsie <imun...@au1.ibm.com> These APIs will be used by the Mellanox CX4 support. While they function standalone to configure existing behaviour, their primary purpose is to allow the Mellanox driver to inform the cxl driver of a hardware limitation, which will be used in a future

[PATCH 07/14] cxl: Add support for using the kernel API with a real PHB

From: Ian Munsie <imun...@au1.ibm.com> This hooks up support for using the kernel API with a real PHB. After the AFU initialisation has completed it calls into the PHB code to pass it the AFU that will be used by other peer physical functions on the adapter. The cxl_pci_to_afu API is ex

[PATCH 06/14] powerpc/powernv: Add support for the cxl kernel api on the real phb

From: Ian Munsie <imun...@au1.ibm.com> This adds support for the peer model of the cxl kernel api to the PowerNV PHB, and exports APIs to enable the mode, check if a PCI device is attached to a PHB in this mode, and to set and get the peer AFU for this mode. The cxl driver will enable thi

[PATCH 05/14] cxl: Allow a default context to be associated with an external pci_dev

From: Ian Munsie <imun...@au1.ibm.com> The cxl kernel API has a concept of a default context associated with each PCI device under the virtual PHB. The Mellanox CX4 will also use the cxl kernel API, but it does not use a virtual PHB - rather, the AFU appears as a physical function as

[PATCH 03/14] cxl: Enable bus mastering for devices using CAPP DMA mode

From: Ian Munsie <imun...@au1.ibm.com> Devices that use CAPP DMA mode (such as the Mellanox CX4) require bus master to be enabled in order for the CAPI traffic to flow. This should be harmless to enable for other cxl devices, so unconditionally enable it in the adapter init flow. Sign

[PATCH 01/14] powerpc/powernv: Split cxl code out into a separate file

From: Ian Munsie <imun...@au1.ibm.com> The support for using the Mellanox CX4 in cxl mode will require additions to the PHB code. In preparation for this, move the existing cxl code out of pci-ioda.c into a separate pci-cxl.c file to keep things more organised. Signed-off-by: Ian Munsie

powerpc / cxl: Add support for the Mellanox CX4 in cxl mode

This series adds support for the Mellanox CX4 network adapter operating in cxl mode to the cxl driver and the PowerNV PHB code. The Mellanox developers will submit a separate patch series that makes use of this in the mlx5 driver. The CX4 card can operate in either pci mode, or cxl mode. In cxl

Re: [PATCH] cxl: remove dead Kconfig options

Acked-by: Ian Munsie <imun...@au1.ibm.com> ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev

Re: [PATCH v2] cxl: Ignore CAPI adapters misplaced in switched slots

Acked-by: Ian Munsie <imun...@au1.ibm.com> ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev

Re: [PATCH] cxl: make base more explicitly non-modular

Acked-by: Ian Munsie <imun...@au1.ibm.com> ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev

[PATCH] powerpc/fadump: Fix compile error due to missing semicolon

From: Ian Munsie <imun...@au1.ibm.com> The commit "powerpc/fadump: trivial fix of spelling mistake, clean up message" removed a semicolon causing the following compile failure: arch/powerpc/kernel/fadump.c: In function ‘fadump_invalidate_dump’: arch/powerpc/kernel/fadump

Re: [PATCH] cxl: Ignore CAPI adapters misplaced in switched slots

Thanks Philippe - this looks like a decent solution to the problem (and I intend to use this for the upcoming cx4 support as well). Acked-by: Ian Munsie <imun...@au1.ibm.com> Excerpts from Philippe Bergheaud's message of 2016-06-30 13:45:37 +0200: > One should not attempt to swi

[PATCH v2] cxl: Fix bug where AFU disable operation had no effect

From: Ian Munsie <imun...@au1.ibm.com> The AFU disable operation has a bug where it will not clear the enable bit and therefore will have no effect. To date this has likely been masked by fact that we perform an AFU reset before the disable, which also has the effect of clearing the enab

Re: [PATCH 1/2] cxl: Fix bug where AFU disable operation had no effect

Excerpts from Frederic Barrat's message of 2016-06-30 17:50:00 +0200: > > Le 30/06/2016 17:32, Ian Munsie a écrit : > >> For dedicated mode, the CAIA recommends an explicit reset of the AFU > >> >(section 2.1.1). > > True, I had forgotten that procedure

Re: [PATCH 1/2] cxl: Fix bug where AFU disable operation had no effect

Excerpts from Frederic Barrat's message of 2016-06-30 16:19:54 +0200: > I'm not a big fan of the new "clear" argument, which forces us to pass > an extra 0 most of the time. Why not always clearing the "action" bits > of the register before applying the command? They are mutually > exclusive,

Re: [PATCH] cxl: Fix NULL pointer dereference on kernel contexts with no AFU interrupts

Excerpts from andrew.donnellan's message of 2016-06-30 15:15:02 +1000: > On 30/06/16 15:00, Michael Ellerman wrote: > > On Thu, 2016-06-30 at 08:28 +1000, Andrew Donnellan wrote: > >> On 30/06/16 04:55, Ian Munsie wrote: > >>> > >>> From: Ian Munsie <

[PATCH] cxl: Fix NULL pointer dereference on kernel contexts with no AFU interrupts

From: Ian Munsie <imun...@au1.ibm.com> If a kernel context is initialised and does not have any AFU interrupts allocated it will cause a NULL pointer dereference when the context is detached since the irq_names list will not have been initialised. Move the initialisation of the irq_name

[PATCH 2/2] cxl: Workaround XSL bug that does not clear the RA bit after a reset

From: Ian Munsie <imun...@au1.ibm.com> An issue was noted in our debug logs where the XSL would leave the RA bit asserted after an AFU reset operation, which would effectively prevent further AFU reset operations from working. Workaround the issue by clearing the RA bit with an MMIO

[PATCH 1/2] cxl: Fix bug where AFU disable operation had no effect

From: Ian Munsie <imun...@au1.ibm.com> The AFU disable operation has a bug where it will not clear the enable bit and therefore will have no effect. To date this has likely been masked by fact that we perform an AFU reset before the disable, which also has the effect of clearing the enab

[PATCH 2/2] cxl: Fix allocating a minimum of 2 pages for the SPA

From: Ian Munsie <imun...@au1.ibm.com> The Scheduled Process Area is allocated dynamically with enough pages to fit at least as many processes as the AFU descriptor indicated. Since the calculation is non-trivial, it does this by calculating how many processes could fit in an allo

[PATCH 1/2] cxl: Fix allowing bogus AFU descriptors with 0 maximum processes

From: Ian Munsie <imun...@au1.ibm.com> If the AFU descriptor of an AFU directed AFU indicates that it supports 0 maximum processes, we will accept that value and attempt to use it. The SPA will still be allocated (with 2 pages due to another minor bug and room for 958 processes), an

Re: [v6, 1/2] cxl: Add mechanism for delivering AFU driver specific events

Excerpts from Vaibhav Jain's message of 2016-06-20 14:20:16 +0530: > > +int cxl_unset_driver_ops(struct cxl_context *ctx) > > +{ > > +if (atomic_read(>afu_driver_events)) > > +return -EBUSY; > > + > > +ctx->afu_driver_ops = NULL; > Need a write memory barrier so that afu_driver_ops

Re: [PATCH] powerpc/mm: Prevent unlikely crash in copro_calculate_slb()

Acked-by: Ian Munsie <imun...@au1.ibm.com> ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev

Re: [PATCH] cxl: Make vPHB device node match adapter's

This could probably use a description in the commit message, perhaps including output showing the before/after difference this makes to lsvpd, but otherwise it looks fine to me. @Mikey - this look OK to you? Acked-by: Ian Munsie <imun...@au1.ibm.com> Excerpts from Frederic Barrat's m

[PATCH, RFC] cxl: Add support for CAPP DMA mode

From: Ian Munsie <imun...@au1.ibm.com> This adds support for using CAPP DMA mode, which is required for XSL based cards such as the Mellanox CX4 to function. This is currently an RFC as it depends on the corresponding support to be merged into skiboot first, which was submitted here

[PATCH] cxl: Abstract the differences between the PSL and XSL

ve one interrupt. The XSL also uses a special DMA cxl mode, which uses a slightly different init sequence for the CAPP and PHB. The kernel support for this will be in a future patch once the corresponding support has been merged into skiboot. Co-authored-by: Ian Munsie <imun...@au1.ibm.com> Signed

[PATCH] cxl: Update process element after allocating interrupts

From: Ian Munsie <imun...@au1.ibm.com> In the kernel API, it is possible to attempt to allocate AFU interrupts after already starting a context. Since the process element structure used by the hardware is only filled out at the time the context is started, it will not be u

Re: [PATCH] cxl: Refine slice error debug messages.

Acked-by: Ian Munsie <imun...@au1.ibm.com> ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev

[PATCH v2] cxl: Add kernel API to allow a context to operate with relocate disabled

From: Ian Munsie <imun...@au1.ibm.com> cxl devices typically access memory using an MMU in much the same way as the CPU, and each context includes a state register much like the MSR in the CPU. Like the CPU, the state register includes a bit to enable relocation, which we currently always

Re: [PATCH] cxl: Add kernel API to allow a context to operate with relocate disabled

Sure thing, that actually simplifies things a great deal. Testing now and will resend shortly :) -Ian ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev

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