Drop it now :)
However, it may be nice to keep the A2 stuff until BGQ EOLs
-jx
On Wed, Nov 20, 2013 at 8:40 PM, Michael Neuling mi...@neuling.org wrote:
chroma_defconfig is horribly broken currently, so add a bunch of
#includes to fix it.
Signed-off-by: Michael Neuling mi...@neuling.org
On Dec 18, 2012, at 10:31 AM, Peter Bergner berg...@vnet.ibm.com wrote:
On Tue, 2012-12-18 at 07:28 -0600, Jimi Xenidis wrote:
On Dec 17, 2012, at 6:26 PM, Peter Bergner berg...@vnet.ibm.com wrote:
Jimi, are you using an old binutils from before my patch that
changed the operand order
On Dec 17, 2012, at 5:33 AM, Anton Blanchard an...@samba.org wrote:
Hi Jimi,
I know this is a little late, but shouldn't these power7 specific
thingies be in obj-$(CONFIG_PPC_BOOK3S_64). The reason I ask is
that my compiler pukes on dcbtst and as I deal with that I wanted
to point this
On Dec 17, 2012, at 6:26 PM, Peter Bergner berg...@vnet.ibm.com wrote:
On Mon, 2012-12-17 at 22:33 +1100, Anton Blanchard wrote:
Hi Jimi,
I know this is a little late, but shouldn't these power7 specific
thingies be in obj-$(CONFIG_PPC_BOOK3S_64). The reason I ask is
that my compiler
Mikey
Here is a are the summary logs:
$ git log --reverse linux-stable/linux-3.4.y..
commit 5a8edb2bdd914597693eed299119ff4c2e6d31f2
Author: Jimi Xenidis ji...@pobox.com
Date: Fri Nov 9 09:26:00 2012 -0600
powerpc: Fix cputable #ifdef where CONFIG_PPC_A2
On Dec 10, 2012, at 3:32 PM, Jimi Xenidis ji...@pobox.com wrote:
On Dec 7, 2012, at 8:31 AM, Andrew Tauferner atau...@us.ibm.com wrote:
Jimi,
Do you actually want this upstream? I assume no.
I needed to get these long-term patches out there for the BGQ
community for test
On Dec 9, 2012, at 6:47 PM, Michael Neuling mi...@neuling.org wrote:
Jimi Xenidis ji...@pobox.com wrote:
On Dec 7, 2012, at 7:38 AM, Jimi Xenidis ji...@pobox.com wrote:
On Dec 6, 2012, at 11:54 PM, Michael Neuling mi...@neuling.org wrote:
commit
On Dec 7, 2012, at 7:38 AM, Jimi Xenidis ji...@pobox.com wrote:
On Dec 6, 2012, at 11:54 PM, Michael Neuling mi...@neuling.org wrote:
commit 279c0615917b959a652e81f4ad0d886e2d426d85
Author: Jimi Xenidis ji...@pobox.com
Date: Wed Dec 5 13:43:22 2012 -0500
powerpc/book3e: IBM Blue
On Dec 6, 2012, at 11:41 PM, Michael Neuling mi...@neuling.org wrote:
commit f6e3c1f706cb6922349d639a74ff6c50acc8b9f8
Author: Jimi Xenidis ji...@pobox.com
Date: Wed Dec 5 13:41:25 2012 -0500
powerpc: Remove unecessary VSX symbols
The symbol THREAD_VSR0 is defined to be the same
On Dec 6, 2012, at 11:54 PM, Michael Neuling mi...@neuling.org wrote:
commit 279c0615917b959a652e81f4ad0d886e2d426d85
Author: Jimi Xenidis ji...@pobox.com
Date: Wed Dec 5 13:43:22 2012 -0500
powerpc/book3e: IBM Blue Gene/Q Quad Processing eXtention (QPX)
This enables kernel
On Dec 6, 2012, at 11:56 PM, Michael Neuling mi...@neuling.org wrote:
Jimi Xenidis ji...@pobox.com wrote:
Rather than flood the mailing list with the patches, I've arranged for a git
repo to hold the changesets.
You can find the repo here:
https://github.com/jimix/linux-bgq
On May 31, 2012, at 1:22 AM, Anton Blanchard an...@samba.org wrote:
Implement a POWER7 optimised memcpy using VMX and enhanced prefetch
instructions.
snip
Index: linux-build/arch/powerpc/lib/Makefile
===
---
and the rest are BGQ specific.
Here is a are the summary logs:
$ git log --reverse linux-stable/linux-3.4.y..
commit 5a8edb2bdd914597693eed299119ff4c2e6d31f2
Author: Jimi Xenidis ji...@pobox.com
Date: Fri Nov 9 09:26:00 2012 -0600
powerpc: Fix cputable #ifdef where CONFIG_PPC_A2 is used
Sorry for the pause, lots of other things getting done... questions below.
On Nov 9, 2012, at 10:33 PM, Michael Neuling mi...@neuling.org wrote:
Benjamin Herrenschmidt b...@kernel.crashing.org wrote:
On Fri, 2012-11-09 at 11:43 -0600, Jimi Xenidis wrote:
The CPU_FTR_* values are pretty
the hold process, so we make
sure that happens.
2) Book3e has no real mode, and the hold code exploits this. Since
these processors ares always translated, we arrange for the kexeced
threads to enter the hold code using the normal kernel linear mapping.
Signed-off-by: Jimi Xenidis ji
So interrupts need to go to FW before Linux, please let not talk about how
silly that is.
Lets talk about something far more silly...
In order to get to the Linux exception handlers, we have to tell FW where the
interrupt page is, and then it _copies_ it.
IFAICT, this means that each vectors on
The CPU_FTR_* values are pretty tight (a few bits left) yes I need to save and
restore the QPX registers.
There are 32 QPX registers, each 32 bytes in size, it is otherwise managed by
the FPSCR and MSR[FP]
I was thinking that I could hijack the VSX, since there is no plan to add it to
embedded
On Nov 4, 2012, at 9:23 PM, Jimi Xenidis wrote:
On Nov 4, 2012, at 5:51 PM, Benjamin Herrenschmidt b...@kernel.crashing.org
wrote:
On Sun, 2012-11-04 at 10:32 -0600, Jimi Xenidis wrote:
I want to use the stuff in arch/platform/sysdev/dcr.c and I have a couple
of questions:
1
I want to use the stuff in arch/platform/sysdev/dcr.c and I have a couple of
questions:
1) anyone have a good devtree binding for this?
I'm thinking:
bgq {
#address-cells = 2;
#size-cells = 2;
...
dcr {
On Nov 4, 2012, at 5:51 PM, Benjamin Herrenschmidt b...@kernel.crashing.org
wrote:
On Sun, 2012-11-04 at 10:32 -0600, Jimi Xenidis wrote:
I want to use the stuff in arch/platform/sysdev/dcr.c and I have a couple of
questions:
1) anyone have a good devtree binding for this?
Not really
, which is heavy handed, but unfortunately
still provides a window where the icswx is issued by other threads and
the ACOP is not up to date.
This patch detects that the ACOP DSI fault was a false positive and
syncs the ACOP and causes the icswx to be replayed.
Signed-off-by: Jimi Xenidis ji
On Feb 26, 2012, at 5:47 PM, Benjamin Herrenschmidt wrote:
+/*
+ * We could be here because another thread has enabled acop
+ * but the ACOP register has yet to be updated.
+ *
+ * This should have been taken care of by the IPI to sync all
+ * the threads (see
, which is heavy handed, but unfortunately
still provides a window where the icswx is issued by other threads and
the ACOP is not up to date.
This patch detects that the ACOP DSI fault was a false positive and
syncs the ACOP and causes the icswx to be replayed.
Signed-off-by: Jimi Xenidis ji
this by selecting the new OF_DYNAMIC when PPC_CHROMA.
Signed-off-by: Michael Neuling mi...@neuling.org
Acked-by: Jimi Xenidis ji...@pobox.com
diff --git a/arch/powerpc/platforms/wsp/Kconfig
b/arch/powerpc/platforms/wsp/Kconfig
index 57d22a2..79d2225 100644
--- a/arch/powerpc/platforms/wsp
On Oct 31, 2011, at 9:18 AM, Kumar Gala wrote:
On Oct 28, 2011, at 2:40 PM, Jimi Xenidis wrote:
On Oct 5, 2011, at 9:53 PM, Kumar Gala wrote:
We had an existing ifdef for 4xx BOOKE processors that got changed to
CONFIG_PPC_ADV_DEBUG_REGS. The define has nothing to do
On Oct 31, 2011, at 9:21 AM, Kumar Gala wrote:
On Oct 28, 2011, at 2:37 PM, Jimi Xenidis wrote:
On Oct 5, 2011, at 9:53 PM, Kumar Gala wrote:
* set_dabr/do_dabr are no longer used when CNFIG_PPC_ADV_DEBUG_REGS is set
refactor code a bit such that we only build the dabr code
On Oct 5, 2011, at 9:53 PM, Kumar Gala wrote:
* set_dabr/do_dabr are no longer used when CNFIG_PPC_ADV_DEBUG_REGS is set
refactor code a bit such that we only build the dabr code for
!CONFIG_PPC_ADV_DEBUG_REGS and removed some CONFIG_PPC_ADV_DEBUG_REGS
code in set_dabr that would never
On Oct 5, 2011, at 9:53 PM, Kumar Gala wrote:
We had an existing ifdef for 4xx BOOKE processors that got changed to
CONFIG_PPC_ADV_DEBUG_REGS. The define has nothing to do with
CONFIG_PPC_ADV_DEBUG_REGS. The define really should be:
#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
arch/powerpc/kernel/head_fsl_booke.S has the following code:
/* Data Storage Interrupt */
START_EXCEPTION(DataStorage)
NORMAL_EXCEPTION_PROLOG
mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
stw r5,_ESR(r11)
mfspr r4,SPRN_DEAR
On Tue Oct 4 05:02:41 EST 2011, Scott Wood wrote:
Looking at your comments below, will the following be acceptable
On 09/29/2011 09:27 PM, Jimi Xenidis wrote:
diff --git a/arch/powerpc/platforms/wsp/Kconfig
b/arch/powerpc/platforms/wsp/Kconfig
index ea2811c..a3eef8e 100644
--- a/arch
-by: Jimi Xenidis ji...@pobox.com
---
Re: ga...@kernel.crashing.org
use make savedefconfig
ARGH!: apparently make savedefconfig does not clean up the INITRAMFS_SOURCE
---
arch/powerpc/configs/chroma_defconfig | 307 +
arch/powerpc/platforms/wsp/Kconfig| 11
the primary xmon's output. This patch fixes it, by ignoring
the RI bit if the processor does not support it.
There's already a version of this for 4xx upstream, which we'll need
to extend to other RI-lacking CPUs at some point. For now this adds
Book3e processors to the mix.
Signed-off-by: Jimi
Some processors, like embedded, that already have a PID register that
is managed by the system. This patch separates the ACOP and PID
processing into separate files so that the ACOP code can be shared.
Signed-off-by: Jimi Xenidis ji...@pobox.com
---
Re: b...@kernel.crashing.org
rebase
ICSWX is also used by the A2 processor to access coprocessors,
although not all chips that contain A2s have coprocessors.
Signed-off-by: Jimi Xenidis ji...@pobox.com
---
Re: ga...@kernel.crashing.org
Fix white space *embarrassed*
Re: b...@kernel.crashing.org
rebase
---
arch/powerpc
not used the record form (icswx) then it is
selectable by config whether the failure is silent (as architected) or
a SIGILL is generated.
In all cases pr_warn() is used to log the bad CT.
Signed-off-by: Jimi Xenidis ji...@pobox.com
---
Re: ga...@kernel.crashing.org
- Fix Kconfig/CONFIG
The 'u' command will print the TLB on book3e parts and the SLB on
Book3s parts, but the help system doesn't say that correctly.
Signed-off-by: Jimi Xenidis ji...@pobox.com
---
arch/powerpc/xmon/xmon.c | 14 +-
1 files changed, 5 insertions(+), 9 deletions(-)
diff --git a/arch
Sorry, there was a typo in the #if
signed-off-by: Jimi Xenidis ji...@pobox.com
---
arch/powerpc/xmon/xmon.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index 13f82f8..e88e7f5 100644
--- a/arch/powerpc/xmon/xmon.c
On Sep 29, 2011, at 6:52 PM, Kumar Gala ga...@kernel.crashing.org wrote:
On Sep 29, 2011, at 4:55 PM, Jimi Xenidis wrote:
arch/powerpc/configs/chroma_defconfig | 1817
+
Seems kind big, you probably need a 'make savedefconfig' ;)
wow had no idea
-by: Jimi Xenidis ji...@pobox.com
---
Re: ga...@kernel.crashing.org
use make savedefconfig
---
arch/powerpc/configs/chroma_defconfig | 307 +
arch/powerpc/platforms/wsp/Kconfig| 11 +-
arch/powerpc/platforms/wsp/Makefile |8 +-
arch/powerpc/platforms
the primary xmon's output. This patch fixes it, by ignoring
the RI bit if the processor does not support it.
There's already a version of this for 4xx upstream, which we'll need
to extend to other RI-lacking CPUs at some point. For now this adds
Book3e processors to the mix.
Signed-off-by: Jimi
Some processors, like embedded, that already have a PID register that
is managed by the system. This patch separates the ACOP and PID
processing into separate files so that the ACOP code can be shared.
Signed-off-by: Jimi Xenidis ji...@pobox.com
---
Re: ga...@kernel.crashing.org
Fix typo
ICSWX is also used by the A2 processor to access coprocessors,
although not all chips that contain A2s have coprocessors.
Signed-off-by: Jimi Xenidis ji...@pobox.com
---
Re: ga...@kernel.crashing.org
Fix white space *embarrassed*
---
arch/powerpc/include/asm/cputable.h |2 +-
arch
not used the record form (icswx) then it is
selectable by config whether the failure is silent (as architected) or
a SIGILL is generated.
In all cases pr_warn() is used to log the bad CT.
Signed-off-by: Jimi Xenidis ji...@pobox.com
---
Re: ga...@kernel.crashing.org
- Fix Kconfig/CONFIG mismatch
On Sep 23, 2011, at 11:32 AM, Scott Wood wrote:
On 09/23/2011 10:01 AM, Jimi Xenidis wrote:
From: David Gibson d...@au1.ibm.com
Based on patch by David Gibson d...@au1.ibm.com
xmon has a longstanding bug on systems which are SMP-capable but lack
the MSR[RI] bit. In these cases, xmon
On Sep 14, 2011, at 2:43 PM, Anton Blanchard wrote:
Hi Anton,
It would really help me a lot if you could review and maybe merge this with my
earlier patch that splits this file.
http://patchwork.ozlabs.org/patch/109103/
All it does is split.. I promise.
You don't have to take the other
On Aug 30, 2011, at 1:08 PM, Scott Wood wrote:
On 08/30/2011 01:11 AM, Benjamin Herrenschmidt wrote:
On Mon, 2011-08-08 at 16:25 -0500, Jimi Xenidis wrote:
From: David Gibson d...@au1.ibm.com
Based on patch by David Gibson d...@au1.ibm.com
xmon has a longstanding bug on systems which
I have some and use them in some code, they represent ISA 2.06 MAVN=1 (version
2)
Can I keep them?
if so, should I put them somewhere useful to others?
Examples:
union mas1 {
u32 _val;
struct {
u32 v:1;
u32 iprot:1;
u32 tid:14;
On Aug 10, 2011, at 12:25 PM, Kumar Gala wrote:
On Aug 10, 2011, at 12:21 PM, Jimi Xenidis wrote:
I have some and use them in some code, they represent ISA 2.06 MAVN=1
(version 2)
Can I keep them?
if so, should I put them somewhere useful to others?
Examples:
union mas1 {
u32
On Aug 10, 2011, at 12:25 PM, David Laight wrote:
I have some and use them in some code, they represent ISA
2.06 MAVN=1 (version 2)
Can I keep them?
if so, should I put them somewhere useful to others?
Examples:
union mas1 {
u32 _val;
struct {
u32 v:1;
On Aug 9, 2011, at 12:26 AM, Kumar Gala wrote:
On Aug 8, 2011, at 5:26 PM, Jimi Xenidis wrote:
This patch adds a fault handler that responds to illegal Coprocessor
types. Currently all CTs are treated and illegal. There are two ways
to report the fault back to the application
On Aug 9, 2011, at 10:15 AM, Benjamin Herrenschmidt wrote:
On Tue, 2011-08-09 at 00:26 -0500, Kumar Gala wrote:
+ /* Some implementations leave us a hint for the CT */
+ ct = ICSWX_GET_CT_HINT(error_code);
+ if (ct 0) {
+ /* we have to peek at the instruction work to
the primary xmon's output. This patch fixes it, by ignoring
the RI bit if the processor does not support it.
There's already a version of this for 4xx upstream, which we'll need
to extend to other RI-lacking CPUs at some point. For now this adds
BookE processors to the mix.
Signed-off-by: Jimi
Some config selections were applied to the platform (reference board)
when they actuall apply to the chip.
Signed-off-by: Jimi Xenidis ji...@pobox.com
---
arch/powerpc/platforms/wsp/Kconfig |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/platforms/wsp
The following patches deal with the fact that Book3e parts already
have a PID register that is managed by the system. Currently an ICSWX
not in the ACOP will get rejected as specified by both architectures.
-JX
___
Linuxppc-dev mailing list
Some processors, like embedded, that already have a PID register that
is managed by the system. This patch separates the ACOP and PID
processing into separate files so that the ACOP code can be shared.
Signed-off-by: Jimi Xenidis ji...@pobox.com
---
arch/powerpc/mm/Makefile |4
ICSWX is also used by the A2 processor to access coprocessors,
although not all chips that contain A2s have coprocessors.
Signed-off-by: Jimi Xenidis ji...@pobox.com
---
arch/powerpc/include/asm/cputable.h |2 +-
arch/powerpc/include/asm/mmu-book3e.h |4
arch/powerpc/include/asm
not used the record form (icswx) then it is
selectable by config whether the failure is silent (as architected) or
a SIGILL is generated.
In all cases pr_warn() is used to log the bad CT.
Signed-off-by: Jimi Xenidis ji...@pobox.com
---
arch/powerpc/mm/fault.c| 16 +
arch
Based on patchs from:
Benjamin Herrenschmidt b...@kernel.crashing.org
Michael Ellerman mich...@ellerman.id.au
I just brought them up to date
-JX
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
From: Benjamin Herrenschmidt b...@kernel.crashing.org
Based on a patch by Benjamin Herrenschmidt b...@kernel.crashing.org
Modernized and slightly modified to not record erros into the nvram
log since we do not have that device driver just yet.
Jimi Xenidis ji...@pobox.com
---
arch/powerpc
From: Michael Ellerman mich...@ellerman.id.au
Based on a patch by Michael Ellerman mich...@ellerman.id.au
Patch was simply forward ported upstream.
Jimi Xenidis ji...@pobox.com
---
arch/powerpc/platforms/wsp/Makefile |1 +
arch/powerpc/platforms/wsp/ics.c| 48
arch
On May 31, 2011, at 8:50 AM, Alexander Graf wrote:
On 31.05.2011, at 14:35, Paul Mackerras wrote:
On Tue, May 31, 2011 at 12:40:31PM +0200, Alexander Graf wrote:
Thinking about the testability of this a bit more ... how much
effort would it be to get this code running on a 970MP with
On Nov 10, 2008, at 10:11 AM, Milton Miller wrote:
On 2008-11-07 at 02:31:40, David Gibson wrote:
On Thu, Nov 06, 2008 at 06:55:44PM +1100, Michael Ellerman wrote:
This commit adds an output format, which produces python
code. When run, the python produces a data structure that
can then be
On Aug 22, 2008, at 4:17 AM, Kumar Gala wrote:
On Aug 22, 2008, at 3:08 AM, Christian Ehrhardt wrote:
Scott Wood wrote:
On Thu, Aug 21, 2008 at 09:21:39AM -0500, Kumar Gala wrote:
Where is the other discussion? I'd like to understand what's
going on here.. (especially since I added
On Jul 27, 2008, at 10:23 AM, Stephen Rothwell wrote:
Hi Jimi,
On Sun, 27 Jul 2008 08:48:09 -0400 Jimi Xenidis
[EMAIL PROTECTED] wrote:
Declate compat_sys_epoll_pwait as a conditional syscall like the rest
of the epoll interfaces.
We could have put an #ifdef around the entry in include
Declate compat_sys_epoll_pwait as a conditional syscall like the rest
of the epoll interfaces.
We could have put an #ifdef around the entry in include/asm-powerpc/
systbl.h, but IMHO this is ultimately correct patch.
Signed-off-by: Jimi Xenidis [EMAIL PROTECTED]
---
diff --git a/kernel
On Apr 4, 2008, at 3:06 AM, Jerone Young wrote:
# HG changeset patch
# User Jerone Young [EMAIL PROTECTED]
# Date 1207292108 18000
# Node ID afed3e5de82ab6c0ac8d6ceeb0292b6c41ece1ed
# Parent a5b2aebbc6ebd2439c655f1c047ed7e3c1991ec1
[v2] Add idle wait support for 44x platforms
This patch adds
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