[PATCH 2/2] powerpc/powernv/idle: Restore CIABR after idle for Power9

2020-12-06 Thread Jordan Niethe
On Power9, CIABR is lost after idle. This means that instruction breakpoints set by xmon which use CIABR do not work. Fix this by restoring CIABR after idle. Signed-off-by: Jordan Niethe --- arch/powerpc/platforms/powernv/idle.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch

[PATCH 1/2] powerpc/book3s64/kexec: Clear CIABR on kexec

2020-12-06 Thread Jordan Niethe
c -l /mnt/vmlinux --initrd=/mnt/rootfs.cpio.gz --append='xmon=off' $ kexec -e $ cat /proc/loadavg Trace/breakpoint trap Make sure CIABR is cleared so this does not happen. Signed-off-by: Jordan Niethe --- arch/powerpc/include/asm/book3s/64/kexec.h | 5 + 1 file changed, 5 insertions(+) diff --g

[PATCH v2] powerpc: Allow relative pointers in bug table entries

2020-11-30 Thread Jordan Niethe
This enables GENERIC_BUG_RELATIVE_POINTERS on Power so that 32-bit offsets are stored in the bug entries rather than 64-bit pointers. While this doesn't save space for 32-bit machines, use it anyway so there is only one code path. Signed-off-by: Jordan Niethe --- v2: Remove non-relative pointers

Re: [PATCH] powerpc: Allow relative pointers in bug table entries

2020-11-29 Thread Jordan Niethe
On Mon, Nov 30, 2020 at 12:42 PM Michael Ellerman wrote: > > Christophe Leroy writes: > > Le 27/11/2020 à 04:02, Jordan Niethe a écrit : > >> This enables GENERIC_BUG_RELATIVE_POINTERS on Power so that 32-bit > >> offsets are stored in the bug entri

Re: [PATCH] powerpc: Allow relative pointers in bug table entries

2020-11-29 Thread Jordan Niethe
On Sun, Nov 29, 2020 at 6:00 AM Christophe Leroy wrote: > > > > Le 27/11/2020 à 04:02, Jordan Niethe a écrit : > > This enables GENERIC_BUG_RELATIVE_POINTERS on Power so that 32-bit > > offsets are stored in the bug entries rather than 64-bit pointers. > > &g

[PATCH] powerpc/64: Fix an EMIT_BUG_ENTRY in head_64.S

2020-11-29 Thread Jordan Niethe
bug is in relative_toc() where the previous "0" label is. Label the trap as "0" so the correct address is used. Fixes: 63ce271b5e37 ("powerpc/prom: convert PROM_BUG() to standard trap") Signed-off-by: Jordan Niethe --- arch/powerpc/kernel/head_64.S | 2 +- 1 file chang

[PATCH] powerpc: Allow relative pointers in bug table entries

2020-11-26 Thread Jordan Niethe
This enables GENERIC_BUG_RELATIVE_POINTERS on Power so that 32-bit offsets are stored in the bug entries rather than 64-bit pointers. Signed-off-by: Jordan Niethe --- arch/powerpc/Kconfig | 4 arch/powerpc/include/asm/bug.h | 37 -- arch/powerpc

Re: [PATCH] powerpc/powernv/memtrace: Fake non-memblock aligned sized traces

2020-11-16 Thread Jordan Niethe
On Mon, Nov 16, 2020 at 11:02 PM Michael Ellerman wrote: > > Jordan Niethe writes: > > The hardware trace macros which use the memory provided by memtrace are > > able to use trace sizes as small as 16MB. Only memblock aligned values > > can be removed from each NUMA no

[PATCH] powerpc/powernv/memtrace: Fake non-memblock aligned sized traces

2020-11-10 Thread Jordan Niethe
. To allow such a trace size, instead align whatever value is written to memtrace/enable to the memblock size for the purpose of removing it from each NUMA node but report the written value from memtrace/enable and memtrace/x/size in debugfs. Signed-off-by: Jordan Niethe --- arch/powerpc/platforms/powernv

Re: [PATCH v2 1/2] powerpc: Introduce POWER10_DD1 feature

2020-10-22 Thread Jordan Niethe
On Thu, Oct 22, 2020 at 4:33 PM Ravi Bangoria wrote: > > > > On 10/22/20 10:41 AM, Jordan Niethe wrote: > > On Thu, Oct 22, 2020 at 2:40 PM Ravi Bangoria > > wrote: > >> > >> POWER10_DD1 feature flag will be needed while adding > >>

Re: [PATCH v2 1/2] powerpc: Introduce POWER10_DD1 feature

2020-10-21 Thread Jordan Niethe
On Thu, Oct 22, 2020 at 2:40 PM Ravi Bangoria wrote: > > POWER10_DD1 feature flag will be needed while adding > conditional code that applies only for Power10 DD1. > > Signed-off-by: Ravi Bangoria > --- > arch/powerpc/include/asm/cputable.h | 8 ++-- > arch/powerpc/kernel/dt_cpu_ftrs.c |

[PATCH v4 2/2] powerpc/64s: Convert some cpu_setup() and cpu_restore() functions to C

2020-10-14 Thread Jordan Niethe
aries before cpu_restore()") means that it is now possible to use C. Rewrite the functions in C so they are a little bit easier to read. This is not changing their functionality. Signed-off-by: Jordan Niethe --- arch/powerpc/include/asm/cpu_setup_power.h | 12 + arch/powerpc/kernel/cpu_set

[PATCH v4 1/2] powerpc/64: Set up a kernel stack for secondaries before cpu_restore()

2020-10-14 Thread Jordan Niethe
econdary CPUs to after the PACAs have been allocated an emergency stack, otherwise the PACA stack pointer will contain garbage and hence the temp kernel stack created from it will be broken. Fixes: 5a61ef74f269 ("powerpc/64s: Support new device tree binding for discovering CPU features"

Re: [PATCH v3 1/2] powerpc/64: Set up a kernel stack for secondaries before cpu_restore()

2020-09-22 Thread Jordan Niethe
On Tue, Sep 22, 2020 at 3:59 PM Christophe Leroy wrote: > > > > Le 22/09/2020 à 07:53, Jordan Niethe a écrit : > > Currently in generic_secondary_smp_init(), cur_cpu_spec->cpu_restore() > > is called before a stack has been set up in r1. This was previously fine > &g

[PATCH v3 2/2] powerpc/64s: Convert some cpu_setup() and cpu_restore() functions to C

2020-09-21 Thread Jordan Niethe
aries before cpu_restore()") means that it is now possible to use C. Rewrite the functions in C so they are a little bit easier to read. This is not changing their functionality. Signed-off-by: Jordan Niethe --- arch/powerpc/include/asm/cpu_setup_power.h | 12 + arch/powerpc/kernel/cpu_set

[PATCH v3 1/2] powerpc/64: Set up a kernel stack for secondaries before cpu_restore()

2020-09-21 Thread Jordan Niethe
econdary CPUs to after the PACAs have been allocated an emergency stack, otherwise the PACA stack pointer will contain garbage and hence the temp kernel stack created from it will be broken. Fixes: 5a61ef74f269 ("powerpc/64s: Support new device tree binding for discovering CPU features"

Re: [PATCH v2 1/2] powerpc/64: Set up a kernel stack for secondaries before cpu_restore()

2020-09-21 Thread Jordan Niethe
On Fri, Sep 18, 2020 at 5:21 PM Michael Ellerman wrote: > > Hi Jordan, > > Jordan Niethe writes: > > Currently in generic_secondary_smp_init(), cur_cpu_spec->cpu_restore() > > is called before a stack has been set up in r1. This was previously fine > > as

[PATCH v2 2/2] powerpc/64s: Convert some cpu_setup() and cpu_restore() functions to C

2020-09-17 Thread Jordan Niethe
aries before cpu_restore()") means that it is now possible to use C. Rewrite the functions in C so they are a little bit easier to read. This is not changing their functionality. Signed-off-by: Jordan Niethe --- arch/powerpc/include/asm/cpu_setup_power.h | 12 + arch/powerpc/kernel/cpu_set

[PATCH v2 1/2] powerpc/64: Set up a kernel stack for secondaries before cpu_restore()

2020-09-17 Thread Jordan Niethe
never returns, but it is still wrong and should be corrected. Create the temp kernel stack before calling cpu_restore(). Fixes: 5a61ef74f269 ("powerpc/64s: Support new device tree binding for discovering CPU features") Signed-off-by: Jordan Niethe --- v2: Add more detail to the commit me

[PATCH 2/2] powerpc/64s: Convert some cpu_setup() and cpu_restore() functions to C

2020-09-16 Thread Jordan Niethe
aries before cpu_restore()") means that it is now possible to use C. Rewrite the functions in C so they are a little bit easier to read. This is not changing their functionality. Signed-off-by: Jordan Niethe --- arch/powerpc/include/asm/cpu_setup_power.h | 12 + arch/powerpc/kernel/cpu_set

[PATCH 1/2] powerpc/64: Set up a kernel stack for secondaries before cpu_restore()

2020-09-16 Thread Jordan Niethe
5a61ef74f269 ("powerpc/64s: Support new device tree binding for discovering CPU features") Signed-off-by: Jordan Niethe --- arch/powerpc/kernel/head_64.S | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_

Re: [RFC PATCH 2/2] KVM: PPC: Book3S HV: Support prefixed instructions

2020-09-02 Thread Jordan Niethe
On Wed, Sep 2, 2020 at 4:18 PM Paul Mackerras wrote: > > On Thu, Aug 20, 2020 at 01:39:22PM +1000, Jordan Niethe wrote: > > There are two main places where instructions are loaded from the guest: > > * Emulate loadstore - such as when performing MMIO emulation > >

Re: [RFC PATCH 1/2] KVM: PPC: Use the ppc_inst type

2020-09-02 Thread Jordan Niethe
On Wed, Sep 2, 2020 at 4:18 PM Paul Mackerras wrote: > > On Thu, Aug 20, 2020 at 01:39:21PM +1000, Jordan Niethe wrote: > > The ppc_inst type was added to help cope with the addition of prefixed > > instructions to the ISA. Convert KVM to use this new type for dealing >

Re: [PATCH v2] powerpc: Update documentation of ISA versions for Power10

2020-08-26 Thread Jordan Niethe
On Thu, Aug 27, 2020 at 2:49 PM Christophe Leroy wrote: > > > > Le 27/08/2020 à 06:05, Jordan Niethe a écrit : > > Update the CPU to ISA Version Mapping document to include Power10 and > > ISA v3.1. > > Maybe Documentation/powerpc/cpu_families.rst should be updat

[PATCH v2] powerpc: Update documentation of ISA versions for Power10

2020-08-26 Thread Jordan Niethe
Update the CPU to ISA Version Mapping document to include Power10 and ISA v3.1. Signed-off-by: Jordan Niethe --- v2: Transactional Memory = No --- Documentation/powerpc/isa-versions.rst | 4 1 file changed, 4 insertions(+) diff --git a/Documentation/powerpc/isa-versions.rst b

[PATCH] powerpc/64s: Remove TM from Power10 features

2020-08-26 Thread Jordan Niethe
WER10 architected mode") Signed-off-by: Jordan Niethe --- arch/powerpc/include/asm/cputable.h | 2 +- arch/powerpc/kernel/cputable.c | 13 ++--- 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputab

Re: [PATCH] selftests/powerpc: Fix prefixes in alignment_handler signal handler

2020-08-26 Thread Jordan Niethe
On Mon, Aug 24, 2020 at 11:12 PM Jordan Niethe wrote: > > The signal handler in the alignment handler self test has the ability to > jump over the instruction that triggered the signal. It does this by > incrementing the PT_NIP in the user context by 4. If it were a prefixed &

Re: [PATCH] powerpc: Update documentation of ISA versions for Power10

2020-08-25 Thread Jordan Niethe
On Tue, Aug 25, 2020 at 10:41 PM Gabriel Paubert wrote: > > On Tue, Aug 25, 2020 at 09:45:07PM +1000, Jordan Niethe wrote: > > Update the CPU to ISA Version Mapping document to include Power10 and > > ISA v3.1. > > > > Signed-off-by: Jordan Niethe > >

[PATCH] powerpc: Update documentation of ISA versions for Power10

2020-08-25 Thread Jordan Niethe
Update the CPU to ISA Version Mapping document to include Power10 and ISA v3.1. Signed-off-by: Jordan Niethe --- Documentation/powerpc/isa-versions.rst | 4 1 file changed, 4 insertions(+) diff --git a/Documentation/powerpc/isa-versions.rst b/Documentation/powerpc/isa-versions.rst index

[PATCH] powerpc/boot: Update Makefile comment for 64bit wrapper

2020-08-24 Thread Jordan Niethe
As of commit 147c05168fc8 ("powerpc/boot: Add support for 64bit little endian wrapper") the comment in the Makefile is misleading. The wrapper packaging 64bit kernel may built as a 32 or 64 bit elf. Update the comment to reflect this. Signed-off-by: Jordan Niethe --- arch/powerpc/boo

[PATCH] selftests/powerpc: Fix prefixes in alignment_handler signal handler

2020-08-24 Thread Jordan Niethe
test") Signed-off-by: Jordan Niethe --- .../selftests/powerpc/alignment/alignment_handler.c | 11 ++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/tools/testing/selftests/powerpc/alignment/alignment_handler.c b/tools/testing/selftests/powerpc/alignment/alignment_handl

[RFC PATCH 2/2] KVM: PPC: Book3S HV: Support prefixed instructions

2020-08-19 Thread Jordan Niethe
. For interrupts caused by a word instruction the instruction is loaded into bits 32:63 and bits 0:31 are zeroed. When caused by a prefixed instruction the prefix and suffix are loaded into bits 0:63. Signed-off-by: Jordan Niethe --- arch/powerpc/kvm/book3s.c | 15

[RFC PATCH 1/2] KVM: PPC: Use the ppc_inst type

2020-08-19 Thread Jordan Niethe
The ppc_inst type was added to help cope with the addition of prefixed instructions to the ISA. Convert KVM to use this new type for dealing wiht instructions. For now do not try to add further support for prefixed instructions. Signed-off-by: Jordan Niethe --- arch/powerpc/include/asm

Re: [v4] powerpc/perf: Initialize power10 PMU registers in cpu setup routine

2020-07-23 Thread Jordan Niethe
D)". This patch also initializes > MMCRA BHRBRD to disable BHRB feature at boot for power10. > > Signed-off-by: Athira Rajeev Reviewed-by: Jordan Niethe > --- > Dependency: > - On power10 PMU base enablement series V3: > https://patchwork.ozlabs.org/project/linuxppc-dev

Re: [v3 11/15] powerpc/perf: BHRB control to disable BHRB logic when not used

2020-07-22 Thread Jordan Niethe
On Thu, Jul 23, 2020 at 11:26 AM Jordan Niethe wrote: > > On Sat, Jul 18, 2020 at 1:26 AM Athira Rajeev > wrote: > > > > PowerISA v3.1 has few updates for the Branch History Rolling Buffer(BHRB). > > > > BHRB disable is controlled via Monitor Mode Control Registe

Re: [v3 11/15] powerpc/perf: BHRB control to disable BHRB logic when not used

2020-07-22 Thread Jordan Niethe
On Sat, Jul 18, 2020 at 1:26 AM Athira Rajeev wrote: > > PowerISA v3.1 has few updates for the Branch History Rolling Buffer(BHRB). > > BHRB disable is controlled via Monitor Mode Control Register A (MMCRA) > bit, namely "BHRB Recording Disable (BHRBRD)". This field controls > whether BHRB

Re: [v3 04/15] powerpc/perf: Add support for ISA3.1 PMU SPRs

2020-07-22 Thread Jordan Niethe
On Wed, Jul 22, 2020 at 6:07 PM Athira Rajeev wrote: > > > > On 22-Jul-2020, at 9:48 AM, Jordan Niethe wrote: > > On Sat, Jul 18, 2020 at 1:02 AM Athira Rajeev > wrote: > > > From: Madhavan Srinivasan > > PowerISA v3.1 includes new performance monitoring u

Re: [v3 07/15] powerpc/perf: Add power10_feat to dt_cpu_ftrs

2020-07-22 Thread Jordan Niethe
On Wed, Jul 22, 2020 at 5:55 PM Athira Rajeev wrote: > > > > On 22-Jul-2020, at 10:11 AM, Jordan Niethe wrote: > > On Sat, Jul 18, 2020 at 1:13 AM Athira Rajeev > wrote: > > > From: Madhavan Srinivasan > > Add power10 feature function to dt_cpu_ftrs.c

Re: [v3 07/15] powerpc/perf: Add power10_feat to dt_cpu_ftrs

2020-07-21 Thread Jordan Niethe
On Sat, Jul 18, 2020 at 1:13 AM Athira Rajeev wrote: > > From: Madhavan Srinivasan > > Add power10 feature function to dt_cpu_ftrs.c along > with a power10 specific init() to initialize pmu sprs, > sets the oprofile_cpu_type and cpu_features. This will > enable performance monitoring unit(PMU)

Re: [v3 04/15] powerpc/perf: Add support for ISA3.1 PMU SPRs

2020-07-21 Thread Jordan Niethe
On Sat, Jul 18, 2020 at 1:02 AM Athira Rajeev wrote: > > From: Madhavan Srinivasan > > PowerISA v3.1 includes new performance monitoring unit(PMU) > special purpose registers (SPRs). They are > > Monitor Mode Control Register 3 (MMCR3) > Sampled Instruction Event Register 2 (SIER2) > Sampled

Re: [PATCH 5/5] powerpc sstep: Add tests for Prefixed Add Immediate

2020-07-21 Thread Jordan Niethe
On Mon, May 25, 2020 at 1:00 PM Jordan Niethe wrote: > > Use the existing support for testing compute type instructions to test > Prefixed Add Immediate (paddi). The R bit of the paddi instruction > controls whether current instruction address is used. Add test cases for > when

Re: [PATCH v4 09/10] powerpc/watchpoint: Return available watchpoints dynamically

2020-07-20 Thread Jordan Niethe
On Tue, Jul 21, 2020 at 1:57 PM Ravi Bangoria wrote: > > > > On 7/20/20 9:12 AM, Jordan Niethe wrote: > > On Fri, Jul 17, 2020 at 2:11 PM Ravi Bangoria > > wrote: > >> > >> So far Book3S Powerpc supported only one watchpoint. Power10 is > >

Re: [v3 01/15] powerpc/perf: Update cpu_hw_event to use `struct` for storing MMCR registers

2020-07-20 Thread Jordan Niethe
On Sat, Jul 18, 2020 at 12:48 AM Athira Rajeev wrote: > > core-book3s currently uses array to store the MMCR registers as part > of per-cpu `cpu_hw_events`. This patch does a clean up to use `struct` > to store mmcr regs instead of array. This will make code easier to read > and reduces chance of

Re: [PATCH 04/11] powerpc/smp: Enable small core scheduling sooner

2020-07-20 Thread Jordan Niethe
On Tue, Jul 14, 2020 at 2:44 PM Srikar Dronamraju wrote: > > Enable small core scheduling as soon as we detect that we are in a > system that supports thread group. Doing so would avoid a redundant > check. > > Cc: linuxppc-dev > Cc: Michael Ellerman > Cc: Nick Piggin > Cc: Oliver OHalloran >

Re: [PATCH v4 10/10] powerpc/watchpoint: Remove 512 byte boundary

2020-07-20 Thread Jordan Niethe
On Fri, Jul 17, 2020 at 2:11 PM Ravi Bangoria wrote: > > Power10 has removed 512 bytes boundary from match criteria. i.e. The watch > range can cross 512 bytes boundary. It looks like this change is not mentioned in ISA v3.1 Book III 9.4 Data Address Watchpoint. It could be useful to mention that

Re: [PATCH v4 09/10] powerpc/watchpoint: Return available watchpoints dynamically

2020-07-19 Thread Jordan Niethe
On Fri, Jul 17, 2020 at 2:11 PM Ravi Bangoria wrote: > > So far Book3S Powerpc supported only one watchpoint. Power10 is > introducing 2nd DAWR. Enable 2nd DAWR support for Power10. > Availability of 2nd DAWR will depend on CPU_FTR_DAWR1. > > Signed-off-by: Ravi Bangoria > --- >

Re: [PATCH v4 07/10] powerpc/watchpoint: Rename current H_SET_MODE DAWR macro

2020-07-19 Thread Jordan Niethe
On Fri, Jul 17, 2020 at 2:11 PM Ravi Bangoria wrote: > > Current H_SET_MODE hcall macro name for setting/resetting DAWR0 is > H_SET_MODE_RESOURCE_SET_DAWR. Add suffix 0 to macro name as well. > > Signed-off-by: Ravi Bangoria Reviewed-by: Jordan Niethe > --- > arch/powerpc

Re: [PATCH v4 06/10] powerpc/watchpoint: Set CPU_FTR_DAWR1 based on pa-features bit

2020-07-19 Thread Jordan Niethe
=off and it does set the CPU_FTR_DAWR1 bit. (using p10 skiboot). Tested-by: Jordan Niethe > --- > arch/powerpc/kernel/prom.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c > index 9cc49f265c86..c76c09b97bc8 1006

Re: [PATCH v4 05/10] powerpc/dt_cpu_ftrs: Add feature for 2nd DAWR

2020-07-16 Thread Jordan Niethe
On Fri, Jul 17, 2020 at 2:10 PM Ravi Bangoria wrote: > > Add new device-tree feature for 2nd DAWR. If this feature is present, > 2nd DAWR is supported, otherwise not. > > Signed-off-by: Ravi Bangoria > --- > arch/powerpc/include/asm/cputable.h | 7 +-- > arch/powerpc/kernel/dt_cpu_ftrs.c

Re: [PATCH v4 04/10] powerpc/watchpoint: Enable watchpoint functionality on power10 guest

2020-07-16 Thread Jordan Niethe
able watchpoint functionality on power10 guest (both kvm > and powervm) by adding CPU_FTR_DAWR to CPU_FTRS_POWER10. Note that > this change does not enable 2nd DAWR support. > > Signed-off-by: Ravi Bangoria I ran the ptrace-hwbreak selftest successfully within a power10 kvm gues

Re: [PATCH v3 2/9] powerpc/watchpoint: Fix DAWR exception constraint

2020-07-14 Thread Jordan Niethe
On Wed, Jul 8, 2020 at 2:52 PM Ravi Bangoria wrote: > > Pedro Miraglia Franco de Carvalho noticed that on p8, DAR value is > inconsistent with different type of load/store. Like for byte,word > etc. load/stores, DAR is set to the address of the first byte of > overlap between watch range and real

Re: [PATCH v3 1/9] powerpc/watchpoint: Fix 512 byte boundary limit

2020-07-14 Thread Jordan Niethe
ging to ALIGN_DOWN() then these tests will fail. Tested-by: Jordan Niethe > --- > arch/powerpc/kernel/hw_breakpoint.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/powerpc/kernel/hw_breakpoint.c > b/arch/powerpc/kernel/hw_breakpoint.c > index 0

Re: [PATCH v3 1/9] powerpc/watchpoint: Fix 512 byte boundary limit

2020-07-08 Thread Jordan Niethe
On Wed, Jul 8, 2020 at 2:53 PM Ravi Bangoria wrote: > > Milton Miller reported that we are aligning start and end address to > wrong size SZ_512M. It should be SZ_512. Fix that. > > While doing this change I also found a case where ALIGN() comparison > fails. Within a given aligned range, ALIGN()

Re: [PATCH 2/6] powerpc test_emulate_step: fix pr_info() to print 8-byte for prefixed instruction

2020-06-22 Thread Jordan Niethe
On Mon, Jun 22, 2020 at 5:10 PM Balamuruhan S wrote: > > On test failure, `pr_log()` prints 4 bytes instruction > irrespective of word/prefix instruction, fix it by printing > them appropriately. This patch to add a ppc_inst_as_str() function should help with this,

Re: [PATCH 1/6] powerpc test_emulate_step: update nip with patched instruction address

2020-06-22 Thread Jordan Niethe
On Mon, Jun 22, 2020 at 5:10 PM Balamuruhan S wrote: > > pt_regs are initialized to zero in the test infrastructure, R bit > in prefixed instruction form is used to specify whether the effective > address of the storage operand is computed relative to the address > of the instruction. > > If R =

Re: [PATCH] powerpc/kvm: Enable support for ISA v3.1 guests

2020-06-02 Thread Jordan Niethe
On Tue, Jun 2, 2020 at 3:55 PM Alistair Popple wrote: > > Adds support for emulating ISAv3.1 guests by adding the appropriate PCR > and FSCR bits. > > Signed-off-by: Alistair Popple > --- > arch/powerpc/include/asm/reg.h | 1 + > arch/powerpc/kvm/book3s_hv.c | 11 --- > 2 files

[PATCH 4/4] powerpc: Handle prefixed instructions in show_instructions()

2020-06-01 Thread Jordan Niethe
000 0x6000 0x6000 0x6000 0x6000 0x6000 0x6000 <0x0400 0x> 0x6000 0x6000 0x6000 Signed-off-by: Jordan Niethe --- arch/powerpc/kernel/process.c | 11 ++- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/kernel/

[PATCH 3/4] powerpc: Handle prefixed instructions in show_user_instructions()

2020-06-01 Thread Jordan Niethe
p the prefix and suffix. Currently showing a prefixed instruction looks like: fbe1fff8 3920 0600 a3e3 <0400> f7e4 ebe1fff8 4e800020 Make it look like: 0xfbe1fff8 0x3920 0x0600 0xa3e3 <0x0400 0xf7e4> 0xebe1fff8 0x4e800020 0x 0x000

[PATCH 2/4] powerpc/xmon: Improve dumping prefixed instructions

2020-06-01 Thread Jordan Niethe
nop c00941a0 0xe9240100ld r9,256(r4) c00941a4 0x3941li r10,1 c00941a8 0x3d02000baddis r8,r2,11 Signed-off-by: Jordan Niethe --- arch/powerpc/xmon/xmon.c | 11 ++- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/xmon/xm

[PATCH 1/4] powerpc: Add a ppc_inst_as_str() helper

2020-06-01 Thread Jordan Niethe
to allocate a buffer on the caller's stack before calling it. Signed-off-by: Jordan Niethe --- arch/powerpc/include/asm/inst.h | 19 +++ arch/powerpc/kernel/kprobes.c| 2 +- arch/powerpc/kernel/trace/ftrace.c | 26 +- arch/powerpc/lib

Re: [PATCH] powerpc/64: Remove unused generic_secondary_thread_init()

2020-05-27 Thread Jordan Niethe
On Tue, May 26, 2020 at 4:36 PM Michael Ellerman wrote: > > The last caller was removed in 2014 in commit fb5a515704d7 ("powerpc: > Remove platforms/wsp and associated pieces"). > > Once generic_secondary_thread_init() is removed there are no longer > any uses of book3e_secondary_thread_init() or

Re: [PATCH] powerpc: Add ppc_inst_as_u64()

2020-05-25 Thread Jordan Niethe
as_u64(instr), patch_addr, err, > "std"); > } > > if (err) > -- > 2.25.1 > I booted a BE and LE kernel - test_prefixed_patching() worked on both. Also on BE and LE kernels I put optprobes on prefixed and non prefixed instructions. The correct value was passed via r4 to emulate_step(). Tested-by: Jordan Niethe

Re: [PATCH v2] powerpc: Add ppc_inst_next()

2020-05-24 Thread Jordan Niethe
6b0..65cf853a4d26 100644 > --- a/arch/powerpc/xmon/xmon.c > +++ b/arch/powerpc/xmon/xmon.c > @@ -939,7 +939,7 @@ static void insert_bpts(void) > } > > patch_instruction(bp->instr, instr); > - patch_instruction((void *)bp->instr + ppc_inst_len(instr), > + patch_instruction(ppc_inst_next(bp->instr, ), > ppc_inst(bpinstr)); > if (bp->enabled & BP_CIABR) > continue; > -- > 2.25.1 > Reviewed-by: Jordan Niethe

[PATCH 5/5] powerpc sstep: Add tests for Prefixed Add Immediate

2020-05-24 Thread Jordan Niethe
and si1. Add tests for the extreme values of this field. Skip the paddi tests if ISA v3.1 is unsupported. Some of these test cases were added by Balamuruhan S. Signed-off-by: Jordan Niethe --- arch/powerpc/lib/test_emulate_step.c | 127 ++ .../lib

[PATCH 4/5] powerpc sstep: Let compute tests specify a required cpu feature

2020-05-24 Thread Jordan Niethe
An a array of struct compute_test's are used to declare tests for compute instructions. Add a cpu_feature field to struct compute_test as an optional way to specify a cpu feature that must be present. If not present then skip the test. Signed-off-by: Jordan Niethe --- arch/powerpc/lib

[PATCH 3/5] powerpc sstep: Set NIP in instruction emulation tests

2020-05-24 Thread Jordan Niethe
of the executed instruction so they will give the same result. This is a rework of a patch by Balamuruhan S. Signed-off-by: Jordan Niethe --- arch/powerpc/lib/test_emulate_step.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/powerpc/lib/test_emulate_step.c b/arch/powerpc/lib

[PATCH 2/5] powerpc sstep: Add tests for prefixed floating-point load/stores

2020-05-24 Thread Jordan Niethe
Store Floating-Point Double (pstfd) Skip the new tests if ISA v3.10 is unsupported. Signed-off-by: Jordan Niethe --- arch/powerpc/include/asm/ppc-opcode.h | 4 + arch/powerpc/lib/test_emulate_step.c | 136 ++ 2 files changed, 140 insertions(+) diff --git a/arch/powerpc

[PATCH 1/5] powerpc sstep: Add tests for prefixed integer load/stores

2020-05-24 Thread Jordan Niethe
-off-by: Jordan Niethe --- arch/powerpc/include/asm/ppc-opcode.h | 9 +++ arch/powerpc/lib/test_emulate_step.c | 95 +++ 2 files changed, 104 insertions(+) diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index 2a39c716c343

Re: [PATCH] powerpc: Add ppc_inst_next()

2020-05-20 Thread Jordan Niethe
On Wed, May 20, 2020 at 9:44 PM Michael Ellerman wrote: > > In a few places we want to calculate the address of the next > instruction. Previously that was simple, we just added 4 bytes, or if > using a u32 * we incremented that pointer by 1. > > But prefixed instructions make it more

[PATCH 2/2] selftests/powerpc: Add prefixed loads/stores to alignment_handler test

2020-05-19 Thread Jordan Niethe
Extend the alignment handler selftest to exercise prefixed load store instructions. Add tests for prefixed VSX, floating point and integer instructions. Skip prefix tests if ISA version does not support prefixed instructions. Signed-off-by: Jordan Niethe --- .../powerpc/alignment

[PATCH 1/2] selftests/powerpc: Allow choice of CI memory location in alignment_handler test

2020-05-19 Thread Jordan Niethe
to be for mmaping this path. Signed-off-by: Jordan Niethe --- .../powerpc/alignment/alignment_handler.c | 63 --- 1 file changed, 42 insertions(+), 21 deletions(-) diff --git a/tools/testing/selftests/powerpc/alignment/alignment_handler.c b/tools/testing/selftests/powerpc/alignment

Re: [PATCH v2 2/7] powerpc: Add support for ISA v3.1

2020-05-18 Thread Jordan Niethe
On Tue, May 19, 2020 at 10:39 AM Alistair Popple wrote: > > Newer ISA versions are enabled by clearing all bits in the PCR > associated with previous versions of the ISA. Enable ISA v3.1 support > by updating the PCR mask to include ISA v3.0. This ensures all PCR > bits corresponding to earlier

Re: [PATCH v2 7/7] powerpc: Add POWER10 architected mode

2020-05-18 Thread Jordan Niethe
On Tue, May 19, 2020 at 10:48 AM Alistair Popple wrote: > > PVR value of 0x0F06 means we are arch v3.1 compliant (i.e. POWER10). > This is used by phyp and kvm when booting as a pseries guest to detect > the presence of new P10 features and to enable the appropriate hwcap and > facility bits.

Re: [PATCH v8 11/30] powerpc: Use a datatype for instructions

2020-05-17 Thread Jordan Niethe
mpe, this is to go with the fixup I posted for mmu_patch_addis() in [PATCH v8 12/30] powerpc: Use a function for reading instructions. Thanks to Christophe pointing it out. diff --git a/arch/powerpc/mm/nohash/8xx.c b/arch/powerpc/mm/nohash/8xx.c --- a/arch/powerpc/mm/nohash/8xx.c +++

Re: [PATCH v8 12/30] powerpc: Use a function for reading instructions

2020-05-17 Thread Jordan Niethe
On Sun, May 17, 2020 at 4:39 AM Christophe Leroy wrote: > > > > Le 06/05/2020 à 05:40, Jordan Niethe a écrit : > > Prefixed instructions will mean there are instructions of different > > length. As a result dereferencing a pointer to an instruction will not > > neces

Re: [PATCH v8 08/30] powerpc: Use a function for getting the instruction op code

2020-05-17 Thread Jordan Niethe
On Sat, May 16, 2020 at 9:08 PM Michael Ellerman wrote: > > Jordan Niethe writes: > > mpe, as suggested by Christophe could you please add this. > > I did that and ... > > > diff --git a/arch/powerpc/include/asm/inst.h > > b/arch/powerpc/include/asm/inst.h &

Re: [PATCH v8 30/30] powerpc sstep: Add support for prefixed fixed-point arithmetic

2020-05-15 Thread Jordan Niethe
mpe, and this thanks. --- diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c --- a/arch/powerpc/lib/sstep.c +++ b/arch/powerpc/lib/sstep.c @@ -1343,7 +1343,7 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs, rd = (suffix >> 21) & 0x1f;

Re: [PATCH v8 29/30] powerpc sstep: Add support for prefixed load/stores

2020-05-15 Thread Jordan Niethe
mpe, and this thanks. diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c --- a/arch/powerpc/lib/sstep.c +++ b/arch/powerpc/lib/sstep.c @@ -1204,7 +1204,7 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs, struct ppc_inst instr) {

Re: [PATCH v8 25/30] powerpc: Test prefixed instructions in feature fixups

2020-05-15 Thread Jordan Niethe
Hey mpe, could you add this thanks. diff --git a/arch/powerpc/lib/feature-fixups.c b/arch/powerpc/lib/feature-fixups.c --- a/arch/powerpc/lib/feature-fixups.c +++ b/arch/powerpc/lib/feature-fixups.c @@ -689,7 +689,7 @@ static void test_lwsync_macros(void) } } -#ifdef __powerpc64__ +#ifdef

Re: [PATCH v8 24/30] powerpc: Test prefixed code patching

2020-05-15 Thread Jordan Niethe
Hey mpe could you add this please. diff --git a/arch/powerpc/lib/code-patching.c b/arch/powerpc/lib/code-patching.c --- a/arch/powerpc/lib/code-patching.c +++ b/arch/powerpc/lib/code-patching.c @@ -707,7 +707,7 @@ static void __init test_translate_branch(void) vfree(buf); } -#ifdef

Re: [PATCH v8 23/30] powerpc: Add prefixed instructions to instruction data type

2020-05-15 Thread Jordan Niethe
Hey mpe, fixes for the issues highlighted by Christophe, except KUAP as discussed. Will make the optprobe change as a preceding patch. diff --git a/arch/powerpc/include/asm/inst.h b/arch/powerpc/include/asm/inst.h --- a/arch/powerpc/include/asm/inst.h +++ b/arch/powerpc/include/asm/inst.h @@

Re: [PATCH v8 08/30] powerpc: Use a function for getting the instruction op code

2020-05-15 Thread Jordan Niethe
mpe, as suggested by Christophe could you please add this. diff --git a/arch/powerpc/include/asm/inst.h b/arch/powerpc/include/asm/inst.h --- a/arch/powerpc/include/asm/inst.h +++ b/arch/powerpc/include/asm/inst.h @@ -2,6 +2,8 @@ #ifndef _ASM_INST_H #define _ASM_INST_H +#include + /* *

Re: [PATCH v8 13/30] powerpc: Add a probe_user_read_inst() function

2020-05-14 Thread Jordan Niethe
On Thu, May 14, 2020 at 3:46 PM Christophe Leroy wrote: > > > > Le 06/05/2020 à 05:40, Jordan Niethe a écrit : > > Introduce a probe_user_read_inst() function to use in cases where > > probe_user_read() is used for getting an instruction. This will be more > > us

Re: [PATCH v8 23/30] powerpc: Add prefixed instructions to instruction data type

2020-05-14 Thread Jordan Niethe
On Thu, May 14, 2020 at 10:06 PM Alistair Popple wrote: > > On Thursday, 14 May 2020 4:11:43 PM AEST Christophe Leroy wrote: > > @@ -249,7 +249,7 @@ int arch_prepare_optimized_kprobe(struct > > optimized_kprobe *op, struct kprobe *p) > > > * Fixup the template with instructions to: > > > * 1.

Re: [PATCH v8 23/30] powerpc: Add prefixed instructions to instruction data type

2020-05-14 Thread Jordan Niethe
On Thu, May 14, 2020 at 4:12 PM Christophe Leroy wrote: > > > > Le 06/05/2020 à 05:40, Jordan Niethe a écrit : > > For powerpc64, redefine the ppc_inst type so both word and prefixed > > instructions can be represented. On powerpc32 the type will remain the > >

Re: [PATCH v8 00/30] Initial Prefixed Instruction support

2020-05-14 Thread Jordan Niethe
On Thu, May 14, 2020 at 3:31 PM Christophe Leroy wrote: > > > > Le 06/05/2020 à 05:40, Jordan Niethe a écrit : > > A future revision of the ISA will introduce prefixed instructions. A > > prefixed instruction is composed of a 4-byte prefix followed by a > > 4-byt

Re: [PATCH v8 16/30] powerpc: Define and use __get_user_instr{, inatomic}()

2020-05-13 Thread Jordan Niethe
Hi mpe, could you please take this. arch/powerpc/include/asm/uaccess.h | 3 +++ arch/powerpc/kernel/vecemu.c | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/uaccess.h b/arch/powerpc/include/asm/uaccess.h ---

Re: [PATCH v8 23/30] powerpc: Add prefixed instructions to instruction data type

2020-05-13 Thread Jordan Niethe
Hi mpe, Relating to your message on [PATCH v8 16/30] powerpc: Define and use __get_user_instr{,inatomic}() - could you please take this. diff --git a/arch/powerpc/include/asm/uaccess.h b/arch/powerpc/include/asm/uaccess.h --- a/arch/powerpc/include/asm/uaccess.h +++

Re: [PATCH v8 16/30] powerpc: Define and use __get_user_instr{, inatomic}()

2020-05-13 Thread Jordan Niethe
On Thu, May 14, 2020 at 12:17 AM Michael Ellerman wrote: > > Jordan Niethe writes: > > Define specific __get_user_instr() and __get_user_instr_inatomic() > > macros for reading instructions from user space. > > At least for fix_alignment() we could be coming from the

Re: [PATCH v8 13/30] powerpc: Add a probe_user_read_inst() function

2020-05-13 Thread Jordan Niethe
On Wed, May 13, 2020 at 10:52 PM Michael Ellerman wrote: > > Jordan Niethe writes: > > diff --git a/arch/powerpc/lib/inst.c b/arch/powerpc/lib/inst.c > > new file mode 100644 > > index ..eaf786afad2b > > --- /dev/null > > +++ b/arch/

Re: [PATCH v8 11/30] powerpc: Use a datatype for instructions

2020-05-10 Thread Jordan Niethe
On Fri, May 8, 2020 at 5:17 PM Christophe Leroy wrote: > > > > Le 08/05/2020 à 03:51, Jordan Niethe a écrit : > > On Wed, May 6, 2020 at 1:45 PM Jordan Niethe wrote: > >> > >> Currently unsigned ints are used to represent instructions on powerpc. > >&

Re: [PATCH v8 22/30] powerpc: Define new SRR1 bits for a future ISA version

2020-05-07 Thread Jordan Niethe
Hi mpe, Could you please take some changes for the commit message. In the patch title s/a future ISA version/ISA v3.1/ On Wed, May 6, 2020 at 1:47 PM Jordan Niethe wrote: > > Add the BOUNDARY SRR1 bit definition for when the cause of an alignment > exception is a prefixed in

Re: [PATCH v8 11/30] powerpc: Use a datatype for instructions

2020-05-07 Thread Jordan Niethe
Hi mpe, On Wed, May 6, 2020 at 1:45 PM Jordan Niethe wrote: > > Currently unsigned ints are used to represent instructions on powerpc. > This has worked well as instructions have always been 4 byte words. > However, a future ISA version will introduce some changes to s/a future

Re: [PATCH v8 11/30] powerpc: Use a datatype for instructions

2020-05-07 Thread Jordan Niethe
On Wed, May 6, 2020 at 1:45 PM Jordan Niethe wrote: > > Currently unsigned ints are used to represent instructions on powerpc. > This has worked well as instructions have always been 4 byte words. > However, a future ISA version will introduce some changes to > instructions that m

[PATCH v8 30/30] powerpc sstep: Add support for prefixed fixed-point arithmetic

2020-05-05 Thread Jordan Niethe
This adds emulation support for the following prefixed Fixed-Point Arithmetic instructions: * Prefixed Add Immediate (paddi) Reviewed-by: Balamuruhan S Signed-off-by: Jordan Niethe --- v3: Since we moved the prefixed loads/stores into the load/store switch statement it no longer makes sense

[PATCH v8 29/30] powerpc sstep: Add support for prefixed load/stores

2020-05-05 Thread Jordan Niethe
-Precision (plxssp) * Prefixed Load VSX Vector [0|1] (plxv, plxv0, plxv1) * Prefixed Store VSX Scalar Doubleword (pstxsd) * Prefixed Store VSX Scalar Single-Precision (pstxssp) * Prefixed Store VSX Vector [0|1] (pstxv, pstxv0, pstxv1) Reviewed-by: Balamuruhan S Signed-off-by: Jordan Niethe

[PATCH v8 28/30] powerpc: Support prefixed instructions in alignment handler

2020-05-05 Thread Jordan Niethe
are not permitted to cross 64-byte boundaries. If they do the alignment interrupt is invoked with SRR1 BOUNDARY bit set. If this occurs send a SIGBUS to the offending process if in user mode. If in kernel mode call bad_page_fault(). Reviewed-by: Alistair Popple Signed-off-by: Jordan Niethe --- v2: - Move

[PATCH v8 27/30] powerpc/kprobes: Don't allow breakpoints on suffixes

2020-05-05 Thread Jordan Niethe
Do not allow inserting breakpoints on the suffix of a prefix instruction in kprobes. Signed-off-by: Jordan Niethe --- v8: Add this back from v3 --- arch/powerpc/kernel/kprobes.c | 13 + 1 file changed, 13 insertions(+) diff --git a/arch/powerpc/kernel/kprobes.c b/arch/powerpc

[PATCH v8 26/30] powerpc/xmon: Don't allow breakpoints on suffixes

2020-05-05 Thread Jordan Niethe
Do not allow placing xmon breakpoints on the suffix of a prefix instruction. Signed-off-by: Jordan Niethe --- v8: Add this back from v3 --- arch/powerpc/xmon/xmon.c | 29 +++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/xmon/xmon.c b/arch

[PATCH v8 25/30] powerpc: Test prefixed instructions in feature fixups

2020-05-05 Thread Jordan Niethe
Expand the feature-fixups self-tests to includes tests for prefixed instructions. Signed-off-by: Jordan Niethe --- v6: New to series v8: Use OP_PREFIX --- arch/powerpc/lib/feature-fixups-test.S | 69 arch/powerpc/lib/feature-fixups.c | 73

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