On PowerPC we should always use generic ISA DMA API implementation
as there is simply no other implementation exist.
Without this patch, the following build error pops up:
sound/built-in.o: In function 'snd_dma_pointer':
(.text+0x74ae): undefined reference to 'dma_spin_lock'
...
Aaron pointed the issue on FSL BookE.
http://lists.ozlabs.org/pipermail/linuxppc-dev/2010-January/079738.htm
l
Right, but I think 64-bit BookE has the same issue. We can
fix that later tho.
Ben,
We also find the _PAGE_USER is different between pte-book3e and old
fsl-booke
It is UR
I've updated the commit message to be a bit more clear on why
we need to do this.
I'm curious why the _PAGE_EXEC have different definition in pte-book3e.h
and pte-fsl-booke.h?
It is UX permission in pte-book3e, but is SX permission in
pte-fsl-booke.h.
Thanks, Dave
Not looking at the code right now ... but do we have the same
issue on 64e ?
Aaron pointed the issue on FSL BookE.
http://lists.ozlabs.org/pipermail/linuxppc-dev/2010-January/079738.html
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On Fri, Nov 27, 2009 at 04:16:43PM +0800, Dave Liu wrote:
current the Rx/Tx FIFO size settings cause problem
when four UEC ethernets work simultaneously.
eg: GETH1, UEM-J15, GETH2, UEC-J5 on 8569MDS board
$ ifconfig eth0 10.193.20.166
$ ifconfig eth1 10.193.20.167
$ ifconfig
One possible cause is the two board has different RCW.
So that the freq of core/csb/ Is different.
-Original Message-
From:
linuxppc-dev-bounces+daveliu=freescale@lists.ozlabs.org
[mailto:linuxppc-dev-bounces+daveliu=freescale@lists.ozlab
s.org] On Behalf Of RONETIX -
On Aug 6, 2009, at 1:00 PM, Lutz Jaenicke wrote:
With the mpc8...@400mhz I get a throughput of approx.
24500 frames/s
using the predefined firewall rules.
With the MPC8313 I get a significantly lower value:
mpc8...@250mhz 12500fps
mpc8...@333mhz 14500fps
I believe the question should be sent to u-b...@lists.denx.de,
not linuxppc-dev list.
What is the TLB settings for NAND FCM buffer? Pay attention
to set the TLB as cache inhibited and guarded attribute.
If not set the guarded bit, it is possible to cause the speculate
load from FCM buffer below
Guys,
The ucc_geth ethernet driver have dozens of strong sync read/write
operation, such as in_be32/16/8, out_be32/16/8.
all of them is sync read/write, it is very expensive for performance.
For the critical patch, we can remove some unnecessary in_be(x),
out_be(x) with normal memory operation,
I have a custom board similar to MPC8560ADS board with 1GB
DDR SDRAM. The DDR SDRAM Make
is MT18VDDF12872DG-335D3. In U-BOOT (2009.01) config file I
have enabled CONFIG_SPD_EEPROM
so U-boot configures MPC8560ADS DDR controller with the
values read from SPD_EEPROM (i2c
address 0x51)
Subject: [PATCH 2/2] powerpc/85xx: Add new LAW MCM device
tree nodes for all85xx systems
One nit/typo, the tittle of the two patches should be ECM
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You are assuming the PCI memory space is prefetchable( no side effect)
for DMA.
Is it possible that DMA is from non-prefetchable memory space?
This should be a safe assumption for this driver. Remember, this
driver just does offload memcpy, from one region to another. So the
PCI memory
By default, the Freescale 83xx DMA controller uses the PCI Read Line
command when reading data over the PCI bus. Setting the
controller to use the PCI Read Multiple command instead allows the
controller to read much larger bursts of data, which provides a
drastic
speed increase.
IIRC, the
You are assuming the PCI memory space is prefetchable( no
side effect) for DMA.
Is it possible that DMA is from non-prefetchable memory space?
This should be a safe assumption for this driver. Remember, this
driver just does offload memcpy, from one region to another. So the
PCI
Here's a few results from DMA tests between two
MPC8349EA boards housed in a CPCI chassis.
1. DMA mode register (DMAMRn)
PCI read command (PRC, bits 11:10)
a) DMAMRn[PRC] = 00 = PCI Read
The PCI read command is 6h on the PCI bus.
For DMA lengths of less than 1
You can mark the pci inbound window on the 83xx as
non-prefetchable(assuming 83xx is host). On a x86 host
I doubt there is any easy way to get non-prefetchable memory.
One more note; we don't have access to a host-mode MPC8349EA,
our boards are all targets.
Actually we also can use the
I' am trying to configure a PCI bridge on a private board, with a
powerpc . In a first time, I tried to get informations about PCI
devices, in order to be sure that my read and write methods work (
using 2 configuration registers, like on an x86 architecture.) . 2
configuration
So the host bridge is important, what is the bridge?
Marvell or Tundra chipset?
From: Nicolas Lavocat [mailto:nicolas.lavo...@fr.thalesgroup.com]
Sent: Wednesday, April 22, 2009 4:32 PM
To: Liu Dave-R63238
Cc: linuxppc-dev
+ L2: l2-cache-control...@2 {
+ compatible = fsl,p2020-l2-cache-controller;
+ reg = 0x2 0x1000;
+ cache-line-size = 32; // 32 bytes
+ cache-size = 0x10; // L2, 1M
+
Guys,
The commit 03d70617 is using the dcbf for all of unaligned start
or non-multi cache line of size. It will cause performance lost
due to dcbf all M-state cache line in the whole address range
(start-end). It causes unnecessary bus traffic (when the mid part
of range with M-state).
However,
It's because the irqs are remapped by the kernel, the number in the
device tree is a hardware irq number. The number you're printing out is
a virtual irq number.
of_irq_to_resource() is doing the remapping for you.
You can turn on CONFIG_VIRQ_DEBUG and you'll get a file in debugfs that
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -22,6 +22,7 @@
#define MPIC_GREG_FEATURE_10x00010
#define MPIC_GREG_GLOBAL_CONF_00x00020
#defineMPIC_GREG_GCONF_RESET 0x8000
+#define
of the initiator's transaction.
For 8315, it is outbound, not inbound transaction.
Thanks, Dave
From: Ben Menchaca [mailto:ben.mench...@gmail.com]
Sent: Saturday, March 07, 2009 12:30 AM
To: Liu Dave-R63238
Cc: linuxppc-dev@ozlabs.org
of the initiator's transaction.
For 8315, it is outbound, not inbound transaction.
Thanks, Dave
From: Ben Menchaca [mailto:ben.mench...@gmail.com]
Sent: Saturday, March 07, 2009 12:30 AM
To: Liu Dave-R63238
Cc: linuxppc-dev@ozlabs.org
Timur,
See the section 14.7.1 DMA Description Format at page 14-112
of MPC8315ERM rev.1.
-Original Message-
From: timur.t...@gmail.com [mailto:timur.t...@gmail.com] On
Behalf Of Tabi Timur-B04825
Sent: Sunday, March 08, 2009 11:20 PM
To: Liu Dave-R63238
Cc: Ben Menchaca; linuxppc
Did you enable the snoop bit at PEX_WDMA_CTRL[SNOOP]
and PEX_RDMA_CTRL[SNOOP]?
What is the freq settings? CORE/CSB bus.
Thanks, Dave
From: linuxppc-dev-bounces+daveliu=freescale@ozlabs.org
and what settings is DMA description bit 3?
-Original Message-
From: linuxppc-dev-bounces+daveliu=freescale@ozlabs.org
[mailto:linuxppc-dev-bounces+daveliu=freescale@ozlabs.org]
On Behalf Of Liu Dave-R63238
Sent: Friday, March 06, 2009 1:22 PM
To: Ben Menchaca; linuxppc
what is the value of ACR register?
From: Ben Menchaca [mailto:ben.mench...@gmail.com]
Sent: Friday, March 06, 2009 1:38 PM
To: Liu Dave-R63238
Cc: linuxppc-dev@ozlabs.org
Subject: Re: 83xx: Marking or Allocating Pages
could you try to set '1' to DMA description bit3?
From: Liu Dave-R63238
Sent: Friday, March 06, 2009 1:41 PM
To: 'Ben Menchaca'
Cc: linuxppc-dev@ozlabs.org
Subject: RE: 83xx: Marking or Allocating Pages as
Cache-Inhibited
Did you enable the descriptor bit 3 to have a try?
From: Ben Menchaca [mailto:ben.mench...@gmail.com]
Sent: Friday, March 06, 2009 2:10 PM
To: Liu Dave-R63238
Cc: linuxppc-dev@ozlabs.org
Subject: Re: 83xx: Marking
The end result simply adds a line to set MBAR to match IMMRBAR.
lis r3, [EMAIL PROTECTED]
ori r3, r3, [EMAIL PROTECTED]
stw r3, IMMRBAR(r4)
+ mtspr MBAR, r3
Are these patches routinely added to the mainstream u-boot code?
Is there
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