RE: [PATCH 00/20] ethernet: ucc_geth: assorted fixes and simplifications

[Qiang Zhao]

On 06/12/2020 05:12, Rasmus Villemoes  wrote:


> -Original Message-
> From: Rasmus Villemoes 
> Sent: 2020年12月6日 5:12
> To: Jakub Kicinski 
> Cc: Leo Li ; David S. Miller ;
> Qiang Zhao ; net...@vger.kernel.org;
> linuxppc-dev@lists.ozlabs.org; linux-ker...@vger.kernel.org;
> linux-arm-ker...@lists.infradead.org; Vladimir Oltean
> 
> Subject: Re: [PATCH 00/20] ethernet: ucc_geth: assorted fixes and
> simplifications
> 
> On 05/12/2020 21.53, Jakub Kicinski wrote:
> > On Sat,  5 Dec 2020 20:17:23 +0100 Rasmus Villemoes wrote:
> >> While trying to figure out how to allow bumping the MTU with the
> >> ucc_geth driver, I fell into a rabbit hole and stumbled on a whole
> >> bunch of issues of varying importance - some are outright bug fixes,
> >> while most are a matter of simplifying the code to make it more
> >> accessible.
> >>
> >> At the end of digging around the code and data sheet to figure out
> >> how it all works, I think the MTU issue might be fixed by a
> >> one-liner, but I'm not sure it can be that simple. It does seem to
> >> work (ping -s X works for larger values of X, and wireshark confirms
> >> that the packets are not fragmented).
> >>
> >> Re patch 2, someone in NXP should check how the hardware actually
> >> works and make an updated reference manual available.
> >
> > Looks like a nice clean up on a quick look.
> >
> > Please separate patches 1 and 11 (which are the two bug fixes I see)
> 
> I think patch 2 is a bug fix as well, but I'd like someone from NXP to 
> comment.

It 's ok for me.


Best Regards,
Qiang Zhao

RE: [PATCH] soc: fsl: qe: Replace one-element array and use struct_size() helper

[Qiang Zhao]

On Wed, May 23, 2020 at 5:22 PM Li Yang 
> -Original Message-
> From: Li Yang 
> Sent: 2020年5月23日 5:22
> To: Kees Cook 
> Cc: Gustavo A. R. Silva ; Qiang Zhao
> ; linuxppc-dev ;
> moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
> ; lkml ;
> Gustavo A. R. Silva 
> Subject: Re: [PATCH] soc: fsl: qe: Replace one-element array and use
> struct_size() helper
> 
> On Wed, May 20, 2020 at 10:24 PM Kees Cook 
> wrote:
> >
> > On Wed, May 20, 2020 at 06:52:21PM -0500, Li Yang wrote:
> > > On Mon, May 18, 2020 at 5:57 PM Kees Cook 
> wrote:
> > > > Hm, looking at this code, I see a few other things that need to be
> > > > fixed:
> > > >
> > > > 1) drivers/tty/serial/ucc_uart.c does not do a be32_to_cpu() conversion
> > > >on the length test (understandably, a little-endian system has never
> run
> > > >this code since it's ppc specific), but it's still wrong:
> > > >
> > > > if (firmware->header.length != fw->size) {
> > > >
> > > >compare to the firmware loader:
> > > >
> > > > length = be32_to_cpu(hdr->length);
> > > >
> > > > 2) drivers/soc/fsl/qe/qe.c does not perform bounds checking on the
> > > >per-microcode offsets, so the uploader might send data outside the
> > > >firmware buffer. Perhaps:
> > >
> > > We do validate the CRC for each microcode, it is unlikely the CRC
> > > check can pass if the offset or length is not correct.  But you are
> > > probably right that it will be safer to check the boundary and fail
> >
> > Right, but a malicious firmware file could still match CRC but trick
> > the kernel code.
> >
> > > quicker before we actually start the CRC check.  Will you come up
> > > with a formal patch or you want us to deal with it?
> >
> > It sounds like Gustavo will be sending one, though I don't think
> > either of us have the hardware to test it with, so if you could do
> > that part, that would be great! :)
> 
> That will be great.  I think Zhao Qiang can help with the testing part.
> 

Now the firmware are loaded in uboot, and kernel will do nothing for it.
So testing on it maybe need some extra codes both in driver and dts.
In the meanwhile, I am so busy on some high priority work that maybe test work 
could not be done in time.
Once I am free, I will do it.

Best Regards
Qiang Zhao

RE: [PATCH] soc: fsl: qe: Replace one-element array and use struct_size() helper

[Qiang Zhao]

On 2020/5/19 6:19, Gustavo A. R. Silva  wrote:

> -Original Message-
> From: Gustavo A. R. Silva 
> Sent: 2020年5月19日 6:19
> To: Qiang Zhao ; Leo Li 
> Cc: linuxppc-dev@lists.ozlabs.org; linux-arm-ker...@lists.infradead.org;
> linux-ker...@vger.kernel.org; Gustavo A. R. Silva ;
> Kees Cook 
> Subject: [PATCH] soc: fsl: qe: Replace one-element array and use struct_size()
> helper
> 
> The current codebase makes use of one-element arrays in the following
> form:
> 
> struct something {
> int length;
> u8 data[1];
> };
> 
> struct something *instance;
> 
> instance = kmalloc(sizeof(*instance) + size, GFP_KERNEL);
> instance->length = size;
> memcpy(instance->data, source, size);
> 
> but the preferred mechanism to declare variable-length types such as these
> ones is a flexible array member[1][2], introduced in C99:
> 
> struct foo {
> int stuff;
> struct boo array[];
> };
> 
> By making use of the mechanism above, we will get a compiler warning in case
> the flexible array does not occur last in the structure, which will help us 
> prevent
> some kind of undefined behavior bugs from being inadvertently introduced[3]
> to the codebase from now on. So, replace the one-element array with a
> flexible-array member.
> 
> Also, make use of the new struct_size() helper to properly calculate the size 
> of
> struct qe_firmware.
> 
> This issue was found with the help of Coccinelle and, audited and fixed
> _manually_.
> 
> [1]
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgcc.gnu.
> org%2Fonlinedocs%2Fgcc%2FZero-Length.htmldata=02%7C01%7Cqiang.
> zhao%40nxp.com%7Cb058bcb9af134df8446808d7fb78cfa9%7C686ea1d3bc2b
> 4c6fa92cd99c5c301635%7C0%7C0%7C637254368610203908sdata=70
> a6VBg3oWQf9a5KICuCEuIj6gw57NKYhNv2JL8JdDY%3Dreserved=0
> [2]
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.c
> om%2FKSPP%2Flinux%2Fissues%2F21data=02%7C01%7Cqiang.zhao%40
> nxp.com%7Cb058bcb9af134df8446808d7fb78cfa9%7C686ea1d3bc2b4c6fa92c
> d99c5c301635%7C0%7C0%7C637254368610213901sdata=kVyNBYHbm
> a5jCO9pbkoHMetHEYGvWDq6Xw%2BBeC7uHII%3Dreserved=0
> [3] commit 76497732932f ("cxgb3/l2t: Fix undefined behaviour")
> 
> Signed-off-by: Gustavo A. R. Silva 
> ---
>  drivers/soc/fsl/qe/qe.c | 4 ++--
>  include/soc/fsl/qe/qe.h | 2 +-
>  2 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c index
> 447146861c2c1..2df20d6f85fa4 100644
> --- a/drivers/soc/fsl/qe/qe.c
> +++ b/drivers/soc/fsl/qe/qe.c
> @@ -448,7 +448,7 @@ int qe_upload_firmware(const struct qe_firmware
> *firmware)
>   unsigned int i;
>   unsigned int j;
>   u32 crc;
> - size_t calc_size = sizeof(struct qe_firmware);
> + size_t calc_size;
>   size_t length;
>   const struct qe_header *hdr;
> 
> @@ -480,7 +480,7 @@ int qe_upload_firmware(const struct qe_firmware
> *firmware)
>   }
> 
>   /* Validate the length and check if there's a CRC */
> - calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
> + calc_size = struct_size(firmware, microcode, firmware->count);
> 
>   for (i = 0; i < firmware->count; i++)
>   /*
> diff --git a/include/soc/fsl/qe/qe.h b/include/soc/fsl/qe/qe.h index
> e282ac01ec081..3feddfec9f87d 100644
> --- a/include/soc/fsl/qe/qe.h
> +++ b/include/soc/fsl/qe/qe.h
> @@ -307,7 +307,7 @@ struct qe_firmware {
>   u8 revision;/* The microcode version revision */
>   u8 padding; /* Reserved, for alignment */
>   u8 reserved[4];     /* Reserved, for future expansion */
> - } __attribute__ ((packed)) microcode[1];
> + } __packed microcode[];
>   /* All microcode binaries should be located here */
>   /* CRC32 should be located here, after the microcode binaries */  }
> __attribute__ ((packed));
> --
> 2.26.2
[>] 

Reviewed-by: Qiang Zhao 

Best Regards
Qiang Zhao

RE: [Regression 5.6-rc1][Bisected b6231ea2b3c6] Powerpc 8xx doesn't boot anymore

[Qiang Zhao]

On 02/13/2020 14:17 PM, Christophe Leroy wrote:
> -Original Message-
> From: Christophe Leroy 
> Sent: 2020年2月13日 14:17
> To: Qiang Zhao ; Rasmus Villemoes
> ; Leo Li ; Greg
> Kroah-Hartman 
> Cc: Scott Wood ; linuxppc-dev@lists.ozlabs.org; LKML
> ; linux-arm-ker...@lists.infradead.org
> Subject: Re: [Regression 5.6-rc1][Bisected b6231ea2b3c6] Powerpc 8xx doesn't
> boot anymore
> 
> 
> 
> Le 13/02/2020 à 04:35, Qiang Zhao a écrit :
> > On 02/12/2020 22:50 PM, Christophe Leroy wrote:
> >> -Original Message-
> >> From: Christophe Leroy 
> >> Sent: 2020年2月12日 22:50
> >> To: Rasmus Villemoes ; Leo Li
> >> ; Qiang Zhao ; Greg
> >> Kroah-Hartman 
> >> Cc: Scott Wood ; linuxppc-dev@lists.ozlabs.org;
> >> LKML ;
> >> linux-arm-ker...@lists.infradead.org
> >> Subject: Re: [Regression 5.6-rc1][Bisected b6231ea2b3c6] Powerpc 8xx
> >> doesn't boot anymore
> >>
> >> ---
> >> diff --git a/drivers/tty/serial/cpm_uart/cpm_uart_core.c
> >> b/drivers/tty/serial/cpm_uart/cpm_uart_core.c
> >> index 4cabded8390b..341d682ec6eb 100644
> >> --- a/drivers/tty/serial/cpm_uart/cpm_uart_core.c
> >> +++ b/drivers/tty/serial/cpm_uart/cpm_uart_core.c
> >> @@ -1351,6 +1351,7 @@ static int __init cpm_uart_console_setup(struct
> >> console *co, char *options)
> >>clrbits32(>sccp->scc_gsmrl, SCC_GSMRL_ENR |
> >> SCC_GSMRL_ENT);
> >>}
> >>
> >> +  cpm_muram_init();
> >>ret = cpm_uart_allocbuf(pinfo, 1);
> >>
> >>if (ret)
> >>
> > How about the patch like below? Just a draft.
> 
> Yes, I see the idea. I think we could go for something like that.
> But in the powerpc 8xx case, we are talking about cpm_init(), not qe_init().

Yes, cpm_init.  

Best Regards
Qiang Zhao

RE: [Regression 5.6-rc1][Bisected b6231ea2b3c6] Powerpc 8xx doesn't boot anymore

[Qiang Zhao]

On 02/12/2020 22:50 PM, Christophe Leroy wrote:
> -Original Message-
> From: Christophe Leroy 
> Sent: 2020年2月12日 22:50
> To: Rasmus Villemoes ; Leo Li
> ; Qiang Zhao ; Greg
> Kroah-Hartman 
> Cc: Scott Wood ; linuxppc-dev@lists.ozlabs.org; LKML
> ; linux-arm-ker...@lists.infradead.org
> Subject: Re: [Regression 5.6-rc1][Bisected b6231ea2b3c6] Powerpc 8xx doesn't
> boot anymore
> 
> ---
> diff --git a/drivers/tty/serial/cpm_uart/cpm_uart_core.c
> b/drivers/tty/serial/cpm_uart/cpm_uart_core.c
> index 4cabded8390b..341d682ec6eb 100644
> --- a/drivers/tty/serial/cpm_uart/cpm_uart_core.c
> +++ b/drivers/tty/serial/cpm_uart/cpm_uart_core.c
> @@ -1351,6 +1351,7 @@ static int __init cpm_uart_console_setup(struct
> console *co, char *options)
>   clrbits32(>sccp->scc_gsmrl, SCC_GSMRL_ENR |
> SCC_GSMRL_ENT);
>   }
> 
> + cpm_muram_init();
>   ret = cpm_uart_allocbuf(pinfo, 1);
> 
>   if (ret)
> 
How about the patch like below? Just a draft.

diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c
index 96c2057..c5c2464 100644
--- a/drivers/soc/fsl/qe/qe.c
+++ b/drivers/soc/fsl/qe/qe.c
@@ -29,6 +29,8 @@
 #include 
 #include 

+static int qe_inited;
+
 static void qe_snums_init(void);
 static int qe_sdma_init(void);

@@ -637,15 +639,19 @@ unsigned int qe_get_num_of_snums(void)
 }
 EXPORT_SYMBOL(qe_get_num_of_snums);

-static int __init qe_init(void)
+int __init qe_init(void)
 {
struct device_node *np;

+   if(qe_inited)
+   return 0;
+
np = of_find_compatible_node(NULL, NULL, "fsl,qe");
if (!np)
return -ENODEV;
qe_reset();
of_node_put(np);
+   qe_inited = 1
return 0;
 }
 subsys_initcall(qe_init);
diff --git a/drivers/tty/serial/cpm_uart/cpm_uart_core.c 
b/drivers/tty/serial/cpm_uart/cpm_uart_core.c
index 19d5a4c..cbf2c32 100644
--- a/drivers/tty/serial/cpm_uart/cpm_uart_core.c
+++ b/drivers/tty/serial/cpm_uart/cpm_uart_core.c
@@ -1373,6 +1373,7 @@ static struct console cpm_scc_uart_console = {

 static int __init cpm_uart_console_init(void)
 {
+   qe_init();
register_console(_scc_uart_console);
return 0;
 }
diff --git a/include/soc/fsl/qe/qe.h b/include/soc/fsl/qe/qe.h
index e282ac0..531ba05 100644
--- a/include/soc/fsl/qe/qe.h
+++ b/include/soc/fsl/qe/qe.h
@@ -88,6 +88,7 @@ static inline bool qe_clock_is_brg(enum qe_clock clk)

 extern spinlock_t cmxgcr_lock;

+int __init  qe_init(void);
 /* Export QE common operations */
 #ifdef CONFIG_QUICC_ENGINE
 extern void qe_reset(void);

Best Regards
Qiang Zhao

RE: [PATCH v4 47/47] soc: fsl: qe: remove PPC32 dependency from CONFIG_QUICC_ENGINE

[Qiang Zhao]

On Fri, Nov 8, 2019 at 21:01, Rasmus Villemoes  wrote:

> -Original Message-
> From: Rasmus Villemoes 
> Sent: 2019年11月8日 21:01
> To: Qiang Zhao ; Leo Li ;
> Christophe Leroy 
> Cc: linuxppc-dev@lists.ozlabs.org; linux-arm-ker...@lists.infradead.org;
> linux-ker...@vger.kernel.org; Scott Wood ; Rasmus
> Villemoes 
> Subject: [PATCH v4 47/47] soc: fsl: qe: remove PPC32 dependency from
> CONFIG_QUICC_ENGINE
> 
> There are also ARM and ARM64 based SOCs with a QUICC Engine, and the core
> QE code as well as net/wan/fsl_ucc_hdlc and tty/serial/ucc_uart has now been
> modified to not rely on ppcisms.
> 
> So extend the architectures that can select QUICC_ENGINE, and add the rather
> modest requirements of OF && HAS_IOMEM.
> 
> The core code as well as the ucc_uart driver has been tested on an LS1021A
> (arm), and it has also been tested that the QE code still works on an mpc8309
> (ppc).
> 
> Signed-off-by: Rasmus Villemoes 
> ---
>  drivers/soc/fsl/qe/Kconfig | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/soc/fsl/qe/Kconfig b/drivers/soc/fsl/qe/Kconfig index
> cfa4b2939992..f1974f811572 100644
> --- a/drivers/soc/fsl/qe/Kconfig
> +++ b/drivers/soc/fsl/qe/Kconfig
> @@ -5,7 +5,8 @@
> 
>  config QUICC_ENGINE
>   bool "QUICC Engine (QE) framework support"
> - depends on FSL_SOC && PPC32
> + depends on OF && HAS_IOMEM
> + depends on PPC32 || ARM || ARM64 || COMPILE_TEST
>   select GENERIC_ALLOCATOR
>   select CRC32
>   help
> --
Tested-by: Qiang Zhao 
Tested QE-HDLC on ARM64!

Best Regards
Qiang Zhao

RE: [PATCH v4 34/47] soc: fsl: qe: change return type of cpm_muram_alloc() to s32

[Qiang Zhao]

On Fri, Nov 8, 2019 at 21:01 Rasmus Villemoes  wrote:

> -Original Message-
> From: Rasmus Villemoes 
> Sent: 2019年11月8日 21:01
> To: Qiang Zhao ; Leo Li ;
> Christophe Leroy 
> Cc: linuxppc-dev@lists.ozlabs.org; linux-arm-ker...@lists.infradead.org;
> linux-ker...@vger.kernel.org; Scott Wood ; Rasmus
> Villemoes 
> Subject: [PATCH v4 34/47] soc: fsl: qe: change return type of
> cpm_muram_alloc() to s32
> 
> -unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long
> size)
> +s32 cpm_muram_alloc_fixed(unsigned long offset, unsigned long size)
>  {
> - unsigned long start;
> + long start;
>   unsigned long flags;
>   struct genpool_data_fixed muram_pool_data_fixed;
 
"start" should be s32 here too?


Best Regards
Qiang Zhao

RE: [PATCH v3 35/36] net/wan: make FSL_UCC_HDLC explicitly depend on PPC32

[Qiang Zhao]

On 01/11/2019 23:31, Rasmus Villemoes wrote :


> -Original Message-
> From: Rasmus Villemoes 
> Sent: 2019年11月4日 16:38
> To: Leo Li ; Christophe Leroy ;
> Qiang Zhao 
> Cc: linuxppc-dev@lists.ozlabs.org; linux-arm-ker...@lists.infradead.org;
> linux-ker...@vger.kernel.org; Scott Wood ;
> net...@vger.kernel.org
> Subject: Re: [PATCH v3 35/36] net/wan: make FSL_UCC_HDLC explicitly depend
> on PPC32
> 
> On 01/11/2019 23.31, Leo Li wrote:
> >
> >
> >> -Original Message-
> >> From: Christophe Leroy 
> >> Sent: Friday, November 1, 2019 11:30 AM
> >> To: Rasmus Villemoes ; Qiang Zhao
> >> ; Leo Li 
> >> Cc: linuxppc-dev@lists.ozlabs.org;
> >> linux-arm-ker...@lists.infradead.org;
> >> linux-ker...@vger.kernel.org; Scott Wood ;
> >> net...@vger.kernel.org
> >> Subject: Re: [PATCH v3 35/36] net/wan: make FSL_UCC_HDLC explicitly
> >> depend on PPC32
> >>
> >>
> >>
> >> Le 01/11/2019 à 13:42, Rasmus Villemoes a écrit :
> >>> Currently, FSL_UCC_HDLC depends on QUICC_ENGINE, which in turn
> >> depends
> >>> on PPC32. As preparation for removing the latter and thus allowing
> >>> the core QE code to be built for other architectures, make
> >>> FSL_UCC_HDLC explicitly depend on PPC32.
> >>
> >> Is that really powerpc specific ? Can't the ARM QE perform HDLC on UCC ?
> 
> I think the driver would build on ARM. Whether it works I don't know. I know 
> it
> does not build on 64 bit hosts (see kbuild report for v2,23/23).
> 
> > No.  Actually the HDLC and TDM are the major reason to integrate a QE on
> the ARM based Layerscape SoCs.
> 
> [citation needed].
> 
> > Since Rasmus doesn't have the hardware to test this feature Qiang Zhao
> probably can help verify the functionality of TDM and we can drop this patch.
> 
> No, this patch cannot be dropped. Please see the kbuild complaints for
> v2,23/23 about use of IS_ERR_VALUE on not-sizeof(long) entities. I see kbuild
> has complained about the same thing for v3 since apparently the same thing
> appears in ucc_slow.c. So I'll fix that.
> 
> Moreover, as you say and know, I do not have the hardware to test it, so I'm
> not going to even attempt to fix up fsl_ucc_hdlc.c. If Qiang Zhao or somebody
> else can verify that it works just fine on ARM and fixes the allmodconfig
> problem(s), he/she is more than welcome to sign off on a patch that removes
> the CONFIG_PPC32 dependency or replaces it with something else.
> 

I tested your v3 patches on ls1043ardb which is arm64 for fsl_ucc_hdlc, it can 
work,
Only it will put a compile warning, I also made a patch to fix it.
I can send a patch to remove PPC32 dependency when I send my patch to support 
ARM64.
Or I add my patch in your patchset.

Best Regards
Qiang Zhao

RE: [PATCH 0/7] towards QE support on ARM

[Qiang Zhao]

On 22/10/2019 18:18, Rasmus Villemoes  wrote:
> -Original Message-
> From: Rasmus Villemoes 
> Sent: 2019年10月22日 18:18
> To: Qiang Zhao ; Leo Li 
> Cc: Timur Tabi ; Greg Kroah-Hartman
> ; linux-ker...@vger.kernel.org;
> linux-ser...@vger.kernel.org; Jiri Slaby ;
> linuxppc-dev@lists.ozlabs.org; linux-arm-ker...@lists.infradead.org
> Subject: Re: [PATCH 0/7] towards QE support on ARM
> 
> On 22/10/2019 04.24, Qiang Zhao wrote:
> > On Mon, Oct 22, 2019 at 6:11 AM Leo Li wrote
> 
> >> Right.  I'm really interested in getting this applied to my tree and
> >> make it upstream.  Zhao Qiang, can you help to review Rasmus's
> >> patches and comment?
> >
> > As you know, I maintained a similar patchset removing PPC, and someone
> told me qe_ic should moved into drivers/irqchip/.
> > I also thought qe_ic is a interrupt control driver, should be moved into dir
> irqchip.
> 
> Yes, and I also plan to do that at some point. However, that's orthogonal to
> making the driver build on ARM, so I don't want to mix the two. Making it
> usable on ARM is my/our priority currently.
> 
> I'd appreciate your input on my patches.

Yes, we can put this patchset in first place, ensure it can build and work on 
ARM, then push another patchset to move qe_ic.

Best Regards,
Qiang

RE: [PATCH 0/7] towards QE support on ARM

[Qiang Zhao]

On Mon, Oct 22, 2019 at 6:11 AM Leo Li wrote
> -Original Message-
> From: Li Yang 
> Sent: 2019年10月22日 6:11
> To: Rasmus Villemoes 
> Cc: Timur Tabi ; Greg Kroah-Hartman
> ; linux-ker...@vger.kernel.org;
> linux-ser...@vger.kernel.org; Jiri Slaby ;
> linuxppc-dev@lists.ozlabs.org; linux-arm-ker...@lists.infradead.org; Qiang
> Zhao 
> Subject: Re: [PATCH 0/7] towards QE support on ARM
> 
> On Mon, Oct 21, 2019 at 3:46 AM Rasmus Villemoes
>  wrote:
> >
> > On 18/10/2019 23.52, Li Yang wrote:
> > > On Fri, Oct 18, 2019 at 3:54 PM Rasmus Villemoes
> > >  wrote:
> > >>
> > >> On 18/10/2019 22.16, Leo Li wrote:
> > >>>
> > >>>>
> > >>>> There have been several attempts in the past few years to allow
> > >>>> building the QUICC engine drivers for platforms other than PPC.
> > >>>> This is (the beginning of) yet another attempt. I hope I can get
> > >>>> someone to pick up these relatively trivial patches (I _think_
> > >>>> they shouldn't change functionality at all), and then I'll
> > >>>> continue slowly working towards removing the PPC32 dependency for
> CONFIG_QUICC_ENGINE.
> > >>>
> > >>> Hi Rasmus,
> > >>>
> > >>> I don't fully understand the motivation of this work.  As far as I know
> the QUICC ENGINE is only used on PowerPC based SoCs.
> > >>
> > >> Hm, you're not the Leo Li that participated in this thread
> > >>
> <https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.ke
> rnel.org%2Flkml%2FAM3PR04MB11857AE8D2B0BE56121B97D391C90%40A
> M3PR04MB1185.eurprd04.prod.outlook.com%2FT%2F%23udata=02%7
> C01%7Cqiang.zhao%40nxp.com%7C1ba8c50c2db14b22bef608d756739d82%
> 7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C6370729268771788
> 75sdata=k4zM75OczXwZF%2Br9ec4RxiVR2a%2F8GhSZmK70JYddIck%3
> Dreserved=0>?
> > >
> > > Oops, I totally forgot about this discussion which is just three
> > > years ago.  :)  The QE-HDLC on LS1021a is kind of a special case.
> > >
> > >>
> > >>
> > >>  Can you give an example on how is it used on ARM system?
> > >>
> > >> LS1021A, for example, which is the one I'm aiming for getting fully
> > >> supported in mainline.
> > >> <https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2F
> > >>
> www.nxp.com%2Fproducts%2Fprocessors-and-microcontrollers%2Farm-proc
> > >> essors%2Flayerscape-communication-process%2Fqoriq-layerscape-1021a-
> > >>
> dual-core-communications-processor-with-lcd-controller%3ALS1021A
> > >>
> p;data=02%7C01%7Cqiang.zhao%40nxp.com%7C1ba8c50c2db14b22bef608d
> 7567
> > >>
> 39d82%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C6370729268
> 771788
> > >>
> 75sdata=vqPYSZqEv6vCEIxJshLuA4gngh9J4IsFAQrTwJKMjm4%3Dr
> es
> > >> erved=0>
> > >>
> > >> The forks at
> > >>
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.
> com%2Fqoriq-open-source%2Flinux.gitdata=02%7C01%7Cqiang.zhao%
> 40nxp.com%7C1ba8c50c2db14b22bef608d756739d82%7C686ea1d3bc2b4c6
> fa92cd99c5c301635%7C0%7C0%7C637072926877178875sdata=v4eG
> 4KqGTWQkQHp%2FYg2OHCKITLWaOgH64JYpY%2B1LilA%3Dreserved=0
> have various degrees of support (grep for commits saying stuff like "remove
> PPCisms"
> > >> - some versions can be found on
> > >> <https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2F
> > >>
> lore.kernel.org%2Flkml%2F%3Fq%3Dremove%2Bppcismsdata=02%7C0
> 1%7
> > >>
> Cqiang.zhao%40nxp.com%7C1ba8c50c2db14b22bef608d756739d82%7C686e
> a1d3
> > >>
> bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637072926877178875sdat
> a=i2WdKNHLV68a1mTOMQ%2FoMr0y5ee8edS07xq61M8%2BvPU%3Dr
> eserved=0>). Our current kernel is based on commits from the now-vanished
> 4.1 branch, and unfortunately at least the 4.14 branch (LSDK-18.06-V4.14)
> trivially doesn't build on ARM, despite the PPC32 dependency having been
> removed from CONFIG_QUICC_ENGINE.
> > >
> > > Can you try the 4.14 branch from a newer LSDK release?  LS1021a
> > > should be supported platform on LSDK.  If it is broken, something is
> wrong.
> >
> > What newer release? LSDK-18.06-V4.14 is the latest -V4.14 tag at
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgith
> >
> ub.com%2Fqoriq-open-source%2Flinux.gitdata=02%7C01%7Cqiang.zha
> o%4
> >
> 0nxp.com%7C1ba8c50c2db14b22bef

RE: [EXT] [PATCH v2 6/6] soc/fsl/qe: qe.c: fold qe_get_num_of_snums into qe_snums_init

[Qiang Zhao]

On 2019/5/1 17:29, Rasmus Villemoes  wrote:

> -Original Message-
> From: Rasmus Villemoes 
> Sent: 2019年5月1日 17:29
> To: devicet...@vger.kernel.org; Qiang Zhao ; Leo Li
> 
> Cc: linuxppc-dev@lists.ozlabs.org; linux-arm-ker...@lists.infradead.org;
> linux-ker...@vger.kernel.org; Rob Herring ; Scott Wood
> ; Christophe Leroy ; Mark
> Rutland ; Rasmus Villemoes
> 
> Subject: [PATCH v2 6/6] soc/fsl/qe: qe.c: fold qe_get_num_of_snums into
> qe_snums_init
> 
> The comment "No QE ever has fewer than 28 SNUMs" is false; e.g. the
> MPC8309 has 14. The code path returning -EINVAL is also a recipe for instant
> disaster, since the caller (qe_snums_init) uncritically assigns the return 
> value to
> the unsigned qe_num_of_snum, and would thus proceed to attempt to copy
> 4GB from snum_init_46[] to the snum[] array.
> 
> So fold the handling of the legacy fsl,qe-num-snums into qe_snums_init, and
> make sure we do not end up using the snum_init_46 array in cases other than
> the two where we know it makes sense.
> 
> Signed-off-by: Rasmus Villemoes 
> ---
 
Reviewed-by: Qiang Zhao 

>  drivers/soc/fsl/qe/qe.c | 46 ++---
>  1 file changed, 16 insertions(+), 30 deletions(-)
> 
> diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c index
> 325d689cbf5c..276d7d78ebfc 100644
> --- a/drivers/soc/fsl/qe/qe.c
> +++ b/drivers/soc/fsl/qe/qe.c
> @@ -308,24 +308,33 @@ static void qe_snums_init(void)
> int i;
> 
> bitmap_zero(snum_state, QE_NUM_OF_SNUM);
> +   qe_num_of_snum = 28; /* The default number of snum for threads
> + is 28 */
> qe = qe_get_device_node();
> if (qe) {
> i = of_property_read_variable_u8_array(qe, "fsl,qe-snums",
>snums, 1,
> QE_NUM_OF_SNUM);
> -   of_node_put(qe);
> if (i > 0) {
> +   of_node_put(qe);
> qe_num_of_snum = i;
> return;
> }
> +   /*
> +* Fall back to legacy binding of using the value of
> +* fsl,qe-num-snums to choose one of the static arrays
> +* above.
> +*/
> +   of_property_read_u32(qe, "fsl,qe-num-snums",
> _num_of_snum);
> +   of_node_put(qe);
> }
> 
> -   qe_num_of_snum = qe_get_num_of_snums();
> -
> -   if (qe_num_of_snum == 76)
> +   if (qe_num_of_snum == 76) {
> snum_init = snum_init_76;
> -   else
> +   } else if (qe_num_of_snum == 28 || qe_num_of_snum == 46) {
> snum_init = snum_init_46;
> -
> +   } else {
> +   pr_err("QE: unsupported value of fsl,qe-num-snums: %u\n",
> qe_num_of_snum);
> +   return;
> +   }
> memcpy(snums, snum_init, qe_num_of_snum);  }
> 
> @@ -641,30 +650,7 @@ EXPORT_SYMBOL(qe_get_num_of_risc);
> 
>  unsigned int qe_get_num_of_snums(void)
>  {
> -   struct device_node *qe;
> -   int size;
> -   unsigned int num_of_snums;
> -   const u32 *prop;
> -
> -   num_of_snums = 28; /* The default number of snum for threads is 28
> */
> -   qe = qe_get_device_node();
> -   if (!qe)
> -   return num_of_snums;
> -
> -   prop = of_get_property(qe, "fsl,qe-num-snums", );
> -   if (prop && size == sizeof(*prop)) {
> -   num_of_snums = *prop;
> -   if ((num_of_snums < 28) || (num_of_snums >
> QE_NUM_OF_SNUM)) {
> -   /* No QE ever has fewer than 28 SNUMs */
> -   pr_err("QE: number of snum is invalid\n");
> -   of_node_put(qe);
> -   return -EINVAL;
> -   }
> -   }
> -
> -   of_node_put(qe);
> -
> -   return num_of_snums;
> +   return qe_num_of_snum;
>  }
>  EXPORT_SYMBOL(qe_get_num_of_snums);
> 
> --
> 2.20.1

Best Regards
Qiang Zhao

RE: [PATCH v2 5/6] soc/fsl/qe: qe.c: support fsl,qe-snums property

[Qiang Zhao]

On 2019/5/1 17:29, Rasmus Villemoes  wrote:

> -Original Message-
> From: Rasmus Villemoes 
> Sent: 2019年5月1日 17:29
> To: devicet...@vger.kernel.org; Qiang Zhao ; Leo Li
> 
> Cc: linuxppc-dev@lists.ozlabs.org; linux-arm-ker...@lists.infradead.org;
> linux-ker...@vger.kernel.org; Rob Herring ; Scott Wood
> ; Christophe Leroy ; Mark
> Rutland ; Rasmus Villemoes
> 
> Subject: [PATCH v2 5/6] soc/fsl/qe: qe.c: support fsl,qe-snums property
> 
> Add driver support for the newly introduced fsl,qe-snums property.
> 
> Conveniently, of_property_read_variable_u8_array does exactly what we
> need: If the property fsl,qe-snums is found (and has an allowed size), the 
> array
> of values get copied to snums, and the return value is the number of snums -
> we cannot assign directly to num_of_snums, since we need to check whether
> the return value is negative.
> 
> Signed-off-by: Rasmus Villemoes 
> ---
 
Reviewed-by: Qiang Zhao 

>  drivers/soc/fsl/qe/qe.c | 16 ++--
>  1 file changed, 14 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c index
> 0fb8b59f61ad..325d689cbf5c 100644
> --- a/drivers/soc/fsl/qe/qe.c
> +++ b/drivers/soc/fsl/qe/qe.c
> @@ -283,7 +283,6 @@ EXPORT_SYMBOL(qe_clock_source);
>   */
>  static void qe_snums_init(void)
>  {
> -   int i;
> static const u8 snum_init_76[] = {
> 0x04, 0x05, 0x0C, 0x0D, 0x14, 0x15, 0x1C, 0x1D,
> 0x24, 0x25, 0x2C, 0x2D, 0x34, 0x35, 0x88, 0x89, @@
> -304,7 +303,21 @@ static void qe_snums_init(void)
> 0x28, 0x29, 0x38, 0x39, 0x48, 0x49, 0x58, 0x59,
> 0x68, 0x69, 0x78, 0x79, 0x80, 0x81,
> };
> +   struct device_node *qe;
> const u8 *snum_init;
> +   int i;
> +
> +   bitmap_zero(snum_state, QE_NUM_OF_SNUM);
> +   qe = qe_get_device_node();
> +   if (qe) {
> +   i = of_property_read_variable_u8_array(qe, "fsl,qe-snums",
> +  snums, 1,
> QE_NUM_OF_SNUM);
> +   of_node_put(qe);
> +   if (i > 0) {
> +   qe_num_of_snum = i;
> +   return;
> +   }
> +   }
> 
> qe_num_of_snum = qe_get_num_of_snums();
> 
> @@ -313,7 +326,6 @@ static void qe_snums_init(void)
> else
> snum_init = snum_init_46;
> 
> -   bitmap_zero(snum_state, QE_NUM_OF_SNUM);
> memcpy(snums, snum_init, qe_num_of_snum);  }
> 
> --
> 2.20.1
Best Regards
Qiang Zhao

RE: [PATCH v2 3/6] soc/fsl/qe: qe.c: introduce qe_get_device_node helper

[Qiang Zhao]

On 2019/5/1 17:29, Rasmus Villemoes  wrote:

> -Original Message-
> From: Rasmus Villemoes 
> Sent: 2019年5月1日 17:29
> To: devicet...@vger.kernel.org; Qiang Zhao ; Leo Li
> 
> Cc: linuxppc-dev@lists.ozlabs.org; linux-arm-ker...@lists.infradead.org;
> linux-ker...@vger.kernel.org; Rob Herring ; Scott Wood
> ; Christophe Leroy ; Mark
> Rutland ; Rasmus Villemoes
> 
> Subject: [PATCH v2 3/6] soc/fsl/qe: qe.c: introduce qe_get_device_node
> helper
> 
> The 'try of_find_compatible_node(NULL, NULL, "fsl,qe"), fall back to
> of_find_node_by_type(NULL, "qe")' pattern is repeated five times. Factor it
> into a common helper.
> 
> Reviewed-by: Christophe Leroy 
> Signed-off-by: Rasmus Villemoes 
> ---
 
Reviewed-by: Qiang Zhao 

>  drivers/soc/fsl/qe/qe.c | 71 +
>  1 file changed, 29 insertions(+), 42 deletions(-)
> 
> diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c index
> 303aa29cb27d..0fb8b59f61ad 100644
> --- a/drivers/soc/fsl/qe/qe.c
> +++ b/drivers/soc/fsl/qe/qe.c
> @@ -56,6 +56,20 @@ static unsigned int qe_num_of_snum;
> 
>  static phys_addr_t qebase = -1;
> 
> +static struct device_node *qe_get_device_node(void) {
> +   struct device_node *qe;
> +
> +   /*
> +* Newer device trees have an "fsl,qe" compatible property for the
> QE
> +* node, but we still need to support older device trees.
> +*/
> +   qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
> +   if (qe)
> +   return qe;
> +   return of_find_node_by_type(NULL, "qe"); }
> +
>  static phys_addr_t get_qe_base(void)
>  {
> struct device_node *qe;
> @@ -65,12 +79,9 @@ static phys_addr_t get_qe_base(void)
> if (qebase != -1)
> return qebase;
> 
> -   qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
> -   if (!qe) {
> -   qe = of_find_node_by_type(NULL, "qe");
> -   if (!qe)
> -   return qebase;
> -   }
> +   qe = qe_get_device_node();
> +   if (!qe)
> +   return qebase;
> 
> ret = of_address_to_resource(qe, 0, );
> if (!ret)
> @@ -164,12 +175,9 @@ unsigned int qe_get_brg_clk(void)
> if (brg_clk)
> return brg_clk;
> 
> -   qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
> -   if (!qe) {
> -   qe = of_find_node_by_type(NULL, "qe");
> -   if (!qe)
> -   return brg_clk;
> -   }
> +   qe = qe_get_device_node();
> +   if (!qe)
> +   return brg_clk;
> 
> prop = of_get_property(qe, "brg-frequency", );
> if (prop && size == sizeof(*prop)) @@ -557,16 +565,9 @@ struct
> qe_firmware_info *qe_get_firmware_info(void)
> 
> initialized = 1;
> 
> -   /*
> -* Newer device trees have an "fsl,qe" compatible property for the QE
> -* node, but we still need to support older device trees.
> -   */
> -   qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
> -   if (!qe) {
> -   qe = of_find_node_by_type(NULL, "qe");
> -   if (!qe)
> -   return NULL;
> -   }
> +   qe = qe_get_device_node();
> +   if (!qe)
> +   return NULL;
> 
> /* Find the 'firmware' child node */
> fw = of_get_child_by_name(qe, "firmware"); @@ -612,16 +613,9
> @@ unsigned int qe_get_num_of_risc(void)
> unsigned int num_of_risc = 0;
> const u32 *prop;
> 
> -   qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
> -   if (!qe) {
> -   /* Older devices trees did not have an "fsl,qe"
> -* compatible property, so we need to look for
> -* the QE node by name.
> -*/
> -   qe = of_find_node_by_type(NULL, "qe");
> -   if (!qe)
> -   return num_of_risc;
> -   }
> +   qe = qe_get_device_node();
> +   if (!qe)
> +   return num_of_risc;
> 
> prop = of_get_property(qe, "fsl,qe-num-riscs", );
> if (prop && size == sizeof(*prop)) @@ -641,16 +635,9 @@ unsigned
> int qe_get_num_of_snums(void)
> const u32 *prop;
> 
> num_of_snums = 28; /* The default number of snum for threads is 28
> */
> -   qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
> -   if (!qe) {
> -   /* Older devices trees did not have an "fsl,qe"
> -* compatible property, so we need to look for
> -* the QE node by name.
> -*/
> -   qe = of_find_node_by_type(NULL, "qe");
> -   if (!qe)
> -   return num_of_snums;
> -   }
> +   qe = qe_get_device_node();
> +   if (!qe)
> +   return num_of_snums;
> 
> prop = of_get_property(qe, "fsl,qe-num-snums", );
> if (prop && size == sizeof(*prop)) {
> --
> 2.20.1


Best Regards
Qiang Zhao

RE: PATCH v2 2/6] soc/fsl/qe: qe.c: reduce static memory footprint by 1.7K

[Qiang Zhao]

On 2019/5/1 17:29, Rasmus Villemoes  wrote:

> -Original Message-
> From: Rasmus Villemoes 
> Sent: 2019年5月1日 17:29
> To: devicet...@vger.kernel.org; Qiang Zhao ; Leo Li
> 
> Cc: linuxppc-dev@lists.ozlabs.org; linux-arm-ker...@lists.infradead.org;
> linux-ker...@vger.kernel.org; Rob Herring ; Scott Wood
> ; Christophe Leroy ; Mark
> Rutland ; Rasmus Villemoes
> 
> Subject: [PATCH v2 2/6] soc/fsl/qe: qe.c: reduce static memory footprint
> by 1.7K
> 
> The current array of struct qe_snum use 256*4 bytes for just keeping track of
> the free/used state of each index, and the struct layout means there's another
> 768 bytes of padding. If we just unzip that structure, the array of snum 
> values
> just use 256 bytes, while the free/inuse state can be tracked in a 32 byte
> bitmap.
> 
> So this reduces the .data footprint by 1760 bytes. It also serves as 
> preparation
> for introducing another DT binding for specifying the snum values.
> 
> Signed-off-by: Rasmus Villemoes 
 
Reviewed-by: Qiang Zhao 

> ---
>  drivers/soc/fsl/qe/qe.c | 43 -
>  1 file changed, 12 insertions(+), 31 deletions(-)
> 
> diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c index
> 855373deb746..303aa29cb27d 100644
> --- a/drivers/soc/fsl/qe/qe.c
> +++ b/drivers/soc/fsl/qe/qe.c
> @@ -14,6 +14,7 @@
>   * Free Software Foundation;  either version 2 of the  License, or (at your
>   * option) any later version.
>   */
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -43,25 +44,14 @@ static DEFINE_SPINLOCK(qe_lock);
> DEFINE_SPINLOCK(cmxgcr_lock);  EXPORT_SYMBOL(cmxgcr_lock);
> 
> -/* QE snum state */
> -enum qe_snum_state {
> -   QE_SNUM_STATE_USED,
> -   QE_SNUM_STATE_FREE
> -};
> -
> -/* QE snum */
> -struct qe_snum {
> -   u8 num;
> -   enum qe_snum_state state;
> -};
> -
>  /* We allocate this here because it is used almost exclusively for
>   * the communication processor devices.
>   */
>  struct qe_immap __iomem *qe_immr;
>  EXPORT_SYMBOL(qe_immr);
> 
> -static struct qe_snum snums[QE_NUM_OF_SNUM];   /* Dynamically
> allocated SNUMs */
> +static u8 snums[QE_NUM_OF_SNUM];   /* Dynamically allocated
> SNUMs */
> +static DECLARE_BITMAP(snum_state, QE_NUM_OF_SNUM);
>  static unsigned int qe_num_of_snum;
> 
>  static phys_addr_t qebase = -1;
> @@ -315,10 +305,8 @@ static void qe_snums_init(void)
> else
> snum_init = snum_init_46;
> 
> -   for (i = 0; i < qe_num_of_snum; i++) {
> -   snums[i].num = snum_init[i];
> -   snums[i].state = QE_SNUM_STATE_FREE;
> -   }
> +   bitmap_zero(snum_state, QE_NUM_OF_SNUM);
> +   memcpy(snums, snum_init, qe_num_of_snum);
>  }
> 
>  int qe_get_snum(void)
> @@ -328,12 +316,10 @@ int qe_get_snum(void)
> int i;
> 
> spin_lock_irqsave(_lock, flags);
> -   for (i = 0; i < qe_num_of_snum; i++) {
> -   if (snums[i].state == QE_SNUM_STATE_FREE) {
> -   snums[i].state = QE_SNUM_STATE_USED;
> -   snum = snums[i].num;
> -   break;
> -   }
> +   i = find_first_zero_bit(snum_state, qe_num_of_snum);
> +   if (i < qe_num_of_snum) {
> +   set_bit(i, snum_state);
> +   snum = snums[i];
> }
> spin_unlock_irqrestore(_lock, flags);
> 
> @@ -343,14 +329,9 @@ EXPORT_SYMBOL(qe_get_snum);
> 
>  void qe_put_snum(u8 snum)
>  {
> -   int i;
> -
> -   for (i = 0; i < qe_num_of_snum; i++) {
> -   if (snums[i].num == snum) {
> -   snums[i].state = QE_SNUM_STATE_FREE;
> -   break;
> -   }
> -   }
> +   const u8 *p = memchr(snums, snum, qe_num_of_snum);
> +   if (p)
> +   clear_bit(p - snums, snum_state);
>  }
>  EXPORT_SYMBOL(qe_put_snum);
> 
> --
> 2.20.1
Best Regards
Qiang Zhao

RE: PATCH v2 1/6] soc/fsl/qe: qe.c: drop useless static qualifier

[Qiang Zhao]

On 2019/5/1 17:29, Rasmus Villemoes  wrote:
> -Original Message-
> From: Rasmus Villemoes 
> Sent: 2019年5月1日 17:29
> To: devicet...@vger.kernel.org; Qiang Zhao ; Leo Li
> 
> Cc: linuxppc-dev@lists.ozlabs.org; linux-arm-ker...@lists.infradead.org;
> linux-ker...@vger.kernel.org; Rob Herring ; Scott Wood
> ; Christophe Leroy ; Mark
> Rutland ; Rasmus Villemoes
> 
> Subject: [PATCH v2 1/6] soc/fsl/qe: qe.c: drop useless static qualifier
> 
> The local variable snum_init has no reason to have static storage duration.
> 
> Reviewed-by: Christophe Leroy 
> Signed-off-by: Rasmus Villemoes 

Reviewed-by: Qiang Zhao 

> ---
>  drivers/soc/fsl/qe/qe.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c index
> 612d9c551be5..855373deb746 100644
> --- a/drivers/soc/fsl/qe/qe.c
> +++ b/drivers/soc/fsl/qe/qe.c
> @@ -306,7 +306,7 @@ static void qe_snums_init(void)
> 0x28, 0x29, 0x38, 0x39, 0x48, 0x49, 0x58, 0x59,
> 0x68, 0x69, 0x78, 0x79, 0x80, 0x81,
> };
> -   static const u8 *snum_init;
> +   const u8 *snum_init;
> 
> qe_num_of_snum = qe_get_num_of_snums();
> 
> --
> 2.20.1


Best Regards
Qiang Zhao

RE: [PATCH] soc/fsl/qe: fix err handling of ucc_of_parse_tdm

[Qiang Zhao]

Hi Wen,

Will you send another version to resolve the issue described in the comments?

BR
Qiang

> -Original Message-
> From: Li Yang 
> Sent: 2018年12月6日 4:10
> To: wang.y...@zte.com.cn
> Cc: Qiang Zhao ; zhong.weid...@zte.com.cn; lkml
> ; julia.law...@lip6.fr; linuxppc-dev
> ; wen.yan...@zte.com.cn; moderated
> list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
> 
> Subject: Re: [PATCH] soc/fsl/qe: fix err handling of ucc_of_parse_tdm
> 
> On Thu, Nov 22, 2018 at 2:42 PM Yi Wang  wrote:
> >
> > From: Wen Yang 
> >
> > Currently there are 2 problems with the ucc_of_parse_tdm function:
> > 1,a possible null pointer dereference in ucc_of_parse_tdm, detected by
> > the semantic patch deref_null.cocci, with the following warning:
> > drivers/soc/fsl/qe/qe_tdm.c:177:21-24: ERROR: pdev is NULL but
> dereferenced.
> > 2,dev gets modified, so in any case that devm_iounmap() will fail even
> > when the new pdev is valid, because the iomap was done with a different
> pdev.
> > This patch fixes them.
> 
> While we are at this, I think this logic need more serious fixing.  I see 
> there is
> no driver bind with the "fsl,t1040-qe-si" or "fsl,t1040-qe-siram" device.  So
> allocating resources using devm_*() with these devices won't provide a
> cleanup path for these resources when the caller fails.  I think we should
> probably allocate resource under device of caller (e.g. ucc-hdlc), so that 
> when
> caller probe fails or is removed it will trigger the cleanup.
> 
> >
> > Suggested-by: Christophe LEROY 
> > Signed-off-by: Wen Yang 
> > CC: Julia Lawall 
> > CC: Zhao Qiang 
> > ---
> >  drivers/soc/fsl/qe/qe_tdm.c | 20 ++--
> >  1 file changed, 10 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/soc/fsl/qe/qe_tdm.c b/drivers/soc/fsl/qe/qe_tdm.c
> > index f78c346..9a29f0b 100644
> > --- a/drivers/soc/fsl/qe/qe_tdm.c
> > +++ b/drivers/soc/fsl/qe/qe_tdm.c
> > @@ -47,7 +47,7 @@ int ucc_of_parse_tdm(struct device_node *np, struct
> ucc_tdm *utdm,
> > struct resource *res;
> > struct device_node *np2;
> > static int siram_init_flag;
> > -   struct platform_device *pdev;
> > +   struct platform_device *pdev_si, *pdev_siram;
> >
> > sprop = of_get_property(np, "fsl,rx-sync-clock", NULL);
> > if (sprop) {
> > @@ -129,16 +129,16 @@ int ucc_of_parse_tdm(struct device_node *np,
> struct ucc_tdm *utdm,
> > if (!np2)
> > return -EINVAL;
> >
> > -   pdev = of_find_device_by_node(np2);
> > -   if (!pdev) {
> > +   pdev_si = of_find_device_by_node(np2);
> > +   if (!pdev_si) {
> > pr_err("%pOFn: failed to lookup pdev\n", np2);
> > of_node_put(np2);
> > return -EINVAL;
> > }
> >
> > of_node_put(np2);
> > -   res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > -   utdm->si_regs = devm_ioremap_resource(>dev, res);
> > +   res = platform_get_resource(pdev_si, IORESOURCE_MEM, 0);
> > +   utdm->si_regs = devm_ioremap_resource(_si->dev, res);
> > if (IS_ERR(utdm->si_regs)) {
> > ret = PTR_ERR(utdm->si_regs);
> > goto err_miss_siram_property; @@ -150,8 +150,8 @@
> int
> > ucc_of_parse_tdm(struct device_node *np, struct ucc_tdm *utdm,
> > goto err_miss_siram_property;
> > }
> >
> > -   pdev = of_find_device_by_node(np2);
> > -   if (!pdev) {
> > +   pdev_siram = of_find_device_by_node(np2);
> > +   if (!pdev_siram) {
> > ret = -EINVAL;
> > pr_err("%pOFn: failed to lookup pdev\n", np2);
> > of_node_put(np2);
> > @@ -159,8 +159,8 @@ int ucc_of_parse_tdm(struct device_node *np, struct
> ucc_tdm *utdm,
> > }
> >
> > of_node_put(np2);
> > -   res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > -   utdm->siram = devm_ioremap_resource(>dev, res);
> > +   res = platform_get_resource(pdev_siram, IORESOURCE_MEM, 0);
> > +   utdm->siram = devm_ioremap_resource(_siram->dev, res);
> > if (IS_ERR(utdm->siram)) {
> > ret = PTR_ERR(utdm->siram);
> > goto err_miss_siram_property; @@ -174,7 +174,7 @@
> int
> > ucc_of_parse_tdm(struct device_node *np, struct ucc_tdm *utdm,
> > return ret;
> >
> >  err_miss_siram_property:
> > -   devm_iounmap(>dev, utdm->si_regs);
> > +   devm_iounmap(_si->dev, utdm->si_regs);
> > return ret;
> >  }
> >  EXPORT_SYMBOL(ucc_of_parse_tdm);
> > --
> > 2.9.5
> >

RE: [PATCH] soc: fsl/qe: Use of_get_child_by_name helper

[Qiang Zhao]

From: Rob Herring 
date: 2018/8/30 4:04

> To: Qiang Zhao 
> Cc: linux-ker...@vger.kernel.org; Leo Li ;
> linuxppc-dev@lists.ozlabs.org; linux-arm-ker...@lists.infradead.org
> Subject: [PATCH] soc: fsl/qe: Use of_get_child_by_name helper
> 
> Use the of_get_child_by_name() helper instead of open coding searching for the
> 'firmware' child node. This removes directly accessing the name pointer as 
> well.
> 
> Cc: Qiang Zhao 
> Cc: Li Yang 
> Cc: linuxppc-dev@lists.ozlabs.org
> Cc: linux-arm-ker...@lists.infradead.org
> Signed-off-by: Rob Herring 
> ---
>  drivers/soc/fsl/qe/qe.c | 6 +-
>  1 file changed, 1 insertion(+), 5 deletions(-)
> 
> diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c index
> 2ef6fc6487c1..612d9c551be5 100644
> --- a/drivers/soc/fsl/qe/qe.c
> +++ b/drivers/soc/fsl/qe/qe.c
> @@ -588,11 +588,7 @@ struct qe_firmware_info *qe_get_firmware_info(void)
>   }
> 
>   /* Find the 'firmware' child node */
> - for_each_child_of_node(qe, fw) {
> - if (strcmp(fw->name, "firmware") == 0)
> - break;
> - }
> -
> + fw = of_get_child_by_name(qe, "firmware");
>   of_node_put(qe);
> 
>   /* Did we find the 'firmware' node? */
> --

Acked-by: Qiang Zhao 

RE: [PATCH] soc: Convert to using %pOFn instead of device_node.name

[Qiang Zhao]

From: Rob Herring 
Date: 2018年8月28日 9:53
> To: linux-ker...@vger.kernel.org
> Cc: Qiang Zhao ; Leo Li ; Andy
> Gross ; David Brown ; Heiko
> Stuebner ; Thierry Reding ;
> Jonathan Hunter ; Santosh Shilimkar
> ; linuxppc-dev@lists.ozlabs.org;
> linux-arm-ker...@lists.infradead.org; linux-...@vger.kernel.org
> Subject: [PATCH] soc: Convert to using %pOFn instead of device_node.name
> 
> In preparation to remove the node name pointer from struct device_node,
> convert printf users to use the %pOFn format specifier.
> 
> Cc: Qiang Zhao 
> Cc: Li Yang 
> Cc: Andy Gross 
> Cc: David Brown 
> Cc: Heiko Stuebner 
> Cc: Thierry Reding 
> Cc: Jonathan Hunter 
> Cc: Santosh Shilimkar 
> Cc: linuxppc-dev@lists.ozlabs.org
> Cc: linux-arm-ker...@lists.infradead.org
> Cc: linux-...@vger.kernel.org
> Signed-off-by: Rob Herring 
> ---
>  drivers/soc/dove/pmu.c|  8 +++---
>  drivers/soc/fsl/qe/qe_tdm.c   |  4 +--
>  drivers/soc/qcom/apr.c|  2 +-
>  drivers/soc/rockchip/pm_domains.c | 44 +++
>  drivers/soc/tegra/pmc.c   | 12 -
>  drivers/soc/ti/knav_dma.c |  8 +++---
>  drivers/soc/ti/knav_qmss_queue.c  |  8 +++---
>  7 files changed, 43 insertions(+), 43 deletions(-)

For qe_tdm part
Acked-by: Qiang Zhao 

RE: [PATCH 4/6] net/wan/fsl_ucc_hdlc: default hmask value

[Qiang Zhao]

From: David Gounaris 
Date: 2018/8/28 19:09
> Subject: [PATCH 4/6] net/wan/fsl_ucc_hdlc: default hmask value
> 
> Set default HMASK to 0x to use
> promiscuous mode in the hdlc controller.
> 
> Signed-off-by: David Gounaris 
> ---
>  drivers/net/wan/fsl_ucc_hdlc.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/net/wan/fsl_ucc_hdlc.h b/drivers/net/wan/fsl_ucc_hdlc.h
> index c21134c1f180..5bc3d1a6ca6e 100644
> --- a/drivers/net/wan/fsl_ucc_hdlc.h
> +++ b/drivers/net/wan/fsl_ucc_hdlc.h
> @@ -134,7 +134,7 @@ struct ucc_hdlc_private {
> 
>  #define HDLC_HEAD_MASK   0x
>  #define DEFAULT_HDLC_HEAD0xff44
> -#define DEFAULT_ADDR_MASK0x00ff
> +#define DEFAULT_ADDR_MASK0x
>  #define DEFAULT_HDLC_ADDR0x00ff
> 
>  #define BMR_GBL  0x2000
> --

It is not proper to set default HMASK to 0x, how about to add a new 
property standing for hmask into device tree,
If get this property from dtb, then set it with the value from dtb, otherwise, 
set it with default HMASK ox00ff?

Best Regards
Qiang Zhao

RE: [PATCH] QE GPIO: Add qe_gpio_set_multiple

[Qiang Zhao]

On 06/19/2018 09:22 AM, Joakim Tjernlund wrote:
-Original Message-
From: Linuxppc-dev 
[mailto:linuxppc-dev-bounces+qiang.zhao=nxp@lists.ozlabs.org] On Behalf Of 
Joakim Tjernlund
Sent: 2018年6月20日 0:22
To: York Sun ; linuxppc-dev 
Subject: [PATCH] QE GPIO: Add qe_gpio_set_multiple

This cousin to gpio-mpc8xxx was lacking a multiple pins method, add one.

Signed-off-by: Joakim Tjernlund 
---
 drivers/soc/fsl/qe/gpio.c | 28 
 1 file changed, 28 insertions(+)

diff --git a/drivers/soc/fsl/qe/gpio.c b/drivers/soc/fsl/qe/gpio.c index 
3b27075c21a7..819bed0f5667 100644
--- a/drivers/soc/fsl/qe/gpio.c
+++ b/drivers/soc/fsl/qe/gpio.c
@@ -83,6 +83,33 @@ static void qe_gpio_set(struct gpio_chip *gc, unsigned int 
gpio, int val)
spin_unlock_irqrestore(_gc->lock, flags);  }
 
+static void qe_gpio_set_multiple(struct gpio_chip *gc,
+unsigned long *mask, unsigned long *bits) {
+   struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+   struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
+   struct qe_pio_regs __iomem *regs = mm_gc->regs;
+   unsigned long flags;
+   int i;
+
+   spin_lock_irqsave(_gc->lock, flags);
+
+   for (i = 0; i < gc->ngpio; i++) {
+   if (*mask == 0)
+   break;
+   if (__test_and_clear_bit(i, mask)) {
+   if (test_bit(i, bits))
+   qe_gc->cpdata |= (1U << (QE_PIO_PINS - 1 - i));
+   else
+   qe_gc->cpdata &= ~(1U << (QE_PIO_PINS - 1 - i));
+   }
+   }
+
+   out_be32(>cpdata, qe_gc->cpdata);
+
+   spin_unlock_irqrestore(_gc->lock, flags); }
+
 static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)  {
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); @@ -298,6 
+325,7 @@ static int __init qe_add_gpiochips(void)
gc->direction_output = qe_gpio_dir_out;
gc->get = qe_gpio_get;
gc->set = qe_gpio_set;
+   gc->set_multiple = qe_gpio_set_multiple;
 
ret = of_mm_gpiochip_add_data(np, mm_gc, qe_gc);
if (ret)

Reviewed-by: Qiang Zhao 

RE: [bug report] fsl/qe: setup clock source for TDM mode

[Qiang Zhao]

On 2018/1/31 23:30, Dan Carpenter <dan.carpen...@oracle.com> wrote

-Original Message-
From: Dan Carpenter [mailto:dan.carpen...@oracle.com] 
Sent: 2018年1月31日 23:30
To: Qiang Zhao <qiang.z...@nxp.com>
Cc: linuxppc-dev@lists.ozlabs.org
Subject: [bug report] fsl/qe: setup clock source for TDM mode

Hello Zhao Qiang,

The patch bb8b2062aff3: "fsl/qe: setup clock source for TDM mode"
from Jun 6, 2016, leads to the following static checker warning:

drivers/soc/fsl/qe/ucc.c:629 ucc_get_tdm_sync_shift()
warn: both sides of ternary the same: '30' RX_SYNC_SHIFT_BASE 
RX_SYNC_SHIFT_BASE

drivers/soc/fsl/qe/ucc.c
   625  static u32 ucc_get_tdm_sync_shift(enum comm_dir mode, u32 tdm_num)
   626  {
   627  u32 shift;
   628  
   629  shift = (mode == COMM_DIR_RX) ? RX_SYNC_SHIFT_BASE : 
RX_SYNC_SHIFT_BASE;
 
^^

Maybe this one should have been TX_?

Thank you very much, it is a typo, I will send a patch to fix it.

BR
Qiang Zhao

RE: [PATCH v10 0/4] this patchset is to remove PPCisms for QEIC

[Qiang Zhao]

On Wed, 1 Nov 2017, Thomas Gleixner <t...@linutronix.de> wrote:


> -Original Message-
> From: Thomas Gleixner [mailto:t...@linutronix.de]
> Sent: Thursday, November 02, 2017 1:10 AM
> To: Qiang Zhao <qiang.z...@nxp.com>
> Cc: Michael Ellerman <m...@ellerman.id.au>; Jason Cooper
> <ja...@lakedaemon.net>; Marc Zyngier <marc.zyng...@arm.com>;
> o...@buserror.net; linuxppc-dev@lists.ozlabs.org; Xiaobo Xie
> <xiaobo@nxp.com>; linux-ker...@vger.kernel.org
> Subject: RE: [PATCH v10 0/4] this patchset is to remove PPCisms for QEIC
> 
> On Wed, 1 Nov 2017, Qiang Zhao wrote:
> > Michael Ellerman <m...@ellerman.id.au> wrote
> > >
> > > Qiang Zhao <qiang.z...@nxp.com> writes:
> > >
> > > > Hi all,
> > > >
> > > > Could anybody review this patchset and take action on them? Thank you!
> > >
> > > Who maintains this? I don't actually know, it's not powerpc code, or is 
> > > it?
> >
> > Yes, it's not powerpc code, it is irqchip code, maintained by Thomas, Jason 
> > and
> Marc according to MAINTAINERS file.
> >
> > Hi Thomas, Jason and Marc,
> >
> > Could you keep an eye on this patchset? Thank you!
> 
> It's on my radar, but I have zero capacity at the moment. Hopefully Marc can
> spare a few cycles.
> 
> Thanks,
> 
>   tglx

Thank you!

Best Regards
Qiang Zhao

RE: [Patch v10] QE: remove PPCisms for QE

[Qiang Zhao]

On 01/11/17 05:19PM, Julien Thierry <julien.thie...@arm.com> wrote:
> -Original Message-
> From: Julien Thierry [mailto:julien.thie...@arm.com]
> Sent: Wednesday, November 01, 2017 5:19 PM
> To: Qiang Zhao <qiang.z...@nxp.com>; o...@buserror.net
> Cc: linuxppc-dev@lists.ozlabs.org; linux-arm-ker...@lists.infradead.org
> Subject: Re: [Patch v10] QE: remove PPCisms for QE
> 
> Hi Zhao,
> 
> I just noticed a small nit.
> 
> > /* wait for the QE_CR_FLG to clear */
> > -   ret = spin_event_timeout((in_be32(_immr->cp.cecr) & QE_CR_FLG)
> == 0,
> > -  100, 0);
> > +   ret = -EIO;
> > +   for (i = 0; i < 100; i++) {
> > +   if ((ioread32be(_immr->cp.cecr) & QE_CR_FLG) == 0) {
> > +   ret = 0;
> > +   break;
> > +   }
> > +   udelay(1);
> > +   }
> > +
> > /* On timeout (e.g. failure), the expression will be false (ret == 0),
> >otherwise it will be true (ret == 1). */
> 
> nit:
> The comment here is no longer valid, on timeout ret == -EIO and on success 0. 
> It
> should probably be removed to avoid confusion.

So thank you for you reminder, I ignored it, and will fix in the next version.
 
BR
-Qiang Zhao

RE: [PATCH v10 0/4] this patchset is to remove PPCisms for QEIC

[Qiang Zhao]

Michael Ellerman <m...@ellerman.id.au> wrote
> 
> Qiang Zhao <qiang.z...@nxp.com> writes:
> 
> > Hi all,
> >
> > Could anybody review this patchset and take action on them? Thank you!
> 
> Who maintains this? I don't actually know, it's not powerpc code, or is it?

Yes, it's not powerpc code, it is irqchip code, maintained by Thomas, Jason and 
Marc according to MAINTAINERS file.

Hi Thomas, Jason and Marc,

Could you keep an eye on this patchset? Thank you!

Best Regards
Qiang Zhao

RE: [PATCH v10 0/4] this patchset is to remove PPCisms for QEIC

[Qiang Zhao]

Hi all,

Could anybody review this patchset and take action on them? Thank you!

Best Regards
Qiang Zhao

> > -Original Message-
> > From: Zhao Qiang [mailto:qiang.z...@nxp.com]
> > Sent: Monday, August 07, 2017 11:07 AM
> > To: t...@linutronix.de
> > Cc: o...@buserror.net; Xiaobo Xie <xiaobo@nxp.com>; linux-
> > ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; Qiang Zhao
> > <qiang.z...@nxp.com>
> > Subject: [PATCH v10 0/4] this patchset is to remove PPCisms for QEIC
> >
> > QEIC is supported more than just powerpc boards, so remove PPCisms.
> >
> > changelog:
> > Changes for v8:
> > - use IRQCHIP_DECLARE() instead of subsys_initcall in qeic driver
> > - remove include/soc/fsl/qe/qe_ic.h
> > Changes for v9:
> > - rebase
> > - fix the compile issue when apply the second patch, in fact, there
> > was no compile issue
> >   when apply all the patches of this patchset
> > Changes for v10:
> > - simplify codes, remove duplicated codes
> >
> > Zhao Qiang (4):
> >   irqchip/qeic: move qeic driver from drivers/soc/fsl/qe
> > Changes for v2:
> > - modify the subject and commit msg
> > Changes for v3:
> > - merge .h file to .c, rename it with irq-qeic.c
> > Changes for v4:
> > - modify comments
> > Changes for v5:
> > - disable rename detection
> > Changes for v6:
> > - rebase
> > Changes for v7:
> > - na
> >
> >   irqchip/qeic: merge qeic init code from platforms to a common function
> > Changes for v2:
> > - modify subject and commit msg
> > - add check for qeic by type
> > Changes for v3:
> > - na
> > Changes for v4:
> > - na
> > Changes for v5:
> > - na
> > Changes for v6:
> > - rebase
> > Changes for v7:
> > - na
> > Changes for v8:
> > - use IRQCHIP_DECLARE() instead of subsys_initcall
> >
> >   irqchip/qeic: merge qeic_of_init into qe_ic_init
> > Changes for v2:
> > - modify subject and commit msg
> > - return 0 and add put node when return in qe_ic_init
> > Changes for v3:
> > - na
> > Changes for v4:
> > - na
> > Changes for v5:
> > - na
> > Changes for v6:
> > - rebase
> > Changes for v7:
> > - na
> >
> >   irqchip/qeic: remove PPCisms for QEIC
> > Changes for v6:
> > - new added
> > Changes for v7:
> > - fix warning
> > Changes for v8:
> > - remove include/soc/fsl/qe/qe_ic.h
> >
> > Zhao Qiang (4):
> >   irqchip/qeic: move qeic driver from drivers/soc/fsl/qe
> >   irqchip/qeic: merge qeic init code from platforms to a common function
> >   irqchip/qeic: merge qeic_of_init into qe_ic_init
> >   irqchip/qeic: remove PPCisms for QEIC
> >
> >  MAINTAINERS|   6 +
> >  arch/powerpc/platforms/83xx/km83xx.c   |   1 -
> >  arch/powerpc/platforms/83xx/misc.c |  16 -
> >  arch/powerpc/platforms/83xx/mpc832x_mds.c  |   1 -
> >  arch/powerpc/platforms/83xx/mpc832x_rdb.c  |   1 -
> >  arch/powerpc/platforms/83xx/mpc836x_mds.c  |   1 -
> >  arch/powerpc/platforms/83xx/mpc836x_rdk.c  |   1 -
> >  arch/powerpc/platforms/85xx/corenet_generic.c  |  10 -
> >  arch/powerpc/platforms/85xx/mpc85xx_mds.c  |  15 -
> >  arch/powerpc/platforms/85xx/mpc85xx_rdb.c  |  17 -
> >  arch/powerpc/platforms/85xx/twr_p102x.c|  15 -
> >  drivers/irqchip/Makefile   |   1 +
> >  drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} | 358 
> > -
> >  drivers/soc/fsl/qe/Makefile|   2 +-
> >  drivers/soc/fsl/qe/qe_ic.h | 103 --
> >  include/soc/fsl/qe/qe_ic.h | 139 
> >  16 files changed, 218 insertions(+), 469 deletions(-)  rename
> > drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} (58%)  delete mode
> > 100644 drivers/soc/fsl/qe/qe_ic.h  delete mode 100644
> > include/soc/fsl/qe/qe_ic.h
> >
> > --
> > 2.1.0.27.g96db324

RE: [PATCH v10 0/4] this patchset is to remove PPCisms for QEIC

[Qiang Zhao]

Hi all,

Could anybody review this patchset and take action on them? Thank you!

Best Regards
Qiang Zhao

> -Original Message-
> From: Zhao Qiang [mailto:qiang.z...@nxp.com]
> Sent: Monday, August 07, 2017 11:07 AM
> To: t...@linutronix.de
> Cc: o...@buserror.net; Xiaobo Xie <xiaobo@nxp.com>; linux-
> ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; Qiang Zhao
> <qiang.z...@nxp.com>
> Subject: [PATCH v10 0/4] this patchset is to remove PPCisms for QEIC
> 
> QEIC is supported more than just powerpc boards, so remove PPCisms.
> 
> changelog:
>   Changes for v8:
>   - use IRQCHIP_DECLARE() instead of subsys_initcall in qeic driver
>   - remove include/soc/fsl/qe/qe_ic.h
>   Changes for v9:
>   - rebase
>   - fix the compile issue when apply the second patch, in fact, there was
> no compile issue
> when apply all the patches of this patchset
>   Changes for v10:
>   - simplify codes, remove duplicated codes
> 
> Zhao Qiang (4):
>   irqchip/qeic: move qeic driver from drivers/soc/fsl/qe
>   Changes for v2:
>   - modify the subject and commit msg
>   Changes for v3:
>   - merge .h file to .c, rename it with irq-qeic.c
>   Changes for v4:
>   - modify comments
>   Changes for v5:
>   - disable rename detection
>   Changes for v6:
>   - rebase
>   Changes for v7:
>   - na
> 
>   irqchip/qeic: merge qeic init code from platforms to a common function
>   Changes for v2:
>   - modify subject and commit msg
>   - add check for qeic by type
>   Changes for v3:
>   - na
>   Changes for v4:
>   - na
>   Changes for v5:
>   - na
>   Changes for v6:
>   - rebase
>   Changes for v7:
>   - na
>   Changes for v8:
>   - use IRQCHIP_DECLARE() instead of subsys_initcall
> 
>   irqchip/qeic: merge qeic_of_init into qe_ic_init
>   Changes for v2:
>   - modify subject and commit msg
>   - return 0 and add put node when return in qe_ic_init
>   Changes for v3:
>   - na
>   Changes for v4:
>   - na
>   Changes for v5:
>   - na
>   Changes for v6:
>   - rebase
>   Changes for v7:
>   - na
> 
>   irqchip/qeic: remove PPCisms for QEIC
>   Changes for v6:
>   - new added
>   Changes for v7:
>   - fix warning
>   Changes for v8:
>   - remove include/soc/fsl/qe/qe_ic.h
> 
> Zhao Qiang (4):
>   irqchip/qeic: move qeic driver from drivers/soc/fsl/qe
>   irqchip/qeic: merge qeic init code from platforms to a common function
>   irqchip/qeic: merge qeic_of_init into qe_ic_init
>   irqchip/qeic: remove PPCisms for QEIC
> 
>  MAINTAINERS|   6 +
>  arch/powerpc/platforms/83xx/km83xx.c   |   1 -
>  arch/powerpc/platforms/83xx/misc.c |  16 -
>  arch/powerpc/platforms/83xx/mpc832x_mds.c  |   1 -
>  arch/powerpc/platforms/83xx/mpc832x_rdb.c  |   1 -
>  arch/powerpc/platforms/83xx/mpc836x_mds.c  |   1 -
>  arch/powerpc/platforms/83xx/mpc836x_rdk.c  |   1 -
>  arch/powerpc/platforms/85xx/corenet_generic.c  |  10 -
>  arch/powerpc/platforms/85xx/mpc85xx_mds.c  |  15 -
>  arch/powerpc/platforms/85xx/mpc85xx_rdb.c  |  17 -
>  arch/powerpc/platforms/85xx/twr_p102x.c|  15 -
>  drivers/irqchip/Makefile   |   1 +
>  drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} | 358 
> -
>  drivers/soc/fsl/qe/Makefile|   2 +-
>  drivers/soc/fsl/qe/qe_ic.h | 103 --
>  include/soc/fsl/qe/qe_ic.h | 139 
>  16 files changed, 218 insertions(+), 469 deletions(-)  rename
> drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} (58%)  delete mode 100644
> drivers/soc/fsl/qe/qe_ic.h  delete mode 100644 include/soc/fsl/qe/qe_ic.h
> 
> --
> 2.1.0.27.g96db324

RE: [PATCH v10 4/4] irqchip/qeic: remove PPCisms for QEIC

[Qiang Zhao]

On Tue 8/8/2017 6:05 PM, Michael Ellerman <m...@ellerman.id.au> wrote:

> -Original Message-
> From: Michael Ellerman [mailto:m...@ellerman.id.au]
> Sent: Tuesday, August 08, 2017 6:05 PM
> To: Qiang Zhao <qiang.z...@nxp.com>; t...@linutronix.de
> Cc: o...@buserror.net; linuxppc-dev@lists.ozlabs.org; Xiaobo Xie
> <xiaobo@nxp.com>; linux-ker...@vger.kernel.org
> Subject: RE: [PATCH v10 4/4] irqchip/qeic: remove PPCisms for QEIC
> 
> Qiang Zhao <qiang.z...@nxp.com> writes:
> 
> > On Mon 8/7/2017 3:02 PM, Michael Ellerman <m...@ellerman.id.au> wrote:
> >
> >> -Original Message-
> >> From: Michael Ellerman [mailto:m...@ellerman.id.au]
> >> Sent: Monday, August 07, 2017 3:02 PM
> >> To: Qiang Zhao <qiang.z...@nxp.com>; t...@linutronix.de
> >> Cc: o...@buserror.net; Qiang Zhao <qiang.z...@nxp.com>; linuxppc-
> >> d...@lists.ozlabs.org; Xiaobo Xie <xiaobo@nxp.com>; linux-
> >> ker...@vger.kernel.org
> >> Subject: Re: [PATCH v10 4/4] irqchip/qeic: remove PPCisms for QEIC
> >>
> >> Zhao Qiang <qiang.z...@nxp.com> writes:
> >>
> >> > QEIC was supported on PowerPC, and dependent on PPC, Now it is
> >> > supported on other platforms, so remove PPCisms.
> >> >
> >> > Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
> >> > ---
> >> >  arch/powerpc/platforms/83xx/km83xx.c  |   1 -
> >> >  arch/powerpc/platforms/83xx/misc.c|   1 -
> >> >  arch/powerpc/platforms/83xx/mpc832x_mds.c |   1 -
> >> >  arch/powerpc/platforms/83xx/mpc832x_rdb.c |   1 -
> >> >  arch/powerpc/platforms/83xx/mpc836x_mds.c |   1 -
> >> >  arch/powerpc/platforms/83xx/mpc836x_rdk.c |   1 -
> >> >  arch/powerpc/platforms/85xx/corenet_generic.c |   1 -
> >> >  arch/powerpc/platforms/85xx/mpc85xx_mds.c |   1 -
> >> >  arch/powerpc/platforms/85xx/mpc85xx_rdb.c |   1 -
> >> >  arch/powerpc/platforms/85xx/twr_p102x.c   |   1 -
> >> >  drivers/irqchip/irq-qeic.c| 188 
> >> > +++---
> >> >  include/soc/fsl/qe/qe_ic.h| 132 --
> >> >  12 files changed, 80 insertions(+), 250 deletions(-)  delete mode
> >> > 100644 include/soc/fsl/qe/qe_ic.h
> >> >
> >> > diff --git a/arch/powerpc/platforms/83xx/km83xx.c
> >> > b/arch/powerpc/platforms/83xx/km83xx.c
> >> > index d8642a4..b1cef0a 100644
> >> > --- a/arch/powerpc/platforms/83xx/km83xx.c
> >> > +++ b/arch/powerpc/platforms/83xx/km83xx.c
> >> > @@ -38,7 +38,6 @@
> >> >  #include 
> >> >  #include 
> >> >  #include 
> >> > -#include 
> >>
> >> You deleted that file in patch 2. So didn't you just break the build
> >> for the last two commits?
> >
> > Sorry, I am not sure what you said. Could you explain?
> 
> Don't worry about it. I was confused by the fact that we have both:
> 
>   drivers/soc/fsl/qe/qe_ic.h
> 
> and:
> 
>   include/soc/fsl/qe/qe_ic.h
> 
> cheers

I think this is a issue left over by history.
In patch with commit id 7aa1aa6ecec2af19d9aa85430ce3e56119e21626, I just move 
them out from arch/powerpc.  
Maybe need to ask the original author why there are 2 qe_ic.h.

Best Regards
Qiang Zhao

RE: [PATCH v10 4/4] irqchip/qeic: remove PPCisms for QEIC

[Qiang Zhao]

On Mon 8/7/2017 3:02 PM, Michael Ellerman <m...@ellerman.id.au> wrote:

> -Original Message-
> From: Michael Ellerman [mailto:m...@ellerman.id.au]
> Sent: Monday, August 07, 2017 3:02 PM
> To: Qiang Zhao <qiang.z...@nxp.com>; t...@linutronix.de
> Cc: o...@buserror.net; Qiang Zhao <qiang.z...@nxp.com>; linuxppc-
> d...@lists.ozlabs.org; Xiaobo Xie <xiaobo@nxp.com>; linux-
> ker...@vger.kernel.org
> Subject: Re: [PATCH v10 4/4] irqchip/qeic: remove PPCisms for QEIC
> 
> Zhao Qiang <qiang.z...@nxp.com> writes:
> 
> > QEIC was supported on PowerPC, and dependent on PPC, Now it is
> > supported on other platforms, so remove PPCisms.
> >
> > Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
> > ---
> >  arch/powerpc/platforms/83xx/km83xx.c  |   1 -
> >  arch/powerpc/platforms/83xx/misc.c|   1 -
> >  arch/powerpc/platforms/83xx/mpc832x_mds.c |   1 -
> >  arch/powerpc/platforms/83xx/mpc832x_rdb.c |   1 -
> >  arch/powerpc/platforms/83xx/mpc836x_mds.c |   1 -
> >  arch/powerpc/platforms/83xx/mpc836x_rdk.c |   1 -
> >  arch/powerpc/platforms/85xx/corenet_generic.c |   1 -
> >  arch/powerpc/platforms/85xx/mpc85xx_mds.c |   1 -
> >  arch/powerpc/platforms/85xx/mpc85xx_rdb.c |   1 -
> >  arch/powerpc/platforms/85xx/twr_p102x.c   |   1 -
> >  drivers/irqchip/irq-qeic.c| 188 
> > +++---
> >  include/soc/fsl/qe/qe_ic.h| 132 --
> >  12 files changed, 80 insertions(+), 250 deletions(-)  delete mode
> > 100644 include/soc/fsl/qe/qe_ic.h
> >
> > diff --git a/arch/powerpc/platforms/83xx/km83xx.c
> > b/arch/powerpc/platforms/83xx/km83xx.c
> > index d8642a4..b1cef0a 100644
> > --- a/arch/powerpc/platforms/83xx/km83xx.c
> > +++ b/arch/powerpc/platforms/83xx/km83xx.c
> > @@ -38,7 +38,6 @@
> >  #include 
> >  #include 
> >  #include 
> > -#include 
> 
> You deleted that file in patch 2. So didn't you just break the build for the 
> last two
> commits?

Sorry, I am not sure what you said. Could you explain?
Thank you!

BR
Qiang Zhao

QRE: [PATCH v2] qe: fix compile issue for arm64

[Qiang Zhao]

Michael Ellerman <m...@ellerman.id.au> wrote:

> -Original Message-
> From: Michael Ellerman [mailto:m...@ellerman.id.au]
> Sent: Monday, July 31, 2017 6:37 PM
> To: Qiang Zhao <qiang.z...@nxp.com>; o...@buserror.net
> Cc: valentin.longch...@keymile.com; linuxppc-dev@lists.ozlabs.org; linux-
> ker...@vger.kernel.org
> Subject: RE: [PATCH v2] qe: fix compile issue for arm64
> 
> Qiang Zhao <qiang.z...@nxp.com> writes:
> 
> > Fri 7/28/2017 2:14 PM, Michael Ellerman <m...@ellerman.id.au> wrote:
> >
> >> -Original Message-
> >> From: Michael Ellerman [mailto:m...@ellerman.id.au]
> >> Sent: Friday, July 28, 2017 2:14 PM
> >> To: Qiang Zhao <qiang.z...@nxp.com>; o...@buserror.net
> >> Cc: valentin.longch...@keymile.com; linuxppc-dev@lists.ozlabs.org;
> >> linux- ker...@vger.kernel.org; Qiang Zhao <qiang.z...@nxp.com>
> >> Subject: Re: [PATCH v2] qe: fix compile issue for arm64
> >>
> >> Zhao Qiang <qiang.z...@nxp.com> writes:
> >>
> >> > Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
> >> > ---
> >> > Changes for v2:
> >> >  - include all Errata QE_General4 in #ifdef
> >> >
> >> >  drivers/soc/fsl/qe/qe.c | 2 ++
> >> >  1 file changed, 2 insertions(+)
> >>
> >> AFAICS this driver can only be built on PPC, what am I missing?
> >>
> >> config QUICC_ENGINE
> >> bool "Freescale QUICC Engine (QE) Support"
> >> depends on FSL_SOC && PPC32
> >>
> >> cheers
> >
> > I sent another patchset to support it on arm64.
> 
> Where? I don't see it.
> 
> Shouldn't this patch be part of that series? Otherwise when that series is 
> merged
> the build will break on arm64.
> 
You are correct, thanks for your recommend.
I will add this patch to the patchset.

Thank you!

BR
Qiang Zhao

RE: [PATCH v2] qe: fix compile issue for arm64

[Qiang Zhao]

Fri 7/28/2017 2:14 PM, Michael Ellerman <m...@ellerman.id.au> wrote:

> -Original Message-
> From: Michael Ellerman [mailto:m...@ellerman.id.au]
> Sent: Friday, July 28, 2017 2:14 PM
> To: Qiang Zhao <qiang.z...@nxp.com>; o...@buserror.net
> Cc: valentin.longch...@keymile.com; linuxppc-dev@lists.ozlabs.org; linux-
> ker...@vger.kernel.org; Qiang Zhao <qiang.z...@nxp.com>
> Subject: Re: [PATCH v2] qe: fix compile issue for arm64
> 
> Zhao Qiang <qiang.z...@nxp.com> writes:
> 
> > Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
> > ---
> > Changes for v2:
> > - include all Errata QE_General4 in #ifdef
> >
> >  drivers/soc/fsl/qe/qe.c | 2 ++
> >  1 file changed, 2 insertions(+)
> 
> AFAICS this driver can only be built on PPC, what am I missing?
> 
> config QUICC_ENGINE
> bool "Freescale QUICC Engine (QE) Support"
> depends on FSL_SOC && PPC32
> 
> cheers

I sent another patchset to support it on arm64.
Thank you! 

Best Regards
Qiang Zhao

RE: [PATCH 1/2] fsl/qe: NULL dereference on error in ucc_of_parse_tdm()

[Qiang Zhao]

On Mon 7/24/2017 3:04 PM, Dan Carpenter <dan.carpen...@oracle.com>

> -Original Message-
> From: Dan Carpenter [mailto:dan.carpen...@oracle.com]
> Sent: Monday, July 24, 2017 3:04 PM
> To: Qiang Zhao <qiang.z...@nxp.com>
> Cc: Leo Li <leoyang...@nxp.com>; linuxppc-dev@lists.ozlabs.org; kernel-
> janit...@vger.kernel.org
> Subject: Re: [PATCH 1/2] fsl/qe: NULL dereference on error in
> ucc_of_parse_tdm()
> 
> On Mon, Jul 24, 2017 at 02:24:14AM +, Qiang Zhao wrote:
> > On Sat 7/22/2017 3:34 PM, Dan Carpenter <dan.carpen...@oracle.com>
> wrote:
> >
> > > -Original Message-
> > > From: Dan Carpenter [mailto:dan.carpen...@oracle.com]
> > > Sent: Saturday, July 22, 2017 3:34 PM
> > > To: Qiang Zhao <qiang.z...@nxp.com>
> > > Cc: Leo Li <leoyang...@nxp.com>; linuxppc-dev@lists.ozlabs.org;
> > > kernel- janit...@vger.kernel.org
> > > Subject: [PATCH 1/2] fsl/qe: NULL dereference on error in
> > > ucc_of_parse_tdm()
> > >
> > > If "pdev = of_find_device_by_node(np2);" fails then it would lead to
> > > a NULL dereference.  This function is called from probe() and we're
> > > using managed resources so we can just return without doing a manual
> cleanup.
> >
> > You mean it will be cleaned up automatically?
> 
> Yes.  At module unload.

Do you mean when insmod it as a module, and when this module is removed, it 
will be cleaned up automatically?
Do I understand correctly?
Well, how about build-in?

Best Regards
Qiang Zhao

RE: [PATCH 1/2] fsl/qe: NULL dereference on error in ucc_of_parse_tdm()

[Qiang Zhao]

On Sat 7/22/2017 3:34 PM, Dan Carpenter <dan.carpen...@oracle.com> wrote:

> -Original Message-
> From: Dan Carpenter [mailto:dan.carpen...@oracle.com]
> Sent: Saturday, July 22, 2017 3:34 PM
> To: Qiang Zhao <qiang.z...@nxp.com>
> Cc: Leo Li <leoyang...@nxp.com>; linuxppc-dev@lists.ozlabs.org; kernel-
> janit...@vger.kernel.org
> Subject: [PATCH 1/2] fsl/qe: NULL dereference on error in ucc_of_parse_tdm()
> 
> If "pdev = of_find_device_by_node(np2);" fails then it would lead to a NULL
> dereference.  This function is called from probe() and we're using managed
> resources so we can just return without doing a manual cleanup.

You mean it will be cleaned up automatically?

> 
> Fixes: 35ef1c20fdb2 ("fsl/qe: Add QE TDM lib")
> Signed-off-by: Dan Carpenter <dan.carpen...@oracle.com>

Best Regards
Qiang Zhao

RE: [PATCH] qe: fix compile issue for arm64

[Qiang Zhao]

On Fri, 2017-07-21 at 02:34PM, Michael Ellerman <m...@ellerman.id.au> wrote:

> -Original Message-
> From: Michael Ellerman [mailto:m...@ellerman.id.au]
> Sent: Friday, July 21, 2017 2:34 PM
> To: Qiang Zhao <qiang.z...@nxp.com>; o...@buserror.net
> Cc: valentin.longch...@keymile.com; linuxppc-dev@lists.ozlabs.org; linux-
> ker...@vger.kernel.org; Qiang Zhao <qiang.z...@nxp.com>
> Subject: Re: [PATCH] qe: fix compile issue for arm64
> 
> Zhao Qiang <qiang.z...@nxp.com> writes:
> 
> > Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
> > ---
> >  drivers/soc/fsl/qe/qe.c | 2 ++
> >  1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c index
> > 2ef6fc6..d48fa4a 100644
> > --- a/drivers/soc/fsl/qe/qe.c
> > +++ b/drivers/soc/fsl/qe/qe.c
> > @@ -229,7 +229,9 @@ int qe_setbrg(enum qe_clock brg, unsigned int rate,
> unsigned int multiplier)
> > /* Errata QE_General4, which affects some MPC832x and MPC836x
> SOCs, says
> >that the BRG divisor must be even if you're not using divide-by-16
> >mode. */
> > +#ifdef CONFIG_PPC
> > if (pvr_version_is(PVR_VER_836x) || pvr_version_is(PVR_VER_832x)
> > +#endif
> > if (!div16 && (divisor & 1) && (divisor > 3))
> > divisor++;
> 
> Are you sure that's what you want to do on arm64 ?

Is there any problem?

Best Regards
Qiang Zhao

RE: [PATCH 2/3] soc/fsl/qe: only apply QE_General4 workaround on affected SoCs

[Qiang Zhao]

Hi Valentin,

This patch you added make the compiling issue on armv8.
Could you send another patch to resolve it?

CC  drivers/soc/samsung/pm_domains.o
  CC  drivers/soc/sunxi/sunxi_sram.o
  CC  drivers/soc/renesas/rcar-rst.o
  CC  drivers/soc/fsl/qe/qe_io.o
drivers/soc/fsl/qe/qe.c: In function 'qe_setbrg':
drivers/soc/fsl/qe/qe.c:248:2: error: implicit declaration of function 
'pvr_version_is' [-Werror=implicit-function-declaration]
  if (pvr_version_is(PVR_VER_836x) || pvr_version_is(PVR_VER_832x))
  ^
  CC  drivers/soc/fsl/qe/ucc.o
  CC  drivers/soc/renesas/rcar-sysc.o
  CHK kernel/config_data.h
cc1: some warnings being treated as errors
  CC  drivers/soc/tegra/fuse/fuse-tegra.o
  LD  drivers/soc/rockchip/built-in.o
  CC  drivers/soc/tegra/fuse/fuse-tegra30.o
scripts/Makefile.build:302: recipe for target 'drivers/soc/fsl/qe/qe.o' failed
make[4]: *** [drivers/soc/fsl/qe/qe.o] Error 1

-Original Message-
From: Valentin Longchamp [mailto:valentin.longch...@keymile.com] 
Sent: Friday, February 17, 2017 6:30 PM
To: linuxppc-dev@lists.ozlabs.org; Qiang Zhao <qiang.z...@nxp.com>
Cc: o...@buserror.net; Valentin Longchamp <valentin.longch...@keymile.com>
Subject: [PATCH 2/3] soc/fsl/qe: only apply QE_General4 workaround on affected 
SoCs

The QE_General4 workaround is only valid for the MPC832x and MPC836x SoCs. The 
other SoCs that embed a QUICC engine are not affected by this hardware bug and 
thus can use the computed divisors (this was successfully tested on the T1040).

Similalry to what was done in commit 8ce795cb0c6b ("i2c: mpc: assign the 
correct prescaler from SVR") in order to avoid changes in the device tree nodes 
of the QE (with maybe a variant of the compatible property), the PVR reg is 
read out to find out if the workaround must be applied or not.

Signed-off-by: Valentin Longchamp <valentin.longch...@keymile.com>
---
 drivers/soc/fsl/qe/qe.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c index 
03874df..b66157fc 100644
--- a/drivers/soc/fsl/qe/qe.c
+++ b/drivers/soc/fsl/qe/qe.c
@@ -202,6 +202,9 @@ unsigned int qe_get_brg_clk(void)  }  
EXPORT_SYMBOL(qe_get_brg_clk);
 
+#define PVR_VER_836x   0x8083
+#define PVR_VER_832x   0x8084
+
 /* Program the BRG to the given sampling rate and multiplier
  *
  * @brg: the BRG, QE_BRG1 - QE_BRG16
@@ -228,8 +231,9 @@ int qe_setbrg(enum qe_clock brg, unsigned int rate, 
unsigned int multiplier)
/* Errata QE_General4, which affects some MPC832x and MPC836x SOCs, says
   that the BRG divisor must be even if you're not using divide-by-16
   mode. */
-   if (!div16 && (divisor & 1) && (divisor > 3))
-   divisor++;
+   if (pvr_version_is(PVR_VER_836x) || pvr_version_is(PVR_VER_832x))
+   if (!div16 && (divisor & 1) && (divisor > 3))
+   divisor++;
 
tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) |
QE_BRGC_ENABLE | div16;
--
1.8.3.1

RE: [PATCH v6 2/4] irqchip/qeic: merge qeic init code from platforms to a common function

[Qiang Zhao]

On 16/12/16 04:33, Marc Zyngier <marc.zyng...@arm.com> wrote:

> -Original Message-
> From: Marc Zyngier [mailto:marc.zyng...@arm.com]
> Sent: Friday, December 16, 2016 4:33 PM
> To: Qiang Zhao <qiang.z...@nxp.com>; o...@buserror.net; t...@linutronix.de
> Cc: ja...@lakedaemon.net; Xiaobo Xie <xiaobo@nxp.com>; linux-
> ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org
> Subject: Re: [PATCH v6 2/4] irqchip/qeic: merge qeic init code from platforms 
> to
> a common function
> 
> On 28/09/16 04:25, Zhao Qiang wrote:
> > The codes of qe_ic init from a variety of platforms are redundant,
> > merge them to a common function and put it to irqchip/irq-qeic.c
> >
> > For non-p1021_mds mpc85xx_mds boards, use "qe_ic_init(np, 0,
> > qe_ic_cascade_low_mpic, qe_ic_cascade_high_mpic);" instead of
> > "qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);".
> >
> > qe_ic_cascade_muxed_mpic was used for boards has the same interrupt
> > number for low interrupt and high interrupt, qe_ic_init has checked if
> > "low interrupt == high interrupt"
> >
> > Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
> > ---
> > Changes for v2:
> > - modify subject and commit msg
> > - add check for qeic by type
> > Changes for v3:
> > - na
> > Changes for v4:
> > - na
> > Changes for v5:
> > - na
> > Changes for v6:
> > - rebase
> >
> >  arch/powerpc/platforms/83xx/misc.c| 15 ---
> >  arch/powerpc/platforms/85xx/corenet_generic.c |  9 -
> >  arch/powerpc/platforms/85xx/mpc85xx_mds.c | 14 --
> >  arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 16 
> >  arch/powerpc/platforms/85xx/twr_p102x.c   | 14 --
> >  drivers/irqchip/irq-qeic.c| 16 
> >  6 files changed, 16 insertions(+), 68 deletions(-)
> >
> 
> [...]
> 
> > --- a/drivers/irqchip/irq-qeic.c
> > +++ b/drivers/irqchip/irq-qeic.c
> > @@ -598,4 +598,20 @@ static int __init init_qe_ic_sysfs(void)
> > return 0;
> >  }
> >
> > +static int __init qeic_of_init(void)
> > +{
> > +   struct device_node *np;
> > +
> > +   np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
> > +   if (!np) {
> > +   np = of_find_node_by_type(NULL, "qeic");
> > +   if (!np)
> > +   return;
> > +   }
> > +   qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
> > +  qe_ic_cascade_high_mpic);
> > +   of_node_put(np);
> > +}
> 
> Have you actually compiled that code?

Yes.

Best Regards
Zhao Qiang

RE: [PATCH v6 1/4] irqchip/qeic: move qeic driver from drivers/soc/fsl/qe

[Qiang Zhao]

Hello,

Any comments on this patchset?

Best Regards
Zhao Qiang

> -Original Message-
> From: Zhao Qiang [mailto:qiang.z...@nxp.com]
> Sent: Wednesday, September 28, 2016 11:25 AM
> To: o...@buserror.net; t...@linutronix.de
> Cc: ja...@lakedaemon.net; marc.zyng...@arm.com; X.B. Xie
> <xiaobo@nxp.com>; linux-ker...@vger.kernel.org; linuxppc-
> d...@lists.ozlabs.org; Qiang Zhao <qiang.z...@nxp.com>
> Subject: [PATCH v6 1/4] irqchip/qeic: move qeic driver from drivers/soc/fsl/qe
> 
> move the driver from drivers/soc/fsl/qe to drivers/irqchip, merge qe_ic.h and
> qe_ic.c into irq-qeic.c.
> 
> Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
> ---
> Changes for v2:
>   - modify the subject and commit msg
> Changes for v3:
>   - merge .h file to .c, rename it with irq-qeic.c Changes for v4:
>   - modify comments
> Changes for v5:
>   - disable rename detection
> Changes for v6:
>   - rebase
> 
>  drivers/irqchip/Makefile   |   1 +
>  drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} |  95 ++-
>  drivers/soc/fsl/qe/Makefile|   2 +-
>  drivers/soc/fsl/qe/qe_ic.h | 103 
> -
>  4 files changed, 94 insertions(+), 107 deletions(-)  rename
> drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} (85%)  delete mode 100644
> drivers/soc/fsl/qe/qe_ic.h
> 
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index
> 4c203b6..face608 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -71,3 +71,4 @@ obj-$(CONFIG_MVEBU_ODMI)+= irq-mvebu-
> odmi.o
>  obj-$(CONFIG_LS_SCFG_MSI)+= irq-ls-scfg-msi.o
>  obj-$(CONFIG_EZNPS_GIC)  += irq-eznps.o
>  obj-$(CONFIG_ARCH_ASPEED)+= irq-aspeed-vic.o
> +obj-$(CONFIG_QUICC_ENGINE)   += irq-qeic.o
> diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/irqchip/irq-qeic.c 
> similarity
> index 85% rename from drivers/soc/fsl/qe/qe_ic.c rename to
> drivers/irqchip/irq-qeic.c index ec2ca86..48ceded 100644
> --- a/drivers/soc/fsl/qe/qe_ic.c
> +++ b/drivers/irqchip/irq-qeic.c
> @@ -1,7 +1,7 @@
>  /*
> - * arch/powerpc/sysdev/qe_lib/qe_ic.c
> + * drivers/irqchip/irq-qeic.c
>   *
> - * Copyright (C) 2006 Freescale Semiconductor, Inc.  All rights reserved.
> + * Copyright (C) 2016 Freescale Semiconductor, Inc.  All rights reserved.
>   *
>   * Author: Li Yang <le...@freescale.com>
>   * Based on code from Shlomi Gridish <grid...@freescale.com> @@ -30,7
> +30,96 @@  #include   #include 
> 
> -#include "qe_ic.h"
> +#define NR_QE_IC_INTS64
> +
> +/* QE IC registers offset */
> +#define QEIC_CICR0x00
> +#define QEIC_CIVEC   0x04
> +#define QEIC_CRIPNR  0x08
> +#define QEIC_CIPNR   0x0c
> +#define QEIC_CIPXCC  0x10
> +#define QEIC_CIPYCC  0x14
> +#define QEIC_CIPWCC  0x18
> +#define QEIC_CIPZCC  0x1c
> +#define QEIC_CIMR0x20
> +#define QEIC_CRIMR   0x24
> +#define QEIC_CICNR   0x28
> +#define QEIC_CIPRTA  0x30
> +#define QEIC_CIPRTB  0x34
> +#define QEIC_CRICR   0x3c
> +#define QEIC_CHIVEC  0x60
> +
> +/* Interrupt priority registers */
> +#define CIPCC_SHIFT_PRI0 29
> +#define CIPCC_SHIFT_PRI1 26
> +#define CIPCC_SHIFT_PRI2 23
> +#define CIPCC_SHIFT_PRI3 20
> +#define CIPCC_SHIFT_PRI4 13
> +#define CIPCC_SHIFT_PRI5 10
> +#define CIPCC_SHIFT_PRI6 7
> +#define CIPCC_SHIFT_PRI7 4
> +
> +/* CICR priority modes */
> +#define CICR_GWCC0x0004
> +#define CICR_GXCC0x0002
> +#define CICR_GYCC0x0001
> +#define CICR_GZCC0x0008
> +#define CICR_GRTA0x0020
> +#define CICR_GRTB0x0040
> +#define CICR_HPIT_SHIFT  8
> +#define CICR_HPIT_MASK   0x0300
> +#define CICR_HP_SHIFT24
> +#define CICR_HP_MASK 0x3f00
> +
> +/* CICNR */
> +#define CICNR_WCC1T_SHIFT20
> +#define CICNR_ZCC1T_SHIFT28
> +#define CICNR_YCC1T_SHIFT12
> +#define CICNR_XCC1T_SHIFT4
> +
> +/* CRICR */
> +#define CRICR_RTA1T_SHIFT20
> +#define CRICR_RTB1T_SHIFT28
> +
> +/* Signal indicator */
> +#define SIGNAL_MASK  3
> +#define SIGNAL_HIGH  2
> +#define SIGNAL_LOW   0
> +
> +struct qe_ic {
> + /* Control registers offset */
> + volatile u32 __iomem *regs;
> +
> + /* The remapper for this QEIC */
> + struct irq_domain *irqhos

RE: [PATCH v9] QE: remove PPCisms for QE

[Qiang Zhao]

This patch depends on the patchset of QEIC as following links:
http://patchwork.ozlabs.org/patch/675925/
http://patchwork.ozlabs.org/patch/675926/
http://patchwork.ozlabs.org/patch/675927/
http://patchwork.ozlabs.org/patch/675928/

> -Original Message-
> From: kbuild test robot [mailto:l...@intel.com]
> Sent: Monday, December 05, 2016 3:00 PM
> To: Qiang Zhao <qiang.z...@nxp.com>
> Cc: kbuild-...@01.org; o...@buserror.net; ba...@kernel.org;
> gre...@linuxfoundation.org; Xiaobo Xie <xiaobo@nxp.com>; linux-
> ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; Qiang Zhao
> <qiang.z...@nxp.com>
> Subject: Re: [PATCH v9] QE: remove PPCisms for QE
> 
> Hi Zhao,
> 
> [auto build test ERROR on linus/master]
> [also build test ERROR on v4.9-rc8]
> [cannot apply to next-20161202]
> [if your patch is applied to the wrong git tree, please drop us a note to help
> improve the system]
> 
> url:https://github.com/0day-ci/linux/commits/Zhao-Qiang/QE-remove-
> PPCisms-for-QE/20161205-131352
> config: i386-allmodconfig (attached as .config)
> compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
> reproduce:
> # save the attached .config to linux build tree
> make ARCH=i386
> 
> All errors (new ones prefixed by >>):
> 
>In file included from drivers/soc/fsl/qe/qe_ic.c:31:0:
>include/soc/fsl/qe/qe_ic.h: In function 'qe_ic_cascade_low_ipic':
> >> include/soc/fsl/qe/qe_ic.h:86:21: error: 'NO_IRQ' undeclared (first use in
> this function)
>  if (cascade_irq != NO_IRQ)
> ^~
>include/soc/fsl/qe/qe_ic.h:86:21: note: each undeclared identifier is 
> reported
> only once for each function it appears in
>include/soc/fsl/qe/qe_ic.h: In function 'qe_ic_cascade_high_ipic':
>include/soc/fsl/qe/qe_ic.h:95:21: error: 'NO_IRQ' undeclared (first use in 
> this
> function)
>  if (cascade_irq != NO_IRQ)
> ^~
>include/soc/fsl/qe/qe_ic.h: In function 'qe_ic_cascade_low_mpic':
>include/soc/fsl/qe/qe_ic.h:105:21: error: 'NO_IRQ' undeclared (first use in
> this function)
>  if (cascade_irq != NO_IRQ)
> ^~
>include/soc/fsl/qe/qe_ic.h: In function 'qe_ic_cascade_high_mpic':
>include/soc/fsl/qe/qe_ic.h:117:21: error: 'NO_IRQ' undeclared (first use in
> this function)
>  if (cascade_irq != NO_IRQ)
> ^~
>include/soc/fsl/qe/qe_ic.h: In function 'qe_ic_cascade_muxed_mpic':
>include/soc/fsl/qe/qe_ic.h:130:21: error: 'NO_IRQ' undeclared (first use in
> this function)
>  if (cascade_irq == NO_IRQ)
> ^~
>drivers/soc/fsl/qe/qe_ic.c: In function 'qe_ic_read':
> >> drivers/soc/fsl/qe/qe_ic.c:180:9: error: implicit declaration of function
> 'in_be32' [-Werror=implicit-function-declaration]
>  return in_be32(base + (reg >> 2));
> ^~~
>drivers/soc/fsl/qe/qe_ic.c: In function 'qe_ic_write':
> >> drivers/soc/fsl/qe/qe_ic.c:186:2: error: implicit declaration of function
> 'out_be32' [-Werror=implicit-function-declaration]
>  out_be32(base + (reg >> 2), value);
>  ^~~~
>drivers/soc/fsl/qe/qe_ic.c: In function 'qe_ic_get_low_irq':
> >> drivers/soc/fsl/qe/qe_ic.c:299:10: error: 'NO_IRQ' undeclared (first use in
> this function)
>   return NO_IRQ;
>  ^~
>drivers/soc/fsl/qe/qe_ic.c: In function 'qe_ic_get_high_irq':
>drivers/soc/fsl/qe/qe_ic.c:315:10: error: 'NO_IRQ' undeclared (first use 
> in this
> function)
>   return NO_IRQ;
>  ^~
>drivers/soc/fsl/qe/qe_ic.c: In function 'qe_ic_init':
>drivers/soc/fsl/qe/qe_ic.c:350:25: error: 'NO_IRQ' undeclared (first use 
> in this
> function)
>  if (qe_ic->virq_low == NO_IRQ) {
> ^~
>drivers/soc/fsl/qe/qe_ic.c: In function 'qe_ic_set_highest_priority':
> >> drivers/soc/fsl/qe/qe_ic.c:392:21: error: implicit declaration of function
> 'virq_to_hw' [-Werror=implicit-function-declaration]
>  unsigned int src = virq_to_hw(virq);
> ^~
>cc1: some warnings being treated as errors
> 
> vim +/in_be32 +180 drivers/soc/fsl/qe/qe_ic.c
> 
> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03  
> 174
>   .pri_reg = QEIC_CIPYCC,
> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03  
> 175
>   },
> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03  
> 176  };
> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03  
> 177
&

RE: [v6,2/2] QE: remove PPCisms for QE

[Qiang Zhao]

On Tue, Sep 27, 2016 at 7:12AM -0500, Scott Wood wrote:

> -Original Message-
> From: Scott Wood [mailto:o...@buserror.net]
> Sent: Tuesday, September 27, 2016 7:12 AM
> To: Qiang Zhao <qiang.z...@nxp.com>
> Cc: linuxppc-dev@lists.ozlabs.org; pku@gmail.com; X.B. Xie
> <xiaobo@nxp.com>; linux-ker...@vger.kernel.org
> Subject: Re: [v6,2/2] QE: remove PPCisms for QE
> 
> On Mon, 2016-09-26 at 01:46 +, Qiang Zhao wrote:
> > On Sun, Sep 25, 2016 at 12:19PM -0500, Scott Wood wrote:
> >
> > >
> > > -Original Message-
> > > From: Scott Wood [mailto:o...@buserror.net]
> > > Sent: Sunday, September 25, 2016 12:19 PM
> > > To: Qiang Zhao <qiang.z...@nxp.com>
> > > Cc: linuxppc-dev@lists.ozlabs.org; pku@gmail.com; X.B. Xie
> > > <xiaobo@nxp.com>; linux-ker...@vger.kernel.org
> > > Subject: Re: [v6,2/2] QE: remove PPCisms for QE
> > >
> > > On Sat, Sep 24, 2016 at 11:14:11PM -0500, Scott Wood wrote:
> > > >
> > > > On Fri, Sep 23, 2016 at 10:20:32AM +0800, Zhao Qiang wrote:
> > > > >
> > > > > QE was supported on PowerPC, and dependent on PPC, Now it is
> > > > > supported on other platforms. so remove PPCisms.
> > > > >
> > > > > Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
> > > > > ---
> > > > > Changes for v2:
> > > > >   - na
> > > > > Changes for v3:
> > > > >   - add NO_IRQ
> > > > > Changes for v4:
> > > > >   - modify spin_event_timeout to opencoded timeout loop
> > > > >   - remove NO_IRQ
> > > > >   - modify virq_to_hw to opencoed code Changes for v5:
> > > > >   - modify commit msg
> > > > >   - modify depends of QUICC_ENGINE
> > > > >   - add kerneldoc header for qe_issue_cmd Changes for v6:
> > > > >   - add dependency on FSL_SOC and PPC32 for drivers
> > > > >     depending on QUICC_ENGING but not available on ARM
> > > > >
> > > > >  drivers/irqchip/qe_ic.c| 28 +++-
> > > > >  drivers/net/ethernet/freescale/Kconfig | 10 ++---
> > > > >  drivers/soc/fsl/qe/Kconfig |  2 +-
> > > > >  drivers/soc/fsl/qe/qe.c| 80
> > > > > -
> > > > > -
> > > > >  drivers/soc/fsl/qe/qe_io.c | 42 --
> > > > >  drivers/soc/fsl/qe/qe_tdm.c|  8 ++--
> > > > >  drivers/soc/fsl/qe/ucc.c   | 10 ++---
> > > > >  drivers/soc/fsl/qe/ucc_fast.c  | 68
> > > > > ++---
> > > > > 
> > > > >  drivers/tty/serial/Kconfig |  2 +-
> > > > >  drivers/usb/gadget/udc/Kconfig |  2 +-
> > > > >  drivers/usb/host/Kconfig   |  2 +-
> > > > >  include/soc/fsl/qe/qe.h|  1 -
> > > > >  include/soc/fsl/qe/qe_ic.h | 12 ++---
> > > > >  13 files changed, 141 insertions(+), 126 deletions(-)
> > > > I assume this means you'll be updating
> > > > http://patchwork.ozlabs.org/patch/654473/
> > > > to be based on top of this...
> > > Apparently that assumption was wrong, since I now see that you're
> > > patching drivers/irqchip/qe_ic.c rather than drivers/soc/fsl/qe/qe_ic.c.
> > > Please keep the drivers/irqchip stuff separate and send to the
> > > appropriate maintainers.
> > >
> > You means separate drivers/irqchip/qe_ic.c part from this patch and
> > send it with the other qe_ic patches?
> > Is it acceptable if I modify qe_ic.c with drivers/soc/fsl/qe/qe_ic.c,
> > then send qe_ic patches to move qe_ic to drivers/irqchip?
> 
> I'd recommend against it.  It would complicate getting the drivers/irqchip
> patchset merged.  In any case, it's too late for 4.9.

Ok, thank you for your recommend.

BR
-Zhao Qiang

RE: [v6,2/2] QE: remove PPCisms for QE

[Qiang Zhao]

On Sun, Sep 25, 2016 at 12:19PM -0500, Scott Wood wrote:

> -Original Message-
> From: Scott Wood [mailto:o...@buserror.net]
> Sent: Sunday, September 25, 2016 12:19 PM
> To: Qiang Zhao <qiang.z...@nxp.com>
> Cc: linuxppc-dev@lists.ozlabs.org; pku@gmail.com; X.B. Xie
> <xiaobo@nxp.com>; linux-ker...@vger.kernel.org
> Subject: Re: [v6,2/2] QE: remove PPCisms for QE
> 
> On Sat, Sep 24, 2016 at 11:14:11PM -0500, Scott Wood wrote:
> > On Fri, Sep 23, 2016 at 10:20:32AM +0800, Zhao Qiang wrote:
> > > QE was supported on PowerPC, and dependent on PPC, Now it is
> > > supported on other platforms. so remove PPCisms.
> > >
> > > Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
> > > ---
> > > Changes for v2:
> > >   - na
> > > Changes for v3:
> > >   - add NO_IRQ
> > > Changes for v4:
> > >   - modify spin_event_timeout to opencoded timeout loop
> > >   - remove NO_IRQ
> > >   - modify virq_to_hw to opencoed code Changes for v5:
> > >   - modify commit msg
> > >   - modify depends of QUICC_ENGINE
> > >   - add kerneldoc header for qe_issue_cmd Changes for v6:
> > >   - add dependency on FSL_SOC and PPC32 for drivers
> > > depending on QUICC_ENGING but not available on ARM
> > >
> > >  drivers/irqchip/qe_ic.c| 28 +++-
> > >  drivers/net/ethernet/freescale/Kconfig | 10 ++---
> > >  drivers/soc/fsl/qe/Kconfig |  2 +-
> > >  drivers/soc/fsl/qe/qe.c| 80 
> > > --
> > >  drivers/soc/fsl/qe/qe_io.c | 42 --
> > >  drivers/soc/fsl/qe/qe_tdm.c|  8 ++--
> > >  drivers/soc/fsl/qe/ucc.c   | 10 ++---
> > >  drivers/soc/fsl/qe/ucc_fast.c  | 68 ++---
> > >  drivers/tty/serial/Kconfig |  2 +-
> > >  drivers/usb/gadget/udc/Kconfig |  2 +-
> > >  drivers/usb/host/Kconfig   |  2 +-
> > >  include/soc/fsl/qe/qe.h|  1 -
> > >  include/soc/fsl/qe/qe_ic.h | 12 ++---
> > >  13 files changed, 141 insertions(+), 126 deletions(-)
> >
> > I assume this means you'll be updating
> > http://patchwork.ozlabs.org/patch/654473/
> > to be based on top of this...
> 
> Apparently that assumption was wrong, since I now see that you're patching
> drivers/irqchip/qe_ic.c rather than drivers/soc/fsl/qe/qe_ic.c.
> Please keep the drivers/irqchip stuff separate and send to the appropriate
> maintainers.
> 

You means separate drivers/irqchip/qe_ic.c part from this patch and send it 
with the other qe_ic patches?
Is it acceptable if I modify qe_ic.c with drivers/soc/fsl/qe/qe_ic.c, then send 
qe_ic patches to move qe_ic to drivers/irqchip?

BR
-Zhao Qiang

RE: [PATCH v5 2/2] QE: remove PPCisms for QE

[Qiang Zhao]

On Fri, Sep 23, 2016 at 3:39 AM, Leo Li wrote:

> -Original Message-
> From: Leo Li [mailto:pku@gmail.com]
> Sent: Friday, September 23, 2016 3:39 AM
> To: Qiang Zhao <qiang.z...@nxp.com>
> Cc: Scott Wood <o...@buserror.net>; linuxppc-dev  d...@lists.ozlabs.org>; lkml <linux-ker...@vger.kernel.org>; X.B. Xie
> <xiaobo@nxp.com>
> Subject: Re: [PATCH v5 2/2] QE: remove PPCisms for QE
> 
> On Wed, Sep 21, 2016 at 8:43 PM, Qiang Zhao <qiang.z...@nxp.com> wrote:
> > On Mon, Sep 22, 2016 at 2:19 AM, Leo Li wrote:
> >> -Original Message-
> >> From: Leo Li [mailto:pku@gmail.com]
> >> Sent: Thursday, September 22, 2016 2:19 AM
> >> To: Qiang Zhao <qiang.z...@nxp.com>
> >> Cc: Scott Wood <o...@buserror.net>; linuxppc-dev  >> d...@lists.ozlabs.org>; lkml <linux-ker...@vger.kernel.org>; X.B. Xie
> >> <xiaobo@nxp.com>
> >> Subject: Re: [PATCH v5 2/2] QE: remove PPCisms for QE
> >>
> >> On Tue, Sep 20, 2016 at 8:13 PM, Qiang Zhao <qiang.z...@nxp.com> wrote:
> >> > On Mon, Sep 20, 2016 at 4:13 AM, Leo Li wrote:
> >> >> -Original Message-
> >> >> From: Leo Li [mailto:pku@gmail.com]
> >> >> Sent: Tuesday, September 20, 2016 4:13 AM
> >> >> To: Qiang Zhao <qiang.z...@nxp.com>
> >> >> Cc: Scott Wood <o...@buserror.net>; linuxppc-dev  >> >> d...@lists.ozlabs.org>; lkml <linux-ker...@vger.kernel.org>; X.B.
> >> >> Xie <xiaobo@nxp.com>
> >> >> Subject: Re: [PATCH v5 2/2] QE: remove PPCisms for QE
> >> >>
> >> >> On Mon, Jul 25, 2016 at 12:43 AM, Zhao Qiang <qiang.z...@nxp.com>
> >> wrote:
> >> >> > QE was supported on PowerPC, and dependent on PPC, Now it is
> >> >> > supported on other platforms. so remove PPCisms.
> >> >> >
> >> >> > Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
> >> >> > ---
> >> >> > Changes for v2:
> >> >> > - na
> >> >> > Changes for v3:
> >> >> > - add NO_IRQ
> >> >> > Changes for v4:
> >> >> > - modify spin_event_timeout to opencoded timeout loop
> >> >> > - remove NO_IRQ
> >> >> > - modify virq_to_hw to opencoed code Changes for v5:
> >> >> > - modify commit msg
> >> >> > - modify depends of QUICC_ENGINE
> >> >> > - add kerneldoc header for qe_issue_cmd
> >> >> >
> >> >> >  drivers/irqchip/qe_ic.c   | 28 +--
> >> >> >  drivers/soc/fsl/qe/Kconfig|  2 +-
> >> >> >  drivers/soc/fsl/qe/qe.c   | 80 ++--
> 
> >> 
> >> >> ---
> >> >> >  drivers/soc/fsl/qe/qe_io.c| 42 ++-
> >> >> >  drivers/soc/fsl/qe/qe_tdm.c   |  8 ++---
> >> >> >  drivers/soc/fsl/qe/ucc.c  | 10 +++---
> >> >> >  drivers/soc/fsl/qe/ucc_fast.c | 68 ++
> --
> >> >> >  include/soc/fsl/qe/qe.h   |  1 -
> >> >> >  include/soc/fsl/qe/qe_ic.h| 12 +++
> >> >> >  9 files changed, 133 insertions(+), 118 deletions(-)
> >> >> >
> >> >>
> >> >> [snip]
> >> >>
> >> >> > diff --git a/drivers/soc/fsl/qe/Kconfig
> >> >> > b/drivers/soc/fsl/qe/Kconfig index 73a2e08..b26b643 100644
> >> >> > --- a/drivers/soc/fsl/qe/Kconfig
> >> >> > +++ b/drivers/soc/fsl/qe/Kconfig
> >> >> > @@ -4,7 +4,7 @@
> >> >> >
> >> >> >  config QUICC_ENGINE
> >> >> > bool "Freescale QUICC Engine (QE) Support"
> >> >> > -   depends on FSL_SOC && PPC32
> >> >> > +   depends on OF && HAS_IOMEM
> >> >> > select GENERIC_ALLOCATOR
> >> >> > select CRC32
> >> >> > help
> >> >>
> >> >> You make it possible to build QE drivers on ARM, but the UCC_GETH
> >> >> fails to build on arm64.  Please make sure all these drivers can
> >> >> build on other architectures.  Or you can simply make them only
> >> >> build for Power architecture as most of them are not available on ARM.
> >> >>
> >> >
> >> > Most of them are not available on ARM and ARM64.
> >> > Now, only qe-hdlc is available on ARM64.
> >>
> >> Then you should update the Kconfig for these drivers too, if they are
> >> only depending on CONFIG_QUICC_ENGINE.
> >
> > You mean adding "depends on FSL_SOC && PPC32 " to the drivers that are
> not available for ARM?
> 
> Yes.  Previously these drivers get the architecture limitation from
> CONFIG_QUICC_ENGINE, but now they need them by their own.
> 


Ok, I will modify it in the next vertion.

BR
-Zhao Qiang

RE: [PATCH v5 2/2] QE: remove PPCisms for QE

[Qiang Zhao]

On Mon, Sep 22, 2016 at 2:19 AM, Leo Li wrote:
> -Original Message-
> From: Leo Li [mailto:pku@gmail.com]
> Sent: Thursday, September 22, 2016 2:19 AM
> To: Qiang Zhao <qiang.z...@nxp.com>
> Cc: Scott Wood <o...@buserror.net>; linuxppc-dev  d...@lists.ozlabs.org>; lkml <linux-ker...@vger.kernel.org>; X.B. Xie
> <xiaobo@nxp.com>
> Subject: Re: [PATCH v5 2/2] QE: remove PPCisms for QE
> 
> On Tue, Sep 20, 2016 at 8:13 PM, Qiang Zhao <qiang.z...@nxp.com> wrote:
> > On Mon, Sep 20, 2016 at 4:13 AM, Leo Li wrote:
> >> -Original Message-
> >> From: Leo Li [mailto:pku@gmail.com]
> >> Sent: Tuesday, September 20, 2016 4:13 AM
> >> To: Qiang Zhao <qiang.z...@nxp.com>
> >> Cc: Scott Wood <o...@buserror.net>; linuxppc-dev  >> d...@lists.ozlabs.org>; lkml <linux-ker...@vger.kernel.org>; X.B. Xie
> >> <xiaobo@nxp.com>
> >> Subject: Re: [PATCH v5 2/2] QE: remove PPCisms for QE
> >>
> >> On Mon, Jul 25, 2016 at 12:43 AM, Zhao Qiang <qiang.z...@nxp.com>
> wrote:
> >> > QE was supported on PowerPC, and dependent on PPC, Now it is
> >> > supported on other platforms. so remove PPCisms.
> >> >
> >> > Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
> >> > ---
> >> > Changes for v2:
> >> > - na
> >> > Changes for v3:
> >> > - add NO_IRQ
> >> > Changes for v4:
> >> > - modify spin_event_timeout to opencoded timeout loop
> >> > - remove NO_IRQ
> >> > - modify virq_to_hw to opencoed code Changes for v5:
> >> > - modify commit msg
> >> > - modify depends of QUICC_ENGINE
> >> > - add kerneldoc header for qe_issue_cmd
> >> >
> >> >  drivers/irqchip/qe_ic.c   | 28 +--
> >> >  drivers/soc/fsl/qe/Kconfig|  2 +-
> >> >  drivers/soc/fsl/qe/qe.c   | 80 ++--
> 
> >> ---
> >> >  drivers/soc/fsl/qe/qe_io.c| 42 ++-
> >> >  drivers/soc/fsl/qe/qe_tdm.c   |  8 ++---
> >> >  drivers/soc/fsl/qe/ucc.c  | 10 +++---
> >> >  drivers/soc/fsl/qe/ucc_fast.c | 68 ++--
> >> >  include/soc/fsl/qe/qe.h   |  1 -
> >> >  include/soc/fsl/qe/qe_ic.h| 12 +++
> >> >  9 files changed, 133 insertions(+), 118 deletions(-)
> >> >
> >>
> >> [snip]
> >>
> >> > diff --git a/drivers/soc/fsl/qe/Kconfig
> >> > b/drivers/soc/fsl/qe/Kconfig index 73a2e08..b26b643 100644
> >> > --- a/drivers/soc/fsl/qe/Kconfig
> >> > +++ b/drivers/soc/fsl/qe/Kconfig
> >> > @@ -4,7 +4,7 @@
> >> >
> >> >  config QUICC_ENGINE
> >> > bool "Freescale QUICC Engine (QE) Support"
> >> > -   depends on FSL_SOC && PPC32
> >> > +   depends on OF && HAS_IOMEM
> >> > select GENERIC_ALLOCATOR
> >> > select CRC32
> >> > help
> >>
> >> You make it possible to build QE drivers on ARM, but the UCC_GETH
> >> fails to build on arm64.  Please make sure all these drivers can
> >> build on other architectures.  Or you can simply make them only build
> >> for Power architecture as most of them are not available on ARM.
> >>
> >
> > Most of them are not available on ARM and ARM64.
> > Now, only qe-hdlc is available on ARM64.
> 
> Then you should update the Kconfig for these drivers too, if they are only
> depending on CONFIG_QUICC_ENGINE.

You mean adding "depends on FSL_SOC && PPC32 " to the drivers that are not 
available for ARM?

BR
-Zhao Qiang

RE: [PATCH v5 2/2] QE: remove PPCisms for QE

[Qiang Zhao]

On Mon, Sep 20, 2016 at 4:13 AM, Leo Li wrote:
> -Original Message-
> From: Leo Li [mailto:pku@gmail.com]
> Sent: Tuesday, September 20, 2016 4:13 AM
> To: Qiang Zhao <qiang.z...@nxp.com>
> Cc: Scott Wood <o...@buserror.net>; linuxppc-dev  d...@lists.ozlabs.org>; lkml <linux-ker...@vger.kernel.org>; X.B. Xie
> <xiaobo@nxp.com>
> Subject: Re: [PATCH v5 2/2] QE: remove PPCisms for QE
> 
> On Mon, Jul 25, 2016 at 12:43 AM, Zhao Qiang <qiang.z...@nxp.com> wrote:
> > QE was supported on PowerPC, and dependent on PPC, Now it is supported
> > on other platforms. so remove PPCisms.
> >
> > Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
> > ---
> > Changes for v2:
> > - na
> > Changes for v3:
> > - add NO_IRQ
> > Changes for v4:
> > - modify spin_event_timeout to opencoded timeout loop
> > - remove NO_IRQ
> > - modify virq_to_hw to opencoed code Changes for v5:
> > - modify commit msg
> > - modify depends of QUICC_ENGINE
> > - add kerneldoc header for qe_issue_cmd
> >
> >  drivers/irqchip/qe_ic.c   | 28 +--
> >  drivers/soc/fsl/qe/Kconfig|  2 +-
> >  drivers/soc/fsl/qe/qe.c   | 80 ++--
> ---
> >  drivers/soc/fsl/qe/qe_io.c| 42 ++-
> >  drivers/soc/fsl/qe/qe_tdm.c   |  8 ++---
> >  drivers/soc/fsl/qe/ucc.c  | 10 +++---
> >  drivers/soc/fsl/qe/ucc_fast.c | 68 ++--
> >  include/soc/fsl/qe/qe.h   |  1 -
> >  include/soc/fsl/qe/qe_ic.h| 12 +++
> >  9 files changed, 133 insertions(+), 118 deletions(-)
> >
> 
> [snip]
> 
> > diff --git a/drivers/soc/fsl/qe/Kconfig b/drivers/soc/fsl/qe/Kconfig
> > index 73a2e08..b26b643 100644
> > --- a/drivers/soc/fsl/qe/Kconfig
> > +++ b/drivers/soc/fsl/qe/Kconfig
> > @@ -4,7 +4,7 @@
> >
> >  config QUICC_ENGINE
> > bool "Freescale QUICC Engine (QE) Support"
> > -   depends on FSL_SOC && PPC32
> > +   depends on OF && HAS_IOMEM
> > select GENERIC_ALLOCATOR
> > select CRC32
> > help
> 
> You make it possible to build QE drivers on ARM, but the UCC_GETH fails to
> build on arm64.  Please make sure all these drivers can build on other
> architectures.  Or you can simply make them only build for Power architecture
> as most of them are not available on ARM.
> 

Most of them are not available on ARM and ARM64.
Now, only qe-hdlc is available on ARM64.

BR
-Zhao Qiang

RE: [PATCH v13 3/6] CPM/QE: use genalloc to manage CPM/QE muram

[Qiang Zhao]

On 6/8/2016 03:48AM,  Christophe Leroy  wrote :

> -Original Message-
> From: Christophe Leroy [mailto:christophe.le...@c-s.fr]
> Sent: Saturday, August 06, 2016 12:59 AM
> To: Zhao Qiang ; lau...@codeaurora.org
> Cc: catalin.mari...@arm.com; linux-ker...@vger.kernel.org; Scott Wood
> ; o...@lixom.net; a...@linux-foundation.org; linuxppc-
> d...@lists.ozlabs.org; x@freescale.com
> Subject: Re: [PATCH v13 3/6] CPM/QE: use genalloc to manage CPM/QE muram
> 
> 
> 
> Le 30/11/2015 à 03:48, Zhao Qiang a écrit :
> > Use genalloc to manage CPM/QE muram instead of rheap.
> >
> > Signed-off-by: Zhao Qiang 
> > ---
> > Changes for v9:
> > - splitted from patch 3/5, modify cpm muram management functions.
> > Changes for v10:
> > - modify cpm muram first, then move to qe_common
> > - modify commit.
> > Changes for v11:
> > - factor out the common alloc code
> > - modify min_alloc_order to zero for cpm_muram_alloc_fixed.
> > Changes for v12:
> > - Nil
> > Changes for v13:
> > - rebase
> >
> >  arch/powerpc/include/asm/cpm.h   |   3 +
> >  arch/powerpc/platforms/Kconfig   |   4 +-
> >  arch/powerpc/sysdev/cpm_common.c | 126
> +++
> >  lib/genalloc.c   |   2 +-
> >  4 files changed, 94 insertions(+), 41 deletions(-)
> >
> 
> With that patch applied, I get the following Oops on a 8xx (Which has a CPM1).
> 
> cpm_muram_init() is called from setup_arch()
> 
> It seems that gen_pool_add() tries to kmalloc() memory but the SLAB is not
> available yet.
> 

Thank you for your comments, I can't find a 8xx board, would you like to test 
the patch 
Attached on your board? 

> [0.00] Unable to handle kernel paging request for data at
> address 0x0008
> [0.00] Faulting instruction address: 0xc01acce0
> [0.00] Oops: Kernel access of bad area, sig: 11 [#1]
> [0.00] PREEMPT CMPC885
> [0.00] CPU: 0 PID: 0 Comm: swapper Not tainted
> 4.4.14-s3k-dev-g0886ed8-svn #5
> [0.00] task: c05183e0 ti: c0536000 task.ti: c0536000
> [0.00] NIP: c01acce0 LR: c0011068 CTR: 
> [0.00] REGS: c0537e50 TRAP: 0300   Not tainted
> (4.4.14-s3k-dev-g0886ed8-svn)
> [0.00] MSR: 1032   CR: 28044428  XER: 
> [0.00] DAR: 0008 DSISR: c000
> GPR00: c0011068 c0537f00 c05183e0  9000  0bc0 
> GPR08: ff003000 ff00b000 ff003bbf  22044422 100d43a8 
> 07ff94e8
> GPR16:  07bb5d70  07ff81f4 07ff81f4 07ff81f4 
> 
> GPR24: 07ffb3a0 07fe7628 c055 c7ffa190 c054 ff003bbf 
> 0001
> [0.00] NIP [c01acce0] gen_pool_add_virt+0x14/0xdc
> [0.00] LR [c0011068] cpm_muram_init+0xd4/0x18c
> [0.00] Call Trace:
> [0.00] [c0537f00] [0200] 0x200 (unreliable)
> [0.00] [c0537f20] [c0011068] cpm_muram_init+0xd4/0x18c
> [0.00] [c0537f70] [c0494684] cpm_reset+0xb4/0xc8
> [0.00] [c0537f90] [c0494c64] cmpc885_setup_arch+0x10/0x30
> [0.00] [c0537fa0] [c0493cd4] setup_arch+0x130/0x168
> [0.00] [c0537fb0] [c04906bc] start_kernel+0x88/0x380
> [0.00] [c0537ff0] [c0002224] start_here+0x38/0x98
> [0.00] Instruction dump:
> [0.00] 91430010 91430014 80010014 83e1000c 7c0803a6 38210010
> 4e800020 7c0802a6
> [0.00] 9421ffe0 bf61000c 90010024 7c7e1b78 <80630008> 7c9c2378
> 7cc31c30 3863001f
> [0.00] ---[ end trace dc8fa200cb88537f ]---


0001-CPM1-use-subsys_initcall-to-init-cpm1.patch
Description: 0001-CPM1-use-subsys_initcall-to-init-cpm1.patch

RE: [Patch v3 1/3] irqchip/qeic: move qeic driver from drivers/soc/fsl/qe

[Qiang Zhao]

Hi Jason,

On Mon, Jul 26, 2016 at 03:24AM, Jason Cooper wrote:
> -Original Message-
> From: Jason Cooper [mailto:ja...@lakedaemon.net]
> Sent: Tuesday, July 26, 2016 3:24 AM
> To: Qiang Zhao <qiang.z...@nxp.com>
> Cc: o...@buserror.net; linuxppc-dev@lists.ozlabs.org; linux-
> ker...@vger.kernel.org; Xiaobo Xie <xiaobo@nxp.com>
> Subject: Re: [Patch v3 1/3] irqchip/qeic: move qeic driver from
> drivers/soc/fsl/qe
> 
> >
> >  static DEFINE_RAW_SPINLOCK(qe_ic_lock);
> >
> > diff --git a/drivers/soc/fsl/qe/Makefile b/drivers/soc/fsl/qe/Makefile
> > index 2031d38..51e4726 100644
> > --- a/drivers/soc/fsl/qe/Makefile
> > +++ b/drivers/soc/fsl/qe/Makefile
> > @@ -1,7 +1,7 @@
> >  #
> >  # Makefile for the linux ppc-specific parts of QE  #
> > -obj-$(CONFIG_QUICC_ENGINE)+= qe.o qe_common.o qe_ic.o qe_io.o
> > +obj-$(CONFIG_QUICC_ENGINE)+= qe.o qe_common.o qe_io.o
> >  obj-$(CONFIG_CPM)  += qe_common.o
> >  obj-$(CONFIG_UCC)  += ucc.o
> >  obj-$(CONFIG_UCC_SLOW) += ucc_slow.o
> > diff --git a/drivers/soc/fsl/qe/qe_ic.h b/drivers/soc/fsl/qe/qe_ic.h
> > deleted file mode 100644 index 926a2ed..000
> > --- a/drivers/soc/fsl/qe/qe_ic.h
> > +++ /dev/null
> > @@ -1,103 +0,0 @@
> > -/*
> > - * drivers/soc/fsl/qe/qe_ic.h
> > - *
> > - * QUICC ENGINE Interrupt Controller Header
> > - *
> > - * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
> > - *
> > - * Author: Li Yang <le...@freescale.com>
> > - * Based on code from Shlomi Gridish <grid...@freescale.com>
> > - *
> > - * This program is free software; you can redistribute  it and/or
> > modify it
> > - * under  the terms of  the GNU General  Public License as published
> > by the
> > - * Free Software Foundation;  either version 2 of the  License, or
> > (at your
> > - * option) any later version.
> > - */
> 
> Please transfer this over as well, and update is as necessary.

Thank you for your review!
The author and the copyright is the same as the .c file, how to transfer this?
And could you tell me what should I do for update?

Thank you!
-Zhao Qiang
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RE: [PATCH v2] irqchip/qeic: move qeic driver from drivers/soc/fsl/qe

[Qiang Zhao]

On Thu, Jul 07, 2016 at 10:25PM , Jason Cooper <ja...@lakedaemon.net> wrote:
> -Original Message-
> From: Jason Cooper [mailto:ja...@lakedaemon.net]
> Sent: Thursday, July 07, 2016 10:25 PM
> To: Qiang Zhao <qiang.z...@nxp.com>
> Cc: o...@buserror.net; t...@linutronix.de; marc.zyng...@arm.com; linuxppc-
> d...@lists.ozlabs.org; linux-ker...@vger.kernel.org; Xiaobo Xie
> <xiaobo@nxp.com>
> Subject: Re: [PATCH v2] irqchip/qeic: move qeic driver from drivers/soc/fsl/qe
> 
> Hi Zhao Qiang,
> 
> On Thu, Jul 07, 2016 at 09:23:55AM +0800, Zhao Qiang wrote:
> > The driver stays the same.
> >
> > Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
> > ---
> > Changes for v2:
> > - modify the subject and commit msg
> >
> >  drivers/irqchip/Makefile| 1 +
> >  drivers/{soc/fsl/qe => irqchip}/qe_ic.c | 0  drivers/{soc/fsl/qe =>
> > irqchip}/qe_ic.h | 0
> >  drivers/soc/fsl/qe/Makefile | 2 +-
> >  4 files changed, 2 insertions(+), 1 deletion(-)  rename
> > drivers/{soc/fsl/qe => irqchip}/qe_ic.c (100%)  rename
> > drivers/{soc/fsl/qe => irqchip}/qe_ic.h (100%)
> 
> Please merge the include file into the C file and rename to follow the naming
> convention in drivers/irqchip/.  e.g. irq-qeic.c or irq-qe_ic.c.
> 
> Once you have that, please resend the entire series with this as the first 
> patch.

Sorry, I have no idea about "Include file", could you explain which file you 
meant?

Thank you!
-Zhao Qiang
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RE: [PATCH v2] irqchip/qeic: move qeic driver from drivers/soc/fsl/qe

[Qiang Zhao]

On Thu, Jul 07, 2016 at 10:25PM , Jason Cooper <ja...@lakedaemon.net> wrote:
> -Original Message-
> From: Jason Cooper [mailto:ja...@lakedaemon.net]
> Sent: Thursday, July 07, 2016 10:25 PM
> To: Qiang Zhao <qiang.z...@nxp.com>
> Cc: o...@buserror.net; t...@linutronix.de; marc.zyng...@arm.com; linuxppc-
> d...@lists.ozlabs.org; linux-ker...@vger.kernel.org; Xiaobo Xie
> <xiaobo@nxp.com>
> Subject: Re: [PATCH v2] irqchip/qeic: move qeic driver from drivers/soc/fsl/qe
> 
> Hi Zhao Qiang,
> 
> On Thu, Jul 07, 2016 at 09:23:55AM +0800, Zhao Qiang wrote:
> > The driver stays the same.
> >
> > Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
> > ---
> > Changes for v2:
> > - modify the subject and commit msg
> >
> >  drivers/irqchip/Makefile| 1 +
> >  drivers/{soc/fsl/qe => irqchip}/qe_ic.c | 0  drivers/{soc/fsl/qe =>
> > irqchip}/qe_ic.h | 0
> >  drivers/soc/fsl/qe/Makefile | 2 +-
> >  4 files changed, 2 insertions(+), 1 deletion(-)  rename
> > drivers/{soc/fsl/qe => irqchip}/qe_ic.c (100%)  rename
> > drivers/{soc/fsl/qe => irqchip}/qe_ic.h (100%)
> 
> Please merge the include file into the C file and rename to follow the naming
> convention in drivers/irqchip/.  e.g. irq-qeic.c or irq-qe_ic.c.
> 
> Once you have that, please resend the entire series with this as the first 
> patch.
> 

OK, I will modify the next version. 

-Zhao Qiang
BR
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RE: [PATCH 1/2] qe/ic: move qe_ic_init from platforms to irqchip

[Qiang Zhao]

On 07/05/2016 11:19 AM, Jason Cooper <ja...@lakedaemon.net> wrote:

> -Original Message-
> From: Jason Cooper [mailto:ja...@lakedaemon.net]
> Sent: Tuesday, July 05, 2016 10:22 PM
> To: Qiang Zhao <qiang.z...@nxp.com>
> Cc: o...@buserror.net; t...@linutronix.de; marc.zyng...@arm.com; linuxppc-
> d...@lists.ozlabs.org; linux-ker...@vger.kernel.org; Xiaobo Xie
> <xiaobo@nxp.com>
> Subject: Re: [PATCH 1/2] qe/ic: move qe_ic_init from platforms to irqchip
> 
> On Tue, Jul 05, 2016 at 07:27:21AM +, Qiang Zhao wrote:
> > On 07/05/2016 11:19 AM, Jason Cooper <ja...@lakedaemon.net> wrote:
> > > -Original Message-
> > > From: Jason Cooper [mailto:ja...@lakedaemon.net]
> > > Sent: Tuesday, July 05, 2016 11:19 AM
> > > To: Qiang Zhao <qiang.z...@nxp.com>
> > > Cc: o...@buserror.net; t...@linutronix.de; marc.zyng...@arm.com;
> > > linuxppc- d...@lists.ozlabs.org; linux-ker...@vger.kernel.org; Xiaobo
> > > Xie <xiaobo@nxp.com>
> > > Subject: Re: [PATCH 1/2] qe/ic: move qe_ic_init from platforms to
> > > > diff --git a/arch/powerpc/platforms/83xx/misc.c
> > > > b/arch/powerpc/platforms/83xx/misc.c
> > > > index 7e923ca..9431fc7 100644
> > > > --- a/arch/powerpc/platforms/83xx/misc.c
> > > > +++ b/arch/powerpc/platforms/83xx/misc.c
> > > > @@ -93,24 +93,9 @@ void __init mpc83xx_ipic_init_IRQ(void)  }
> > > >
> > > >  #ifdef CONFIG_QUICC_ENGINE
> > > > -void __init mpc83xx_qe_init_IRQ(void) -{
> > > > -   struct device_node *np;
> > > > -
> > > > -   np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
> > > > -   if (!np) {
> > > > -   np = of_find_node_by_type(NULL, "qeic");
> > > > -   if (!np)
> > > > -   return;
> > > > -   }
> > >
> > > This block isn't preserved in the irqchip driver.  Why not?
> >
> > I grep qeic in arch/powerpc/boot/dts/*, doesn't find which board use qeic as
> type.
> 
> Unfortunately, checking powerpc/boot/dts/* isn't sufficient for confirming we
> aren't going to break backwards compatibility with boards *in the field*.
> 
> Please take a look at:
> 
>   d4fb5ebd83c70 powerpc/83xx: consolidate init_IRQ functions
>   8159df72d43e2 83xx: add support for the kmeter1 board.
> 
> Perhaps one or two of the authors is still around and can say why that check 
> is
> there and if it's ok to remove it.
> 
> Or, we could just play it safe and keep the check.
> 

Ok, I will add this check in next version.

Thanks
-Zhao Qiang
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RE: [PATCH 1/2] qe/ic: move qe_ic_init from platforms to irqchip

[Qiang Zhao]

On 07/05/2016 11:19 AM, Jason Cooper <ja...@lakedaemon.net> wrote:
> -Original Message-
> From: Jason Cooper [mailto:ja...@lakedaemon.net]
> Sent: Tuesday, July 05, 2016 11:19 AM
> To: Qiang Zhao <qiang.z...@nxp.com>
> Cc: o...@buserror.net; t...@linutronix.de; marc.zyng...@arm.com; linuxppc-
> d...@lists.ozlabs.org; linux-ker...@vger.kernel.org; Xiaobo Xie
> <xiaobo@nxp.com>
> Subject: Re: [PATCH 1/2] qe/ic: move qe_ic_init from platforms to irqchip
> 
> Hi Zhao Qiang,
> 
> Please reword your subject line to conform to the standard in irqchip (since
> that's where the code is added).  Also, please adjust the subject line to 
> express
> *why* the change is being made.
> 
> On Tue, Jul 05, 2016 at 09:46:58AM +0800, Zhao Qiang wrote:
> > The codes of qe_ic_init in platforms are redundant, move them to qe_ic
> > under irqchip
> 
> This needs to be a lot more clear.  How is backwards compatibility preserved?
> Why is lookup by type "qeic" dropped?  In short, please explain everything 
> that
> looks funny so we don't have to guess.

Thank you for your review and feedback.

> 
> > Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
> > ---
> >  arch/powerpc/platforms/83xx/misc.c| 15 ---
> >  arch/powerpc/platforms/85xx/corenet_generic.c |  9 -
> >  arch/powerpc/platforms/85xx/mpc85xx_mds.c | 14 --
> >  arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 16 
> >  arch/powerpc/platforms/85xx/twr_p102x.c   | 14 --
> >  drivers/irqchip/qe_ic.c   | 14 ++
> >  6 files changed, 14 insertions(+), 68 deletions(-)
> >
> > diff --git a/arch/powerpc/platforms/83xx/misc.c
> > b/arch/powerpc/platforms/83xx/misc.c
> > index 7e923ca..9431fc7 100644
> > --- a/arch/powerpc/platforms/83xx/misc.c
> > +++ b/arch/powerpc/platforms/83xx/misc.c
> > @@ -93,24 +93,9 @@ void __init mpc83xx_ipic_init_IRQ(void)  }
> >
> >  #ifdef CONFIG_QUICC_ENGINE
> > -void __init mpc83xx_qe_init_IRQ(void) -{
> > -   struct device_node *np;
> > -
> > -   np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
> > -   if (!np) {
> > -   np = of_find_node_by_type(NULL, "qeic");
> > -   if (!np)
> > -   return;
> > -   }
> 
> This block isn't preserved in the irqchip driver.  Why not?

I grep qeic in arch/powerpc/boot/dts/*, doesn't find which board use qeic as 
type.

> 
> > -   qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
> > -   of_node_put(np);
> > -}
> > -
> >  void __init mpc83xx_ipic_and_qe_init_IRQ(void)
> >  {
> > mpc83xx_ipic_init_IRQ();
> > -   mpc83xx_qe_init_IRQ();
> >  }
> >  #endif /* CONFIG_QUICC_ENGINE */
> >
> > diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c
> > b/arch/powerpc/platforms/85xx/corenet_generic.c
> > index a2b0bc8..526fc2b 100644
> > --- a/arch/powerpc/platforms/85xx/corenet_generic.c
> > +++ b/arch/powerpc/platforms/85xx/corenet_generic.c
> > @@ -41,8 +41,6 @@ void __init corenet_gen_pic_init(void)
> > unsigned int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU |
> > MPIC_NO_RESET;
> >
> > -   struct device_node *np;
> > -
> > if (ppc_md.get_irq == mpic_get_coreint_irq)
> > flags |= MPIC_ENABLE_COREINT;
> >
> > @@ -50,13 +48,6 @@ void __init corenet_gen_pic_init(void)
> > BUG_ON(mpic == NULL);
> >
> > mpic_init(mpic);
> > -
> > -   np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
> > -   if (np) {
> > -   qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
> > -   qe_ic_cascade_high_mpic);
> > -   of_node_put(np);
> > -   }
> >  }
> >
> >  /*
> > diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
> > b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
> > index f61cbe2..7ae4901 100644
> > --- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
> > +++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
> > @@ -279,20 +279,6 @@ static void __init mpc85xx_mds_qeic_init(void)
> > of_node_put(np);
> > return;
> > }
> > -
> > -   np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
> > -   if (!np) {
> > -   np = of_find_node_by_type(NULL, "qeic");
> > -   if (!np)
> > -   return;
> > -   }
> > -
> > -   if (machine_is(p1021_mds))
> > -   qe_ic_init(

RE: [PATCH 2/2] qe/ic: refactor qe_ic to simplify

[Qiang Zhao]

On 07/05/2016 11:51 AM, Jason Cooper <ja...@lakedaemon.net> wrote:

> -Original Message-
> From: Jason Cooper [mailto:ja...@lakedaemon.net]
> Sent: Tuesday, July 05, 2016 11:51 AM
> To: Qiang Zhao <qiang.z...@nxp.com>
> Cc: o...@buserror.net; t...@linutronix.de; marc.zyng...@arm.com; linuxppc-
> d...@lists.ozlabs.org; linux-ker...@vger.kernel.org; Xiaobo Xie
> <xiaobo@nxp.com>
> Subject: Re: [PATCH 2/2] qe/ic: refactor qe_ic to simplify
> 
> Hi Zhao Qiang,
> 
> Same comment as previous patch regarding the subject line.
> 
> On Tue, Jul 05, 2016 at 09:46:59AM +0800, Zhao Qiang wrote:
> > there are init_qe_ic_sysfs and qeic_of_init, refactor them.
> 
> Same comment from previous patch about commit log.
> 
> >
> > Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
> > ---
> >  drivers/irqchip/qe_ic.c| 83 +--
> ---
> >  include/soc/fsl/qe/qe_ic.h |  7 
> >  2 files changed, 45 insertions(+), 45 deletions(-)
> >
> > diff --git a/drivers/irqchip/qe_ic.c b/drivers/irqchip/qe_ic.c index
> > f7f9a81..46652c0 100644
> > --- a/drivers/irqchip/qe_ic.c
> > +++ b/drivers/irqchip/qe_ic.c
> > @@ -317,27 +317,35 @@ unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
> > return irq_linear_revmap(qe_ic->irqhost, irq);  }
> >
> > -void __init qe_ic_init(struct device_node *node, unsigned int flags,
> > -  void (*low_handler)(struct irq_desc *desc),
> > -  void (*high_handler)(struct irq_desc *desc))
> > +static int __init qe_ic_init(unsigned int flags)
> >  {
> > +   struct device_node *node;
> > struct qe_ic *qe_ic;
> > struct resource res;
> > -   u32 temp = 0, ret, high_active = 0;
> > +   u32 temp = 0, high_active = 0;
> > +   int ret = 0;
> > +
> > +   node = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
> > +   if (!node)
> > +   return -ENODEV;
> >
> > ret = of_address_to_resource(node, 0, );
> > -   if (ret)
> > -   return;
> > +   if (ret) {
> > +   ret = -ENODEV;
> > +   goto err_put_node;
> > +   }
> >
> > qe_ic = kzalloc(sizeof(*qe_ic), GFP_KERNEL);
> > -   if (qe_ic == NULL)
> > -   return;
> > +   if (qe_ic == NULL) {
> > +   ret = -ENOMEM;
> > +   goto err_put_node;
> > +   }
> >
> > qe_ic->irqhost = irq_domain_add_linear(node, NR_QE_IC_INTS,
> >_ic_host_ops, qe_ic);
> > if (qe_ic->irqhost == NULL) {
> > -   kfree(qe_ic);
> > -   return;
> > +   ret = -ENOMEM;
> > +   goto err_free_qe_ic;
> > }
> >
> > qe_ic->regs = ioremap(res.start, resource_size()); @@ -348,9
> > +356,9 @@ void __init qe_ic_init(struct device_node *node, unsigned int
> flags,
> > qe_ic->virq_low = irq_of_parse_and_map(node, 1);
> >
> > if (qe_ic->virq_low == NO_IRQ) {
> > -   printk(KERN_ERR "Failed to map QE_IC low IRQ\n");
> > -   kfree(qe_ic);
> > -   return;
> > +   pr_err("Failed to map QE_IC low IRQ\n");
> > +   ret = -ENOMEM;
> > +   goto err_domain_remove;
> > }
> >
> > /* default priority scheme is grouped. If spread mode is*/
> > @@ -377,13 +385,23 @@ void __init qe_ic_init(struct device_node *node,
> unsigned int flags,
> > qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
> >
> > irq_set_handler_data(qe_ic->virq_low, qe_ic);
> > -   irq_set_chained_handler(qe_ic->virq_low, low_handler);
> > +   irq_set_chained_handler(qe_ic->virq_low, qe_ic_cascade_low_mpic);
> >
> > if (qe_ic->virq_high != NO_IRQ &&
> > qe_ic->virq_high != qe_ic->virq_low) {
> > irq_set_handler_data(qe_ic->virq_high, qe_ic);
> > -   irq_set_chained_handler(qe_ic->virq_high, high_handler);
> > +   irq_set_chained_handler(qe_ic->virq_high,
> > +   qe_ic_cascade_high_mpic);
> > }
> > +   return ret;
> 
> of_node_put(node)?  Explicitly return success?

Yes, thank you very much!

> 
> > +
> > +err_domain_remove:
> > +   irq_domain_remove(qe_ic->irqhost);
> > +err_free_qe_ic:
> > +   kfree(qe_ic);
> > +err_put_node:
> > +   of_node_put(node);
> > +   return ret;
> >  }
> >
> >  void qe_ic_set_highest_priority(uns

RE: [v5,1/7] QE: Add IC, SI and SIRAM document to device tree bindings.

[Qiang Zhao]

On Tue, May 17, 2016 at 07:22AM, Scott Wood wrote:
> -Original Message-
> From: Scott Wood [mailto:o...@buserror.net]
> Sent: Tuesday, May 17, 2016 7:22 AM
> To: Qiang Zhao <qiang.z...@nxp.com>
> Cc: robh...@kernel.org; devicet...@vger.kernel.org; linux-
> ker...@vger.kernel.org; Xiaobo Xie <xiaobo@nxp.com>; Yang-Leo Li
> <leoyang...@nxp.com>; linuxppc-dev@lists.ozlabs.org
> Subject: Re: [v5,1/7] QE: Add IC, SI and SIRAM document to device tree
> bindings.
> 
> On Wed, Mar 09, 2016 at 09:21:28AM +0800, Zhao Qiang wrote:
> > Add IC, SI and SIRAM document of QE to
> > Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt
> >
> > Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
> > Acked-by: Rob Herring <r...@kernel.org>
> > ---
> > changes for v2
> > - Add interrupt-controller in Required properties
> > - delete address-cells and size-cells for qe-si and qe-siram Changes
> > for v3
> > - Add SoC specific caompatible strings to qe-si and qe-siram Changes
> > for v4
> > - NA
> > Changes for v5
> > - NA
> >
> >  .../devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt  | 50
> > ++
> >  1 file changed, 50 insertions(+)
> > +* Serial Interface Block (SI)
> > +
> > +The SI manages the routing of eight TDM lines to the QE block serial
> > +drivers , the MCC and the UCCs, for receive and transmit.
> > +
> > +Required properties:
> > +- compatible : should be "fsl,t1040-qe-si".
> > +- reg : Address range of SI register set.
> 
> Is t1040 the only chip that has or will ever have this?

There also be t1024 and ls1043 supporting si.
I thought to add them when adding their device node.
If you think it is better to add them now, I will modify.

-Zhao Qiang


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RE: [v9, 6/7] MAINTAINERS: add entry for Freescale SoC driver

[Qiang Zhao]

On Wed, 2016-05-04 at 11:24 +0800, Yangbo Lu wrote:
> -Original Message-
> From: Yangbo Lu [mailto:yangbo...@nxp.com]
> Sent: Wednesday, May 04, 2016 11:25 AM
> To: linux-...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux-
> ker...@vger.kernel.org; linux-...@vger.kernel.org; linux-...@vger.kernel.org;
> io...@lists.linux-foundation.org; net...@vger.kernel.org
> Cc: ulf.hans...@linaro.org; Scott Wood <o...@buserror.net>; Mark Rutland
> <mark.rutl...@arm.com>; Rob Herring <robh...@kernel.org>; Russell King
> <li...@arm.linux.org.uk>; Jochen Friedrich <joc...@scram.de>; Joerg Roedel
> <j...@8bytes.org>; Claudiu Manoil <claudiu.man...@freescale.com>; Bhupesh
> Sharma <bhupesh.sha...@freescale.com>; Qiang Zhao
> <qiang.z...@nxp.com>; Kumar Gala <ga...@codeaurora.org>; Santosh
> Shilimkar <ssant...@kernel.org>; Yang-Leo Li <leoyang...@nxp.com>; Xiaobo
> Xie <xiaobo@nxp.com>; Yangbo Lu <yangbo...@nxp.com>
> Subject: [v9, 6/7] MAINTAINERS: add entry for Freescale SoC driver
> 
> Add maintainer entry for Freescale SoC driver including the QE library and the
> GUTS driver now. Also add maintainer for QE library.
> 
> Signed-off-by: Yangbo Lu <yangbo...@nxp.com>
> ---
> Changes for v8:
>   - Added this patch
> Changes for v9:
>   - Added linux-arm mail list
>   - Removed GUTS driver entry
> ---
>  MAINTAINERS | 11 ++-
>  1 file changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 42e65d1..ce91db7 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -4622,9 +4622,18 @@ F: drivers/net/ethernet/freescale/fec_ptp.c
>  F:   drivers/net/ethernet/freescale/fec.h
>  F:   Documentation/devicetree/bindings/net/fsl-fec.txt
> 
> +FREESCALE SOC DRIVER
> +M:   Scott Wood <o...@buserror.net>
> +L:   linuxppc-dev@lists.ozlabs.org
> +L:   linux-arm-ker...@lists.infradead.org
> +S:   Maintained
> +F:   drivers/soc/fsl/
> +F:   include/linux/fsl/
> +
>  FREESCALE QUICC ENGINE LIBRARY
> +M:   Qiang Zhao <qiang.z...@nxp.com>
>  L:   linuxppc-dev@lists.ozlabs.org
> -S:   Orphan
> +S:   Maintained
>  F:   drivers/soc/fsl/qe/
>  F:   include/soc/fsl/*qe*.h
>  F:   include/soc/fsl/*ucc*.h
> --
> 2.1.0.27.g96db324

I am ok!

-Zhao Qiang

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RE: [PATCH 5/5] drivers/net: support hdlc function for QE-UCC

[Qiang Zhao]

On 20/04/2016 12:22AM, Christophe Leroy <christophe.le...@c-s.fr> wrote
> -Original Message-
> From: Christophe Leroy [mailto:christophe.le...@c-s.fr]
> Sent: Wednesday, April 20, 2016 12:22 AM
> To: Qiang Zhao <qiang.z...@nxp.com>; da...@davemloft.net
> Cc: gre...@linuxfoundation.org; Xiaobo Xie <xiaobo@nxp.com>; linux-
> ker...@vger.kernel.org; o...@buserror.net; net...@vger.kernel.org;
> a...@linux-foundation.org; linuxppc-dev@lists.ozlabs.org
> Subject: Re: [PATCH 5/5] drivers/net: support hdlc function for QE-UCC
> 
> Le 30/03/2016 10:50, Zhao Qiang a écrit :
> > The driver add hdlc support for Freescale QUICC Engine.
> > It support NMSI and TSA mode.
> When using TSA, how does the TSA gets configured ? Especially how do you
> describe which Timeslot is switched to HDLC channels ?

the TSA is configured statically according to device tree node. 
For " which Timeslot is switched to HDLC channels ", there is a property 
"fsl,tx-timeslot-mask" in device tree to describe it.

> Is it possible to route some Timeslots to one UCC for HDLC, and route some
> others to another UCC for an ALSA sound driver ?

The feature you describe is not supported at present.

> The QE also have a QMC which allows to split all timeslots to a given UCC into
> independant channels that can either be used with HDLC or transparents (for
> audio for instance). Do you intent to also support QMC ?

new QE use UMCC instead of QMC in old QE, we have started to develop UMCC.
 
> According to the compatible property, it looks like your driver is for 
> freescale
> T1040. The MPC83xx also has a Quick Engine, would it work on it too ?

The driver is common, but tested on t1040, it is needed to add node to MPC83xx
If you want to test on mpc83xx.

-Zhao Qiang
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RE: [PATCH 4/5] fsl/qe: Add QE TDM lib

[Qiang Zhao]

On Wed, 2016-03-30 at 07:50PM, Joakim Tjernlund wrote:
> -Original Message-
> From: Joakim Tjernlund [mailto:joakim.tjernl...@infinera.com]
> Sent: Wednesday, March 30, 2016 7:50 PM
> To: da...@davemloft.net; Qiang Zhao <qiang.z...@nxp.com>
> Cc: linuxppc-dev@lists.ozlabs.org; linux-ker...@vger.kernel.org; Xiaobo Xie
> <xiaobo@nxp.com>; o...@buserror.net; gre...@linuxfoundation.org;
> a...@linux-foundation.org; net...@vger.kernel.org
> Subject: Re: [PATCH 4/5] fsl/qe: Add QE TDM lib
> 
> On Wed, 2016-03-30 at 16:50 +0800, Zhao Qiang wrote:
> > QE has module to support TDM, some other protocols supported by QE are
> > based on TDM.
> > add a qe-tdm lib, this lib provides functions to the protocols using
> > TDM to configurate QE-TDM.
> >
> > Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
> > +   utdm->siram_entry_id = val;
> > +
> > +   set_si_param(utdm, ut_info);
> > +
> > +   np2 = of_find_compatible_node(NULL, NULL, "fsl,t1040-qe-si");
> 
> fsl,t1040-qe-si only? What about mpc83xx?
> I recall QE is a little bit different compared to T1040 or will this 
> work(including
> the hdlc driver) on 83xx as well?

The " fsl,t1040-qe-si " is new added to dts and bindings, it is required to 
have SoC specific compatible strings.
mpc83xx will not use qe-si node. If there will be other soc useing qe-si, " 
fsl,t1040-qe-si " will follow the soc specific compatible,
like : 
si1: si@700 {
compatible = "fsl,ls1043-qe-si", "fsl,t1040-qe-si";
reg = <0x700 0x80>;
};

Best Regards
Zhao Qiang
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RE: [PATCH v5 3/7] QE: Add uqe_serial document to bindings

[Qiang Zhao]

On Fri, Mar 18, 2016 at 12:28AM, Rob Herring wrote:
> -Original Message-
> From: Rob Herring [mailto:r...@kernel.org]
> Sent: Friday, March 18, 2016 12:28 AM
> To: Qiang Zhao <qiang.z...@nxp.com>
> Cc: o...@buserror.net; Yang-Leo Li <leoyang...@nxp.com>; Xiaobo Xie
> <xiaobo@nxp.com>; linux-ker...@vger.kernel.org;
> devicet...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org
> Subject: Re: [PATCH v5 3/7] QE: Add uqe_serial document to bindings
> 
> On Wed, Mar 09, 2016 at 09:21:30AM +0800, Zhao Qiang wrote:
> > Add uqe_serial document to
> > Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/uqe_serial.txt
> >
> > Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
> > ---
> > Changes for v2
> > - modify tx/rx-clock-name specification Changes for v3
> > - NA
> > Changes for v4
> > - drop device_type
> > - modify to SoC specific compatible
> > Changes for v5
> > - add fsl to compatible as prefix
> >
> >  .../bindings/powerpc/fsl/cpm_qe/uqe_serial.txt | 18
> ++
> >  1 file changed, 18 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/uqe_serial.txt
> 
> Acked-by: Rob Herring <r...@kernel.org>

Thank you for reviewing!

BR
-Zhao Qiang
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RE: [PATCH v3 3/7] QE: Add uqe_serial document to bindings

[Qiang Zhao]

On Tue, Mar 08, 2016 at 1:28AM, Scott Wood wrote:
> -Original Message-
> From: Scott Wood [mailto:o...@buserror.net]
> Sent: Tuesday, March 08, 2016 1:28 AM
> To: Qiang Zhao <qiang.z...@nxp.com>; Rob Herring <r...@kernel.org>
> Cc: Yang-Leo Li <leoyang...@nxp.com>; Xiaobo Xie <xiaobo@nxp.com>;
> linux-ker...@vger.kernel.org; devicet...@vger.kernel.org; linuxppc-
> d...@lists.ozlabs.org
> Subject: Re: [PATCH v3 3/7] QE: Add uqe_serial document to bindings
> 
> On Mon, 2016-03-07 at 02:35 +, Qiang Zhao wrote:
> > On Tue, Mar 05, 2016 at 12:26PM, Rob Herring wrote:
> > > -Original Message-
> > > From: Rob Herring [mailto:r...@kernel.org]
> > > Sent: Saturday, March 05, 2016 12:26 PM
> > > To: Qiang Zhao <qiang.z...@nxp.com>
> > > Cc: o...@buserror.net; Yang-Leo Li <leoyang...@nxp.com>; Xiaobo Xie
> > > <xiaobo@nxp.com>; linux-ker...@vger.kernel.org;
> > > devicet...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org
> > > Subject: Re: [PATCH v3 3/7] QE: Add uqe_serial document to bindings
> > >
> > > On Tue, Mar 01, 2016 at 03:09:39PM +0800, Zhao Qiang wrote:
> > > > Add uqe_serial document to
> > > > Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/uqe_serial.tx
> > > > t
> > > >
> > > > Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
> > > > ---
> > > > Changes for v2
> > > > - modify tx/rx-clock-name specification Changes for v2
> > > > - NA
> > > >
> > > >  .../bindings/powerpc/fsl/cpm_qe/uqe_serial.txt| 19
> > > +++
> > > >  1 file changed, 19 insertions(+)
> > > >  create mode 100644
> > > > Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/uqe_serial.tx
> > > > t
> > > >
> > > > diff --git
> > > > a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/uqe_serial.
> > > > txt
> > > > b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/uqe_serial.
> > > > txt
> > > > new file mode 100644
> > > > index 000..436c71c
> > > > --- /dev/null
> > > > +++
> b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/uqe_serial.
> > > > +++ txt
> > > > @@ -0,0 +1,19 @@
> > > > +* Serial
> > > > +
> > > > +Currently defined compatibles:
> > > > +- ucc_uart
> > >
> > > I guess this is in use already and okay. However, looking at the
> > > driver there really should be SoC specific compatible strings here
> > > since the driver is looking up the SoC compatible string and
> > > composing the firmware filename from that.
> >
> > Ok, I will changed both driver and this compatible.
> 
> But don't break existing device trees while doing so.

Do I need to send driver patch in this patchset or a individual patch?

BR
-Zhao Qiang

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RE: [PATCH v3 3/7] QE: Add uqe_serial document to bindings

[Qiang Zhao]

On Tue, Mar 05, 2016 at 12:26PM, Rob Herring wrote:
> -Original Message-
> From: Rob Herring [mailto:r...@kernel.org]
> Sent: Saturday, March 05, 2016 12:26 PM
> To: Qiang Zhao <qiang.z...@nxp.com>
> Cc: o...@buserror.net; Yang-Leo Li <leoyang...@nxp.com>; Xiaobo Xie
> <xiaobo@nxp.com>; linux-ker...@vger.kernel.org;
> devicet...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org
> Subject: Re: [PATCH v3 3/7] QE: Add uqe_serial document to bindings
> 
> On Tue, Mar 01, 2016 at 03:09:39PM +0800, Zhao Qiang wrote:
> > Add uqe_serial document to
> > Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/uqe_serial.txt
> >
> > Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
> > ---
> > Changes for v2
> > - modify tx/rx-clock-name specification Changes for v2
> > - NA
> >
> >  .../bindings/powerpc/fsl/cpm_qe/uqe_serial.txt| 19
> +++
> >  1 file changed, 19 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/uqe_serial.txt
> >
> > diff --git
> > a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/uqe_serial.txt
> > b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/uqe_serial.txt
> > new file mode 100644
> > index 000..436c71c
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/uqe_serial.
> > +++ txt
> > @@ -0,0 +1,19 @@
> > +* Serial
> > +
> > +Currently defined compatibles:
> > +- ucc_uart
> 
> I guess this is in use already and okay. However, looking at the driver there
> really should be SoC specific compatible strings here since the driver is 
> looking
> up the SoC compatible string and composing the firmware filename from that.

Ok, I will changed both driver and this compatible.

> 
> > +
> > +Properties for ucc_uart:
> > +port-number : port number of UCC-UART tx/rx-clock-name : should be
> > +"brg1"-"brg16" for internal clock source,
> > +  should be "clk1"-"clk28" for external clock source.
> > +
> > +Example:
> > +
> > +   ucc_serial: ucc@2200 {
> > +   device_type = "serial";
> 
> Drop device_type. It should only be used in a few legacy cases.
> 
> Looks like the driver is matching on this. Please drop it from the driver 
> too. I'd
> leave dts files for now, but they should be updated too later.

Ok, Thank you for your Reviewing, I will drop it

> 
> > +   compatible = "ucc_uart";
> > +   port-number = <1>;
> > +   rx-clock-name = "brg2";
> > +   tx-clock-name = "brg2";
> > +   };
> > --
> > 2.1.0.27.g96db324
> >
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RE: [PATCH v2 1/7] QE: Add IC, SI and SIRAM document to device tree bindings.

[Qiang Zhao]

On Thu, 2016-02-25 at 11:12  AM, Scott Wood wrote:
> -Original Message-
> From: Scott Wood [mailto:o...@buserror.net]
> Sent: Thursday, February 25, 2016 11:12 AM
> To: Qiang Zhao <qiang.z...@nxp.com>; Rob Herring <r...@kernel.org>
> Cc: Yang-Leo Li <leoyang...@nxp.com>; linux-ker...@vger.kernel.org;
> devicet...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org
> Subject: Re: [PATCH v2 1/7] QE: Add IC, SI and SIRAM document to device tree
> bindings.
> 
> On Thu, 2016-02-25 at 03:10 +, Qiang Zhao wrote:
> > On Wed, 2016-02-24 at 04:20  AM, Scott Wood wrote:
> > > -Original Message-
> > > From: Scott Wood [mailto:o...@buserror.net]
> > > Sent: Wednesday, February 24, 2016 4:20 AM
> > > To: Rob Herring <r...@kernel.org>; Qiang Zhao <qiang.z...@nxp.com>
> > > Cc: Yang-Leo Li <leoyang...@nxp.com>; linux-ker...@vger.kernel.org;
> > > devicet...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org
> > > Subject: Re: [PATCH v2 1/7] QE: Add IC, SI and SIRAM document to
> > > device tree bindings.
> > >
> > > On Tue, 2016-02-23 at 14:15 -0600, Rob Herring wrote:
> > > > On Thu, Feb 18, 2016 at 09:06:06AM +0800, Zhao Qiang wrote:
> > > > > Add IC, SI and SIRAM document of QE to
> > > > > Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt
> > > > >
> > > > > Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
> > > > > ---
> > > > > Changes for v2
> > > > >   - Add interrupt-controller in Required properties
> > > > >   - delete address-cells and size-cells for qe-si and qe-siram
> > > > >
> > > > >  .../devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt  | 50
> > > > > ++
> > > > >  1 file changed, 50 insertions(+)
> > > > >
> > > > > diff --git
> > > > > a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt
> > > > > b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt
> > > > > index 4f89302..84052a7 100644
> > > > > ---
> > > > > a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt
> > > > > +++ b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.tx
> > > > > +++ t
> > > > > @@ -69,6 +69,56 @@ Example:
> > > > >   };
> > > > >   };
> > > > >
> > > > > +* Interrupt Controller (IC)
> > > > > +
> > > > > +Required properties:
> > > > > +- compatible : should be "fsl,qe-ic".
> > > >
> > > > > +- compatible : should be "fsl,qe-si".
> > > >
> > > > > +- compatible : should be "fsl,qe-siram".
> > > >
> > > > These compatible strings are all a bit generic and should have SoC
> > > > specific compatible strings.
> > >
> > > I don't know about si/siram, but "fsl,qe-ic" has been around since
> > > 2008, so it should be documented even if a more specific compatible
> > > is also added.
> >
> > Agree, and si/siram are also has been around since 2008.
> 
> Where?  I couldn't find them when grepping.

Sorry, I make a mistake, they have not been in upstream.

> 
> > In addition, I don’t think it is needed to add specific compatible,
> > because they are the same in qe-supported soc.
> 
> How do we know that they are 100% the same?

You mean it will be changed in later version?

BR
-Zhao

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RE: [PATCH v2 1/7] QE: Add IC, SI and SIRAM document to device tree bindings.

[Qiang Zhao]

On Wed, 2016-02-24 at 04:20  AM, Scott Wood wrote:
> -Original Message-
> From: Scott Wood [mailto:o...@buserror.net]
> Sent: Wednesday, February 24, 2016 4:20 AM
> To: Rob Herring <r...@kernel.org>; Qiang Zhao <qiang.z...@nxp.com>
> Cc: Yang-Leo Li <leoyang...@nxp.com>; linux-ker...@vger.kernel.org;
> devicet...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org
> Subject: Re: [PATCH v2 1/7] QE: Add IC, SI and SIRAM document to device tree
> bindings.
> 
> On Tue, 2016-02-23 at 14:15 -0600, Rob Herring wrote:
> > On Thu, Feb 18, 2016 at 09:06:06AM +0800, Zhao Qiang wrote:
> > > Add IC, SI and SIRAM document of QE to
> > > Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt
> > >
> > > Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
> > > ---
> > > Changes for v2
> > >   - Add interrupt-controller in Required properties
> > >   - delete address-cells and size-cells for qe-si and qe-siram
> > >
> > >  .../devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt  | 50
> > > ++
> > >  1 file changed, 50 insertions(+)
> > >
> > > diff --git
> > > a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt
> > > b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt
> > > index 4f89302..84052a7 100644
> > > --- a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt
> > > +++ b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt
> > > @@ -69,6 +69,56 @@ Example:
> > >   };
> > >   };
> > >
> > > +* Interrupt Controller (IC)
> > > +
> > > +Required properties:
> > > +- compatible : should be "fsl,qe-ic".
> >
> > > +- compatible : should be "fsl,qe-si".
> >
> > > +- compatible : should be "fsl,qe-siram".
> >
> > These compatible strings are all a bit generic and should have SoC
> > specific compatible strings.
> 
> I don't know about si/siram, but "fsl,qe-ic" has been around since 2008, so it
> should be documented even if a more specific compatible is also added.

Agree, and si/siram are also has been around since 2008.
In addition, I don’t think it is needed to add specific compatible, because 
they are
the same in qe-supported soc.

BR
-Zhao
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RE: [PATCH v2 2/7] QE: Add ucc hdlc document to bindings

[Qiang Zhao]

On Wen, Feb 24, 2016 at 04:22AM, Rob Herring wrote:
> -Original Message-
> From: Rob Herring [mailto:r...@kernel.org]
> Sent: Wednesday, February 24, 2016 4:22 AM
> To: Qiang Zhao <qiang.z...@nxp.com>
> Cc: o...@buserror.net; Yang-Leo Li <leoyang...@nxp.com>; linux-
> ker...@vger.kernel.org; devicet...@vger.kernel.org; linuxppc-
> d...@lists.ozlabs.org
> Subject: Re: [PATCH v2 2/7] QE: Add ucc hdlc document to bindings
> 
> On Thu, Feb 18, 2016 at 09:06:07AM +0800, Zhao Qiang wrote:
> > Add ucc hdlc document to
> > Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/network.txt
> 
> Not a very useful description.

Could you give a example for me?

> 
> > Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
> > ---
> > Changes for v2
> > - use ucc-hdlc instead of ucc_hdlc
> > - add more information to properties.
> >
> >  .../bindings/powerpc/fsl/cpm_qe/network.txt| 93
> ++
> >  1 file changed, 93 insertions(+)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/network.txt
> > b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/network.txt
> > index 29b28b8..936158c 100644
> > --- a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/network.txt
> > +++
> b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/network.txt
> > @@ -41,3 +41,96 @@ Example:
> > fsl,mdio-pin = <12>;
> > fsl,mdc-pin = <13>;
> > };
> > +
> > +* HDLC
> > +
> > +Currently defined compatibles:
> > +- fsl,ucc-hdlc
> > +
> > +Properties for fsl,ucc-hdlc:
> > +- rx-clock-name
> > +- tx-clock-name
> > +   Usage: required
> > +   Value type: 
> > +   Definition : should be "brg1"-"brg16" for internal clock source,
> > +should be "clk1"-"clk28" for external clock source.
> > +
> > +- fsl,rx-sync-clock
> > +   Usage: required
> > +   Value type: 
> > +   Definition : should be "none" when using internal clock source,
> > +should be "rsync_pin" when using external clock source.
> 
> Why not a boolean property here?

fsl,rx-sync-clock should have other values.
But now we just use rsync_pin and none.

> > +
> > +- fsl,tx-timeslot
> > +- fsl,rx-timeslot
> 
> Perhaps append "-mask"

Agree, I will modify in next version.

> 
> > +   Usage: required
> > +   Value type: 
> > +   Definition : time slot for TDM operation. Indicates which time slots
> > +used for transmitting and receiving.
> > +
> > +- fsl,tdm-framer-type
> > +   Usage: required
> > +   Value type: 
> > +   Definition : "e1" or "t1"
> 
> Boolean?

We just support e1 and t1, in fact, there are more TDM framer types.

> 
> > +
> > +- fsl,tdm-mode
> > +   Usage: required
> > +   Value type: 
> > +   Definition : "normal" or "internal-loopback"
> 
> Boolean?

It can be Boolean.

BR
-Zhao
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RE: [PATCH v2 3/7] QE: Add uqe_serial document to bindings

[Qiang Zhao]

On Wed, Feb 24, 2016 at 04:24AM, Rob Herring wrote:
> -Original Message-
> From: Rob Herring [mailto:r...@kernel.org]
> Sent: Wednesday, February 24, 2016 4:24 AM
> To: Qiang Zhao <qiang.z...@nxp.com>
> Cc: o...@buserror.net; Yang-Leo Li <leoyang...@nxp.com>; linux-
> ker...@vger.kernel.org; devicet...@vger.kernel.org; linuxppc-
> d...@lists.ozlabs.org
> Subject: Re: [PATCH v2 3/7] QE: Add uqe_serial document to bindings
> 
> On Thu, Feb 18, 2016 at 09:06:08AM +0800, Zhao Qiang wrote:
> > Add uqe_serial document to
> > Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/uqe_serial.txt
> >
> > Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
> > ---
> > Changes for v2
> > - modify tx/rx-clock-name specification
> >
> >  .../bindings/powerpc/fsl/cpm_qe/uqe_serial.txt| 19
> +++
> >  1 file changed, 19 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/uqe_serial.txt
> >
> > diff --git
> > a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/uqe_serial.txt
> > b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/uqe_serial.txt
> > new file mode 100644
> > index 000..436c71c
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/uqe_serial.
> > +++ txt
> > @@ -0,0 +1,19 @@
> > +* Serial
> > +
> > +Currently defined compatibles:
> > +- ucc_uart
> > +
> > +Properties for ucc_uart:
> > +port-number : port number of UCC-UART
> 
> How is this used?

It used for uart port index.

BR
-Zhao
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RE: [PATCH 3/6] QE: Add uqe_serial document to bindings

[Qiang Zhao]

On Fri, Jan 18, 2016 at 05:10 PM, Li Yang <le...@freescale.com>wrote:
> -Original Message-
> From: pku@gmail.com [mailto:pku@gmail.com] On Behalf Of Li Yang
> Sent: Monday, January 18, 2016 5:10 PM
> To: Qiang Zhao <qiang.z...@nxp.com>
> Cc: devicet...@vger.kernel.org; lkml <linux-ker...@vger.kernel.org>;
> linuxppc-dev <linuxppc-dev@lists.ozlabs.org>; priyanka.j...@freescale.com;
> o...@buserror.net
> Subject: Re: [PATCH 3/6] QE: Add uqe_serial document to bindings
> 
> On Fri, Jan 8, 2016 at 10:18 AM, Zhao Qiang <qiang.z...@nxp.com> wrote:
> > Add uqe_serial document to
> > Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/uqe_serial.txt
> 
> As you have submitted patch to move QE code from arch/powerpc into
> drivers/soc/fsl for the reuse of ARM and powerpc,  you should also move the
> binding documents out of the powerpc folder into a more common place and
> add new bindings in the new location.

Thank you for your recommendation. 
How about create a new directory named qe under 
"Documentation/devicetree/bindings/"? 
Or you have a better suggestion?

Regards 
-Zhao Qiang
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RE: [PATCH 3/6] QE: Add uqe_serial document to bindings

[Qiang Zhao]

On Fri, Jan 19, 2016 at 07:08 PM, Scott Wood <o...@buserror.net> wrote:
> -Original Message-
> From: Scott Wood [mailto:o...@buserror.net]
> Sent: Tuesday, January 19, 2016 7:08 AM
> To: Qiang Zhao <qiang.z...@nxp.com>; Li Yang <le...@freescale.com>
> Cc: devicet...@vger.kernel.org; lkml <linux-ker...@vger.kernel.org>;
> linuxppc-dev <linuxppc-dev@lists.ozlabs.org>; priyanka.j...@freescale.com
> Subject: Re: [PATCH 3/6] QE: Add uqe_serial document to bindings
> 
> On Mon, 2016-01-18 at 09:24 +, Qiang Zhao wrote:
> > On Fri, Jan 18, 2016 at 05:10 PM, Li Yang <le...@freescale.com>wrote:
> > > -Original Message-
> > > From: pku@gmail.com [mailto:pku@gmail.com] On Behalf Of Li
> > > Yang
> > > Sent: Monday, January 18, 2016 5:10 PM
> > > To: Qiang Zhao <qiang.z...@nxp.com>
> > > Cc: devicet...@vger.kernel.org; lkml <linux-ker...@vger.kernel.org>;
> > > linuxppc-dev <linuxppc-dev@lists.ozlabs.org>;
> > > priyanka.j...@freescale.com; o...@buserror.net
> > > Subject: Re: [PATCH 3/6] QE: Add uqe_serial document to bindings
> > >
> > > On Fri, Jan 8, 2016 at 10:18 AM, Zhao Qiang <qiang.z...@nxp.com> wrote:
> > > > Add uqe_serial document to
> > > > Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/uqe_serial.tx
> > > > t
> > >
> > > As you have submitted patch to move QE code from arch/powerpc into
> > > drivers/soc/fsl for the reuse of ARM and powerpc,  you should also
> > > move the binding documents out of the powerpc folder into a more
> > > common place and add new bindings in the new location.
> >
> > Thank you for your recommendation.
> > How about create a new directory named qe under
> > "Documentation/devicetree/bindings/"?
> > Or you have a better suggestion?
> 
> Documentation/devicetree/bindings/soc/fsl/cpm_qe

Thank you very much!

Best Regards
Zhao Qiang
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RE: [PATCH 3/6] QE: Add uqe_serial document to bindings

[Qiang Zhao]

Hi Rob,

Please, is there any update regarding of my question?
Thank you!

Best Regards
Zhao Qiang

> -Original Message-
> From: Qiang Zhao
> Sent: Monday, January 11, 2016 4:19 PM
> To: 'Rob Herring' <r...@kernel.org>
> Cc: devicet...@vger.kernel.org; linux-ker...@vger.kernel.org; linuxppc-
> d...@lists.ozlabs.org; priyanka.j...@freescale.com; o...@buserror.net
> Subject: RE: [PATCH 3/6] QE: Add uqe_serial document to bindings
> 
> On Fri, Jan 09, 2016 at 04:12AM, Rob Herring <r...@kernel.org> wrote:
> > -Original Message-
> > From: Rob Herring [mailto:r...@kernel.org]
> > Sent: Saturday, January 09, 2016 4:12 AM
> > To: Qiang Zhao <qiang.z...@nxp.com>
> > Cc: devicet...@vger.kernel.org; linux-ker...@vger.kernel.org;
> > linuxppc- d...@lists.ozlabs.org; priyanka.j...@freescale.com;
> > o...@buserror.net
> > Subject: Re: [PATCH 3/6] QE: Add uqe_serial document to bindings
> >
> > On Fri, Jan 08, 2016 at 10:18:11AM +0800, Zhao Qiang wrote:
> > > Add uqe_serial document to
> > > Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/uqe_serial.txt
> > >
> > > Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
> > > ---
> > >  .../bindings/powerpc/fsl/cpm_qe/uqe_serial.txt   | 20
> > 
> > >  1 file changed, 20 insertions(+)
> > >  create mode 100644
> > > Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/uqe_serial.txt
> > >
> > > diff --git
> > > a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/uqe_serial.tx
> > > t
> > > b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/uqe_serial.tx
> > > t
> > > new file mode 100644
> > > index 000..e677599
> > > --- /dev/null
> > > +++
> b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/uqe_serial.
> > > +++ txt
> > > @@ -0,0 +1,20 @@
> > > +* Serial
> > > +
> > > +Currently defined compatibles:
> > > +- ucc_uart
> > > +
> > > +Properties for ucc_uart:
> > > +device_type : which type the device is
> >
> > Drop this please.
> 
> Yes, I will drop it in next version.
> 
> >
> > > +port-number : port number of UCC-UART
> >
> > Use aliases instead.
> 
> I don't understand, can you explain more?
> 
> >
> > > +rx-clock-name : which clock QE use for RX tx-clock-name : which
> > > +clock QE use for TX
> >
> > These should use the clock binding.
> 
> This property means which clock source the UCC use, the QE just use this
> property to route UCC clock to clock source.
> The clock source maybe either internal or outside(from clock input pin).
> So clock binding is not apply in this case.
> 
> >
> > > +
> > > +Example:
> > > +
> > > + serial: ucc@2200 {
> > > + device_type = "serial";
> > > + compatible = "ucc_uart";
> > > + port-number = <1>;
> > > + rx-clock-name = "brg2";
> > > + tx-clock-name = "brg2";
> > > + };
> > > --
> > > 2.1.0.27.g96db324
> > >
> > > --
> > > To unsubscribe from this list: send the line "unsubscribe devicetree"
> > > in the body of a message to majord...@vger.kernel.org More
> majordomo
> > > info at  http://vger.kernel.org/majordomo-info.html
> Best Regards
> Zhao Qiang
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RE: [PATCH 3/6] QE: Add uqe_serial document to bindings

[Qiang Zhao]

On Fri, Jan 09, 2016 at 04:12AM, Rob Herring <r...@kernel.org> wrote:
> -Original Message-
> From: Rob Herring [mailto:r...@kernel.org]
> Sent: Saturday, January 09, 2016 4:12 AM
> To: Qiang Zhao <qiang.z...@nxp.com>
> Cc: devicet...@vger.kernel.org; linux-ker...@vger.kernel.org; linuxppc-
> d...@lists.ozlabs.org; priyanka.j...@freescale.com; o...@buserror.net
> Subject: Re: [PATCH 3/6] QE: Add uqe_serial document to bindings
> 
> On Fri, Jan 08, 2016 at 10:18:11AM +0800, Zhao Qiang wrote:
> > Add uqe_serial document to
> > Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/uqe_serial.txt
> >
> > Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
> > ---
> >  .../bindings/powerpc/fsl/cpm_qe/uqe_serial.txt   | 20
> 
> >  1 file changed, 20 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/uqe_serial.txt
> >
> > diff --git
> > a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/uqe_serial.txt
> > b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/uqe_serial.txt
> > new file mode 100644
> > index 000..e677599
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/uqe_serial.
> > +++ txt
> > @@ -0,0 +1,20 @@
> > +* Serial
> > +
> > +Currently defined compatibles:
> > +- ucc_uart
> > +
> > +Properties for ucc_uart:
> > +device_type : which type the device is
> 
> Drop this please.

Yes, I will drop it in next version.

> 
> > +port-number : port number of UCC-UART
> 
> Use aliases instead.

I don't understand, can you explain more?

> 
> > +rx-clock-name : which clock QE use for RX tx-clock-name : which clock
> > +QE use for TX
> 
> These should use the clock binding.

This property means which clock source the UCC use, 
the QE just use this property to route UCC clock to clock source.
The clock source maybe either internal or outside(from clock input pin).
So clock binding is not apply in this case.

> 
> > +
> > +Example:
> > +
> > +   serial: ucc@2200 {
> > +   device_type = "serial";
> > +   compatible = "ucc_uart";
> > +   port-number = <1>;
> > +   rx-clock-name = "brg2";
> > +   tx-clock-name = "brg2";
> > +   };
> > --
> > 2.1.0.27.g96db324
> >
> > --
> > To unsubscribe from this list: send the line "unsubscribe devicetree"
> > in the body of a message to majord...@vger.kernel.org More majordomo
> > info at  http://vger.kernel.org/majordomo-info.html
Best Regards
Zhao Qiang
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