Re: [PATCH 1/2] powerpc: Introduce POWER10_DD1 feature

2020-10-26 Thread Ravi Bangoria
Hi Michael, +static void __init fixup_cpu_features(void) +{ + unsigned long version = mfspr(SPRN_PVR); + + if ((version & 0x) == 0x00800100) + cur_cpu_spec->cpu_features |= CPU_FTR_POWER10_DD1; +} + static int __init early_init_dt_scan_cpus(unsigned long

Re: [PATCH v2 1/2] powerpc: Introduce POWER10_DD1 feature

2020-10-23 Thread Ravi Bangoria
+static void __init fixup_cpu_features(void) +{ + unsigned long version = mfspr(SPRN_PVR); + + if ((version & 0x) == 0x00800100) + cur_cpu_spec->cpu_features |= CPU_FTR_POWER10_DD1; +} + I am just wondering why this is needed here, but the same thing is not

Re: [PATCH v2 1/2] powerpc: Introduce POWER10_DD1 feature

2020-10-21 Thread Ravi Bangoria
On 10/22/20 10:41 AM, Jordan Niethe wrote: On Thu, Oct 22, 2020 at 2:40 PM Ravi Bangoria wrote: POWER10_DD1 feature flag will be needed while adding conditional code that applies only for Power10 DD1. Signed-off-by: Ravi Bangoria --- arch/powerpc/include/asm/cputable.h | 8

[PATCH v2 2/2] powerpc/watchpoint: Workaround P10 DD1 issue with VSX-32 byte instructions

2020-10-21 Thread Ravi Bangoria
+ 64B' generates an address that has a carry into bit 52 (crosses 2K boundary) Handle such spurious exception by considering them as extraneous and emulating/single-steeping instruction without generating an event. Signed-off-by: Ravi Bangoria [Fixed build warning reported by kernel test

[PATCH v2 1/2] powerpc: Introduce POWER10_DD1 feature

2020-10-21 Thread Ravi Bangoria
POWER10_DD1 feature flag will be needed while adding conditional code that applies only for Power10 DD1. Signed-off-by: Ravi Bangoria --- arch/powerpc/include/asm/cputable.h | 8 ++-- arch/powerpc/kernel/dt_cpu_ftrs.c | 3 +++ arch/powerpc/kernel/prom.c | 9 + 3 files

[PATCH 1/2] powerpc: Introduce POWER10_DD1 feature

2020-10-19 Thread Ravi Bangoria
POWER10_DD1 feature flag will be needed while adding conditional code that applies only for Power10 DD1. Signed-off-by: Ravi Bangoria --- arch/powerpc/include/asm/cputable.h | 8 ++-- arch/powerpc/kernel/dt_cpu_ftrs.c | 3 +++ arch/powerpc/kernel/prom.c | 9 + 3 files

[PATCH 2/2] powerpc/watchpoint: Workaround P10 DD1 issue with VSX-32 byte instructions

2020-10-19 Thread Ravi Bangoria
+ 64B' generates an address that has a carry into bit 52 (crosses 2K boundary) Handle such spurious exception by considering them as extraneous and emulating/single-steeping instruction without generating an event. Signed-off-by: Ravi Bangoria --- Dependency: VSX-32 byte emulation support

Re: [PATCH v5 1/5] powerpc/sstep: Emulate prefixed instructions only when CPU_FTR_ARCH_31 is set

2020-10-14 Thread Ravi Bangoria
Hi Daniel, On 10/12/20 7:14 PM, Daniel Axtens wrote: Hi, To review this, I looked through the supported instructions to see if there were any that I thought might have been missed. I didn't find any other v3.1 ones, although I don't have a v3.1 ISA to hand so I was basically looking for

Re: [PATCH v5 1/5] powerpc/sstep: Emulate prefixed instructions only when CPU_FTR_ARCH_31 is set

2020-10-12 Thread Ravi Bangoria
Hi Daniel, On 10/12/20 7:21 AM, Daniel Axtens wrote: Hi, Apologies if this has come up in a previous revision. case 1: + if (!cpu_has_feature(CPU_FTR_ARCH_31)) + return -1; + prefix_r = GET_PREFIX_R(word); ra =

[PATCH v5 5/5] powerpc/sstep: Add testcases for VSX vector paired load/store instructions

2020-10-10 Thread Ravi Bangoria
: PASS emulate_step_test: pstxvp : PASS Signed-off-by: Balamuruhan S Signed-off-by: Ravi Bangoria --- arch/powerpc/lib/test_emulate_step.c | 270 +++ 1 file changed, 270 insertions(+) diff --git a/arch/powerpc/lib/test_emulate_step.c b/arch/powerpc/lib

[PATCH v5 4/5] powerpc/ppc-opcode: Add encoding macros for VSX vector paired instructions

2020-10-10 Thread Ravi Bangoria
) * Store VSX Vector Paired Indexed (stxvpx) * Prefixed Store VSX Vector Paired (pstxvp) Suggested-by: Naveen N. Rao Signed-off-by: Balamuruhan S Signed-off-by: Ravi Bangoria --- arch/powerpc/include/asm/ppc-opcode.h | 13 + 1 file changed, 13 insertions(+) diff --git a/arch

[PATCH v5 3/5] powerpc/sstep: Support VSX vector paired storage access instructions

2020-10-10 Thread Ravi Bangoria
(plxvp) * Store VSX Vector Paired (stxvp) * Store VSX Vector Paired Indexed (stxvpx) * Prefixed Store VSX Vector Paired (pstxvp) Suggested-by: Naveen N. Rao Signed-off-by: Balamuruhan S Signed-off-by: Ravi Bangoria [kernel test robot reported a build failure] Reported-by: kernel test robot

[PATCH v5 2/5] powerpc/sstep: Cover new VSX instructions under CONFIG_VSX

2020-10-10 Thread Ravi Bangoria
fixed load/stores") Signed-off-by: Ravi Bangoria --- arch/powerpc/lib/sstep.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c index e6242744c71b..faf0bbf3efb7 100644 --- a/arch/powerpc/lib/sstep.c +++ b/arch/powerpc/l

[PATCH v5 1/5] powerpc/sstep: Emulate prefixed instructions only when CPU_FTR_ARCH_31 is set

2020-10-10 Thread Ravi Bangoria
erpc sstep: Add support for prefixed load/stores") Signed-off-by: Balamuruhan S Signed-off-by: Ravi Bangoria --- arch/powerpc/lib/sstep.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c index e9dcaba9a4f8..e6242744c71b 100644 --

[PATCH v5 0/5] powerpc/sstep: VSX 32-byte vector paired load/store instructions

2020-10-10 Thread Ravi Bangoria
: Add testcases for VSX vector paired load/store instructions Ravi Bangoria (1): powerpc/sstep: Cover new VSX instructions under CONFIG_VSX arch/powerpc/include/asm/ppc-opcode.h | 13 ++ arch/powerpc/lib/sstep.c | 160 --- arch/powerpc/lib/test_emulate_step.c

[PATCH v4 4/4] powerpc/sstep: Add testcases for VSX vector paired load/store instructions

2020-10-08 Thread Ravi Bangoria
: PASS emulate_step_test: pstxvp : PASS Signed-off-by: Balamuruhan S Signed-off-by: Ravi Bangoria --- arch/powerpc/lib/test_emulate_step.c | 270 +++ 1 file changed, 270 insertions(+) diff --git a/arch/powerpc/lib/test_emulate_step.c b/arch/powerpc/lib

[PATCH v4 3/4] powerpc/ppc-opcode: Add encoding macros for VSX vector paired instructions

2020-10-08 Thread Ravi Bangoria
) * Store VSX Vector Paired Indexed (stxvpx) * Prefixed Store VSX Vector Paired (pstxvp) Suggested-by: Naveen N. Rao Signed-off-by: Balamuruhan S Signed-off-by: Ravi Bangoria --- arch/powerpc/include/asm/ppc-opcode.h | 13 + 1 file changed, 13 insertions(+) diff --git a/arch

[PATCH v4 2/4] powerpc/sstep: Support VSX vector paired storage access instructions

2020-10-08 Thread Ravi Bangoria
(plxvp) * Store VSX Vector Paired (stxvp) * Store VSX Vector Paired Indexed (stxvpx) * Prefixed Store VSX Vector Paired (pstxvp) Suggested-by: Naveen N. Rao Signed-off-by: Balamuruhan S Signed-off-by: Ravi Bangoria --- arch/powerpc/lib/sstep.c | 146 +-- 1

[PATCH v4 0/4] powerpc/sstep: VSX 32-byte vector paired load/store instructions

2020-10-08 Thread Ravi Bangoria
VSX vector paired instructions operates with octword (32-byte) operand for loads and stores between storage and a pair of two sequential Vector-Scalar Registers (VSRs). There are 4 word instructions and 2 prefixed instructions that provides this 32-byte storage access operations - lxvp, lxvpx,

[PATCH v4 1/4] powerpc/sstep: Emulate prefixed instructions only when CPU_FTR_ARCH_31 is set

2020-10-08 Thread Ravi Bangoria
From: Balamuruhan S Unconditional emulation of prefixed instructions will allow emulation of them on Power10 predecessors which might cause issues. Restrict that. Signed-off-by: Balamuruhan S Signed-off-by: Ravi Bangoria --- arch/powerpc/lib/sstep.c | 6 ++ 1 file changed, 6 insertions

Re: [PATCH v6 0/8] powerpc/watchpoint: Bug fixes plus new feature flag

2020-09-18 Thread Ravi Bangoria
On 9/17/20 6:54 PM, Rogerio Alves wrote: On 9/2/20 1:29 AM, Ravi Bangoria wrote: Patch #1 fixes issue for quardword instruction on p10 predecessors. Patch #2 fixes issue for vector instructions. Patch #3 fixes a bug about watchpoint not firing when created with   ptrace

Re: [PATCH 0/7] powerpc/watchpoint: 2nd DAWR kvm enablement + selftests

2020-09-01 Thread Ravi Bangoria
Hi Paul, On 9/2/20 8:02 AM, Paul Mackerras wrote: On Thu, Jul 23, 2020 at 03:50:51PM +0530, Ravi Bangoria wrote: Patch #1, #2 and #3 enables p10 2nd DAWR feature for Book3S kvm guest. DAWR is a hypervisor resource and thus H_SET_MODE hcall is used to set/unset it. A new case

Re: [PATCH 2/7] powerpc/watchpoint/kvm: Add infrastructure to support 2nd DAWR

2020-09-01 Thread Ravi Bangoria
Hi Paul, diff --git a/arch/powerpc/include/asm/hvcall.h b/arch/powerpc/include/asm/hvcall.h index 33793444144c..03f401d7be41 100644 --- a/arch/powerpc/include/asm/hvcall.h +++ b/arch/powerpc/include/asm/hvcall.h @@ -538,6 +538,8 @@ struct hv_guest_state { s64 tb_offset; u64

Re: [PATCH 1/7] powerpc/watchpoint/kvm: Rename current DAWR macros and variables

2020-09-01 Thread Ravi Bangoria
Hi Paul, On 9/2/20 7:19 AM, Paul Mackerras wrote: On Thu, Jul 23, 2020 at 03:50:52PM +0530, Ravi Bangoria wrote: Power10 is introducing second DAWR. Use real register names (with suffix 0) from ISA for current macros and variables used by kvm. Most of this looks fine, but I think we should

Re: [PATCH 2/7] powerpc/watchpoint/kvm: Add infrastructure to support 2nd DAWR

2020-09-01 Thread Ravi Bangoria
Hi Paul, On 9/2/20 7:31 AM, Paul Mackerras wrote: On Thu, Jul 23, 2020 at 03:50:53PM +0530, Ravi Bangoria wrote: kvm code assumes single DAWR everywhere. Add code to support 2nd DAWR. DAWR is a hypervisor resource and thus H_SET_MODE hcall is used to set/ unset it. Introduce new case

[PATCH v6 8/8] powerpc/watchpoint/selftests: Tests for kernel accessing user memory

2020-09-01 Thread Ravi Bangoria
, Kernel Access Userspace, len: 1: Ok success: ptrace-hwbreak Suggested-by: Pedro Miraglia Franco de Carvalho Signed-off-by: Ravi Bangoria --- .../selftests/powerpc/ptrace/ptrace-hwbreak.c | 48 ++- 1 file changed, 46 insertions(+), 2 deletions(-) diff --git a/tools/testing

[PATCH v6 7/8] powerpc/watchpoint/ptrace: Introduce PPC_DEBUG_FEATURE_DATA_BP_ARCH_31

2020-09-01 Thread Ravi Bangoria
that availability of 2nd DAWR is independent of this flag and should be checked using ppc_debug_info->num_data_bps. Signed-off-by: Ravi Bangoria --- Documentation/powerpc/ptrace.rst | 1 + arch/powerpc/include/uapi/asm/ptrace.h| 1 + arch/powerpc/kernel/ptrace/ptrace-noadv.c | 2 ++ 3 fi

[PATCH v6 6/8] powerpc/watchpoint: Add hw_len wherever missing

2020-09-01 Thread Ravi Bangoria
, hw_len needs to be set directly. Fixes: b57aeab811db ("powerpc/watchpoint: Fix length calculation for unaligned target") Signed-off-by: Ravi Bangoria --- arch/powerpc/kernel/ptrace/ptrace-noadv.c | 1 + arch/powerpc/xmon/xmon.c | 1 + 2 files changed, 2 insertions(+)

[PATCH v6 5/8] powerpc/watchpoint: Fix exception handling for CONFIG_HAVE_HW_BREAKPOINT=N

2020-09-01 Thread Ravi Bangoria
dware breakpoints rewrite to handle non DABR breakpoint registers") Reported-by: Pedro Miraglia Franco de Carvalho Signed-off-by: Ravi Bangoria --- arch/powerpc/include/asm/hw_breakpoint.h | 3 ++ arch/powerpc/kernel/process.c | 48 +++ arch/powerpc/kernel/ptr

[PATCH v6 4/8] powerpc/watchpoint: Move DAWR detection logic outside of hw_breakpoint.c

2020-09-01 Thread Ravi Bangoria
CONFIG_HAVE_HW_BREAKPOINT is not set. Signed-off-by: Ravi Bangoria --- arch/powerpc/include/asm/hw_breakpoint.h | 8 + arch/powerpc/kernel/Makefile | 3 +- arch/powerpc/kernel/hw_breakpoint.c | 159 + .../kernel/hw_breakpoint_constraints.c

[PATCH v6 3/8] powerpc/watchpoint/ptrace: Fix SETHWDEBUG when CONFIG_HAVE_HW_BREAKPOINT=N

2020-09-01 Thread Ravi Bangoria
really leak any kernel address in signal info. Setting HW_BRK_TYPE_PRIV_ALL will also help to find scenarios when kernel accesses user memory. Reported-by: Pedro Miraglia Franco de Carvalho Suggested-by: Pedro Miraglia Franco de Carvalho Signed-off-by: Ravi Bangoria --- arch/powerpc/kernel

[PATCH v6 2/8] powerpc/watchpoint: Fix handling of vector instructions

2020-09-01 Thread Ravi Bangoria
one watchpoint") Signed-off-by: Ravi Bangoria --- arch/powerpc/kernel/hw_breakpoint.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/powerpc/kernel/hw_breakpoint.c b/arch/powerpc/kernel/hw_breakpoint.c index 9f7df1c37233..f6b24838ca3c 100644 --- a/arch/powerpc/kernel/hw_breakpoi

[PATCH v6 1/8] powerpc/watchpoint: Fix quarword instruction handling on p10 predecessors

2020-09-01 Thread Ravi Bangoria
it as extraneous and emulate/single-step it before continuing. Reported-by: Pedro Miraglia Franco de Carvalho Fixes: 74c6881019b7 ("powerpc/watchpoint: Prepare handler to handle more than one watchpoint") Signed-off-by: Ravi Bangoria --- arch/powerpc/include/asm/hw_breakpoint.h | 1 + ar

[PATCH v6 0/8] powerpc/watchpoint: Bug fixes plus new feature flag

2020-09-01 Thread Ravi Bangoria
act if condition, suggested by Christophe Ravi Bangoria (8): powerpc/watchpoint: Fix quarword instruction handling on p10 predecessors powerpc/watchpoint: Fix handling of vector instructions powerpc/watchpoint/ptrace: Fix SETHWDEBUG when CONFIG_HAVE_HW_BREAKPOINT=N powerpc/watchpoint: Move D

Re: [PATCH v5 4/8] powerpc/watchpoint: Move DAWR detection logic outside of hw_breakpoint.c

2020-08-25 Thread Ravi Bangoria
Hi Christophe, +static int cache_op_size(void) +{ +#ifdef __powerpc64__ +    return ppc64_caches.l1d.block_size; +#else +    return L1_CACHE_BYTES; +#endif +} You've got l1_dcache_bytes() in arch/powerpc/include/asm/cache.h to do that. + +void wp_get_instr_detail(struct pt_regs *regs,

Re: [PATCH v5 5/8] powerpc/watchpoint: Fix exception handling for CONFIG_HAVE_HW_BREAKPOINT=N

2020-08-25 Thread Ravi Bangoria
Hi Christophe, diff --git a/arch/powerpc/kernel/ptrace/ptrace-noadv.c b/arch/powerpc/kernel/ptrace/ptrace-noadv.c index 57a0ab822334..866597b407bc 100644 --- a/arch/powerpc/kernel/ptrace/ptrace-noadv.c +++ b/arch/powerpc/kernel/ptrace/ptrace-noadv.c @@ -286,11 +286,16 @@ long

[PATCH v5 5/8] powerpc/watchpoint: Fix exception handling for CONFIG_HAVE_HW_BREAKPOINT=N

2020-08-24 Thread Ravi Bangoria
dware breakpoints rewrite to handle non DABR breakpoint registers") Reported-by: Pedro Miraglia Franco de Carvalho Signed-off-by: Ravi Bangoria --- arch/powerpc/include/asm/hw_breakpoint.h | 3 ++ arch/powerpc/kernel/process.c | 48 +++ arch/powerpc/kernel/ptr

[PATCH v5 8/8] powerpc/watchpoint/selftests: Tests for kernel accessing user memory

2020-08-24 Thread Ravi Bangoria
, Kernel Access Userspace, len: 1: Ok success: ptrace-hwbreak Suggested-by: Pedro Miraglia Franco de Carvalho Signed-off-by: Ravi Bangoria --- .../selftests/powerpc/ptrace/ptrace-hwbreak.c | 48 ++- 1 file changed, 46 insertions(+), 2 deletions(-) diff --git a/tools/testing

[PATCH v5 7/8] powerpc/watchpoint/ptrace: Introduce PPC_DEBUG_FEATURE_DATA_BP_ARCH_31

2020-08-24 Thread Ravi Bangoria
that availability of 2nd DAWR is independent of this flag and should be checked using ppc_debug_info->num_data_bps. Signed-off-by: Ravi Bangoria --- Documentation/powerpc/ptrace.rst | 1 + arch/powerpc/include/uapi/asm/ptrace.h| 1 + arch/powerpc/kernel/ptrace/ptrace-noadv.c | 2 ++ 3 fi

[PATCH v5 6/8] powerpc/watchpoint: Add hw_len wherever missing

2020-08-24 Thread Ravi Bangoria
, hw_len needs to be set directly. Fixes: b57aeab811db ("powerpc/watchpoint: Fix length calculation for unaligned target") Signed-off-by: Ravi Bangoria --- arch/powerpc/kernel/ptrace/ptrace-noadv.c | 1 + arch/powerpc/xmon/xmon.c | 1 + 2 files changed, 2 insertions(+)

[PATCH v5 4/8] powerpc/watchpoint: Move DAWR detection logic outside of hw_breakpoint.c

2020-08-24 Thread Ravi Bangoria
CONFIG_HAVE_HW_BREAKPOINT is not set. Signed-off-by: Ravi Bangoria --- arch/powerpc/include/asm/hw_breakpoint.h | 8 + arch/powerpc/kernel/Makefile | 3 +- arch/powerpc/kernel/hw_breakpoint.c | 159 + .../kernel/hw_breakpoint_constraints.c

[PATCH v5 3/8] powerpc/watchpoint/ptrace: Fix SETHWDEBUG when CONFIG_HAVE_HW_BREAKPOINT=N

2020-08-24 Thread Ravi Bangoria
really leak any kernel address in signal info. Setting HW_BRK_TYPE_PRIV_ALL will also help to find scenarios when kernel corrupts user memory. Reported-by: Pedro Miraglia Franco de Carvalho Suggested-by: Pedro Miraglia Franco de Carvalho Signed-off-by: Ravi Bangoria --- arch/powerpc/kernel

[PATCH v5 2/8] powerpc/watchpoint: Fix handling of vector instructions

2020-08-24 Thread Ravi Bangoria
point") Signed-off-by: Ravi Bangoria --- arch/powerpc/kernel/hw_breakpoint.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/powerpc/kernel/hw_breakpoint.c b/arch/powerpc/kernel/hw_breakpoint.c index 9f7df1c37233..f6b24838ca3c 100644 --- a/arch/powerpc/kernel/hw_breakpoint.c +++ b/ar

[PATCH v5 1/8] powerpc/watchpoint: Fix quarword instruction handling on p10 predecessors

2020-08-24 Thread Ravi Bangoria
it as extraneous and emulate/single-step it before continuing. Reported-by: Pedro Miraglia Franco de Carvalho Fixes: 74c6881019b7 ("powerpc/watchpoint: Prepare handler to handle more than one watchpoint") Signed-off-by: Ravi Bangoria --- arch/powerpc/include/asm/hw_breakpoint.h | 3

[PATCH v5 0/8] powerpc/watchpoint: Bug fixes plus new feature flag

2020-08-24 Thread Ravi Bangoria
INT. - Patch #3 to #8 are carry forwarded from v4 - Rebased to powerpc/next Ravi Bangoria (8): powerpc/watchpoint: Fix quarword instruction handling on p10 predecessors powerpc/watchpoint: Fix handling of vector instructions powerpc/watchpoint/ptrace: Fix SETHWDEBUG w

[PATCH v4 6/6] powerpc/watchpoint/selftests: Tests for kernel accessing user memory

2020-08-17 Thread Ravi Bangoria
, Kernel Access Userspace, len: 1: Ok success: ptrace-hwbreak Suggested-by: Pedro Miraglia Franco de Carvalho Signed-off-by: Ravi Bangoria --- .../selftests/powerpc/ptrace/ptrace-hwbreak.c | 48 ++- 1 file changed, 46 insertions(+), 2 deletions(-) diff --git a/tools/testing

[PATCH v4 5/6] powerpc/watchpoint/ptrace: Introduce PPC_DEBUG_FEATURE_DATA_BP_ARCH_31

2020-08-17 Thread Ravi Bangoria
that availability of 2nd DAWR is independent of this flag and should be checked using ppc_debug_info->num_data_bps. Signed-off-by: Ravi Bangoria --- Documentation/powerpc/ptrace.rst | 1 + arch/powerpc/include/uapi/asm/ptrace.h| 1 + arch/powerpc/kernel/ptrace/ptrace-noadv.c | 2 ++ 3 fi

[PATCH v4 4/6] powerpc/watchpoint: Add hw_len wherever missing

2020-08-17 Thread Ravi Bangoria
, hw_len needs to be set directly. Fixes: b57aeab811db ("powerpc/watchpoint: Fix length calculation for unaligned target") Signed-off-by: Ravi Bangoria --- arch/powerpc/kernel/ptrace/ptrace-noadv.c | 1 + arch/powerpc/xmon/xmon.c | 1 + 2 files changed, 2 insertions(+)

[PATCH v4 3/6] powerpc/watchpoint: Fix exception handling for CONFIG_HAVE_HW_BREAKPOINT=N

2020-08-17 Thread Ravi Bangoria
dware breakpoints rewrite to handle non DABR breakpoint registers") Reported-by: Pedro Miraglia Franco de Carvalho Signed-off-by: Ravi Bangoria --- arch/powerpc/include/asm/hw_breakpoint.h | 3 ++ arch/powerpc/kernel/process.c | 48 +++ arch/powerpc/kernel/ptr

[PATCH v4 1/6] powerpc/watchpoint/ptrace: Fix SETHWDEBUG when CONFIG_HAVE_HW_BREAKPOINT=N

2020-08-17 Thread Ravi Bangoria
really leak any kernel address in signal info. Setting HW_BRK_TYPE_PRIV_ALL will also help to find scenarios when kernel corrupts user memory. Reported-by: Pedro Miraglia Franco de Carvalho Suggested-by: Pedro Miraglia Franco de Carvalho Signed-off-by: Ravi Bangoria --- arch/powerpc/kernel

[PATCH v4 2/6] powerpc/watchpoint: Move DAWR detection logic outside of hw_breakpoint.c

2020-08-17 Thread Ravi Bangoria
CONFIG_HAVE_HW_BREAKPOINT is not set. Signed-off-by: Ravi Bangoria --- arch/powerpc/include/asm/hw_breakpoint.h | 8 + arch/powerpc/kernel/Makefile | 3 +- arch/powerpc/kernel/hw_breakpoint.c | 149 + .../kernel/hw_breakpoint_constraints.c

[PATCH v4 0/6] powerpc/watchpoint: Bug fixes plus new feature flag

2020-08-17 Thread Ravi Bangoria
. v3: https://lore.kernel.org/r/20200805062750.290289-1-ravi.bango...@linux.ibm.com v3->v4: - Patch #1. Allow HW_BRK_TYPE_PRIV_ALL instead of HW_BRK_TYPE_USER - Patch #2, #3, #4 and #6 are new. - Rebased to powerpc/next. Ravi Bangoria (6): powerpc/watchpoint/ptrace: Fix SETHWDEBUG w

[PATCH v3 2/2] powerpc/watchpoint/ptrace: Introduce PPC_DEBUG_FEATURE_DATA_BP_ARCH_31

2020-08-05 Thread Ravi Bangoria
that availability of 2nd DAWR is independent of this flag and should be checked using ppc_debug_info->num_data_bps. Signed-off-by: Ravi Bangoria --- Documentation/powerpc/ptrace.rst | 1 + arch/powerpc/include/uapi/asm/ptrace.h| 1 + arch/powerpc/kernel/ptrace/ptrace-noadv.c | 2 ++ 3 fi

[PATCH v3 1/2] powerpc/watchpoint/ptrace: Fix SETHWDEBUG when CONFIG_HAVE_HW_BREAKPOINT=N

2020-08-05 Thread Ravi Bangoria
Suggested-by: Pedro Miraglia Franco de Carvalho Signed-off-by: Ravi Bangoria --- arch/powerpc/kernel/ptrace/ptrace-noadv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/kernel/ptrace/ptrace-noadv.c b/arch/powerpc/kernel/ptrace/ptrace-noadv.c index 697c7e4b5877

[PATCH v3 0/2] powerpc/watchpoint/ptrace: Buf fix plus new feature flag

2020-08-05 Thread Ravi Bangoria
-1-ravi.bango...@linux.ibm.com v2->v3: - #1: is new - #2: Set PPC_DEBUG_FEATURE_DATA_BP_ARCH_31 unconditionally while running on p10. - Rebased to powerpc/next (cf1ae052e073) Ravi Bangoria (2): powerpc/watchpoint/ptrace: Fix SETHWDEBUG when CONFIG_HAVE_HW_BREAKPOINT=N powe

Re: [PATCH V4 0/4] powerpc/perf: Add support for perf extended regs in powerpc

2020-07-27 Thread Ravi Bangoria
and 4/4 adds extended regs to sample_reg_mask in the tool side to use with `-I?` option for power9 and power10 respectively. Ravi bangoria found an issue with `perf record -I` while testing the changes. The same issue is currently being worked on here: https://lkml.org/lkml/2020/7/19/413

Re: [PATCH V4 1/4] powerpc/perf: Add support for outputting extended regs in perf intr_regs

2020-07-27 Thread Ravi Bangoria
Hi Athira, +/* Function to return the extended register values */ +static u64 get_ext_regs_value(int idx) +{ + switch (idx) { + case PERF_REG_POWERPC_MMCR0: + return mfspr(SPRN_MMCR0); + case PERF_REG_POWERPC_MMCR1: + return mfspr(SPRN_MMCR1); +

Re: [v3 12/15] powerpc/perf: Add support for outputting extended regs in perf intr_regs

2020-07-24 Thread Ravi Bangoria
Hi Athira, +/* Function to return the extended register values */ +static u64 get_ext_regs_value(int idx) +{ + switch (idx) { + case PERF_REG_POWERPC_MMCR0: + return mfspr(SPRN_MMCR0); + case PERF_REG_POWERPC_MMCR1: + return mfspr(SPRN_MMCR1); +

Re: [v3 13/15] tools/perf: Add perf tools support for extended register capability in powerpc

2020-07-24 Thread Ravi Bangoria
Hi Athira, On 7/17/20 8:08 PM, Athira Rajeev wrote: From: Anju T Sudhakar Add extended regs to sample_reg_mask in the tool side to use with `-I?` option. Perf tools side uses extended mask to display the platform supported register names (with -I? option) to the user and also send this mask

Re: [PATCH 0/7] powerpc/watchpoint: 2nd DAWR kvm enablement + selftests

2020-07-23 Thread Ravi Bangoria
On 7/23/20 3:50 PM, Ravi Bangoria wrote: Patch #1, #2 and #3 enables p10 2nd DAWR feature for Book3S kvm guest. DAWR is a hypervisor resource and thus H_SET_MODE hcall is used to set/unset it. A new case H_SET_MODE_RESOURCE_SET_DAWR1 is introduced in H_SET_MODE hcall for setting/unsetting 2nd

[PATCH 7/7] powerpc/selftests: Add selftest to test concurrent perf/ptrace events

2020-07-23 Thread Ravi Bangoria
erlapping): Ok ptrace thread event -> perf other thread & cpu event: Ok success: ptrace-perf-hwbreak Signed-off-by: Ravi Bangoria --- .../selftests/powerpc/ptrace/.gitignore | 1 + .../testing/selftests/powerpc/ptrace/Makefile | 2 +- .../powerpc/ptrace/ptrace-perf-hwbreak.

[PATCH 6/7] powerpc/selftests/perf-hwbreak: Add testcases for 2nd DAWR

2020-07-23 Thread Ravi Bangoria
, one is RO, other is WO TESTED: Process specific, 512 bytes, unaligned success: perf_hwbreak Signed-off-by: Ravi Bangoria --- .../selftests/powerpc/ptrace/perf-hwbreak.c | 568 +- 1 file changed, 567 insertions(+), 1 deletion(-) diff --git a/tools/testing/selftests/powerpc

[PATCH 5/7] powerpc/selftests/perf-hwbreak: Coalesce event creation code

2020-07-23 Thread Ravi Bangoria
perf-hwbreak selftest opens hw-breakpoint event at multiple places for which it has same code repeated. Coalesce that code into a function. Signed-off-by: Ravi Bangoria --- .../selftests/powerpc/ptrace/perf-hwbreak.c | 78 +-- 1 file changed, 38 insertions(+), 40 deletions

[PATCH 4/7] powerpc/selftests/ptrace-hwbreak: Add testcases for 2nd DAWR

2020-07-23 Thread Ravi Bangoria
, len: 6: Ok PPC_PTRACE_SETHWDEBUG 2, MODE_RANGE, DAWR Overlap, RO, len: 6: Ok Signed-off-by: Ravi Bangoria --- .../selftests/powerpc/ptrace/ptrace-hwbreak.c | 79 +++ 1 file changed, 79 insertions(+) diff --git a/tools/testing/selftests/powerpc/ptrace/ptrace-hwbreak.c b/tools

[PATCH 1/7] powerpc/watchpoint/kvm: Rename current DAWR macros and variables

2020-07-23 Thread Ravi Bangoria
Power10 is introducing second DAWR. Use real register names (with suffix 0) from ISA for current macros and variables used by kvm. Signed-off-by: Ravi Bangoria --- Documentation/virt/kvm/api.rst| 4 +-- arch/powerpc/include/asm/kvm_host.h | 4 +-- arch/powerpc/include/uapi

[PATCH 3/7] powerpc/watchpoint/kvm: Introduce new capability for 2nd DAWR

2020-07-23 Thread Ravi Bangoria
Introduce KVM_CAP_PPC_DAWR1 which can be used by Qemu to query whether kvm supports 2nd DAWR or not. Signed-off-by: Ravi Bangoria --- arch/powerpc/kvm/powerpc.c | 3 +++ include/uapi/linux/kvm.h | 1 + 2 files changed, 4 insertions(+) diff --git a/arch/powerpc/kvm/powerpc.c b/arch/powerpc

[PATCH 2/7] powerpc/watchpoint/kvm: Add infrastructure to support 2nd DAWR

2020-07-23 Thread Ravi Bangoria
kvm code assumes single DAWR everywhere. Add code to support 2nd DAWR. DAWR is a hypervisor resource and thus H_SET_MODE hcall is used to set/ unset it. Introduce new case H_SET_MODE_RESOURCE_SET_DAWR1 for 2nd DAWR. Also, kvm will support 2nd DAWR only if CPU_FTR_DAWR1 is set. Signed-off-by: Ravi

[PATCH 0/7] powerpc/watchpoint: 2nd DAWR kvm enablement + selftests

2020-07-23 Thread Ravi Bangoria
://lore.kernel.org/linuxppc-dev/20200723093330.306341-1-ravi.bango...@linux.ibm.com Patches in this series applies fine on top of powerpc/next (9a77c4a0a125) plus above dependency patches. Ravi Bangoria (7): powerpc/watchpoint/kvm: Rename current DAWR macros and variables powerpc/watchpoint/kvm: Add

[PATCH v2] powerpc/watchpoint/ptrace: Introduce PPC_DEBUG_FEATURE_DATA_BP_DAWR_ARCH_31

2020-07-23 Thread Ravi Bangoria
that availability of 2nd DAWR is independent of this flag and should be checked using ppc_debug_info->num_data_bps. Signed-off-by: Ravi Bangoria --- v1->v2: - Mention new flag in Documentaion/ as well. Documentation/powerpc/ptrace.rst | 1 + arch/powerpc/include/uapi/asm/ptrace.h

[PATCH v5 10/10] powerpc/watchpoint: Remove 512 byte boundary

2020-07-23 Thread Ravi Bangoria
mentions about removal of 512B boundary: Multiple DEAW: Added a second Data Address Watchpoint. [H]DAR is set to the first byte of overlap. 512B boundary is removed. Signed-off-by: Ravi Bangoria --- arch/powerpc/kernel/hw_breakpoint.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions

[PATCH v5 09/10] powerpc/watchpoint: Return available watchpoints dynamically

2020-07-23 Thread Ravi Bangoria
So far Book3S Powerpc supported only one watchpoint. Power10 is introducing 2nd DAWR. Enable 2nd DAWR support for Power10. Availability of 2nd DAWR will depend on CPU_FTR_DAWR1. Signed-off-by: Ravi Bangoria --- arch/powerpc/include/asm/cputable.h | 5 +++-- arch/powerpc/include/asm

[PATCH v5 08/10] powerpc/watchpoint: Guest support for 2nd DAWR hcall

2020-07-23 Thread Ravi Bangoria
2nd DAWR can be set/unset using H_SET_MODE hcall with resource value 5. Enable powervm guest support with that. This has no effect on kvm guest because kvm will return error if guest does hcall with resource value 5. Signed-off-by: Ravi Bangoria --- arch/powerpc/include/asm/hvcall.h | 1

[PATCH v5 07/10] powerpc/watchpoint: Rename current H_SET_MODE DAWR macro

2020-07-23 Thread Ravi Bangoria
Current H_SET_MODE hcall macro name for setting/resetting DAWR0 is H_SET_MODE_RESOURCE_SET_DAWR. Add suffix 0 to macro name as well. Signed-off-by: Ravi Bangoria Reviewed-by: Jordan Niethe --- arch/powerpc/include/asm/hvcall.h | 2 +- arch/powerpc/include/asm/plpar_wrappers.h | 2

[PATCH v5 06/10] powerpc/watchpoint: Set CPU_FTR_DAWR1 based on pa-features bit

2020-07-23 Thread Ravi Bangoria
or guests and thus this change is mostly applicable for guests only. Signed-off-by: Ravi Bangoria Tested-by: Jordan Niethe --- arch/powerpc/kernel/prom.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c index 033d43819ed8..01dda206

[PATCH v5 05/10] powerpc/dt_cpu_ftrs: Add feature for 2nd DAWR

2020-07-23 Thread Ravi Bangoria
Add new device-tree feature for 2nd DAWR. If this feature is present, 2nd DAWR is supported, otherwise not. Signed-off-by: Ravi Bangoria --- arch/powerpc/include/asm/cputable.h | 3 ++- arch/powerpc/kernel/dt_cpu_ftrs.c | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch

[PATCH v5 04/10] powerpc/watchpoint: Enable watchpoint functionality on power10 guest

2020-07-23 Thread Ravi Bangoria
CPU_FTR_DAWR to CPU_FTRS_POWER10. Note that this change does not enable 2nd DAWR support. Signed-off-by: Ravi Bangoria Tested-by: Jordan Niethe --- arch/powerpc/include/asm/cputable.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/cputable.h b/arch

[PATCH v5 03/10] powerpc/watchpoint: Fix DAWR exception for CACHEOP

2020-07-23 Thread Ravi Bangoria
ot;) Fixes: 74c6881019b7 ("powerpc/watchpoint: Prepare handler to handle more than one watchpoint") Signed-off-by: Ravi Bangoria --- arch/powerpc/kernel/hw_breakpoint.c | 21 - 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/kernel/hw_breakpoi

[PATCH v5 02/10] powerpc/watchpoint: Fix DAWR exception constraint

2020-07-23 Thread Ravi Bangoria
Franco de Carvalho Signed-off-by: Ravi Bangoria --- arch/powerpc/kernel/hw_breakpoint.c | 72 - 1 file changed, 41 insertions(+), 31 deletions(-) diff --git a/arch/powerpc/kernel/hw_breakpoint.c b/arch/powerpc/kernel/hw_breakpoint.c index 031e6defc08e..a971e22aea81 10

[PATCH v5 01/10] powerpc/watchpoint: Fix 512 byte boundary limit

2020-07-23 Thread Ravi Bangoria
: Use builtin ALIGN*() macros") Reported-by: Milton Miller Signed-off-by: Ravi Bangoria Tested-by: Jordan Niethe --- arch/powerpc/kernel/hw_breakpoint.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/kernel/hw_breakpoint.c b/arch/powerpc/kernel/hw_breakpoi

[PATCH v5 00/10] powerpc/watchpoint: Enable 2nd DAWR on baremetal and powervm

2020-07-23 Thread Ravi Bangoria
com/ Ravi Bangoria (10): powerpc/watchpoint: Fix 512 byte boundary limit powerpc/watchpoint: Fix DAWR exception constraint powerpc/watchpoint: Fix DAWR exception for CACHEOP powerpc/watchpoint: Enable watchpoint functionality on power10 guest powerpc/dt_cpu_ftrs: Add feature for 2nd D

Re: [PATCH v4 05/10] powerpc/dt_cpu_ftrs: Add feature for 2nd DAWR

2020-07-21 Thread Ravi Bangoria
On 7/21/20 7:37 PM, Michael Ellerman wrote: Ravi Bangoria writes: On 7/21/20 4:59 PM, Michael Ellerman wrote: Ravi Bangoria writes: On 7/17/20 11:14 AM, Jordan Niethe wrote: On Fri, Jul 17, 2020 at 2:10 PM Ravi Bangoria wrote: Add new device-tree feature for 2nd DAWR. If this feature

Re: [PATCH v4 05/10] powerpc/dt_cpu_ftrs: Add feature for 2nd DAWR

2020-07-21 Thread Ravi Bangoria
On 7/21/20 4:59 PM, Michael Ellerman wrote: Ravi Bangoria writes: On 7/17/20 11:14 AM, Jordan Niethe wrote: On Fri, Jul 17, 2020 at 2:10 PM Ravi Bangoria wrote: Add new device-tree feature for 2nd DAWR. If this feature is present, 2nd DAWR is supported, otherwise not. Signed-off

Re: [PATCH v4 09/10] powerpc/watchpoint: Return available watchpoints dynamically

2020-07-21 Thread Ravi Bangoria
On 7/21/20 5:06 PM, Michael Ellerman wrote: Ravi Bangoria writes: On 7/20/20 9:12 AM, Jordan Niethe wrote: On Fri, Jul 17, 2020 at 2:11 PM Ravi Bangoria wrote: So far Book3S Powerpc supported only one watchpoint. Power10 is introducing 2nd DAWR. Enable 2nd DAWR support for Power10

Re: [PATCH v4 09/10] powerpc/watchpoint: Return available watchpoints dynamically

2020-07-21 Thread Ravi Bangoria
@@ -46,7 +47,7 @@ struct arch_hw_breakpoint { static inline int nr_wp_slots(void) { - return HBP_NUM_MAX; + return cpu_has_feature(CPU_FTR_DAWR1) ? HBP_NUM_TWO : HBP_NUM_ONE; So it'd be something like: + return cpu_has_feature(CPU_FTR_DAWR1) ? HBP_NUM_MAX : 1; But

Re: [PATCH v4 05/10] powerpc/dt_cpu_ftrs: Add feature for 2nd DAWR

2020-07-21 Thread Ravi Bangoria
On 7/17/20 11:14 AM, Jordan Niethe wrote: On Fri, Jul 17, 2020 at 2:10 PM Ravi Bangoria wrote: Add new device-tree feature for 2nd DAWR. If this feature is present, 2nd DAWR is supported, otherwise not. Signed-off-by: Ravi Bangoria --- arch/powerpc/include/asm/cputable.h | 7

Re: [PATCH v4 09/10] powerpc/watchpoint: Return available watchpoints dynamically

2020-07-20 Thread Ravi Bangoria
On 7/20/20 9:12 AM, Jordan Niethe wrote: On Fri, Jul 17, 2020 at 2:11 PM Ravi Bangoria wrote: So far Book3S Powerpc supported only one watchpoint. Power10 is introducing 2nd DAWR. Enable 2nd DAWR support for Power10. Availability of 2nd DAWR will depend on CPU_FTR_DAWR1. Signed-off

Re: [PATCH v4 10/10] powerpc/watchpoint: Remove 512 byte boundary

2020-07-20 Thread Ravi Bangoria
Hi Jordan, On 7/20/20 12:24 PM, Jordan Niethe wrote: On Fri, Jul 17, 2020 at 2:11 PM Ravi Bangoria wrote: Power10 has removed 512 bytes boundary from match criteria. i.e. The watch range can cross 512 bytes boundary. It looks like this change is not mentioned in ISA v3.1 Book III 9.4 Data

Re: [PATCH v2 2/3] powerpc/powernv/idle: save-restore DAWR0, DAWRX0 for P10

2020-07-19 Thread Ravi Bangoria
Hi Nick, On 7/13/20 11:22 AM, Nicholas Piggin wrote: Excerpts from Pratik Rajesh Sampat's message of July 10, 2020 3:22 pm: Additional registers DAWR0, DAWRX0 may be lost on Power 10 for stop levels < 4. Therefore save the values of these SPRs before entering a "stop" state and restore their

Re: [PATCH v2 2/3] powerpc/powernv/idle: save-restore DAWR0,DAWRX0 for P10

2020-07-19 Thread Ravi Bangoria
Hi Pratik, On 7/10/20 10:52 AM, Pratik Rajesh Sampat wrote: Additional registers DAWR0, DAWRX0 may be lost on Power 10 for stop levels < 4. p10 has one more pair DAWR1/DAWRX1. Please include that as well. Ravi

[PATCH v4 10/10] powerpc/watchpoint: Remove 512 byte boundary

2020-07-16 Thread Ravi Bangoria
Power10 has removed 512 bytes boundary from match criteria. i.e. The watch range can cross 512 bytes boundary. Signed-off-by: Ravi Bangoria --- arch/powerpc/kernel/hw_breakpoint.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/kernel/hw_breakpoint.c b

[PATCH v4 09/10] powerpc/watchpoint: Return available watchpoints dynamically

2020-07-16 Thread Ravi Bangoria
So far Book3S Powerpc supported only one watchpoint. Power10 is introducing 2nd DAWR. Enable 2nd DAWR support for Power10. Availability of 2nd DAWR will depend on CPU_FTR_DAWR1. Signed-off-by: Ravi Bangoria --- arch/powerpc/include/asm/cputable.h | 4 +++- arch/powerpc/include/asm

[PATCH v4 08/10] powerpc/watchpoint: Guest support for 2nd DAWR hcall

2020-07-16 Thread Ravi Bangoria
2nd DAWR can be set/unset using H_SET_MODE hcall with resource value 5. Enable powervm guest support with that. This has no effect on kvm guest because kvm will return error if guest does hcall with resource value 5. Signed-off-by: Ravi Bangoria --- arch/powerpc/include/asm/hvcall.h | 1

[PATCH v4 07/10] powerpc/watchpoint: Rename current H_SET_MODE DAWR macro

2020-07-16 Thread Ravi Bangoria
Current H_SET_MODE hcall macro name for setting/resetting DAWR0 is H_SET_MODE_RESOURCE_SET_DAWR. Add suffix 0 to macro name as well. Signed-off-by: Ravi Bangoria --- arch/powerpc/include/asm/hvcall.h | 2 +- arch/powerpc/include/asm/plpar_wrappers.h | 2 +- arch/powerpc/kvm/book3s_hv.c

[PATCH v4 06/10] powerpc/watchpoint: Set CPU_FTR_DAWR1 based on pa-features bit

2020-07-16 Thread Ravi Bangoria
or guests and thus this change is mostly applicable for guests only. Signed-off-by: Ravi Bangoria --- arch/powerpc/kernel/prom.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c index 9cc49f265c86..c76c09b97bc8 100644 --- a/arch/po

[PATCH v4 05/10] powerpc/dt_cpu_ftrs: Add feature for 2nd DAWR

2020-07-16 Thread Ravi Bangoria
Add new device-tree feature for 2nd DAWR. If this feature is present, 2nd DAWR is supported, otherwise not. Signed-off-by: Ravi Bangoria --- arch/powerpc/include/asm/cputable.h | 7 +-- arch/powerpc/kernel/dt_cpu_ftrs.c | 7 +++ 2 files changed, 12 insertions(+), 2 deletions(-) diff

[PATCH v4 04/10] powerpc/watchpoint: Enable watchpoint functionality on power10 guest

2020-07-16 Thread Ravi Bangoria
CPU_FTR_DAWR to CPU_FTRS_POWER10. Note that this change does not enable 2nd DAWR support. Signed-off-by: Ravi Bangoria --- arch/powerpc/include/asm/cputable.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h

[PATCH v4 03/10] powerpc/watchpoint: Fix DAWR exception for CACHEOP

2020-07-16 Thread Ravi Bangoria
ot;) Fixes: 74c6881019b7 ("powerpc/watchpoint: Prepare handler to handle more than one watchpoint") Signed-off-by: Ravi Bangoria --- arch/powerpc/kernel/hw_breakpoint.c | 21 - 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/kernel/hw_breakpoi

[PATCH v4 02/10] powerpc/watchpoint: Fix DAWR exception constraint

2020-07-16 Thread Ravi Bangoria
Franco de Carvalho Signed-off-by: Ravi Bangoria --- arch/powerpc/kernel/hw_breakpoint.c | 72 - 1 file changed, 41 insertions(+), 31 deletions(-) diff --git a/arch/powerpc/kernel/hw_breakpoint.c b/arch/powerpc/kernel/hw_breakpoint.c index 031e6defc08e..a971e22aea81 10

[PATCH v4 01/10] powerpc/watchpoint: Fix 512 byte boundary limit

2020-07-16 Thread Ravi Bangoria
: Use builtin ALIGN*() macros") Reported-by: Milton Miller Signed-off-by: Ravi Bangoria Tested-by: Jordan Niethe --- arch/powerpc/kernel/hw_breakpoint.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/kernel/hw_breakpoint.c b/arch/powerpc/kernel/hw_breakpoi

[PATCH v4 00/10] powerpc/watchpoint: Enable 2nd DAWR on baremetal and powervm

2020-07-16 Thread Ravi Bangoria
->v4: - v3 patch #2 is split into two v4 patches: #2 and #3 - Few other minor neats suggested by Jordan Niethe - Rebased to powerpc/next [1]: https://lore.kernel.org/linuxppc-dev/20200514111741.97993-1-ravi.bango...@linux.ibm.com/ Ravi Bangoria (10): powerpc/watchpoint: Fix 512 byte bound

  1   2   3   4   5   >