Please see my answers in line.
-Original Message-
From: Benjamin Herrenschmidt [mailto:b...@kernel.crashing.org]
Sent: Sunday, January 03, 2010 10:25 PM
To: Tirumala Reddy Marri
Cc: jwbo...@linux.vnet.ibm.com; linuxppc-dev@lists.ozlabs.org;
linuxppc-...@ozlabs.org; writetoma
It should be able to access any region in 32bit mode as long as it is
smaller than 4GB size. Usually whole SDRAM is mapped to inbound PCI
memory region.
-Original Message-
From: linuxppc-dev-bounces+tmarri=amcc@lists.ozlabs.org
, December 23, 2009 12:19 AM
To: linuxppc-dev@lists.ozlabs.org
Cc: linuxppc-...@ozlabs.org; writetoma...@yahoo.com; Tirumala Reddy
Marri
Subject: Re: [PATCH 2/2] Adding PCI-E MSI support for PowerPC 460SX SOC.
On Wednesday 23 December 2009 08:52:23 tma...@amcc.com wrote:
From: Tirumala Marri tma
BTW once this patch gets in I will add the 405Ex,460Ex and 440Spe
support to the same.
-Original Message-
From: linuxppc-dev-bounces+tmarri=amcc@lists.ozlabs.org
[mailto:linuxppc-dev-bounces+tmarri=amcc@lists.ozlabs.org] On Behalf
Of Tirumala Reddy Marri
Sent: Wednesday, December
Josh,
Thanks for the comments. I will fix them re-submit it.
Regards,
Marri
-Original Message-
From: Josh Boyer [mailto:jwbo...@gmail.com] On Behalf Of Josh Boyer
Sent: Tuesday, December 22, 2009 4:08 AM
To: Tirumala Reddy Marri
Cc: linuxppc-dev@lists.ozlabs.org; writetoma...@yahoo.com
root complex as well as endpoint.
Regards,
Marri
-Original Message-
From: tm...@amcc.com [mailto:tm...@amcc.com]
Sent: Monday, November 30, 2009 1:16 PM
To: b...@kernel.crashing.org
Cc: linuxppc-...@ozlabs.org; Tirumala Reddy Marri
Subject: [PATCH] Adding PCI-E support for 460SX based
A URL to it would be fine. I still haven't managed to find it, but
perhaps
the 'ALL available documents/types listed' link on this page:
http://www.appliedmicro.com/MyAMCC/jsp/public/productDetail/product_de
tail.jsp?productID=PPC460SX
doesn't really mean all?
Looks like need a login to get
Hi Ben,
Did you get the chance to review the patch I sent it on Dec-1 2009
http://lists.ozlabs.org/pipermail/linuxppc-dev/2009-December/078436.html
Regards,
MArri
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,
Marri
-Original Message-
From: Josh Boyer [mailto:jwbo...@linux.vnet.ibm.com]
Sent: Monday, December 07, 2009 4:53 PM
To: Tirumala Reddy Marri
Cc: b...@kernel.crashing.org; linuxppc-dev@lists.ozlabs.org
Subject: Re: patch status
On Mon, Dec 07, 2009 at 02:01:58PM -0800, Tirumala Reddy
Sorry I meant drver/. Probably you should consider how the iop-dma is
done.
-Original Message-
From: Anatolij Gustschin [mailto:ag...@denx.de]
Sent: Friday, November 27, 2009 2:27 AM
To: Tirumala Reddy Marri
Cc: linux-r...@vger.kernel.org; w...@denx.de; d...@denx.de; Yuri Tikhonov
Hi Ben,
Could you please review the patch I sent .
Thanks,
Marri
-Original Message-
From: tma...@amcc.com [mailto:tma...@amcc.com]
Sent: Wednesday, November 25, 2009 3:49 PM
To: linuxppc-...@ozlabs.org
Cc: tma...@macc.com; Tirumala Reddy Marri
Subject: [PATCH] Adding PCI-E support
1) It looks like the correct entry in kilauea.dts file should be:
208 IIC1: i...@ef600500 {
209 compatible = ibm,iic-405ex, ibm,iic;
210 reg = ef600500 14;
211 interrupt-parent = UIC0;
212 interrupts = 7 4;
213
You will have to program GPIO's to select appropriate external IRQ as
they are shared .
From: linuxppc-dev-bounces+tmarri=amcc@lists.ozlabs.org
[mailto:linuxppc-dev-bounces+tmarri=amcc@lists.ozlabs.org] On Behalf
Of Lada Podivin
Sent: Friday, June 19, 2009 1:01 AM
To:
Hi Ilya,
Are you going to push further in submitting the ADMA driver for 440SPE
? If you are not I am planning to pursue this effort. I also have
couple later version of Soc's needed to submit.
Thank and Regards,
Marri
From: linux-raid-ow...@vger.kernel.org
Some debuggers like BDI(Abatron) they setup the debug registers. If you
have different debugger which doesn't support configuring debug
registers I suggest you to program then in the head_44x.S file.
From: linuxppc-dev-bounces+tmarri=amcc@ozlabs.org
I agree. Every processor(SOC) has unique of setting inbound window. What I
noticed is Inbound regions are created big enough to map whole DDR region. And
uses physical address of ram as a source/destination address. For example if a
PCI-E SATA card wants to do DMA transfers to DDR region. It
I am not sure if I understand correctly. But Looks like you are not
passing the device tree along with kernel image and RAMDISK(you may not
need it if you are using NFS mount). You boot command should some what
look like this bootm kernel_addr ramdisk_addr devtree_addr or bootm
kernel_addr -
There is PKA/TRNG driver for sure. Let me check if it was accepted in
opensource yet. Otherwise I will forward you the driver which may not be
there in opensource yet.
-Original Message-
From: linuxppc-dev-bounces+tmarri=amcc@ozlabs.org
Did you have dts entries for IIC in device tree ? also did you have I2C enabled
in make menuconfig
device drivers - i2c support -- I2C bus support - IBM ppc 4xx On chip I2C
support selected. Then you should i2c see an entry /proc/devices . Use that
major address and create a device node
What PCI Sata card is this ? Is you device tree entrees are correct for
PCI ? Especially the interrupt numbers etc ? Also check your ioremap()
function in the SATA driver. Make sure that data type of physical
address in the driver using is unsigned long long instead of unsigned
long
Can you post your lspci -vvv dump .
From: linuxppc-dev-bounces+tmarri=amcc@ozlabs.org on behalf of rizwan ahmad
Sent: Mon 3/23/2009 1:07 AM
To: linuxppc-dev@ozlabs.org
Subject: sata device failed to IDENTIFY...
BM/AMCC PowerPC 440 GR Rev. B
Board: AMCC
.
Signed-off-by: Madhulika Madishetty mmadishe...@amcc.com, Tirumala
Reddy
Marri tma...@amcc.com,
Feng Kan f...@amcc.com, Vidhyananth Venkatasamy
vvenkatas...@amcc.com,
Preetesh Parekh ppar...@amcc.com
Acked-by: Loc Ho l...@amcc.com, Feng Kan f...@amcc.com
One Signed-off-by: per person, per line
Reddy Marri
Cc: Olof Johansson; linuxppc-dev@ozlabs.org
Subject: RE: Disabling L1 D-cache and side effects
On Tue, 2008-09-30 at 15:26 -0700, Tirumala Reddy Marri wrote:
Ben,
I got to bring up Linux on one of the 440 processors with out L1
dcache to do some bench marking and compare with L1
Ben,
Thanks for the response. I am wondering how user space would get
affected by absence of L1 Dcache.
Thanks,
Marri
-Original Message-
From: Benjamin Herrenschmidt [mailto:[EMAIL PROTECTED]
Sent: Tuesday, September 30, 2008 12:16 AM
To: Tirumala Reddy Marri
Cc: Olof Johansson
To: Tirumala Reddy Marri
Cc: Olof Johansson; linuxppc-dev@ozlabs.org
Subject: RE: Disabling L1 D-cache and side effects
On Tue, 2008-09-30 at 09:57 -0700, Tirumala Reddy Marri wrote:
Ben,
Thanks for the response. I am wondering how user space would get
affected by absence of L1 Dcache.
You
are the different side
effects might be causing this.
Thanks,
Marri
From: Tirumala Reddy Marri
Sent: Saturday, September 27, 2008 2:37 PM
To: linuxppc-dev@ozlabs.org
Subject: rootfs mount problem
Hi ,
I am trying to bring up a new SOC. I am seeing the following error.
Has
Reddy Marri
Cc: linuxppc-dev@ozlabs.org
Subject: Re: Disabling L1 D-cache and side effects
On Mon, Sep 29, 2008 at 10:05:41AM -0700, Tirumala Reddy Marri wrote:
Hi,
I had to bring up a PPC based SOC with L1 dcache disabled. I did
that and tried to boot Linux using RAMDISK/NFS mount
are cache inhibited. Ando
also made sure none of the misc_32.S , entry_32.S and head.S makes any
references to d-cache.
Thanks,
Marri
-Original Message-
From: Olof Johansson [mailto:[EMAIL PROTECTED]
Sent: Monday, September 29, 2008 2:14 PM
To: Tirumala Reddy Marri
Cc: linuxppc-dev
Hi ,
I am trying to bring up a new SOC. I am seeing the following error.
Has any one seen this error before. I am pretty sure RAMDISK is not
corrupted.
Thanks,
Marri
--- LOG ---
NET: Registered protocol family 17
RPC: Registered udp transport module.
RPC: Registered
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