On Fri, Jan 31, 2014 at 03:18:30PM -0800, David Hawkins wrote:
1. Peripheral board DMA (board-to-board)
2. Peripheral board DMA to host memory.
3. Host (root complex) DMA.
As far as verification of your custom peripheral board FPGA IP is
concerned, if I was a customer, and you had data for
From: Michael Moese
Thank you for your help - we might be satisfied with the achieved
18 MB/s.
We achieved about twice that using the PEX dma controller.
I found the following comment I wrote:
/* Long transfer requests are cut into smaller DMA requests.
* Each PCIe request can contain a
On Mon, Feb 03, 2014 at 10:17:43AM +, David Laight wrote:
We achieved about twice that using the PEX dma controller.
Your 3MB/s for single word transfers is similar to what we saw.
Cycle times that make an ISA bus look fast.
Indeed, this is a really poor performance. I know we could
From: Michael Moese
On Mon, Feb 03, 2014 at 10:17:43AM +, David Laight wrote:
We achieved about twice that using the PEX dma controller.
Your 3MB/s for single word transfers is similar to what we saw.
Cycle times that make an ISA bus look fast.
Indeed, this is a really poor
Hi Michael,
On Fri, Jan 31, 2014 at 03:18:30PM -0800, David Hawkins wrote:
1. Peripheral board DMA (board-to-board)
2. Peripheral board DMA to host memory.
3. Host (root complex) DMA.
As far as verification of your custom peripheral board FPGA IP is
concerned, if I was a customer, and you had
On Thu, Jan 30, 2014 at 12:20:21PM +, Moese, Michael wrote:
Hello PPC-developers,
I'm currently trying to benchmark access speeds to our PCIe-connected IP-cores
located inside our FPGA. On x86-based systems I was able to achieve bursts for
both read and write access. On PPC32, using an
On Thu, 2014-01-30 at 12:20 +, Moese, Michael wrote:
Hello PPC-developers,
I'm currently trying to benchmark access speeds to our PCIe-connected IP-cores
located inside our FPGA. On x86-based systems I was able to achieve bursts for
both read and write access. On PPC32, using an e500v2, I
Hi Michael,
I'm currently trying to benchmark access speeds to our PCIe-connected IP-cores
located inside our FPGA. On x86-based systems I was able to achieve bursts for
both read and write access. On PPC32, using an e500v2, I had no success at all
so far.
Whenever I want to benchmark
Hello PPC-developers,
I'm currently trying to benchmark access speeds to our PCIe-connected IP-cores
located inside our FPGA. On x86-based systems I was able to achieve bursts for
both read and write access. On PPC32, using an e500v2, I had no success at all
so far.
I tried using ioremap_wc(),
From Moese, Michael
Hello PPC-developers,
I'm currently trying to benchmark access speeds to our PCIe-connected IP-cores
located inside our FPGA. On x86-based systems I was able to achieve bursts for
both read and write access. On PPC32, using an e500v2, I had no success at all
so far.
I'm
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