Re: [PATCH] [V2] Add non-Virtex5 support for LL TEMAC driver
David, are you going to pick up this patch, or would you like me to?
Thanks,
g
On Wed, Mar 17, 2010 at 2:02 PM, Grant Likely grant.lik...@secretlab.ca wrote:
On Fri, Mar 12, 2010 at 7:05 PM, John Linn john.l...@xilinx.com wrote:
This patch adds support for using the LL TEMAC Ethernet driver on
non-Virtex 5 platforms by adding support for accessing the Soft DMA
registers as if they were memory mapped instead of solely through the
DCR's (available on the Virtex 5).
The patch also updates the driver so that it runs on the MicroBlaze.
The changes were tested on the PowerPC 440, PowerPC 405, and the
MicroBlaze platforms.
Signed-off-by: John Tyner jty...@cs.ucr.edu
Signed-off-by: John Linn john.l...@xilinx.com
---
I've not booted this, but it looks right, and it compiles fine. The
issues that Michal raised need to be delt with too, but they are
preexisting bugs unrelated to this change which you should fix up in a
separate patch.
Acked-by: Grant Likely grant.lik...@secretlab.ca
V2 - Incorporated comments from Grant and added more logic to allow the
driver
to work on MicroBlaze.
drivers/net/Kconfig | 1 -
drivers/net/ll_temac.h | 17 +-
drivers/net/ll_temac_main.c | 124
++-
3 files changed, 113 insertions(+), 29 deletions(-)
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 9b6efe1..5402105 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -2443,7 +2443,6 @@ config MV643XX_ETH
config XILINX_LL_TEMAC
tristate Xilinx LL TEMAC (LocalLink Tri-mode Ethernet MAC) driver
select PHYLIB
- depends on PPC_DCR_NATIVE
help
This driver supports the Xilinx 10/100/1000 LocalLink TEMAC
core used in Xilinx Spartan and Virtex FPGAs
diff --git a/drivers/net/ll_temac.h b/drivers/net/ll_temac.h
index 1af66a1..915aa34 100644
--- a/drivers/net/ll_temac.h
+++ b/drivers/net/ll_temac.h
@@ -5,8 +5,11 @@
#include linux/netdevice.h
#include linux/of.h
#include linux/spinlock.h
+
+#ifdef CONFIG_PPC_DCR
#include asm/dcr.h
#include asm/dcr-regs.h
+#endif
/* packet size info */
#define XTE_HDR_SIZE 14 /* size of Ethernet header */
@@ -290,8 +293,12 @@ This option defaults to enabled (set) */
#define TX_CONTROL_CALC_CSUM_MASK 1
+/* Align the IP data in the packet on word boundaries as MicroBlaze
+ * needs it.
+ */
+
#define XTE_ALIGN 32
-#define BUFFER_ALIGN(adr) ((XTE_ALIGN - ((u32) adr)) % XTE_ALIGN)
+#define BUFFER_ALIGN(adr) ((34 - ((u32) adr)) % XTE_ALIGN)
#define MULTICAST_CAM_TABLE_NUM 4
@@ -335,9 +342,15 @@ struct temac_local {
struct mii_bus *mii_bus; /* MII bus reference */
int mdio_irqs[PHY_MAX_ADDR]; /* IRQs table for MDIO bus */
- /* IO registers and IRQs */
+ /* IO registers, dma functions and IRQs */
void __iomem *regs;
+ void __iomem *sdma_regs;
+#ifdef CONFIG_PPC_DCR
dcr_host_t sdma_dcrs;
+#endif
+ u32 (*dma_in)(struct temac_local *, int);
+ void (*dma_out)(struct temac_local *, int, u32);
+
int tx_irq;
int rx_irq;
int emac_num;
diff --git a/drivers/net/ll_temac_main.c b/drivers/net/ll_temac_main.c
index a18e348..9aedf9b 100644
--- a/drivers/net/ll_temac_main.c
+++ b/drivers/net/ll_temac_main.c
@@ -20,9 +20,6 @@
* or rx, so this should be okay.
*
* TODO:
- * - Fix driver to work on more than just Virtex5. Right now the driver
- * assumes that the locallink DMA registers are accessed via DCR
- * instructions.
* - Factor out locallink DMA code into separate driver
* - Fix multicast assignment.
* - Fix support for hardware checksumming.
@@ -115,17 +112,86 @@ void temac_indirect_out32(struct temac_local *lp, int
reg, u32 value)
temac_iow(lp, XTE_CTL0_OFFSET, CNTLREG_WRITE_ENABLE_MASK | reg);
}
+/**
+ * temac_dma_in32 - Memory mapped DMA read, this function expects a
+ * register input that is based on DCR word addresses which
+ * are then converted to memory mapped byte addresses
+ */
static u32 temac_dma_in32(struct temac_local *lp, int reg)
{
- return dcr_read(lp-sdma_dcrs, reg);
+ return in_be32((u32 *)(lp-sdma_regs + (reg 2)));
}
+/**
+ * temac_dma_out32 - Memory mapped DMA read, this function expects a
+ * register input that is based on DCR word addresses which
+ * are then converted to memory mapped byte addresses
+ */
static void temac_dma_out32(struct temac_local *lp, int reg, u32 value)
{
+ out_be32((u32 *)(lp-sdma_regs + (reg 2)), value);
+}
+
+/* DMA register access functions can be DCR based or memory mapped.
+ * The PowerPC 440 is DCR based, the PowerPC 405 and MicroBlaze are both
+ * memory mapped.
+ */
+#ifdef CONFIG_PPC_DCR
+
+/**
+ * temac_dma_dcr_in32 - DCR based DMA read
+ */
+static u32 temac_dma_dcr_in(struct temac_local *lp, int reg)
+{
+ return
Re: [PATCH] [V2] Add non-Virtex5 support for LL TEMAC driver
From: Grant Likely grant.lik...@secretlab.ca Date: Mon, 5 Apr 2010 12:10:51 -0600 David, are you going to pick up this patch, or would you like me to? The submitter, when asked, stated that he couldn't even get the driver to build on microblaze against mainline. So I marked the patch changed requested because being able to build is... you know... sort of a requirement for integration. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] [V2] Add non-Virtex5 support for LL TEMAC driver
On Mon, Apr 5, 2010 at 1:16 PM, David Miller da...@davemloft.net wrote: From: Grant Likely grant.lik...@secretlab.ca Date: Mon, 5 Apr 2010 12:10:51 -0600 David, are you going to pick up this patch, or would you like me to? The submitter, when asked, stated that he couldn't even get the driver to build on microblaze against mainline. So I marked the patch changed requested because being able to build is... you know... sort of a requirement for integration. Heh, the current driver doesn't build on microblaze either. However, John, since you're removing the depends on PPC_DCR_NATIVE, can you please respin the patch to make it depend on CONFIG_PPC and CONFIG_OF. Looking at it now I see that as-is it will cause collateral damage to allmodconfig on every other architecture. g. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH] [V2] Add non-Virtex5 support for LL TEMAC driver
-Original Message- From: David Miller [mailto:da...@davemloft.net] Sent: Monday, April 05, 2010 1:17 PM To: grant.lik...@secretlab.ca Cc: net...@vger.kernel.org; linuxppc-...@ozlabs.org; jwbo...@linux.vnet.ibm.com; john.willi...@petalogix.com; michal.si...@petalogix.com; jty...@cs.ucr.edu; John Linn Subject: Re: [PATCH] [V2] Add non-Virtex5 support for LL TEMAC driver From: Grant Likely grant.lik...@secretlab.ca Date: Mon, 5 Apr 2010 12:10:51 -0600 David, are you going to pick up this patch, or would you like me to? The submitter, when asked, stated that he couldn't even get the driver to build on microblaze against mainline. So I marked the patch changed requested because being able to build is... you know... sort of a requirement for integration. More changes made it into the MicroBlaze mainline and it looks like I need to respin the patch again as there are some minor changes on the top of the tree. It built and ran fine on PowerPc, but not MicroBlaze. I'll check now. Thanks, John This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH] [V2] Add non-Virtex5 support for LL TEMAC driver
-Original Message- From: David Miller [mailto:da...@davemloft.net] Sent: Monday, April 05, 2010 1:17 PM To: grant.lik...@secretlab.ca Cc: net...@vger.kernel.org; linuxppc-...@ozlabs.org; jwbo...@linux.vnet.ibm.com; john.willi...@petalogix.com; michal.si...@petalogix.com; jty...@cs.ucr.edu; John Linn Subject: Re: [PATCH] [V2] Add non-Virtex5 support for LL TEMAC driver From: Grant Likely grant.lik...@secretlab.ca Date: Mon, 5 Apr 2010 12:10:51 -0600 David, are you going to pick up this patch, or would you like me to? The submitter, when asked, stated that he couldn't even get the driver to build on microblaze against mainline. So I marked the patch changed requested because being able to build is... you know... sort of a requirement for integration. Pushed out V3 of the patch, forgot to copy you David. Thanks, John This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] [V2] Add non-Virtex5 support for LL TEMAC driver
On Mon, Mar 15, 2010 at 03:39:49PM +0100, Michal Simek wrote: John Linn wrote: -Original Message- From: Michal Simek [mailto:michal.si...@petalogix.com] Sent: Monday, March 15, 2010 2:40 AM To: John Linn Cc: net...@vger.kernel.org; linuxppc-...@ozlabs.org; grant.lik...@secretlab.ca; jwbo...@linux.vnet.ibm.com; john.willi...@petalogix.com; John Tyner Subject: Re: [PATCH] [V2] Add non-Virtex5 support for LL TEMAC driver John Linn wrote: This patch adds support for using the LL TEMAC Ethernet driver on non-Virtex 5 platforms by adding support for accessing the Soft DMA registers as if they were memory mapped instead of solely through the DCR's (available on the Virtex 5). The patch also updates the driver so that it runs on the MicroBlaze. The changes were tested on the PowerPC 440, PowerPC 405, and the MicroBlaze platforms. Which git-tree have you tested on? (Of course microblaze) It was tested on the Xilinx tree for MicroBlaze which is based on the mainline and the Petalogix tree as DMA was needed. I tried to build against the mainline head but got errors with the DMA routines. I guess it's possible that it was a configuration issue there as I didn't dig real deep. New dma api is in for-linus branch. I tested it on that version and I am seeing some weird things. :-( Access to bad area. I will try your tree. The second thing which I see is in ll_temac_recv function. On the following line is read a packet length which could be 0-16k. length = cur_p-app4 0x3FFF; But allocated skb has max size XTE_MAX_JUMBO_FRAME_SIZE + XTE_ALIGN. What happen if driver get packet greater than 9kB? I got it (I don't know how) but skb_put has one checking mechanism which will cal skb_over_panic which caused panic. That's why I think that will be good always to check that length is less than XTE_MAX_JUMBO_FRAME_SIZE + XTE_ALIGN. What do you think? I agree. IIRC the LLTEMAC when configured to accept jumboframes will accepts packets up to 16K and the driver should handle that without raising panics. I remeber beeing a bit surprised about that when hacking the QEMU model. Not sure if I remember correctly though. Cheers ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] [V2] Add non-Virtex5 support for LL TEMAC driver
John Linn wrote:
This patch adds support for using the LL TEMAC Ethernet driver on
non-Virtex 5 platforms by adding support for accessing the Soft DMA
registers as if they were memory mapped instead of solely through the
DCR's (available on the Virtex 5).
The patch also updates the driver so that it runs on the MicroBlaze.
The changes were tested on the PowerPC 440, PowerPC 405, and the
MicroBlaze platforms.
Which git-tree have you tested on? (Of course microblaze)
Michal
Signed-off-by: John Tyner jty...@cs.ucr.edu
Signed-off-by: John Linn john.l...@xilinx.com
---
V2 - Incorporated comments from Grant and added more logic to allow the driver
to work on MicroBlaze.
drivers/net/Kconfig |1 -
drivers/net/ll_temac.h | 17 +-
drivers/net/ll_temac_main.c | 124 ++-
3 files changed, 113 insertions(+), 29 deletions(-)
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 9b6efe1..5402105 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -2443,7 +2443,6 @@ config MV643XX_ETH
config XILINX_LL_TEMAC
tristate Xilinx LL TEMAC (LocalLink Tri-mode Ethernet MAC) driver
select PHYLIB
- depends on PPC_DCR_NATIVE
help
This driver supports the Xilinx 10/100/1000 LocalLink TEMAC
core used in Xilinx Spartan and Virtex FPGAs
diff --git a/drivers/net/ll_temac.h b/drivers/net/ll_temac.h
index 1af66a1..915aa34 100644
--- a/drivers/net/ll_temac.h
+++ b/drivers/net/ll_temac.h
@@ -5,8 +5,11 @@
#include linux/netdevice.h
#include linux/of.h
#include linux/spinlock.h
+
+#ifdef CONFIG_PPC_DCR
#include asm/dcr.h
#include asm/dcr-regs.h
+#endif
/* packet size info */
#define XTE_HDR_SIZE 14 /* size of Ethernet header */
@@ -290,8 +293,12 @@ This option defaults to enabled (set) */
#define TX_CONTROL_CALC_CSUM_MASK 1
+/* Align the IP data in the packet on word boundaries as MicroBlaze
+ * needs it.
+ */
+
#define XTE_ALIGN 32
-#define BUFFER_ALIGN(adr) ((XTE_ALIGN - ((u32) adr)) % XTE_ALIGN)
+#define BUFFER_ALIGN(adr) ((34 - ((u32) adr)) % XTE_ALIGN)
#define MULTICAST_CAM_TABLE_NUM 4
@@ -335,9 +342,15 @@ struct temac_local {
struct mii_bus *mii_bus;/* MII bus reference */
int mdio_irqs[PHY_MAX_ADDR];/* IRQs table for MDIO bus */
- /* IO registers and IRQs */
+ /* IO registers, dma functions and IRQs */
void __iomem *regs;
+ void __iomem *sdma_regs;
+#ifdef CONFIG_PPC_DCR
dcr_host_t sdma_dcrs;
+#endif
+ u32 (*dma_in)(struct temac_local *, int);
+ void (*dma_out)(struct temac_local *, int, u32);
+
int tx_irq;
int rx_irq;
int emac_num;
diff --git a/drivers/net/ll_temac_main.c b/drivers/net/ll_temac_main.c
index a18e348..9aedf9b 100644
--- a/drivers/net/ll_temac_main.c
+++ b/drivers/net/ll_temac_main.c
@@ -20,9 +20,6 @@
* or rx, so this should be okay.
*
* TODO:
- * - Fix driver to work on more than just Virtex5. Right now the driver
- * assumes that the locallink DMA registers are accessed via DCR
- * instructions.
* - Factor out locallink DMA code into separate driver
* - Fix multicast assignment.
* - Fix support for hardware checksumming.
@@ -115,17 +112,86 @@ void temac_indirect_out32(struct temac_local *lp, int
reg, u32 value)
temac_iow(lp, XTE_CTL0_OFFSET, CNTLREG_WRITE_ENABLE_MASK | reg);
}
+/**
+ * temac_dma_in32 - Memory mapped DMA read, this function expects a
+ * register input that is based on DCR word addresses which
+ * are then converted to memory mapped byte addresses
+ */
static u32 temac_dma_in32(struct temac_local *lp, int reg)
{
- return dcr_read(lp-sdma_dcrs, reg);
+ return in_be32((u32 *)(lp-sdma_regs + (reg 2)));
}
+/**
+ * temac_dma_out32 - Memory mapped DMA read, this function expects a
+ * register input that is based on DCR word addresses which
+ * are then converted to memory mapped byte addresses
+ */
static void temac_dma_out32(struct temac_local *lp, int reg, u32 value)
{
+ out_be32((u32 *)(lp-sdma_regs + (reg 2)), value);
+}
+
+/* DMA register access functions can be DCR based or memory mapped.
+ * The PowerPC 440 is DCR based, the PowerPC 405 and MicroBlaze are both
+ * memory mapped.
+ */
+#ifdef CONFIG_PPC_DCR
+
+/**
+ * temac_dma_dcr_in32 - DCR based DMA read
+ */
+static u32 temac_dma_dcr_in(struct temac_local *lp, int reg)
+{
+ return dcr_read(lp-sdma_dcrs, reg);
+}
+
+/**
+ * temac_dma_dcr_out32 - DCR based DMA write
+ */
+static void temac_dma_dcr_out(struct temac_local *lp, int reg, u32 value)
+{
dcr_write(lp-sdma_dcrs, reg, value);
}
/**
+ * temac_dcr_setup - If the DMA is DCR based, then setup the address and
+ * I/O functions
+ */
+static int temac_dcr_setup(struct temac_local *lp, struct of_device *op,
+ struct device_node *np)
+{
+ unsigned int dcrs;
+
+ /* setup the dcr address mapping
RE: [PATCH] [V2] Add non-Virtex5 support for LL TEMAC driver
-Original Message-
From: Michal Simek [mailto:michal.si...@petalogix.com]
Sent: Monday, March 15, 2010 2:40 AM
To: John Linn
Cc: net...@vger.kernel.org; linuxppc-...@ozlabs.org;
grant.lik...@secretlab.ca;
jwbo...@linux.vnet.ibm.com; john.willi...@petalogix.com; John Tyner
Subject: Re: [PATCH] [V2] Add non-Virtex5 support for LL TEMAC driver
John Linn wrote:
This patch adds support for using the LL TEMAC Ethernet driver on
non-Virtex 5 platforms by adding support for accessing the Soft DMA
registers as if they were memory mapped instead of solely through
the
DCR's (available on the Virtex 5).
The patch also updates the driver so that it runs on the MicroBlaze.
The changes were tested on the PowerPC 440, PowerPC 405, and the
MicroBlaze platforms.
Which git-tree have you tested on? (Of course microblaze)
It was tested on the Xilinx tree for MicroBlaze which is based on the
mainline and the Petalogix tree as DMA was needed. I tried to build
against the mainline head but got errors with the DMA routines. I guess
it's possible that it was a configuration issue there as I didn't dig
real deep.
I tested the PowerPC against the head of mainline.
Thanks,
John
Michal
Signed-off-by: John Tyner jty...@cs.ucr.edu
Signed-off-by: John Linn john.l...@xilinx.com
---
V2 - Incorporated comments from Grant and added more logic to allow
the driver
to work on MicroBlaze.
drivers/net/Kconfig |1 -
drivers/net/ll_temac.h | 17 +-
drivers/net/ll_temac_main.c | 124
++-
3 files changed, 113 insertions(+), 29 deletions(-)
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 9b6efe1..5402105 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -2443,7 +2443,6 @@ config MV643XX_ETH
config XILINX_LL_TEMAC
tristate Xilinx LL TEMAC (LocalLink Tri-mode Ethernet MAC)
driver
select PHYLIB
- depends on PPC_DCR_NATIVE
help
This driver supports the Xilinx 10/100/1000 LocalLink TEMAC
core used in Xilinx Spartan and Virtex FPGAs
diff --git a/drivers/net/ll_temac.h b/drivers/net/ll_temac.h
index 1af66a1..915aa34 100644
--- a/drivers/net/ll_temac.h
+++ b/drivers/net/ll_temac.h
@@ -5,8 +5,11 @@
#include linux/netdevice.h
#include linux/of.h
#include linux/spinlock.h
+
+#ifdef CONFIG_PPC_DCR
#include asm/dcr.h
#include asm/dcr-regs.h
+#endif
/* packet size info */
#define XTE_HDR_SIZE 14 /* size of
Ethernet header */
@@ -290,8 +293,12 @@ This option defaults to enabled (set) */
#define TX_CONTROL_CALC_CSUM_MASK 1
+/* Align the IP data in the packet on word boundaries as MicroBlaze
+ * needs it.
+ */
+
#define XTE_ALIGN 32
-#define BUFFER_ALIGN(adr) ((XTE_ALIGN - ((u32) adr)) % XTE_ALIGN)
+#define BUFFER_ALIGN(adr) ((34 - ((u32) adr)) % XTE_ALIGN)
#define MULTICAST_CAM_TABLE_NUM 4
@@ -335,9 +342,15 @@ struct temac_local {
struct mii_bus *mii_bus;/* MII bus reference */
int mdio_irqs[PHY_MAX_ADDR];/* IRQs table for MDIO bus */
- /* IO registers and IRQs */
+ /* IO registers, dma functions and IRQs */
void __iomem *regs;
+ void __iomem *sdma_regs;
+#ifdef CONFIG_PPC_DCR
dcr_host_t sdma_dcrs;
+#endif
+ u32 (*dma_in)(struct temac_local *, int);
+ void (*dma_out)(struct temac_local *, int, u32);
+
int tx_irq;
int rx_irq;
int emac_num;
diff --git a/drivers/net/ll_temac_main.c
b/drivers/net/ll_temac_main.c
index a18e348..9aedf9b 100644
--- a/drivers/net/ll_temac_main.c
+++ b/drivers/net/ll_temac_main.c
@@ -20,9 +20,6 @@
* or rx, so this should be okay.
*
* TODO:
- * - Fix driver to work on more than just Virtex5. Right now the
driver
- * assumes that the locallink DMA registers are accessed via DCR
- * instructions.
* - Factor out locallink DMA code into separate driver
* - Fix multicast assignment.
* - Fix support for hardware checksumming.
@@ -115,17 +112,86 @@ void temac_indirect_out32(struct temac_local
*lp, int reg, u32 value)
temac_iow(lp, XTE_CTL0_OFFSET, CNTLREG_WRITE_ENABLE_MASK | reg);
}
+/**
+ * temac_dma_in32 - Memory mapped DMA read, this function expects a
+ * register input that is based on DCR word addresses which
+ * are then converted to memory mapped byte addresses
+ */
static u32 temac_dma_in32(struct temac_local *lp, int reg)
{
- return dcr_read(lp-sdma_dcrs, reg);
+ return in_be32((u32 *)(lp-sdma_regs + (reg 2)));
}
+/**
+ * temac_dma_out32 - Memory mapped DMA read, this function expects
a
+ * register input that is based on DCR word addresses which
+ * are then converted to memory mapped byte addresses
+ */
static void temac_dma_out32(struct temac_local *lp, int reg, u32
value)
{
+ out_be32((u32 *)(lp-sdma_regs + (reg 2)), value
Re: [PATCH] [V2] Add non-Virtex5 support for LL TEMAC driver
John Linn wrote:
-Original Message-
From: Michal Simek [mailto:michal.si...@petalogix.com]
Sent: Monday, March 15, 2010 2:40 AM
To: John Linn
Cc: net...@vger.kernel.org; linuxppc-...@ozlabs.org;
grant.lik...@secretlab.ca;
jwbo...@linux.vnet.ibm.com; john.willi...@petalogix.com; John Tyner
Subject: Re: [PATCH] [V2] Add non-Virtex5 support for LL TEMAC driver
John Linn wrote:
This patch adds support for using the LL TEMAC Ethernet driver on
non-Virtex 5 platforms by adding support for accessing the Soft DMA
registers as if they were memory mapped instead of solely through
the
DCR's (available on the Virtex 5).
The patch also updates the driver so that it runs on the MicroBlaze.
The changes were tested on the PowerPC 440, PowerPC 405, and the
MicroBlaze platforms.
Which git-tree have you tested on? (Of course microblaze)
It was tested on the Xilinx tree for MicroBlaze which is based on the
mainline and the Petalogix tree as DMA was needed. I tried to build
against the mainline head but got errors with the DMA routines. I guess
it's possible that it was a configuration issue there as I didn't dig
real deep.
New dma api is in for-linus branch.
I tested it on that version and I am seeing some weird things. :-(
Access to bad area. I will try your tree.
The second thing which I see is in ll_temac_recv function.
On the following line is read a packet length which could be 0-16k.
length = cur_p-app4 0x3FFF;
But allocated skb has max size XTE_MAX_JUMBO_FRAME_SIZE + XTE_ALIGN.
What happen if driver get packet greater than 9kB?
I got it (I don't know how) but skb_put has one checking mechanism which
will cal skb_over_panic which caused panic.
That's why I think that will be good always to check that length is less
than XTE_MAX_JUMBO_FRAME_SIZE + XTE_ALIGN.
What do you think?
Thanks,
Michal
I tested the PowerPC against the head of mainline.
Thanks,
John
Michal
Signed-off-by: John Tyner jty...@cs.ucr.edu
Signed-off-by: John Linn john.l...@xilinx.com
---
V2 - Incorporated comments from Grant and added more logic to allow
the driver
to work on MicroBlaze.
drivers/net/Kconfig |1 -
drivers/net/ll_temac.h | 17 +-
drivers/net/ll_temac_main.c | 124
++-
3 files changed, 113 insertions(+), 29 deletions(-)
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 9b6efe1..5402105 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -2443,7 +2443,6 @@ config MV643XX_ETH
config XILINX_LL_TEMAC
tristate Xilinx LL TEMAC (LocalLink Tri-mode Ethernet MAC)
driver
select PHYLIB
- depends on PPC_DCR_NATIVE
help
This driver supports the Xilinx 10/100/1000 LocalLink TEMAC
core used in Xilinx Spartan and Virtex FPGAs
diff --git a/drivers/net/ll_temac.h b/drivers/net/ll_temac.h
index 1af66a1..915aa34 100644
--- a/drivers/net/ll_temac.h
+++ b/drivers/net/ll_temac.h
@@ -5,8 +5,11 @@
#include linux/netdevice.h
#include linux/of.h
#include linux/spinlock.h
+
+#ifdef CONFIG_PPC_DCR
#include asm/dcr.h
#include asm/dcr-regs.h
+#endif
/* packet size info */
#define XTE_HDR_SIZE 14 /* size of
Ethernet header */
@@ -290,8 +293,12 @@ This option defaults to enabled (set) */
#define TX_CONTROL_CALC_CSUM_MASK 1
+/* Align the IP data in the packet on word boundaries as MicroBlaze
+ * needs it.
+ */
+
#define XTE_ALIGN 32
-#define BUFFER_ALIGN(adr) ((XTE_ALIGN - ((u32) adr)) % XTE_ALIGN)
+#define BUFFER_ALIGN(adr) ((34 - ((u32) adr)) % XTE_ALIGN)
#define MULTICAST_CAM_TABLE_NUM 4
@@ -335,9 +342,15 @@ struct temac_local {
struct mii_bus *mii_bus;/* MII bus reference */
int mdio_irqs[PHY_MAX_ADDR];/* IRQs table for MDIO bus */
- /* IO registers and IRQs */
+ /* IO registers, dma functions and IRQs */
void __iomem *regs;
+ void __iomem *sdma_regs;
+#ifdef CONFIG_PPC_DCR
dcr_host_t sdma_dcrs;
+#endif
+ u32 (*dma_in)(struct temac_local *, int);
+ void (*dma_out)(struct temac_local *, int, u32);
+
int tx_irq;
int rx_irq;
int emac_num;
diff --git a/drivers/net/ll_temac_main.c
b/drivers/net/ll_temac_main.c
index a18e348..9aedf9b 100644
--- a/drivers/net/ll_temac_main.c
+++ b/drivers/net/ll_temac_main.c
@@ -20,9 +20,6 @@
* or rx, so this should be okay.
*
* TODO:
- * - Fix driver to work on more than just Virtex5. Right now the
driver
- * assumes that the locallink DMA registers are accessed via DCR
- * instructions.
* - Factor out locallink DMA code into separate driver
* - Fix multicast assignment.
* - Fix support for hardware checksumming.
@@ -115,17 +112,86 @@ void temac_indirect_out32(struct temac_local
*lp, int reg, u32 value)
temac_iow(lp, XTE_CTL0_OFFSET, CNTLREG_WRITE_ENABLE_MASK | reg);
}
+/**
+ * temac_dma_in32 - Memory mapped DMA read, this function expects a
+ * register input
RE: [PATCH] [V2] Add non-Virtex5 support for LL TEMAC driver
-Original Message-
From: Michal Simek [mailto:michal.si...@petalogix.com]
Sent: Monday, March 15, 2010 8:40 AM
To: John Linn
Cc: net...@vger.kernel.org; linuxppc-...@ozlabs.org;
grant.lik...@secretlab.ca;
jwbo...@linux.vnet.ibm.com; john.willi...@petalogix.com; John Tyner
Subject: Re: [PATCH] [V2] Add non-Virtex5 support for LL TEMAC driver
John Linn wrote:
-Original Message-
From: Michal Simek [mailto:michal.si...@petalogix.com]
Sent: Monday, March 15, 2010 2:40 AM
To: John Linn
Cc: net...@vger.kernel.org; linuxppc-...@ozlabs.org;
grant.lik...@secretlab.ca;
jwbo...@linux.vnet.ibm.com; john.willi...@petalogix.com; John Tyner
Subject: Re: [PATCH] [V2] Add non-Virtex5 support for LL TEMAC
driver
John Linn wrote:
This patch adds support for using the LL TEMAC Ethernet driver on
non-Virtex 5 platforms by adding support for accessing the Soft
DMA
registers as if they were memory mapped instead of solely through
the
DCR's (available on the Virtex 5).
The patch also updates the driver so that it runs on the
MicroBlaze.
The changes were tested on the PowerPC 440, PowerPC 405, and the
MicroBlaze platforms.
Which git-tree have you tested on? (Of course microblaze)
It was tested on the Xilinx tree for MicroBlaze which is based on
the
mainline and the Petalogix tree as DMA was needed. I tried to build
against the mainline head but got errors with the DMA routines. I
guess
it's possible that it was a configuration issue there as I didn't
dig
real deep.
New dma api is in for-linus branch.
I tested it on that version and I am seeing some weird things. :-(
Access to bad area. I will try your tree.
The second thing which I see is in ll_temac_recv function.
On the following line is read a packet length which could be 0-16k.
length = cur_p-app4 0x3FFF;
But allocated skb has max size XTE_MAX_JUMBO_FRAME_SIZE + XTE_ALIGN.
What happen if driver get packet greater than 9kB?
I got it (I don't know how) but skb_put has one checking mechanism
which
will cal skb_over_panic which caused panic.
That's the whole reason for that panic to me and when I got it in the
past and looked it up it made sense to me. I personally don't see a
good reason to check for it in the driver since the kernel catches it,
but maybe others do.
Thanks,
John
That's why I think that will be good always to check that length is
less
than XTE_MAX_JUMBO_FRAME_SIZE + XTE_ALIGN.
What do you think?
Thanks,
Michal
I tested the PowerPC against the head of mainline.
Thanks,
John
Michal
Signed-off-by: John Tyner jty...@cs.ucr.edu
Signed-off-by: John Linn john.l...@xilinx.com
---
V2 - Incorporated comments from Grant and added more logic to
allow
the driver
to work on MicroBlaze.
drivers/net/Kconfig |1 -
drivers/net/ll_temac.h | 17 +-
drivers/net/ll_temac_main.c | 124
++-
3 files changed, 113 insertions(+), 29 deletions(-)
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 9b6efe1..5402105 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -2443,7 +2443,6 @@ config MV643XX_ETH
config XILINX_LL_TEMAC
tristate Xilinx LL TEMAC (LocalLink Tri-mode Ethernet MAC)
driver
select PHYLIB
- depends on PPC_DCR_NATIVE
help
This driver supports the Xilinx 10/100/1000 LocalLink TEMAC
core used in Xilinx Spartan and Virtex FPGAs
diff --git a/drivers/net/ll_temac.h b/drivers/net/ll_temac.h
index 1af66a1..915aa34 100644
--- a/drivers/net/ll_temac.h
+++ b/drivers/net/ll_temac.h
@@ -5,8 +5,11 @@
#include linux/netdevice.h
#include linux/of.h
#include linux/spinlock.h
+
+#ifdef CONFIG_PPC_DCR
#include asm/dcr.h
#include asm/dcr-regs.h
+#endif
/* packet size info */
#define XTE_HDR_SIZE 14 /* size of
Ethernet header */
@@ -290,8 +293,12 @@ This option defaults to enabled (set) */
#define TX_CONTROL_CALC_CSUM_MASK 1
+/* Align the IP data in the packet on word boundaries as
MicroBlaze
+ * needs it.
+ */
+
#define XTE_ALIGN 32
-#define BUFFER_ALIGN(adr) ((XTE_ALIGN - ((u32) adr)) % XTE_ALIGN)
+#define BUFFER_ALIGN(adr) ((34 - ((u32) adr)) % XTE_ALIGN)
#define MULTICAST_CAM_TABLE_NUM 4
@@ -335,9 +342,15 @@ struct temac_local {
struct mii_bus *mii_bus;/* MII bus reference */
int mdio_irqs[PHY_MAX_ADDR];/* IRQs table for MDIO bus */
- /* IO registers and IRQs */
+ /* IO registers, dma functions and IRQs */
void __iomem *regs;
+ void __iomem *sdma_regs;
+#ifdef CONFIG_PPC_DCR
dcr_host_t sdma_dcrs;
+#endif
+ u32 (*dma_in)(struct temac_local *, int);
+ void (*dma_out)(struct temac_local *, int, u32);
+
int tx_irq;
int rx_irq;
int emac_num;
diff --git a/drivers/net/ll_temac_main.c
b/drivers/net/ll_temac_main.c
index a18e348..9aedf9b 100644
Re: [PATCH] [V2] Add non-Virtex5 support for LL TEMAC driver
John Linn wrote:
-Original Message-
From: Michal Simek [mailto:michal.si...@petalogix.com]
Sent: Monday, March 15, 2010 8:40 AM
To: John Linn
Cc: net...@vger.kernel.org; linuxppc-...@ozlabs.org;
grant.lik...@secretlab.ca;
jwbo...@linux.vnet.ibm.com; john.willi...@petalogix.com; John Tyner
Subject: Re: [PATCH] [V2] Add non-Virtex5 support for LL TEMAC driver
John Linn wrote:
-Original Message-
From: Michal Simek [mailto:michal.si...@petalogix.com]
Sent: Monday, March 15, 2010 2:40 AM
To: John Linn
Cc: net...@vger.kernel.org; linuxppc-...@ozlabs.org;
grant.lik...@secretlab.ca;
jwbo...@linux.vnet.ibm.com; john.willi...@petalogix.com; John Tyner
Subject: Re: [PATCH] [V2] Add non-Virtex5 support for LL TEMAC
driver
John Linn wrote:
This patch adds support for using the LL TEMAC Ethernet driver on
non-Virtex 5 platforms by adding support for accessing the Soft
DMA
registers as if they were memory mapped instead of solely through
the
DCR's (available on the Virtex 5).
The patch also updates the driver so that it runs on the
MicroBlaze.
The changes were tested on the PowerPC 440, PowerPC 405, and the
MicroBlaze platforms.
Which git-tree have you tested on? (Of course microblaze)
It was tested on the Xilinx tree for MicroBlaze which is based on
the
mainline and the Petalogix tree as DMA was needed. I tried to build
against the mainline head but got errors with the DMA routines. I
guess
it's possible that it was a configuration issue there as I didn't
dig
real deep.
New dma api is in for-linus branch.
I tested it on that version and I am seeing some weird things. :-(
Access to bad area. I will try your tree.
The second thing which I see is in ll_temac_recv function.
On the following line is read a packet length which could be 0-16k.
length = cur_p-app4 0x3FFF;
But allocated skb has max size XTE_MAX_JUMBO_FRAME_SIZE + XTE_ALIGN.
What happen if driver get packet greater than 9kB?
I got it (I don't know how) but skb_put has one checking mechanism
which
will cal skb_over_panic which caused panic.
That's the whole reason for that panic to me and when I got it in the
past and looked it up it made sense to me. I personally don't see a
good reason to check for it in the driver since the kernel catches it,
but maybe others do.
yes, kernel is checking it but caused panic which ends in fault in
kernel and caused kernel crash. :-( This could be a good reason to check
it in driver. I don't want to reset the board when ll_temac gets longer
packet, do you?
I have seen the second type of fault which caused kernel access to bad
area (+ kernel panic). Have you done any iperf tests or flood ping?
Thanks,
Michal
Thanks,
John
That's why I think that will be good always to check that length is
less
than XTE_MAX_JUMBO_FRAME_SIZE + XTE_ALIGN.
What do you think?
Thanks,
Michal
I tested the PowerPC against the head of mainline.
Thanks,
John
Michal
Signed-off-by: John Tyner jty...@cs.ucr.edu
Signed-off-by: John Linn john.l...@xilinx.com
---
V2 - Incorporated comments from Grant and added more logic to
allow
the driver
to work on MicroBlaze.
drivers/net/Kconfig |1 -
drivers/net/ll_temac.h | 17 +-
drivers/net/ll_temac_main.c | 124
++-
3 files changed, 113 insertions(+), 29 deletions(-)
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 9b6efe1..5402105 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -2443,7 +2443,6 @@ config MV643XX_ETH
config XILINX_LL_TEMAC
tristate Xilinx LL TEMAC (LocalLink Tri-mode Ethernet MAC)
driver
select PHYLIB
- depends on PPC_DCR_NATIVE
help
This driver supports the Xilinx 10/100/1000 LocalLink TEMAC
core used in Xilinx Spartan and Virtex FPGAs
diff --git a/drivers/net/ll_temac.h b/drivers/net/ll_temac.h
index 1af66a1..915aa34 100644
--- a/drivers/net/ll_temac.h
+++ b/drivers/net/ll_temac.h
@@ -5,8 +5,11 @@
#include linux/netdevice.h
#include linux/of.h
#include linux/spinlock.h
+
+#ifdef CONFIG_PPC_DCR
#include asm/dcr.h
#include asm/dcr-regs.h
+#endif
/* packet size info */
#define XTE_HDR_SIZE 14 /* size of
Ethernet header */
@@ -290,8 +293,12 @@ This option defaults to enabled (set) */
#define TX_CONTROL_CALC_CSUM_MASK 1
+/* Align the IP data in the packet on word boundaries as
MicroBlaze
+ * needs it.
+ */
+
#define XTE_ALIGN 32
-#define BUFFER_ALIGN(adr) ((XTE_ALIGN - ((u32) adr)) % XTE_ALIGN)
+#define BUFFER_ALIGN(adr) ((34 - ((u32) adr)) % XTE_ALIGN)
#define MULTICAST_CAM_TABLE_NUM 4
@@ -335,9 +342,15 @@ struct temac_local {
struct mii_bus *mii_bus;/* MII bus reference */
int mdio_irqs[PHY_MAX_ADDR];/* IRQs table for MDIO bus */
- /* IO registers and IRQs */
+ /* IO registers, dma functions and IRQs */
void __iomem *regs;
+ void __iomem *sdma_regs;
+#ifdef
RE: [PATCH] [V2] Add non-Virtex5 support for LL TEMAC driver
-Original Message- From: linuxppc-dev-bounces+stephen=neuendorffer.n...@lists.ozlabs.org [mailto:linuxppc-dev- bounces+stephen=neuendorffer.n...@lists.ozlabs.org] On Behalf Of John Linn Sent: Friday, March 12, 2010 5:06 PM To: net...@vger.kernel.org; linuxppc-...@ozlabs.org; grant.lik...@secretlab.ca; jwbo...@linux.vnet.ibm.com Cc: michal.si...@petalogix.com; John Tyner; John Linn; john.willi...@petalogix.com Subject: [PATCH] [V2] Add non-Virtex5 support for LL TEMAC driver This patch adds support for using the LL TEMAC Ethernet driver on non-Virtex 5 platforms by adding support for accessing the Soft DMA registers as if they were memory mapped instead of solely through the DCR's (available on the Virtex 5). The patch also updates the driver so that it runs on the MicroBlaze. The changes were tested on the PowerPC 440, PowerPC 405, and the MicroBlaze platforms. Signed-off-by: John Tyner jty...@cs.ucr.edu Signed-off-by: John Linn john.l...@xilinx.com --- V2 - Incorporated comments from Grant and added more logic to allow the driver to work on MicroBlaze. drivers/net/Kconfig |1 - drivers/net/ll_temac.h | 17 +- drivers/net/ll_temac_main.c | 124 ++- 3 files changed, 113 insertions(+), 29 deletions(-) diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 9b6efe1..5402105 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -2443,7 +2443,6 @@ config MV643XX_ETH config XILINX_LL_TEMAC tristate Xilinx LL TEMAC (LocalLink Tri-mode Ethernet MAC) driver select PHYLIB - depends on PPC_DCR_NATIVE help This driver supports the Xilinx 10/100/1000 LocalLink TEMAC core used in Xilinx Spartan and Virtex FPGAs diff --git a/drivers/net/ll_temac.h b/drivers/net/ll_temac.h index 1af66a1..915aa34 100644 --- a/drivers/net/ll_temac.h +++ b/drivers/net/ll_temac.h @@ -5,8 +5,11 @@ #include linux/netdevice.h #include linux/of.h #include linux/spinlock.h + +#ifdef CONFIG_PPC_DCR #include asm/dcr.h #include asm/dcr-regs.h +#endif /* packet size info */ #define XTE_HDR_SIZE 14 /* size of Ethernet header */ @@ -290,8 +293,12 @@ This option defaults to enabled (set) */ #define TX_CONTROL_CALC_CSUM_MASK 1 +/* Align the IP data in the packet on word boundaries as MicroBlaze + * needs it. + */ + #define XTE_ALIGN 32 -#define BUFFER_ALIGN(adr) ((XTE_ALIGN - ((u32) adr)) % XTE_ALIGN) +#define BUFFER_ALIGN(adr) ((34 - ((u32) adr)) % XTE_ALIGN) Is '34' really XTE_ALIGN + 2? (I really have no idea it just looks like a suspicious change.) Steve This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH] [V2] Add non-Virtex5 support for LL TEMAC driver
-Original Message- From: Stephen Neuendorffer Sent: Monday, March 15, 2010 11:03 AM To: John Linn; net...@vger.kernel.org; linuxppc-...@ozlabs.org; grant.lik...@secretlab.ca; jwbo...@linux.vnet.ibm.com Cc: michal.si...@petalogix.com; John Tyner; john.willi...@petalogix.com Subject: RE: [PATCH] [V2] Add non-Virtex5 support for LL TEMAC driver -Original Message- From: linuxppc-dev-bounces+stephen=neuendorffer.n...@lists.ozlabs.org [mailto:linuxppc-dev- bounces+stephen=neuendorffer.n...@lists.ozlabs.org] On Behalf Of John Linn Sent: Friday, March 12, 2010 5:06 PM To: net...@vger.kernel.org; linuxppc-...@ozlabs.org; grant.lik...@secretlab.ca; jwbo...@linux.vnet.ibm.com Cc: michal.si...@petalogix.com; John Tyner; John Linn; john.willi...@petalogix.com Subject: [PATCH] [V2] Add non-Virtex5 support for LL TEMAC driver This patch adds support for using the LL TEMAC Ethernet driver on non-Virtex 5 platforms by adding support for accessing the Soft DMA registers as if they were memory mapped instead of solely through the DCR's (available on the Virtex 5). The patch also updates the driver so that it runs on the MicroBlaze. The changes were tested on the PowerPC 440, PowerPC 405, and the MicroBlaze platforms. Signed-off-by: John Tyner jty...@cs.ucr.edu Signed-off-by: John Linn john.l...@xilinx.com --- V2 - Incorporated comments from Grant and added more logic to allow the driver to work on MicroBlaze. drivers/net/Kconfig |1 - drivers/net/ll_temac.h | 17 +- drivers/net/ll_temac_main.c | 124 ++- 3 files changed, 113 insertions(+), 29 deletions(-) diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 9b6efe1..5402105 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -2443,7 +2443,6 @@ config MV643XX_ETH config XILINX_LL_TEMAC tristate Xilinx LL TEMAC (LocalLink Tri-mode Ethernet MAC) driver select PHYLIB - depends on PPC_DCR_NATIVE help This driver supports the Xilinx 10/100/1000 LocalLink TEMAC core used in Xilinx Spartan and Virtex FPGAs diff --git a/drivers/net/ll_temac.h b/drivers/net/ll_temac.h index 1af66a1..915aa34 100644 --- a/drivers/net/ll_temac.h +++ b/drivers/net/ll_temac.h @@ -5,8 +5,11 @@ #include linux/netdevice.h #include linux/of.h #include linux/spinlock.h + +#ifdef CONFIG_PPC_DCR #include asm/dcr.h #include asm/dcr-regs.h +#endif /* packet size info */ #define XTE_HDR_SIZE 14 /* size of Ethernet header */ @@ -290,8 +293,12 @@ This option defaults to enabled (set) */ #define TX_CONTROL_CALC_CSUM_MASK 1 +/* Align the IP data in the packet on word boundaries as MicroBlaze + * needs it. + */ + #define XTE_ALIGN 32 -#define BUFFER_ALIGN(adr) ((XTE_ALIGN - ((u32) adr)) % XTE_ALIGN) +#define BUFFER_ALIGN(adr) ((34 - ((u32) adr)) % XTE_ALIGN) Is '34' really XTE_ALIGN + 2? (I really have no idea it just looks like a suspicious change.) Steve Valid point that it is XTE_ALIGN + 2. As the comment says, it aligns the IP data in the packet. -- John This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] [V2] Add non-Virtex5 support for LL TEMAC driver
This patch adds support for using the LL TEMAC Ethernet driver on
non-Virtex 5 platforms by adding support for accessing the Soft DMA
registers as if they were memory mapped instead of solely through the
DCR's (available on the Virtex 5).
The patch also updates the driver so that it runs on the MicroBlaze.
The changes were tested on the PowerPC 440, PowerPC 405, and the
MicroBlaze platforms.
Signed-off-by: John Tyner jty...@cs.ucr.edu
Signed-off-by: John Linn john.l...@xilinx.com
---
V2 - Incorporated comments from Grant and added more logic to allow the driver
to work on MicroBlaze.
drivers/net/Kconfig |1 -
drivers/net/ll_temac.h | 17 +-
drivers/net/ll_temac_main.c | 124 ++-
3 files changed, 113 insertions(+), 29 deletions(-)
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 9b6efe1..5402105 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -2443,7 +2443,6 @@ config MV643XX_ETH
config XILINX_LL_TEMAC
tristate Xilinx LL TEMAC (LocalLink Tri-mode Ethernet MAC) driver
select PHYLIB
- depends on PPC_DCR_NATIVE
help
This driver supports the Xilinx 10/100/1000 LocalLink TEMAC
core used in Xilinx Spartan and Virtex FPGAs
diff --git a/drivers/net/ll_temac.h b/drivers/net/ll_temac.h
index 1af66a1..915aa34 100644
--- a/drivers/net/ll_temac.h
+++ b/drivers/net/ll_temac.h
@@ -5,8 +5,11 @@
#include linux/netdevice.h
#include linux/of.h
#include linux/spinlock.h
+
+#ifdef CONFIG_PPC_DCR
#include asm/dcr.h
#include asm/dcr-regs.h
+#endif
/* packet size info */
#define XTE_HDR_SIZE 14 /* size of Ethernet header */
@@ -290,8 +293,12 @@ This option defaults to enabled (set) */
#define TX_CONTROL_CALC_CSUM_MASK 1
+/* Align the IP data in the packet on word boundaries as MicroBlaze
+ * needs it.
+ */
+
#define XTE_ALIGN 32
-#define BUFFER_ALIGN(adr) ((XTE_ALIGN - ((u32) adr)) % XTE_ALIGN)
+#define BUFFER_ALIGN(adr) ((34 - ((u32) adr)) % XTE_ALIGN)
#define MULTICAST_CAM_TABLE_NUM 4
@@ -335,9 +342,15 @@ struct temac_local {
struct mii_bus *mii_bus;/* MII bus reference */
int mdio_irqs[PHY_MAX_ADDR];/* IRQs table for MDIO bus */
- /* IO registers and IRQs */
+ /* IO registers, dma functions and IRQs */
void __iomem *regs;
+ void __iomem *sdma_regs;
+#ifdef CONFIG_PPC_DCR
dcr_host_t sdma_dcrs;
+#endif
+ u32 (*dma_in)(struct temac_local *, int);
+ void (*dma_out)(struct temac_local *, int, u32);
+
int tx_irq;
int rx_irq;
int emac_num;
diff --git a/drivers/net/ll_temac_main.c b/drivers/net/ll_temac_main.c
index a18e348..9aedf9b 100644
--- a/drivers/net/ll_temac_main.c
+++ b/drivers/net/ll_temac_main.c
@@ -20,9 +20,6 @@
* or rx, so this should be okay.
*
* TODO:
- * - Fix driver to work on more than just Virtex5. Right now the driver
- * assumes that the locallink DMA registers are accessed via DCR
- * instructions.
* - Factor out locallink DMA code into separate driver
* - Fix multicast assignment.
* - Fix support for hardware checksumming.
@@ -115,17 +112,86 @@ void temac_indirect_out32(struct temac_local *lp, int
reg, u32 value)
temac_iow(lp, XTE_CTL0_OFFSET, CNTLREG_WRITE_ENABLE_MASK | reg);
}
+/**
+ * temac_dma_in32 - Memory mapped DMA read, this function expects a
+ * register input that is based on DCR word addresses which
+ * are then converted to memory mapped byte addresses
+ */
static u32 temac_dma_in32(struct temac_local *lp, int reg)
{
- return dcr_read(lp-sdma_dcrs, reg);
+ return in_be32((u32 *)(lp-sdma_regs + (reg 2)));
}
+/**
+ * temac_dma_out32 - Memory mapped DMA read, this function expects a
+ * register input that is based on DCR word addresses which
+ * are then converted to memory mapped byte addresses
+ */
static void temac_dma_out32(struct temac_local *lp, int reg, u32 value)
{
+ out_be32((u32 *)(lp-sdma_regs + (reg 2)), value);
+}
+
+/* DMA register access functions can be DCR based or memory mapped.
+ * The PowerPC 440 is DCR based, the PowerPC 405 and MicroBlaze are both
+ * memory mapped.
+ */
+#ifdef CONFIG_PPC_DCR
+
+/**
+ * temac_dma_dcr_in32 - DCR based DMA read
+ */
+static u32 temac_dma_dcr_in(struct temac_local *lp, int reg)
+{
+ return dcr_read(lp-sdma_dcrs, reg);
+}
+
+/**
+ * temac_dma_dcr_out32 - DCR based DMA write
+ */
+static void temac_dma_dcr_out(struct temac_local *lp, int reg, u32 value)
+{
dcr_write(lp-sdma_dcrs, reg, value);
}
/**
+ * temac_dcr_setup - If the DMA is DCR based, then setup the address and
+ * I/O functions
+ */
+static int temac_dcr_setup(struct temac_local *lp, struct of_device *op,
+ struct device_node *np)
+{
+ unsigned int dcrs;
+
+ /* setup the dcr address mapping if it's in the device tree */
+
+ dcrs = dcr_resource_start(np, 0);
+ if (dcrs
