Re: [PATCH 00/18] Initial Prefixed Instruction support
On 26/11/19 4:21 pm, Jordan Niethe wrote: A future revision of the ISA will introduce prefixed instructions. A prefixed instruction is composed of a 4-byte prefix followed by a 4-byte suffix. All prefixes have the major opcode 1. A prefix will never be a valid word instruction. A suffix may be an existing word instruction or a new instruction. The new instruction formats are: * Eight-Byte Load/Store Instructions * Eight-Byte Register-to-Register Instructions * Modified Load/Store Instructions * Modified Register-to-Register Instructions This series enables prefixed instructions and extends the instruction emulation to support them. Then the places where prefixed instructions might need to be emulated are updated. A future series will add prefixed instruction support to guests running in KVM. Snowpatch found sparse warnings: https://openpower.xyz/job/snowpatch/job/snowpatch-linux-sparse/14381//artifact/linux/report.txt (And a few minor checkpatch things too) -- Andrew Donnellan OzLabs, ADL Canberra a...@linux.ibm.com IBM Australia Limited
[PATCH 00/18] Initial Prefixed Instruction support
A future revision of the ISA will introduce prefixed instructions. A prefixed instruction is composed of a 4-byte prefix followed by a 4-byte suffix. All prefixes have the major opcode 1. A prefix will never be a valid word instruction. A suffix may be an existing word instruction or a new instruction. The new instruction formats are: * Eight-Byte Load/Store Instructions * Eight-Byte Register-to-Register Instructions * Modified Load/Store Instructions * Modified Register-to-Register Instructions This series enables prefixed instructions and extends the instruction emulation to support them. Then the places where prefixed instructions might need to be emulated are updated. A future series will add prefixed instruction support to guests running in KVM. Alistair Popple (1): powerpc: Enable Prefixed Instructions Jordan Niethe (17): powerpc: Add BOUNDARY SRR1 bit for future ISA version powerpc: Add PREFIXED SRR1 bit for future ISA version powerpc: Rename Bit 35 of SRR1 to indicate new purpose powerpc sstep: Prepare to support prefixed instructions powerpc sstep: Add support for prefixed integer load/stores powerpc sstep: Add support for prefixed floating-point load/stores powerpc sstep: Add support for prefixed VSX load/stores powerpc sstep: Add support for prefixed fixed-point arithmetic powerpc: Support prefixed instructions in alignment handler powerpc/traps: Check for prefixed instructions in facility_unavailable_exception() powerpc/xmon: Add initial support for prefixed instructions powerpc/xmon: Dump prefixed instructions powerpc/kprobes: Support kprobes on prefixed instructions powerpc/uprobes: Add support for prefixed instructions powerpc/hw_breakpoints: Initial support for prefixed instructions powerpc: Add prefix support to mce_find_instr_ea_and_pfn() powerpc/fault: Use analyse_instr() to check for store with updates to sp arch/powerpc/include/asm/kprobes.h| 5 +- arch/powerpc/include/asm/ppc-opcode.h | 3 + arch/powerpc/include/asm/reg.h| 7 +- arch/powerpc/include/asm/sstep.h | 8 +- arch/powerpc/include/asm/uaccess.h| 30 + arch/powerpc/include/asm/uprobes.h| 18 ++- arch/powerpc/kernel/align.c | 8 +- arch/powerpc/kernel/dt_cpu_ftrs.c | 23 arch/powerpc/kernel/hw_breakpoint.c | 8 +- arch/powerpc/kernel/kprobes.c | 46 +-- arch/powerpc/kernel/mce_power.c | 6 +- arch/powerpc/kernel/optprobes.c | 31 +++-- arch/powerpc/kernel/optprobes_head.S | 6 + arch/powerpc/kernel/traps.c | 18 ++- arch/powerpc/kernel/uprobes.c | 4 +- arch/powerpc/kvm/book3s_hv_nested.c | 2 +- arch/powerpc/kvm/book3s_hv_rm_mmu.c | 2 +- arch/powerpc/kvm/emulate_loadstore.c | 2 +- arch/powerpc/lib/sstep.c | 180 +- arch/powerpc/lib/test_emulate_step.c | 30 ++--- arch/powerpc/mm/fault.c | 39 ++ arch/powerpc/xmon/xmon.c | 132 +++ 22 files changed, 490 insertions(+), 118 deletions(-) -- 2.20.1
