Re: [PATCH 03/17] powerpc/qspinlock: use a half-word store to unlock to avoid larx/stcx.

2022-11-10 Thread Nicholas Piggin
On Thu Nov 10, 2022 at 10:39 AM AEST, Jordan Niethe wrote: > On Thu, 2022-07-28 at 16:31 +1000, Nicholas Piggin wrote: > [resend as utf-8, not utf-7] > > The first 16 bits of the lock are only modified by the owner, and other > > modifications always use atomic operations on the entire 32 bits, so

Re: [PATCH 03/17] powerpc/qspinlock: use a half-word store to unlock to avoid larx/stcx.

2022-11-09 Thread Jordan Niethe
On Thu, 2022-07-28 at 16:31 +1000, Nicholas Piggin wrote: [resend as utf-8, not utf-7] > The first 16 bits of the lock are only modified by the owner, and other > modifications always use atomic operations on the entire 32 bits, so > unlocks can use plain stores on the 16 bits. This is the same

Re: [PATCH 03/17] powerpc/qspinlock: use a half-word store to unlock to avoid larx/stcx.

2022-08-09 Thread Jordan Niethe
On Thu, 2022-07-28 at 16:31 +1000, Nicholas Piggin wrote: > The first 16 bits of the lock are only modified by the owner, and other > modifications always use atomic operations on the entire 32 bits, so > unlocks can use plain stores on the 16 bits. This is the same kind of > optimisation done by

[PATCH 03/17] powerpc/qspinlock: use a half-word store to unlock to avoid larx/stcx.

2022-07-28 Thread Nicholas Piggin
The first 16 bits of the lock are only modified by the owner, and other modifications always use atomic operations on the entire 32 bits, so unlocks can use plain stores on the 16 bits. This is the same kind of optimisation done by core qspinlock code. --- arch/powerpc/include/asm/qspinlock.h