Re: [PATCH 09/13] KVM: PPC: Book3S HV: Adapt TLB invalidations to work on POWER9

On Sat, 2016-11-19 at 15:14 +1100, Paul Mackerras wrote: > > > These should be a device-tree property. We can fallback to hard wired > > values if it doesn't exist but we should at least look for one. > > Tell me what the property is called and I'll add code to use it. :) > That's the whole

Re: [PATCH 09/13] KVM: PPC: Book3S HV: Adapt TLB invalidations to work on POWER9

On Sat, Nov 19, 2016 at 08:57:28AM +1100, Benjamin Herrenschmidt wrote: > On Fri, 2016-11-18 at 20:11 +0530, Aneesh Kumar K.V wrote: > > > +  * Work out how many sets the TLB has, for the use of > > > +  * the TLB invalidation loop in book3s_hv_rmhandlers.S. > > > +  */ > > > + if

Re: [PATCH 09/13] KVM: PPC: Book3S HV: Adapt TLB invalidations to work on POWER9

On Fri, Nov 18, 2016 at 08:11:34PM +0530, Aneesh Kumar K.V wrote: > > @@ -3287,6 +3290,17 @@ static int kvmppc_core_init_vm_hv(struct kvm *kvm) > > kvm->arch.lpcr = lpcr; > > > > /* > > +* Work out how many sets the TLB has, for the use of > > +* the TLB invalidation loop in

Re: [PATCH 09/13] KVM: PPC: Book3S HV: Adapt TLB invalidations to work on POWER9

On Fri, 2016-11-18 at 20:11 +0530, Aneesh Kumar K.V wrote: > > +  * Work out how many sets the TLB has, for the use of > > +  * the TLB invalidation loop in book3s_hv_rmhandlers.S. > > +  */ > > + if (cpu_has_feature(CPU_FTR_ARCH_300)) > > + kvm->arch.tlb_sets = 256;

Re: [PATCH 09/13] KVM: PPC: Book3S HV: Adapt TLB invalidations to work on POWER9

Paul Mackerras writes: > POWER9 adds new capabilities to the tlbie (TLB invalidate entry) > and tlbiel (local tlbie) instructions. Both instructions get a > set of new parameters (RIC, PRS and R) which appear as bits in the > instruction word. The tlbiel instruction now has

[PATCH 09/13] KVM: PPC: Book3S HV: Adapt TLB invalidations to work on POWER9

POWER9 adds new capabilities to the tlbie (TLB invalidate entry) and tlbiel (local tlbie) instructions. Both instructions get a set of new parameters (RIC, PRS and R) which appear as bits in the instruction word. The tlbiel instruction now has a second register operand, which contains a PID