"Oliver O'Halloran" writes:
> On Tue, Oct 1, 2019 at 3:09 AM Bjorn Helgaas wrote:
>> On Mon, Sep 30, 2019 at 12:08:46PM +1000, Oliver O'Halloran wrote:
>> This is all powerpc, so I assume Michael will handle this. Just
>> random things I noticed; ignore if they don't make sense:
>>
>> > On Power
On 30/09/2019 12:08, Oliver O'Halloran wrote:
> On PowerNV we use the pcibios_sriov_enable() hook to do two things:
>
> 1. Create a pci_dn structure for each of the VFs, and
> 2. Configure the PHB's internal BARs that map MMIO ranges to PEs
>so that each VF has it's own PE. Note that the PE
On Tue, Oct 1, 2019 at 3:09 AM Bjorn Helgaas wrote:
>
> On Mon, Sep 30, 2019 at 12:08:46PM +1000, Oliver O'Halloran wrote:
>
> This is all powerpc, so I assume Michael will handle this. Just
> random things I noticed; ignore if they don't make sense:
>
> > On PowerNV we use the pcibios_sriov_enab
On Mon, Sep 30, 2019 at 12:08:46PM +1000, Oliver O'Halloran wrote:
This is all powerpc, so I assume Michael will handle this. Just
random things I noticed; ignore if they don't make sense:
> On PowerNV we use the pcibios_sriov_enable() hook to do two things:
>
> 1. Create a pci_dn structure for
On PowerNV we use the pcibios_sriov_enable() hook to do two things:
1. Create a pci_dn structure for each of the VFs, and
2. Configure the PHB's internal BARs that map MMIO ranges to PEs
so that each VF has it's own PE. Note that the PE also determines
the IOMMU table the HW uses for the dev
