Re: [PATCH 2/2] KVM: PPC: hypervisor large decrementer support

2016-06-22 Thread oliver
On Wed, Jun 1, 2016 at 4:23 PM, Michael Neuling wrote: > On Tue, 2016-05-31 at 17:16 +1000, Oliver O'Halloran wrote: >> +#define IS_LD_ENABLED(reg) \ >> + mfspr reg,SPRN_LPCR; \ >> + andis. reg,reg,(LPCR_LD >> 16); > > FWIW you can use: >

Re: [PATCH 2/2] KVM: PPC: hypervisor large decrementer support

2016-06-07 Thread Michael Ellerman
On Fri, 2016-06-03 at 07:46 +1000, Benjamin Herrenschmidt wrote: > On Wed, 2016-06-01 at 16:23 +1000, Michael Neuling wrote: > > FWIW you can use: > > andis. reg,reg,(LPCR_LD)@ha > > @h in that case. Probably the same result but technically @ha is for > arithmetic operations. In this

Re: [PATCH 2/2] KVM: PPC: hypervisor large decrementer support

2016-06-02 Thread Benjamin Herrenschmidt
On Wed, 2016-06-01 at 16:23 +1000, Michael Neuling wrote: > FWIW you can use: >         andis. reg,reg,(LPCR_LD)@ha @h in that case. Probably the same result but technically @ha is for arithmetic operations. Cheers, Ben. ___ Linuxppc-dev mailing list

Re: [PATCH 2/2] KVM: PPC: hypervisor large decrementer support

2016-06-01 Thread Michael Neuling
On Tue, 2016-05-31 at 17:16 +1000, Oliver O'Halloran wrote: > Power ISAv3 extends the width of the decrementer register from 32 bits. > The enlarged register width is implementation dependent, but reads from > these registers are automatically sign extended to produce a 64 bit > output when

[PATCH 2/2] KVM: PPC: hypervisor large decrementer support

2016-05-31 Thread Oliver O'Halloran
Power ISAv3 extends the width of the decrementer register from 32 bits. The enlarged register width is implementation dependent, but reads from these registers are automatically sign extended to produce a 64 bit output when operating in large mode. The HDEC always operates in large mode while the

Re: [PATCH 2/2] KVM: PPC: hypervisor large decrementer support

2016-04-12 Thread Balbir Singh
On 12/04/16 14:38, Oliver O'Halloran wrote: > Power ISAv3 extends the width of the decrementer register from 32 bits. > The enlarged register width is implementation dependent, but reads from > these registers are automatically sign extended to produce a 64 bit output > when operating in large

Re: [PATCH 2/2] KVM: PPC: hypervisor large decrementer support

2016-04-11 Thread kbuild test robot
Hi Oliver, [auto build test WARNING on powerpc/next] [also build test WARNING on v4.6-rc3 next-20160411] [if your patch is applied to the wrong git tree, please drop us a note to help improving the system] url:

[PATCH 2/2] KVM: PPC: hypervisor large decrementer support

2016-04-11 Thread Oliver O'Halloran
Power ISAv3 extends the width of the decrementer register from 32 bits. The enlarged register width is implementation dependent, but reads from these registers are automatically sign extended to produce a 64 bit output when operating in large mode. The HDEC always operates in large mode while the