> On 09-Mar-2024, at 11:13 PM, Segher Boessenkool
> wrote:
>
> All instructions with a primary opcode from 32 to 63 are memory insns,
> and no others. It's trivial to see whether it is a load or store, too
> (just bit 3 of the insn). Trying to parse disassembled code is much
> harder, and
All instructions with a primary opcode from 32 to 63 are memory insns,
and no others. It's trivial to see whether it is a load or store, too
(just bit 3 of the insn). Trying to parse disassembled code is much
harder, and you easily make some mistakes here.
On Sat, Mar 09, 2024 at 12:55:12PM
To identify if the instruction has any memory reference,
"memory_ref_char" field needs to be set for specific architecture.
Example memory instruction:
lwz r10,0(r9)
Here "(" is the memory_ref_char. Set this as part of arch->objdump
To get register number and access offset from the given
To identify if the instruction has any memory reference,
"memory_ref_char" field needs to be set for specific architecture.
Example memory instruction:
lwz r10,0(r9)
Here "(" is the memory_ref_char. Set this as part of arch->objdump
To get register number and access offset from the given
