Re: [PATCH 3/3] powerpc/corenet: add support for the kmcent2 board
On 15/12/16 15:00, Joakim Tjernlund wrote:
> On Thu, 2016-12-15 at 14:22 +0100, Valentin Longchamp wrote:
>> This board is built around Freescale's T1040 SoC.
>>
>> The peripherals used by this design are:
>> - DDR3 RAM with SPD support
>> - parallel NOR Flash as boot medium
>> - 1 PCIe bus (PCIe1 x1)
>> - 3 FMAN Ethernet devices (FMAN1 DTSEC1/2/5)
>> - 4 IFC bus devices:
>> - NOR flash
>> - NAND flash
>> - QRIO reset/power mgmt CPLD
>> - BFTIC chassis management CPLD
>> - 2 I2C buses
>> - 1 SPI bus
>> - HDLC bus with the QE's UCC1
>> - last but not least, the mandatory serial port
>>
>> The board can be used with the corenet32_smp_defconfig.
>>
>> Signed-off-by: Valentin Longchamp
>> ---
>> arch/powerpc/boot/dts/fsl/kmcent2.dts | 303
>> ++
>> arch/powerpc/platforms/85xx/corenet_generic.c | 1 +
>> 2 files changed, 304 insertions(+)
>> create mode 100644 arch/powerpc/boot/dts/fsl/kmcent2.dts
>>
>> diff --git a/arch/powerpc/boot/dts/fsl/kmcent2.dts
>> b/arch/powerpc/boot/dts/fsl/kmcent2.dts
>> new file mode 100644
>> index 000..47afa43
>> --- /dev/null
>> +++ b/arch/powerpc/boot/dts/fsl/kmcent2.dts
>> @@ -0,0 +1,303 @@
>> +/*
>> + * Keymile kmcent2 Device Tree Source, based on T1040RDB DTS
>> + *
>> + * (C) Copyright 2016
>> + * Valentin Longchamp, Keymile AG, valentin.longch...@keymile.com
>> + *
>> + * Copyright 2014 - 2015 Freescale Semiconductor Inc.
>> + *
>> + * This program is free software; you can redistribute it and/or modify it
>> + * under the terms of the GNU General Public License as published by the
>> + * Free Software Foundation; either version 2 of the License, or (at your
>> + * option) any later version.
>> + */
>> +
>
> [SNIP]
>
>> +
>> +ucc_hdlc: ucc@2000 {
>> +device_type = "hdlc";
>> +compatible = "fsl,ucc-hdlc";
>> +rx-clock-name = "clk9";
>> +tx-clock-name = "clk9";
>
> Should it be clk9 on both tx and rx clock?
>
Yeah, why not ? The bus clock is generated somewhere else and is connected to
the clk9 input. Or maybe have I not understood your question ?
Re: [PATCH 3/3] powerpc/corenet: add support for the kmcent2 board
On Thu, 2016-12-15 at 14:22 +0100, Valentin Longchamp wrote:
> This board is built around Freescale's T1040 SoC.
>
> The peripherals used by this design are:
> - DDR3 RAM with SPD support
> - parallel NOR Flash as boot medium
> - 1 PCIe bus (PCIe1 x1)
> - 3 FMAN Ethernet devices (FMAN1 DTSEC1/2/5)
> - 4 IFC bus devices:
> - NOR flash
> - NAND flash
> - QRIO reset/power mgmt CPLD
> - BFTIC chassis management CPLD
> - 2 I2C buses
> - 1 SPI bus
> - HDLC bus with the QE's UCC1
> - last but not least, the mandatory serial port
>
> The board can be used with the corenet32_smp_defconfig.
>
> Signed-off-by: Valentin Longchamp
> ---
> arch/powerpc/boot/dts/fsl/kmcent2.dts | 303
> ++
> arch/powerpc/platforms/85xx/corenet_generic.c | 1 +
> 2 files changed, 304 insertions(+)
> create mode 100644 arch/powerpc/boot/dts/fsl/kmcent2.dts
>
> diff --git a/arch/powerpc/boot/dts/fsl/kmcent2.dts
> b/arch/powerpc/boot/dts/fsl/kmcent2.dts
> new file mode 100644
> index 000..47afa43
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/fsl/kmcent2.dts
> @@ -0,0 +1,303 @@
> +/*
> + * Keymile kmcent2 Device Tree Source, based on T1040RDB DTS
> + *
> + * (C) Copyright 2016
> + * Valentin Longchamp, Keymile AG, valentin.longch...@keymile.com
> + *
> + * Copyright 2014 - 2015 Freescale Semiconductor Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + */
> +
[SNIP]
> +
> + ucc_hdlc: ucc@2000 {
> + device_type = "hdlc";
> + compatible = "fsl,ucc-hdlc";
> + rx-clock-name = "clk9";
> + tx-clock-name = "clk9";
Should it be clk9 on both tx and rx clock?
Jocke
[PATCH 3/3] powerpc/corenet: add support for the kmcent2 board
This board is built around Freescale's T1040 SoC.
The peripherals used by this design are:
- DDR3 RAM with SPD support
- parallel NOR Flash as boot medium
- 1 PCIe bus (PCIe1 x1)
- 3 FMAN Ethernet devices (FMAN1 DTSEC1/2/5)
- 4 IFC bus devices:
- NOR flash
- NAND flash
- QRIO reset/power mgmt CPLD
- BFTIC chassis management CPLD
- 2 I2C buses
- 1 SPI bus
- HDLC bus with the QE's UCC1
- last but not least, the mandatory serial port
The board can be used with the corenet32_smp_defconfig.
Signed-off-by: Valentin Longchamp
---
arch/powerpc/boot/dts/fsl/kmcent2.dts | 303 ++
arch/powerpc/platforms/85xx/corenet_generic.c | 1 +
2 files changed, 304 insertions(+)
create mode 100644 arch/powerpc/boot/dts/fsl/kmcent2.dts
diff --git a/arch/powerpc/boot/dts/fsl/kmcent2.dts
b/arch/powerpc/boot/dts/fsl/kmcent2.dts
new file mode 100644
index 000..47afa43
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/kmcent2.dts
@@ -0,0 +1,303 @@
+/*
+ * Keymile kmcent2 Device Tree Source, based on T1040RDB DTS
+ *
+ * (C) Copyright 2016
+ * Valentin Longchamp, Keymile AG, valentin.longch...@keymile.com
+ *
+ * Copyright 2014 - 2015 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/include/ "t104xsi-pre.dtsi"
+
+/ {
+ model = "keymile,kmcent2";
+ compatible = "keymile,kmcent2";
+
+ aliases {
+ front_phy = &front_phy;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ bman_fbpr: bman-fbpr {
+ size = <0 0x100>;
+ alignment = <0 0x100>;
+ };
+ qman_fqd: qman-fqd {
+ size = <0 0x40>;
+ alignment = <0 0x40>;
+ };
+ qman_pfdr: qman-pfdr {
+ size = <0 0x200>;
+ alignment = <0 0x200>;
+ };
+ };
+
+ ifc: localbus@ffe124000 {
+ reg = <0xf 0xfe124000 0 0x2000>;
+ ranges = <0 0 0xf 0xe800 0x0400
+ 1 0 0xf 0xfa00 0x0001
+ 2 0 0xf 0xfb00 0x0001
+ 4 0 0xf 0xc000 0x0800
+ 6 0 0xf 0xd000 0x0800
+ 7 0 0xf 0xd800 0x0800>;
+
+ nor@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x0400>;
+ bank-width = <2>;
+ device-width = <2>;
+ };
+
+ nand@1,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,ifc-nand";
+ reg = <0x1 0x0 0x1>;
+ };
+
+ board-control@2,0 {
+ compatible = "keymile,qriox";
+ reg = <0x2 0x0 0x80>;
+ };
+
+ chassis-mgmt@6,0 {
+ compatible = "keymile,bfticu";
+ reg = <6 0 0x100>;
+ interrupt-controller;
+ interrupt-parent = <&mpic>;
+ interrupts = <11 1 0 0>;
+ #interrupt-cells = <1>;
+ };
+
+ };
+
+ memory {
+ device_type = "memory";
+ };
+
+ dcsr: dcsr@f {
+ ranges = <0x 0xf 0x 0x01072000>;
+ };
+
+ bportals: bman-portals@ff400 {
+ ranges = <0x0 0xf 0xf400 0x200>;
+ };
+
+ qportals: qman-portals@ff600 {
+ ranges = <0x0 0xf 0xf600 0x200>;
+ };
+
+ soc: soc@ffe00 {
+ ranges = <0x 0xf 0xfe00 0x100>;
+ reg = <0xf 0xfe00 0 0x1000>;
+
+ spi@11 {
+ network-clock@1 {
+ compatible = "zarlink,zl30364";
+ reg = <1>;
+ spi-max-frequency = <100>;
+ };
+ };
+
+ sdhc@114000 {
+ status = "disabled";
+ };
+
+ i2c@118000 {
+ clock-frequency = <10>;
+
+ mux@70 {
+ compatible = "nxp,pca9547";
+ reg = <0x70>;
+ #address-cells = <1>;
+
