On 05/06/2014 04:12 PM, Aneesh Kumar K.V wrote:
Alexander Graf writes:
On 06.05.14 02:41, Paul Mackerras wrote:
On Mon, May 05, 2014 at 01:19:30PM +0200, Alexander Graf wrote:
On 05/04/2014 07:21 PM, Aneesh Kumar K.V wrote:
+#ifdef CONFIG_PPC_BOOK3S_64
+ return vcpu->arch.fault_dar;
Alexander Graf writes:
> On 06.05.14 02:41, Paul Mackerras wrote:
>> On Mon, May 05, 2014 at 01:19:30PM +0200, Alexander Graf wrote:
>>> On 05/04/2014 07:21 PM, Aneesh Kumar K.V wrote:
+#ifdef CONFIG_PPC_BOOK3S_64
+ return vcpu->arch.fault_dar;
>>> How about PA6T and G5s?
>> G5 sets DA
Alexander Graf writes:
> On 06.05.14 02:41, Paul Mackerras wrote:
>> On Mon, May 05, 2014 at 01:19:30PM +0200, Alexander Graf wrote:
>>> On 05/04/2014 07:21 PM, Aneesh Kumar K.V wrote:
+#ifdef CONFIG_PPC_BOOK3S_64
+ return vcpu->arch.fault_dar;
>>> How about PA6T and G5s?
>> G5 sets DA
On 06.05.14 02:41, Paul Mackerras wrote:
On Mon, May 05, 2014 at 01:19:30PM +0200, Alexander Graf wrote:
On 05/04/2014 07:21 PM, Aneesh Kumar K.V wrote:
+#ifdef CONFIG_PPC_BOOK3S_64
+ return vcpu->arch.fault_dar;
How about PA6T and G5s?
G5 sets DAR on an alignment interrupt.
As for PA
On Mon, May 05, 2014 at 01:19:30PM +0200, Alexander Graf wrote:
> On 05/04/2014 07:21 PM, Aneesh Kumar K.V wrote:
> >+#ifdef CONFIG_PPC_BOOK3S_64
> >+return vcpu->arch.fault_dar;
>
> How about PA6T and G5s?
G5 sets DAR on an alignment interrupt.
As for PA6T, I don't know for sure, but if it
On Mon, 2014-05-05 at 16:43 +0200, Alexander Graf wrote:
> > Paul mentioned that BOOK3S always had DAR value set on alignment
> > interrupt. And the patch is to enable/collect correct DAR value when
> > running with Little Endian PR guest. Now to limit the impact and to
> > enable Little Endian PR
On Mon, 2014-05-05 at 19:56 +0530, Aneesh Kumar K.V wrote:
>
> Paul mentioned that BOOK3S always had DAR value set on alignment
> interrupt. And the patch is to enable/collect correct DAR value when
> running with Little Endian PR guest. Now to limit the impact and to
> enable Little Endian PR gue
2014-05-05 8:03 GMT-07:00 Aneesh Kumar K.V :
> Olof Johansson writes:
>
>> 2014-05-05 7:43 GMT-07:00 Alexander Graf :
>>
>>> On 05/05/2014 04:26 PM, Aneesh Kumar K.V wrote:
>>>
Alexander Graf writes:
On 05/04/2014 07:21 PM, Aneesh Kumar K.V wrote:
>
>> Although it's option
Am 05.05.14 16:57, schrieb Olof Johansson:
[Now without HTML email -- it's what you get for cc:ing me at work
instead of my upstream email :)]
2014-05-05 7:43 GMT-07:00 Alexander Graf :
On 05/05/2014 04:26 PM, Aneesh Kumar K.V wrote:
Alexander Graf writes:
On 05/04/2014 07:21 PM, Aneesh Kum
> Am 05.05.2014 um 16:50 schrieb "Aneesh Kumar K.V"
> :
>
> Alexander Graf writes:
>
>>> On 05/05/2014 04:26 PM, Aneesh Kumar K.V wrote:
>>> Alexander Graf writes:
>>>
> On 05/04/2014 07:21 PM, Aneesh Kumar K.V wrote:
> Although it's optional IBM POWER cpus always had DAR value set
> Am 05.05.2014 um 16:57 schrieb Olof Johansson :
>
> [Now without HTML email -- it's what you get for cc:ing me at work
> instead of my upstream email :)]
>
> 2014-05-05 7:43 GMT-07:00 Alexander Graf :
>>
>>> On 05/05/2014 04:26 PM, Aneesh Kumar K.V wrote:
>>>
>>> Alexander Graf writes:
>>>
[Now without HTML email -- it's what you get for cc:ing me at work
instead of my upstream email :)]
2014-05-05 7:43 GMT-07:00 Alexander Graf :
>
> On 05/05/2014 04:26 PM, Aneesh Kumar K.V wrote:
>>
>> Alexander Graf writes:
>>
>>> On 05/04/2014 07:21 PM, Aneesh Kumar K.V wrote:
Although
Olof Johansson writes:
> 2014-05-05 7:43 GMT-07:00 Alexander Graf :
>
>> On 05/05/2014 04:26 PM, Aneesh Kumar K.V wrote:
>>
>>> Alexander Graf writes:
>>>
>>> On 05/04/2014 07:21 PM, Aneesh Kumar K.V wrote:
> Although it's optional IBM POWER cpus always had DAR value set on
> align
Alexander Graf writes:
> On 05/05/2014 04:26 PM, Aneesh Kumar K.V wrote:
>> Alexander Graf writes:
>>
>>> On 05/04/2014 07:21 PM, Aneesh Kumar K.V wrote:
Although it's optional IBM POWER cpus always had DAR value set on
alignment interrupt. So don't try to compute these values.
>>
On 05/05/2014 04:26 PM, Aneesh Kumar K.V wrote:
Alexander Graf writes:
On 05/04/2014 07:21 PM, Aneesh Kumar K.V wrote:
Although it's optional IBM POWER cpus always had DAR value set on
alignment interrupt. So don't try to compute these values.
Signed-off-by: Aneesh Kumar K.V
---
Changes fro
Alexander Graf writes:
> On 05/04/2014 07:21 PM, Aneesh Kumar K.V wrote:
>> Although it's optional IBM POWER cpus always had DAR value set on
>> alignment interrupt. So don't try to compute these values.
>>
>> Signed-off-by: Aneesh Kumar K.V
>> ---
>> Changes from V3:
>> * Use make_dsisr instead
On 05/04/2014 07:21 PM, Aneesh Kumar K.V wrote:
Although it's optional IBM POWER cpus always had DAR value set on
alignment interrupt. So don't try to compute these values.
Signed-off-by: Aneesh Kumar K.V
---
Changes from V3:
* Use make_dsisr instead of checking feature flag to decide whether t
Although it's optional IBM POWER cpus always had DAR value set on
alignment interrupt. So don't try to compute these values.
Signed-off-by: Aneesh Kumar K.V
---
Changes from V3:
* Use make_dsisr instead of checking feature flag to decide whether to use
saved dsisr or not
arch/powerpc/include/
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