[PATCH v1 38/55] KVM: PPC: Book3S HV P9: Restrict DSISR canary workaround to processors that require it

[Nicholas Piggin]

Use CPU_FTR_P9_RADIX_PREFETCH_BUG for this, to test for DD2.1 and below
processors.

-43 cycles (7178) POWER9 virt-mode NULL hcall

Signed-off-by: Nicholas Piggin <npig...@gmail.com>
---
 arch/powerpc/kvm/book3s_hv.c          | 3 ++-
 arch/powerpc/kvm/book3s_hv_p9_entry.c | 6 ++++--
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index e7dfc33e2b38..47ccea5ffba2 100644
--- a/arch/powerpc/kvm/book3s_hv.c
+++ b/arch/powerpc/kvm/book3s_hv.c
@@ -1598,7 +1598,8 @@ XXX benchmark guest exits
                unsigned long vsid;
                long err;
 
-               if (vcpu->arch.fault_dsisr == HDSISR_CANARY) {
+               if (cpu_has_feature(CPU_FTR_P9_RADIX_PREFETCH_BUG) &&
+                   unlikely(vcpu->arch.fault_dsisr == HDSISR_CANARY)) {
                        r = RESUME_GUEST; /* Just retry if it's the canary */
                        break;
                }
diff --git a/arch/powerpc/kvm/book3s_hv_p9_entry.c 
b/arch/powerpc/kvm/book3s_hv_p9_entry.c
index 737d4eaf74bc..d83b5d4d02c1 100644
--- a/arch/powerpc/kvm/book3s_hv_p9_entry.c
+++ b/arch/powerpc/kvm/book3s_hv_p9_entry.c
@@ -671,9 +671,11 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 
time_limit, unsigned long lpc
         * HDSI which should correctly update the HDSISR the second time HDSI
         * entry.
         *
-        * Just do this on all p9 processors for now.
+        * The "radix prefetch bug" test can be used to test for this bug, as
+        * it also exists fo DD2.1 and below.
         */
-       mtspr(SPRN_HDSISR, HDSISR_CANARY);
+       if (cpu_has_feature(CPU_FTR_P9_RADIX_PREFETCH_BUG))
+               mtspr(SPRN_HDSISR, HDSISR_CANARY);
 
        mtspr(SPRN_SPRG0, vcpu->arch.shregs.sprg0);
        mtspr(SPRN_SPRG1, vcpu->arch.shregs.sprg1);
-- 
2.23.0