From: Wang Dongsheng dongsheng.w...@freescale.com
Each core's AltiVec unit may be placed into a power savings mode
by turning off power to the unit. Core hardware will automatically
power down the AltiVec unit after no AltiVec instructions have
executed in N cycles. The AltiVec power-control is triggered by hardware.
Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
*v2:
Remove:
delete setup_idle_hw_governor function.
delete Fix erratum for rev1.
Move:
move setup_* into __setup/restore_cpu_e6500.
diff --git a/arch/powerpc/include/asm/reg_booke.h
b/arch/powerpc/include/asm/reg_booke.h
index 86ede76..8364bbe 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -217,6 +217,9 @@
#defineCCR1_DPC0x0100 /* Disable L1 I-Cache/D-Cache parity
checking */
#defineCCR1_TCS0x0080 /* Timer Clock Select */
+/* Bit definitions for PWRMGTCR0. */
+#define PWRMGTCR0_ALTIVEC_IDLE (1 22) /* Altivec idle enable */
+
/* Bit definitions for the MCSR. */
#define MCSR_MCS 0x8000 /* Machine Check Summary */
#define MCSR_IB0x4000 /* Instruction PLB Error */
diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index bfb18c7..90bbb46 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -58,6 +58,7 @@ _GLOBAL(__setup_cpu_e6500)
#ifdef CONFIG_PPC64
bl .setup_altivec_ivors
#endif
+ bl setup_altivec_idle
bl __setup_cpu_e5500
mtlrr6
blr
@@ -119,6 +120,7 @@ _GLOBAL(__setup_cpu_e5500)
_GLOBAL(__restore_cpu_e6500)
mflrr5
bl .setup_altivec_ivors
+ bl setup_altivec_idle
bl __restore_cpu_e5500
mtlrr5
blr
diff --git a/arch/powerpc/platforms/85xx/common.c
b/arch/powerpc/platforms/85xx/common.c
index d0861a0..93b563b 100644
--- a/arch/powerpc/platforms/85xx/common.c
+++ b/arch/powerpc/platforms/85xx/common.c
@@ -11,6 +11,16 @@
#include mpc85xx.h
+#define MAX_BIT64
+
+#define ALTIVEC_COUNT_OFFSET 16
+#define ALTIVEC_IDLE_COUNT_MASK0x003f
+
+/*
+ * FIXME - We don't know the AltiVec application scenarios.
+ */
+#define ALTIVEC_IDLE_TIME_BIT 14 /* 1ms */
+
static struct of_device_id __initdata mpc85xx_common_ids[] = {
{ .type = soc, },
{ .compatible = soc, },
@@ -80,3 +90,38 @@ void __init mpc85xx_cpm2_pic_init(void)
irq_set_chained_handler(irq, cpm2_cascade);
}
#endif
+
+static bool has_pw20_altivec_idle(void)
+{
+ u32 pvr;
+
+ pvr = mfspr(SPRN_PVR);
+
+ /* PW20 AltiVec idle feature only exists for E6500 */
+ if (PVR_VER(pvr) != PVR_VER_E6500)
+ return false;
+
+ return true;
+}
+
+void setup_altivec_idle(void)
+{
+ u32 altivec_idle;
+
+ if (!has_pw20_altivec_idle())
+ return;
+
+ /* Enable Altivec Idle */
+ altivec_idle = mfspr(SPRN_PWRMGTCR0);
+ altivec_idle |= PWRMGTCR0_ALTIVEC_IDLE;
+
+ /* Set Automatic AltiVec Idle Count */
+ /* clear count */
+ altivec_idle = ~ALTIVEC_IDLE_COUNT_MASK;
+
+ /* set count */
+ altivec_idle |=
+ ((MAX_BIT - ALTIVEC_IDLE_TIME_BIT) ALTIVEC_COUNT_OFFSET);
+
+ mtspr(SPRN_PWRMGTCR0, altivec_idle);
+}
--
1.8.0
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