Re: [PATCH v2 2/5] fsl/qe: setup clock source for TDM mode

[David Miller]

From: Zhao Qiang 
Date: Thu, 2 Jun 2016 09:44:58 +0800

> +static int ucc_get_tdm_sync_source(u32 tdm_num, enum qe_clock clock,
> +enum comm_dir mode)
> +{
> + int source = -EINVAL;
> +
> + if (mode == COMM_DIR_RX && clock == QE_RSYNC_PIN) {
> + source = 0;
> + return source;
> + }
> + if (mode == COMM_DIR_TX && clock == QE_TSYNC_PIN) {
> + source = 0;
> + return source;
> + }
> +
> + switch (tdm_num) {
> + case 0:
> + case 1:
> + switch (clock) {
> + case QE_BRG9:
> + source = 1;
> + break;
> + case QE_BRG10:
> + source = 2;
> + break;

These switch case bodies are over indented.  Same goes for the rest of
this function.
___
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[PATCH v2 2/5] fsl/qe: setup clock source for TDM mode

[Zhao Qiang]

Add tdm clock configuration in both qe clock system and ucc
fast controller.

Signed-off-by: Zhao Qiang 
---
Changes for v2:
- break codes getting clock_bits and source to smaller functions.
- add __iomem to qe_mux_reg
- add bits operation functions for qe and use it
- retrun -EINVAL when clock_bits is invalid

 drivers/soc/fsl/qe/ucc.c  | 450 ++
 drivers/soc/fsl/qe/ucc_fast.c |  36 
 include/soc/fsl/qe/qe.h   |  16 ++
 include/soc/fsl/qe/ucc.h  |   4 +
 include/soc/fsl/qe/ucc_fast.h |   1 +
 5 files changed, 507 insertions(+)

diff --git a/drivers/soc/fsl/qe/ucc.c b/drivers/soc/fsl/qe/ucc.c
index b59d335..5e1a850 100644
--- a/drivers/soc/fsl/qe/ucc.c
+++ b/drivers/soc/fsl/qe/ucc.c
@@ -25,6 +25,12 @@
 #include 
 #include 
 
+#define UCC_TDM_NUM 8
+#define RX_SYNC_SHIFT_BASE 30
+#define TX_SYNC_SHIFT_BASE 14
+#define RX_CLK_SHIFT_BASE 28
+#define TX_CLK_SHIFT_BASE 12
+
 int ucc_set_qe_mux_mii_mng(unsigned int ucc_num)
 {
unsigned long flags;
@@ -210,3 +216,447 @@ int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum 
qe_clock clock,
 
return 0;
 }
+
+static int ucc_get_tdm_common_clk(u32 tdm_num, enum qe_clock clock)
+{
+   int clock_bits = -EINVAL;
+
+   /*
+* for TDM[0, 1, 2, 3], TX and RX use  common
+* clock source BRG3,4 and CLK1,2
+* for TDM[4, 5, 6, 7], TX and RX use  common
+* clock source BRG12,13 and CLK23,24
+*/
+   switch (tdm_num) {
+   case 0:
+   case 1:
+   case 2:
+   case 3:
+   switch (clock) {
+   case QE_BRG3:
+   clock_bits = 1;
+   break;
+   case QE_BRG4:
+   clock_bits = 2;
+   break;
+   case QE_CLK1:
+   clock_bits = 4;
+   break;
+   case QE_CLK2:
+   clock_bits = 5;
+   break;
+   default:
+   break;
+   }
+   break;
+   case 4:
+   case 5:
+   case 6:
+   case 7:
+   switch (clock) {
+   case QE_BRG12:
+   clock_bits = 1;
+   break;
+   case QE_BRG13:
+   clock_bits = 2;
+   break;
+   case QE_CLK23:
+   clock_bits = 4;
+   break;
+   case QE_CLK24:
+   clock_bits = 5;
+   break;
+   default:
+   break;
+   }
+   break;
+   default:
+   break;
+   }
+
+   return clock_bits;
+}
+
+static int ucc_get_tdm_rx_clk(u32 tdm_num, enum qe_clock clock)
+{
+   int clock_bits = -EINVAL;
+
+   switch (tdm_num) {
+   case 0:
+   switch (clock) {
+   case QE_CLK3:
+   clock_bits = 6;
+   break;
+   case QE_CLK8:
+   clock_bits = 7;
+   break;
+   default:
+   break;
+   }
+   break;
+   case 1:
+   switch (clock) {
+   case QE_CLK5:
+   clock_bits = 6;
+   break;
+   case QE_CLK10:
+   clock_bits = 7;
+   break;
+   default:
+   break;
+   }
+   break;
+   case 2:
+   switch (clock) {
+   case QE_CLK7:
+   clock_bits = 6;
+   break;
+   case QE_CLK12:
+   clock_bits = 7;
+   break;
+   default:
+   break;
+   }
+   break;
+   case 3:
+   switch (clock) {
+   case QE_CLK9:
+   clock_bits = 6;
+   break;
+   case QE_CLK14:
+   clock_bits = 7;
+   break;
+   default:
+   break;
+   }
+   break;
+   case 4:
+   switch (clock) {
+   case QE_CLK11:
+   clock_bits = 6;
+   break;
+   case QE_CLK16:
+   clock_bits = 7;
+   break;
+   default:
+   break;
+   }
+   break;
+   case 5:
+   switch (clock) {
+   case QE_CLK13:
+   clock_bits = 6;
+   break;
+   case QE_CLK18:
+   clock_bits = 7;
+   break;
+   default:
+