VSX vector paired instructions operates with octword (32-byte) operand for loads and stores between storage and a pair of two sequential Vector-Scalar Registers (VSRs). There are 4 word instructions and 2 prefixed instructions that provides this 32-byte storage access operations - lxvp, lxvpx, stxvp, stxvpx, plxvpx, pstxvpx.
Emulation infrastructure doesn't have support for these instructions, to operate with 32-byte storage access and to operate with 2 VSX registers. This patch series enables the instruction emulation support and adds test cases for them respectively. Changes in v3: ------------- Worked on review comments and suggestions from Ravi and Naveen, * Fix the do_vsx_load() to handle vsx instructions if MSR_FP/MSR_VEC cleared in exception conditions and it reaches to read/write to thread_struct member fp_state/vr_state respectively. * Fix wrongly used `__vector128 v[2]` in struct vsx_reg as it should hold a single vsx register size. * Remove unnecessary `VSX_CHECK_VEC` flag set and condition to check `VSX_LDLEFT` that is not applicable for these vsx instructions. * Fix comments in emulate_vsx_load() that were misleading. * Rebased on latest powerpc next branch. Changes in v2: ------------- * Fix suggestion from Sandipan, wrap ISA 3.1 instructions with cpu_has_feature(CPU_FTR_ARCH_31) check. * Rebase on latest powerpc next branch. Balamuruhan S (4): powerpc/sstep: support new VSX vector paired storage access instructions powerpc/sstep: support emulation for vsx vector paired storage access instructions powerpc ppc-opcode: add encoding macros for vsx vector paired instructions powerpc sstep: add testcases for vsx load/store instructions arch/powerpc/include/asm/ppc-opcode.h | 17 ++ arch/powerpc/lib/sstep.c | 122 +++++++++++-- arch/powerpc/lib/test_emulate_step.c | 252 ++++++++++++++++++++++++++ 3 files changed, 374 insertions(+), 17 deletions(-) base-commit: 71d7bca373d5fa0ec977ca4814f49140621bd7ae -- 2.24.1