Re: [PATCH v3 6/9] KVM: PPC: Ultravisor: Restrict flush of the partition tlb cache

2019-06-06 Thread Paul Mackerras 
On Thu, Jun 06, 2019 at 04:39:04PM -0300, Murilo Opsfelder Araújo wrote:
> Claudio Carvalho  writes:
> 
> > From: Ram Pai 
> >
> > Ultravisor is responsible for flushing the tlb cache, since it manages
> > the PATE entries. Hence skip tlb flush, if the ultravisor firmware is
> > available.
> >
> > Signed-off-by: Ram Pai 
> > Signed-off-by: Claudio Carvalho 
> > ---
> >  arch/powerpc/mm/book3s64/pgtable.c | 33 +-
> >  1 file changed, 19 insertions(+), 14 deletions(-)
> >
> > diff --git a/arch/powerpc/mm/book3s64/pgtable.c 
> > b/arch/powerpc/mm/book3s64/pgtable.c
> > index 40a9fc8b139f..1eeb5fe87023 100644
> > --- a/arch/powerpc/mm/book3s64/pgtable.c
> > +++ b/arch/powerpc/mm/book3s64/pgtable.c
> > @@ -224,6 +224,23 @@ void __init mmu_partition_table_init(void)
> > powernv_set_nmmu_ptcr(ptcr);
> >  }
> >
> > +static void flush_partition(unsigned int lpid, unsigned long dw0)
> > +{
> > +   if (dw0 & PATB_HR) {
> > +   asm volatile(PPC_TLBIE_5(%0, %1, 2, 0, 1) : :
> > +"r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
> > +   asm volatile(PPC_TLBIE_5(%0, %1, 2, 1, 1) : :
> > +"r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
> > +   trace_tlbie(lpid, 0, TLBIEL_INVAL_SET_LPID, lpid, 2, 0, 1);
> > +   } else {
> > +   asm volatile(PPC_TLBIE_5(%0, %1, 2, 0, 0) : :
> > +"r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
> > +   trace_tlbie(lpid, 0, TLBIEL_INVAL_SET_LPID, lpid, 2, 0, 0);
> > +   }
> > +   /* do we need fixup here ?*/
> > +   asm volatile("eieio; tlbsync; ptesync" : : : "memory");
> > +}
> > +
> 
> checkpatch.pl seems to complain:
> 
> ERROR: need consistent spacing around '%' (ctx:WxV)
> #125: FILE: arch/powerpc/mm/book3s64/pgtable.c:230:
> +   asm volatile(PPC_TLBIE_5(%0, %1, 2, 0, 1) : :
>  ^
> 
> ERROR: need consistent spacing around '%' (ctx:WxV)
> #127: FILE: arch/powerpc/mm/book3s64/pgtable.c:232:
> +   asm volatile(PPC_TLBIE_5(%0, %1, 2, 1, 1) : :
>  ^
> 
> ERROR: need consistent spacing around '%' (ctx:WxV)
> #131: FILE: arch/powerpc/mm/book3s64/pgtable.c:236:
> +   asm volatile(PPC_TLBIE_5(%0, %1, 2, 0, 0) : :
>  ^

Then clearly checkpatch.pl has a bug.

Paul.

Re: [PATCH v3 6/9] KVM: PPC: Ultravisor: Restrict flush of the partition tlb cache

2019-06-06 Thread Murilo Opsfelder Araújo 
Claudio Carvalho  writes:

> From: Ram Pai 
>
> Ultravisor is responsible for flushing the tlb cache, since it manages
> the PATE entries. Hence skip tlb flush, if the ultravisor firmware is
> available.
>
> Signed-off-by: Ram Pai 
> Signed-off-by: Claudio Carvalho 
> ---
>  arch/powerpc/mm/book3s64/pgtable.c | 33 +-
>  1 file changed, 19 insertions(+), 14 deletions(-)
>
> diff --git a/arch/powerpc/mm/book3s64/pgtable.c 
> b/arch/powerpc/mm/book3s64/pgtable.c
> index 40a9fc8b139f..1eeb5fe87023 100644
> --- a/arch/powerpc/mm/book3s64/pgtable.c
> +++ b/arch/powerpc/mm/book3s64/pgtable.c
> @@ -224,6 +224,23 @@ void __init mmu_partition_table_init(void)
>   powernv_set_nmmu_ptcr(ptcr);
>  }
>
> +static void flush_partition(unsigned int lpid, unsigned long dw0)
> +{
> + if (dw0 & PATB_HR) {
> + asm volatile(PPC_TLBIE_5(%0, %1, 2, 0, 1) : :
> +  "r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
> + asm volatile(PPC_TLBIE_5(%0, %1, 2, 1, 1) : :
> +  "r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
> + trace_tlbie(lpid, 0, TLBIEL_INVAL_SET_LPID, lpid, 2, 0, 1);
> + } else {
> + asm volatile(PPC_TLBIE_5(%0, %1, 2, 0, 0) : :
> +  "r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
> + trace_tlbie(lpid, 0, TLBIEL_INVAL_SET_LPID, lpid, 2, 0, 0);
> + }
> + /* do we need fixup here ?*/
> + asm volatile("eieio; tlbsync; ptesync" : : : "memory");
> +}
> +

checkpatch.pl seems to complain:

ERROR: need consistent spacing around '%' (ctx:WxV)
#125: FILE: arch/powerpc/mm/book3s64/pgtable.c:230:
+   asm volatile(PPC_TLBIE_5(%0, %1, 2, 0, 1) : :
 ^

ERROR: need consistent spacing around '%' (ctx:WxV)
#127: FILE: arch/powerpc/mm/book3s64/pgtable.c:232:
+   asm volatile(PPC_TLBIE_5(%0, %1, 2, 1, 1) : :
 ^

ERROR: need consistent spacing around '%' (ctx:WxV)
#131: FILE: arch/powerpc/mm/book3s64/pgtable.c:236:
+   asm volatile(PPC_TLBIE_5(%0, %1, 2, 0, 0) : :
 ^

>  static void __mmu_partition_table_set_entry(unsigned int lpid,
>   unsigned long dw0,
>   unsigned long dw1)
> @@ -238,20 +255,8 @@ static void __mmu_partition_table_set_entry(unsigned int 
> lpid,
>* The type of flush (hash or radix) depends on what the previous
>* use of this partition ID was, not the new use.
>*/
> - asm volatile("ptesync" : : : "memory");
> - if (old & PATB_HR) {
> - asm volatile(PPC_TLBIE_5(%0,%1,2,0,1) : :
> -  "r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
> - asm volatile(PPC_TLBIE_5(%0,%1,2,1,1) : :
> -  "r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
> - trace_tlbie(lpid, 0, TLBIEL_INVAL_SET_LPID, lpid, 2, 0, 1);
> - } else {
> - asm volatile(PPC_TLBIE_5(%0,%1,2,0,0) : :
> -  "r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
> - trace_tlbie(lpid, 0, TLBIEL_INVAL_SET_LPID, lpid, 2, 0, 0);
> - }
> - /* do we need fixup here ?*/
> - asm volatile("eieio; tlbsync; ptesync" : : : "memory");
> + if (!firmware_has_feature(FW_FEATURE_ULTRAVISOR))
> + flush_partition(lpid, old);
>  }
>
>  void mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0,
> --
> 2.20.1

[PATCH v3 6/9] KVM: PPC: Ultravisor: Restrict flush of the partition tlb cache

2019-06-06 Thread Claudio Carvalho 
From: Ram Pai 

Ultravisor is responsible for flushing the tlb cache, since it manages
the PATE entries. Hence skip tlb flush, if the ultravisor firmware is
available.

Signed-off-by: Ram Pai 
Signed-off-by: Claudio Carvalho 
---
 arch/powerpc/mm/book3s64/pgtable.c | 33 +-
 1 file changed, 19 insertions(+), 14 deletions(-)

diff --git a/arch/powerpc/mm/book3s64/pgtable.c 
b/arch/powerpc/mm/book3s64/pgtable.c
index 40a9fc8b139f..1eeb5fe87023 100644
--- a/arch/powerpc/mm/book3s64/pgtable.c
+++ b/arch/powerpc/mm/book3s64/pgtable.c
@@ -224,6 +224,23 @@ void __init mmu_partition_table_init(void)
powernv_set_nmmu_ptcr(ptcr);
 }
 
+static void flush_partition(unsigned int lpid, unsigned long dw0)
+{
+   if (dw0 & PATB_HR) {
+   asm volatile(PPC_TLBIE_5(%0, %1, 2, 0, 1) : :
+"r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
+   asm volatile(PPC_TLBIE_5(%0, %1, 2, 1, 1) : :
+"r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
+   trace_tlbie(lpid, 0, TLBIEL_INVAL_SET_LPID, lpid, 2, 0, 1);
+   } else {
+   asm volatile(PPC_TLBIE_5(%0, %1, 2, 0, 0) : :
+"r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
+   trace_tlbie(lpid, 0, TLBIEL_INVAL_SET_LPID, lpid, 2, 0, 0);
+   }
+   /* do we need fixup here ?*/
+   asm volatile("eieio; tlbsync; ptesync" : : : "memory");
+}
+
 static void __mmu_partition_table_set_entry(unsigned int lpid,
unsigned long dw0,
unsigned long dw1)
@@ -238,20 +255,8 @@ static void __mmu_partition_table_set_entry(unsigned int 
lpid,
 * The type of flush (hash or radix) depends on what the previous
 * use of this partition ID was, not the new use.
 */
-   asm volatile("ptesync" : : : "memory");
-   if (old & PATB_HR) {
-   asm volatile(PPC_TLBIE_5(%0,%1,2,0,1) : :
-"r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
-   asm volatile(PPC_TLBIE_5(%0,%1,2,1,1) : :
-"r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
-   trace_tlbie(lpid, 0, TLBIEL_INVAL_SET_LPID, lpid, 2, 0, 1);
-   } else {
-   asm volatile(PPC_TLBIE_5(%0,%1,2,0,0) : :
-"r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
-   trace_tlbie(lpid, 0, TLBIEL_INVAL_SET_LPID, lpid, 2, 0, 0);
-   }
-   /* do we need fixup here ?*/
-   asm volatile("eieio; tlbsync; ptesync" : : : "memory");
+   if (!firmware_has_feature(FW_FEATURE_ULTRAVISOR))
+   flush_partition(lpid, old);
 }
 
 void mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0,
-- 
2.20.1