From: Igal Liberman igal.liber...@freescale.com
Describe the PHY topology for all configurations supported by each board
Based on prior work by Andy Fleming aflem...@freescale.com
Signed-off-by: Igal Liberman igal.liber...@freescale.com
Signed-off-by: Shruti Kanetkar shr...@freescale.com
Signed-off-by: Emil Medve emilian.me...@freescale.com
---
Depends on the following patch set:
https://patchwork.ozlabs.org/patch/502018/
https://patchwork.ozlabs.org/patch/502019/
v3 --- v4:
- Added T1024 support
v2 --- v3:
- Fixed incorrect E-Mail address (signed-off-by)
v1 --- v2
- Remove 'Change-Id'
arch/powerpc/boot/dts/b4860qds.dts| 60 -
arch/powerpc/boot/dts/b4qds.dtsi | 51 -
arch/powerpc/boot/dts/p1023rdb.dts| 24 +-
arch/powerpc/boot/dts/p2041rdb.dts| 92 +++-
arch/powerpc/boot/dts/p3041ds.dts | 112 -
arch/powerpc/boot/dts/p4080ds.dts | 184 ++-
arch/powerpc/boot/dts/p5020ds.dts | 112 -
arch/powerpc/boot/dts/p5040ds.dts | 234 ++-
arch/powerpc/boot/dts/t1023rdb.dts| 41
arch/powerpc/boot/dts/t1024rdb.dts| 45
arch/powerpc/boot/dts/t1040rdb.dts| 32 ++-
arch/powerpc/boot/dts/t1042rdb.dts| 30 ++-
arch/powerpc/boot/dts/t1042rdb_pi.dts | 18 +-
arch/powerpc/boot/dts/t104xqds.dtsi | 178 ++-
arch/powerpc/boot/dts/t104xrdb.dtsi | 33 ++-
arch/powerpc/boot/dts/t2080qds.dts| 158 -
arch/powerpc/boot/dts/t2080rdb.dts| 67 +-
arch/powerpc/boot/dts/t2081qds.dts| 221 +-
arch/powerpc/boot/dts/t4240qds.dts| 400 -
arch/powerpc/boot/dts/t4240rdb.dts| 149 +++-
20 files changed, 2221 insertions(+), 20 deletions(-)
diff --git a/arch/powerpc/boot/dts/b4860qds.dts
b/arch/powerpc/boot/dts/b4860qds.dts
index 6bb3707..98b1ef4 100644
--- a/arch/powerpc/boot/dts/b4860qds.dts
+++ b/arch/powerpc/boot/dts/b4860qds.dts
@@ -1,7 +1,7 @@
/*
* B4860DS Device Tree Source
*
- * Copyright 2012 Freescale Semiconductor Inc.
+ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -39,12 +39,69 @@
model = fsl,B4860QDS;
compatible = fsl,B4860QDS;
+ aliases {
+ phy_sgmii_1e = phy_sgmii_1e;
+ phy_sgmii_1f = phy_sgmii_1f;
+ phy_xaui_slot1 = phy_xaui_slot1;
+ phy_xaui_slot2 = phy_xaui_slot2;
+ };
+
ifc: localbus@ffe124000 {
board-control@3,0 {
compatible = fsl,b4860qds-fpga, fsl,fpga-qixis;
};
};
+ soc@ffe00 {
+ fman@40 {
+ ethernet@e8000 {
+ phy-handle = phy_sgmii_1e;
+ phy-connection-type = sgmii;
+ };
+
+ ethernet@ea000 {
+ phy-handle = phy_sgmii_1f;
+ phy-connection-type = sgmii;
+ };
+
+ ethernet@f {
+ phy-handle = phy_xaui_slot1;
+ phy-connection-type = xgmii;
+ };
+
+ ethernet@f2000 {
+ phy-handle = phy_xaui_slot2;
+ phy-connection-type = xgmii;
+ };
+
+ mdio@fc000 {
+ phy_sgmii_1e: ethernet-phy@1e {
+ reg = 0x1e;
+ status = disabled;
+ };
+
+ phy_sgmii_1f: ethernet-phy@1f {
+ reg = 0x1f;
+ status = disabled;
+ };
+ };
+
+ mdio@fd000 {
+ phy_xaui_slot1: xaui-phy@slot1 {
+ compatible =
ethernet-phy-ieee802.3-c45;
+ reg = 0x7;
+ status = disabled;
+ };
+
+ phy_xaui_slot2: xaui-phy@slot2 {
+ compatible =
ethernet-phy-ieee802.3-c45;
+ reg = 0x6;
+ status = disabled;
+ };
+ };
+ };
+ };
+
rio: rapidio@ffe0c {
reg = 0xf 0xfe0c 0 0x11000;
@@ -55,7 +112,6 @@
ranges = 0 0 0xc 0x3000 0 0x1000;
};
