Re: [PATCH v6 2/3] arm64: dts: ls1028a: Add PCIe controller DT nodes
Am 2020-02-24 10:22, schrieb Z.q. Hou: Hi Michael and Shawn, I'll update the patch with iommu-map property. friendly ping :) -michael Thanks, Zhiqiang -Original Message- From: Michael Walle Sent: 2020年2月24日 16:54 To: Shawn Guo Cc: Xiaowei Bao ; Z.q. Hou ; bhelg...@google.com; devicet...@vger.kernel.org; Leo Li ; linux-arm-ker...@lists.infradead.org; linux-ker...@vger.kernel.org; linux-...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; lorenzo.pieral...@arm.com; mark.rutl...@arm.com; M.h. Lian ; Mingkai Hu ; robh...@kernel.org; Roy Zang Subject: Re: [PATCH v6 2/3] arm64: dts: ls1028a: Add PCIe controller DT nodes Hi Shawn, all, Am 2020-02-24 09:43, schrieb Shawn Guo: > On Mon, Feb 24, 2020 at 09:11:05AM +0100, Michael Walle wrote: >> Hi Xiaowei, Hi Shawn, >> >> > LS1028a implements 2 PCIe 3.0 controllers. >> >> Patch 1/3 and 3/3 are in Linus' tree but nobody seems to care about >> this patch anymore :( >> >> This doesn't work well with the IOMMU, because the iommu-map property >> is missing. The bootloader needs the phandle to fixup the >> entry. >> See >> below. >> >> Shawn, will you add this patch to your tree once its fixed, >> considering it just adds the device tree node for the LS1028A? > > The patch/thread is a bit aged. You may want to send an updated patch > for discussion. So should I just pick up the patch add my two fixes and send it again? What about the Signed-off-by tags? Leave them? Replace them? Add mine? -michael
RE: [PATCH v6 2/3] arm64: dts: ls1028a: Add PCIe controller DT nodes
Hi Michael and Shawn, I'll update the patch with iommu-map property. Thanks, Zhiqiang > -Original Message- > From: Michael Walle > Sent: 2020年2月24日 16:54 > To: Shawn Guo > Cc: Xiaowei Bao ; Z.q. Hou > ; bhelg...@google.com; > devicet...@vger.kernel.org; Leo Li ; > linux-arm-ker...@lists.infradead.org; linux-ker...@vger.kernel.org; > linux-...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; > lorenzo.pieral...@arm.com; mark.rutl...@arm.com; M.h. Lian > ; Mingkai Hu ; > robh...@kernel.org; Roy Zang > Subject: Re: [PATCH v6 2/3] arm64: dts: ls1028a: Add PCIe controller DT > nodes > > Hi Shawn, all, > > Am 2020-02-24 09:43, schrieb Shawn Guo: > > On Mon, Feb 24, 2020 at 09:11:05AM +0100, Michael Walle wrote: > >> Hi Xiaowei, Hi Shawn, > >> > >> > LS1028a implements 2 PCIe 3.0 controllers. > >> > >> Patch 1/3 and 3/3 are in Linus' tree but nobody seems to care about > >> this patch anymore :( > >> > >> This doesn't work well with the IOMMU, because the iommu-map property > >> is missing. The bootloader needs the phandle to fixup the > >> entry. > >> See > >> below. > >> > >> Shawn, will you add this patch to your tree once its fixed, > >> considering it just adds the device tree node for the LS1028A? > > > > The patch/thread is a bit aged. You may want to send an updated patch > > for discussion. > > So should I just pick up the patch add my two fixes and send it again? > What about > the Signed-off-by tags? Leave them? Replace them? Add mine? > > -michael
Re: [PATCH v6 2/3] arm64: dts: ls1028a: Add PCIe controller DT nodes
Hi Shawn, all, Am 2020-02-24 09:43, schrieb Shawn Guo: On Mon, Feb 24, 2020 at 09:11:05AM +0100, Michael Walle wrote: Hi Xiaowei, Hi Shawn, > LS1028a implements 2 PCIe 3.0 controllers. Patch 1/3 and 3/3 are in Linus' tree but nobody seems to care about this patch anymore :( This doesn't work well with the IOMMU, because the iommu-map property is missing. The bootloader needs the phandle to fixup the entry. See below. Shawn, will you add this patch to your tree once its fixed, considering it just adds the device tree node for the LS1028A? The patch/thread is a bit aged. You may want to send an updated patch for discussion. So should I just pick up the patch add my two fixes and send it again? What about the Signed-off-by tags? Leave them? Replace them? Add mine? -michael
Re: [PATCH v6 2/3] arm64: dts: ls1028a: Add PCIe controller DT nodes
On Mon, Feb 24, 2020 at 09:11:05AM +0100, Michael Walle wrote: > Hi Xiaowei, Hi Shawn, > > > LS1028a implements 2 PCIe 3.0 controllers. > > Patch 1/3 and 3/3 are in Linus' tree but nobody seems to care about this patch > anymore :( > > This doesn't work well with the IOMMU, because the iommu-map property is > missing. The bootloader needs the phandle to fixup the entry. See > below. > > Shawn, will you add this patch to your tree once its fixed, considering it > just adds the device tree node for the LS1028A? The patch/thread is a bit aged. You may want to send an updated patch for discussion. Shawn > > > > > Signed-off-by: Xiaowei Bao > > Signed-off-by: Hou Zhiqiang
Re: [PATCH v6 2/3] arm64: dts: ls1028a: Add PCIe controller DT nodes
Hi Xiaowei, Hi Shawn,
> LS1028a implements 2 PCIe 3.0 controllers.
Patch 1/3 and 3/3 are in Linus' tree but nobody seems to care about this patch
anymore :(
This doesn't work well with the IOMMU, because the iommu-map property is
missing. The bootloader needs the phandle to fixup the entry. See
below.
Shawn, will you add this patch to your tree once its fixed, considering it
just adds the device tree node for the LS1028A?
>
> Signed-off-by: Xiaowei Bao
> Signed-off-by: Hou Zhiqiang
> ---
> v2:
> - Fix up the legacy INTx allocate failed issue.
> v3:
> - No change.
> v4:
> - Remove the num-lanes property.
> v5:
> - Add the num-viewport property.
> v6:
> - move num-viewport to 8.
>
> arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 52
> ++
> 1 file changed, 52 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> index 72b9a75..c043b1d 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> @@ -625,6 +625,58 @@
> };
> };
>
> + pcie@340 {
> + compatible = "fsl,ls1028a-pcie";
> + reg = <0x00 0x0340 0x0 0x0010 /* controller
> registers */
> +0x80 0x 0x0 0x2000>; /*
> configuration space */
> + reg-names = "regs", "config";
> + interrupts = , /* PME
> interrupt */
> + ; /* aer
> interrupt */
> + interrupt-names = "pme", "aer";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + dma-coherent;
> + num-viewport = <8>;
> + bus-range = <0x0 0xff>;
> + ranges = <0x8100 0x0 0x 0x80 0x0001 0x0
> 0x0001 /* downstream I/O */
> + 0x8200 0x0 0x4000 0x80 0x4000 0x0
> 0x4000>; /* non-prefetchable memory */
> + msi-parent = <>;
iommu-map = <0 0 0>; /* fixed up by bootloader */
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = < 0 0 1 0 0 GIC_SPI 109
> IRQ_TYPE_LEVEL_HIGH>,
> + < 0 0 2 0 0 GIC_SPI 110
> IRQ_TYPE_LEVEL_HIGH>,
> + < 0 0 3 0 0 GIC_SPI 111
> IRQ_TYPE_LEVEL_HIGH>,
> + < 0 0 4 0 0 GIC_SPI 112
> IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + pcie@350 {
> + compatible = "fsl,ls1028a-pcie";
> + reg = <0x00 0x0350 0x0 0x0010 /* controller
> registers */
> +0x88 0x 0x0 0x2000>; /*
> configuration space */
> + reg-names = "regs", "config";
> + interrupts = ,
> + ;
> + interrupt-names = "pme", "aer";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + dma-coherent;
> + num-viewport = <8>;
> + bus-range = <0x0 0xff>;
> + ranges = <0x8100 0x0 0x 0x88 0x0001 0x0
> 0x0001 /* downstream I/O */
> + 0x8200 0x0 0x4000 0x88 0x4000 0x0
> 0x4000>; /* non-prefetchable memory */
> + msi-parent = <>;
likewise
With these two fixes:
Tested-by: Michael Walle
-michael
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = < 0 0 1 0 0 GIC_SPI 114
> IRQ_TYPE_LEVEL_HIGH>,
> + < 0 0 2 0 0 GIC_SPI 115
> IRQ_TYPE_LEVEL_HIGH>,
> + < 0 0 3 0 0 GIC_SPI 116
> IRQ_TYPE_LEVEL_HIGH>,
> + < 0 0 4 0 0 GIC_SPI 117
> IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> pcie@1f000 { /* Integrated Endpoint Root Complex */
> compatible = "pci-host-ecam-generic";
> reg = <0x01 0xf000 0x0 0x10>;
> --
> 2.9.5
>
>
[PATCH v6 2/3] arm64: dts: ls1028a: Add PCIe controller DT nodes
LS1028a implements 2 PCIe 3.0 controllers.
Signed-off-by: Xiaowei Bao
Signed-off-by: Hou Zhiqiang
---
v2:
- Fix up the legacy INTx allocate failed issue.
v3:
- No change.
v4:
- Remove the num-lanes property.
v5:
- Add the num-viewport property.
v6:
- move num-viewport to 8.
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 52 ++
1 file changed, 52 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 72b9a75..c043b1d 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -625,6 +625,58 @@
};
};
+ pcie@340 {
+ compatible = "fsl,ls1028a-pcie";
+ reg = <0x00 0x0340 0x0 0x0010 /* controller
registers */
+ 0x80 0x 0x0 0x2000>; /*
configuration space */
+ reg-names = "regs", "config";
+ interrupts = , /* PME
interrupt */
+; /* aer
interrupt */
+ interrupt-names = "pme", "aer";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ dma-coherent;
+ num-viewport = <8>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x8100 0x0 0x 0x80 0x0001 0x0
0x0001 /* downstream I/O */
+ 0x8200 0x0 0x4000 0x80 0x4000 0x0
0x4000>; /* non-prefetchable memory */
+ msi-parent = <>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = < 0 0 1 0 0 GIC_SPI 109
IRQ_TYPE_LEVEL_HIGH>,
+ < 0 0 2 0 0 GIC_SPI 110
IRQ_TYPE_LEVEL_HIGH>,
+ < 0 0 3 0 0 GIC_SPI 111
IRQ_TYPE_LEVEL_HIGH>,
+ < 0 0 4 0 0 GIC_SPI 112
IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ pcie@350 {
+ compatible = "fsl,ls1028a-pcie";
+ reg = <0x00 0x0350 0x0 0x0010 /* controller
registers */
+ 0x88 0x 0x0 0x2000>; /*
configuration space */
+ reg-names = "regs", "config";
+ interrupts = ,
+;
+ interrupt-names = "pme", "aer";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ dma-coherent;
+ num-viewport = <8>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x8100 0x0 0x 0x88 0x0001 0x0
0x0001 /* downstream I/O */
+ 0x8200 0x0 0x4000 0x88 0x4000 0x0
0x4000>; /* non-prefetchable memory */
+ msi-parent = <>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = < 0 0 1 0 0 GIC_SPI 114
IRQ_TYPE_LEVEL_HIGH>,
+ < 0 0 2 0 0 GIC_SPI 115
IRQ_TYPE_LEVEL_HIGH>,
+ < 0 0 3 0 0 GIC_SPI 116
IRQ_TYPE_LEVEL_HIGH>,
+ < 0 0 4 0 0 GIC_SPI 117
IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
pcie@1f000 { /* Integrated Endpoint Root Complex */
compatible = "pci-host-ecam-generic";
reg = <0x01 0xf000 0x0 0x10>;
--
2.9.5
